--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity Cal_Limits is
+ generic (
+ cal_Limit_gen : unsigned(19 downto 0) := "00000000000100000000"
+ );
+ port (
+ CLK : in std_logic;
+ cal_Limit_reg : in unsigned(19 downto 0);
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ min_curr_in : in std_logic_vector( 9 downto 0);
+ max_curr_in : in std_logic_vector( 9 downto 0);
+ min_next_in : in std_logic_vector( 9 downto 0);
+ max_next_in : in std_logic_vector( 9 downto 0);
+ FPGA : in std_logic_vector( 3 downto 0);
+ FPGA_next : in std_logic_vector( 3 downto 0);
+ chnl : in std_logic_vector( 6 downto 0);
+ chnl_next : in std_logic_vector( 6 downto 0);
+ Do_Cal_in : in std_logic;
+ default_val_in : in std_logic := '1';
+ chnl_cnt_in : in unsigned(19 downto 0);
+ new_data : in std_logic;
+ write_curr : out std_logic;
+ write_next : out std_logic;
+ min_next : out std_logic_vector( 9 downto 0);
+ max_next : out std_logic_vector( 9 downto 0);
+ min_curr : out std_logic_vector( 9 downto 0);
+ max_curr : out std_logic_vector( 9 downto 0);
+ min_out : out std_logic_vector( 9 downto 0);
+ max_out : out std_logic_vector( 9 downto 0);
+ Delta : out std_logic_vector( 9 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ chnl_out : out std_logic_vector( 6 downto 0);
+ FPGA_out_curr : out std_logic_vector( 3 downto 0);
+ chnl_out_curr : out std_logic_vector( 6 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ Do_Cal_out : out std_logic;
+ chnl_cnt_out : out unsigned (19 downto 0) :="00000000000000000000";
+ write_chnl_cnt : out std_logic;
+ chnl_out_write : out std_logic_vector( 6 downto 0);
+ FPGA_out_write : out std_logic_vector( 3 downto 0);
+ cal_Limit_set : out unsigned (19 downto 0);
+ BUS_Flash_value : in std_logic_vector(26 downto 0);
+ Flash_flag : in std_logic
+ );
+end Cal_Limits;
+
+architecture Behavioral of Cal_Limits is
+
+ signal FPGA_i : std_logic_vector(3 downto 0);
+ signal Delta_i : std_logic_vector(9 downto 0) := "0110110100";
+
+ signal min_curr_i : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_curr_i : std_logic_vector( 9 downto 0);--:= "1000000001";
+ signal min_next_i : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_next_i : std_logic_vector( 9 downto 0);--:= "1000000001";
+
+ signal min_curr_ii : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_curr_ii : std_logic_vector( 9 downto 0);--:= "1000000001";
+ signal min_next_ii : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_next_ii : std_logic_vector( 9 downto 0);--:= "1000000001";
+
+ signal min_curr_iii : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_curr_iii : std_logic_vector( 9 downto 0);--:= "1000000001";
+ signal min_next_iii : std_logic_vector( 9 downto 0);--:= "0000000001";
+ signal max_next_iii : std_logic_vector( 9 downto 0);--:= "1000000001";
+
+ signal cnt_i : unsigned(19 downto 0):="00000000000000000000";
+ signal cnt_ii : unsigned(19 downto 0):="00000000000000000000";
+ signal cnt_iii : unsigned(19 downto 0):="00000000000000000000";
+
+ signal chnl_i : std_logic_vector( 6 downto 0);
+ signal FPGA_ii : std_logic_vector( 3 downto 0);
+ signal chnl_ii : std_logic_vector( 6 downto 0);
+ signal use_old : std_logic:='0';
+
+ signal write_curr_i : std_logic;
+
+ signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";--:="00011000011010100000";
+
+ type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+ signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
+ "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010",
+ "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010",
+ "10000011010000000010","10000011100000000010", others => "11111000010000001111" ));
+
+ --signal write_curr_ii : std_logic;
+
+begin
+
+ Limit : process (CLK)
+ begin
+ if rising_edge(CLK) then
+
+ if (cal_Limit_reg <= cal_Limit_gen) then
+ cal_Limit <= cal_Limit_gen;
+ cal_Limit_set <= cal_Limit_gen;
+ else
+ cal_Limit <= cal_Limit_reg;
+ cal_Limit_set <= cal_Limit_reg;
+ end if;
+
+ end if;
+ end process;
+
+ Count : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then
+ if cnt_i < cal_Limit then
+ cnt_i <= cnt_i + 1;
+ chnl_cnt_out <= cnt_i + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ chnl_cnt_out <= to_unsigned(0,20);
+ end if;
+ write_chnl_cnt <= '0';
+ use_old <= '0';
+ else -- new data
+ chnl_cnt_out <= cnt_i;
+ write_chnl_cnt <= '1';
+
+ if FPGA_next = FPGA_i and chnl_next = chnl_i then
+ use_old <= '1';
+ else
+ use_old <= '0';
+ end if;
+
+ if use_old = '0' then
+ if chnl_cnt_in < cal_Limit then
+ cnt_i <= chnl_cnt_in + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ end if;
+ else
+ if cnt_ii < cal_Limit then
+ cnt_i <= cnt_ii + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ end if;
+ end if;
+ end if; --new data
+
+ FPGA_out <= FPGA;
+
+ FPGA_i <= FPGA;
+ FPGA_ii <= FPGA_i;
+
+ chnl_out <= chnl;
+ chnl_i <= chnl;
+ chnl_ii <= chnl_i;
+
+ cnt_ii <= cnt_i;
+ cnt_iii <= cnt_ii;
+
+ FPGA_out_write <= FPGA_i;
+ chnl_out_write <= chnl_i;
+
+ FPGA_out_curr <= FPGA;
+ chnl_out_curr <= chnl;
+ else
+ write_chnl_cnt <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ Mem_next : process(CLK)--DIN_in
+ begin
+ if rising_edge(CLK) then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then -- old Data/ FPGA/CHNL
+ if cnt_i /= to_unsigned(0,20) then --next memory
+ if unsigned(DIN_in(21 downto 12)) > unsigned(max_next_i) then
+ max_next_i <= DIN_in(21 downto 12);
+ end if;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_i) then
+ min_next_i <= DIN_in(21 downto 12);
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if;
+ write_next <= '0';
+ min_next <= min_next_i;
+ max_next <= max_next_i;
+ else -- new data/FPGA/CHNL
+ write_next <= '1';
+ min_next <= min_next_i;
+ max_next <= max_next_i;
+ if use_old = '1' then
+ if cnt_ii /= to_unsigned(0,20) then
+ if unsigned(DIN_in(21 downto 12)) >= unsigned(max_next_ii) then
+ max_next_i <= DIN_in(21 downto 12);
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_ii) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_ii;
+ end if;
+ else
+ max_next_i <= max_next_ii;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_ii;
+ end if;
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if;
+ else -- fpga/=fpga_ii and chnl_iii /= chnl
+ if chnl_cnt_in /= to_unsigned(0,20) then --next memory
+ if unsigned(DIN_in(21 downto 12)) >= unsigned(max_next_in) then
+ max_next_i <= DIN_in(21 downto 12);
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_in;
+ end if;
+ else
+ max_next_i <= max_next_in;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_in;
+ end if;
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if; --/= 0
+ end if;
+ end if;--new data
+
+ min_next_ii <= min_next_i;
+ max_next_ii <= max_next_i;
+ min_next_iii <= min_next_ii;
+ max_next_iii <= max_next_ii;
+
+ else
+ write_next <= '0';
+ end if;
+ end if;--rising_edge
+ end process;
+
+
+ Mem_curr : process(CLK)--DIN_in)
+ begin
+ if rising_edge(CLK) then
+ if default_val_in = '0' then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then
+ if cnt_i /= to_unsigned(0,20) then
+ min_out <= min_curr_i;
+ max_out <= max_curr_i;
+ if (unsigned(min_curr_i) < unsigned(max_curr_i)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_i) - unsigned(min_curr_i));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ min_curr <= min_curr_i;
+ max_curr <= max_curr_i;
+ write_curr <= '0';
+ else
+ min_out <= min_next_i;
+ max_out <= max_next_i;
+ min_curr_i <= min_next_i;
+ max_curr_i <= max_next_i;
+ min_curr <= min_next_i;
+ max_curr <= max_next_i;
+ if (unsigned(min_next_i) < unsigned(max_next_i)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_i) - unsigned(min_next_i));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '1';
+ end if;
+
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ else -- new data
+ if use_old = '1' then
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ if cnt_ii = to_unsigned(0,20) then
+ write_curr <= '1';
+ min_curr_i <= min_next_ii;
+ max_curr_i <= max_next_ii;
+ min_out <= min_next_ii;
+ max_out <= max_next_ii;
+ min_curr <= min_next_ii;
+ max_curr <= max_next_ii;
+ if (unsigned(min_next_ii) < unsigned(max_next_ii)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_ii) - unsigned(min_next_ii));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ else
+ min_curr_i <= min_curr_ii;
+ max_curr_i <= max_curr_ii;
+ min_out <= min_curr_ii;
+ max_out <= max_curr_ii;
+ min_curr <= min_curr_ii;
+ max_curr <= max_curr_ii;
+ if (unsigned(min_curr_ii) < unsigned(max_curr_ii)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_ii) - unsigned(min_curr_ii));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '0';
+ end if;
+ else --use_old ='0'
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ if chnl_cnt_in = to_unsigned(0,20) then
+ write_curr <= '1';
+ min_curr_i <= min_next_in;
+ max_curr_i <= max_next_in;
+ min_out <= min_next_in;
+ max_out <= max_next_in;
+ min_curr <= min_next_in;
+ max_curr <= max_next_in;
+ if (unsigned(min_next_in) < unsigned(max_next_in)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_in) - unsigned(min_next_in));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ else
+ min_curr_i <= min_curr_in;
+ max_curr_i <= max_curr_in;
+ min_out <= min_curr_in;
+ max_out <= max_curr_in;
+ min_curr <= min_curr_in;
+ max_curr <= max_curr_in;
+ if (unsigned(min_curr_in) < unsigned(max_curr_in)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_in) - unsigned(min_curr_in));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '0';
+ end if;
+ end if;
+ end if;
+ else -- no calibr
+ write_curr <= '0';
+ end if;
+ elsif default_val_in = '1' then
+ --FLASH
+ write_curr <= '1';
+ min_out <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_out <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ min_curr <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_curr <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ min_curr_i <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_curr_i <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ Delta_i <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl)))(9 downto 0)));
+ else
+ write_curr <= '0';
+ min_out <= "0000000100";
+ max_out <= "1000000000";
+ min_curr <= "0000000100";
+ max_curr <= "1000000000";
+ min_curr_i <= "0000000100";
+ max_curr_i <= "1000000000";
+ Delta_i <= "0111111011";--"0111111110";
+ end if;--default value
+
+ min_curr_ii <= min_curr_i;
+ max_curr_ii <= max_curr_i;
+ min_curr_iii <= min_curr_ii;
+ max_curr_iii <= max_curr_ii;
+ --write_curr_ii <= write_curr_i;
+ --write_curr <= write_curr_i;
+
+ --max_curr <= "1000000001";
+ end if;--rising_edge
+ end process;
+
+ proc_Flash_input : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if Flash_flag = '1' then
+ def_value(0,to_integer(unsigned(BUS_Flash_value(26 downto 20))))( 19 downto 0) <= BUS_Flash_value(19 downto 0);
+
+ end if;
+ end if;
+ end process;
+
+
+ --synchronous output
+ proc_slope : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ Do_Cal_out <= Do_Cal_in;
+ end if;
+ end process;
+
+ Delta <= Delta_i;
+end Behavioral;
\ No newline at end of file
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity Cal_Limits_v2 is
+ generic (
+ cal_Limit_gen : unsigned(19 downto 0) := "00000000000100000000"
+ );
+ port (
+ CLK : in std_logic;
+ cal_Limit_reg : in unsigned(19 downto 0);
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ min_curr_in : in std_logic_vector( 9 downto 0);
+ max_curr_in : in std_logic_vector( 9 downto 0);
+ min_next_in : in std_logic_vector( 9 downto 0);
+ max_next_in : in std_logic_vector( 9 downto 0);
+ FPGA : in std_logic_vector( 3 downto 0);
+ FPGA_next : in std_logic_vector( 3 downto 0);
+ chnl : in std_logic_vector( 6 downto 0);
+ chnl_next : in std_logic_vector( 6 downto 0);
+ Do_Cal_in : in std_logic;
+-- default_val_in : in std_logic := '1';
+ chnl_cnt_in : in unsigned(19 downto 0);
+ new_data : in std_logic;
+ write_curr : out std_logic;
+ write_next : out std_logic;
+ min_next : out std_logic_vector( 9 downto 0);
+ max_next : out std_logic_vector( 9 downto 0);
+ min_curr : out std_logic_vector( 9 downto 0);
+ max_curr : out std_logic_vector( 9 downto 0);
+ min_out : out std_logic_vector( 9 downto 0);
+ max_out : out std_logic_vector( 9 downto 0);
+ Delta : out std_logic_vector( 9 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ chnl_out : out std_logic_vector( 6 downto 0);
+ FPGA_out_curr : out std_logic_vector( 3 downto 0);
+ chnl_out_curr : out std_logic_vector( 6 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ Do_Cal_out : out std_logic;
+ chnl_cnt_out : out unsigned (19 downto 0);--:="00000000000000000000";
+ write_chnl_cnt : out std_logic;
+ chnl_out_write : out std_logic_vector( 6 downto 0);
+ FPGA_out_write : out std_logic_vector( 3 downto 0);
+ cal_Limit_set : out unsigned (19 downto 0);
+ BUS_Flash_value : in std_logic_vector(27 downto 0);
+ Flash_flag : in std_logic
+ );
+end Cal_Limits_v2;
+
+architecture Behavioral of Cal_Limits_v2 is
+
+ signal FPGA_i : std_logic_vector( 3 downto 0);
+ signal Delta_i : std_logic_vector( 9 downto 0) := "0110110100";
+ signal min_curr_i : std_logic_vector( 9 downto 0);
+ signal max_curr_i : std_logic_vector( 9 downto 0);
+ signal min_next_i : std_logic_vector( 9 downto 0);
+ signal max_next_i : std_logic_vector( 9 downto 0);
+ signal min_curr_ii : std_logic_vector( 9 downto 0);
+ signal max_curr_ii : std_logic_vector( 9 downto 0);
+ signal min_next_ii : std_logic_vector( 9 downto 0);
+ signal max_next_ii : std_logic_vector( 9 downto 0);
+ signal cnt_i : unsigned(19 downto 0):="00000000000000000000";
+ signal cnt_ii : unsigned(19 downto 0):="00000000000000000000";
+ signal chnl_i : std_logic_vector( 6 downto 0);
+ signal use_old : std_logic:='0';
+ signal cal_Limit : unsigned(19 downto 0):="00011000011010100000";
+
+ type array2D is array (1 downto 0, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+ signal def_value : array2D := (others => ("10000000010000000010","10000000100000000010","10000000110000000010","10000001000000000010",
+ "10000001010000000010","10000001100000000010","10000001110000000010","10000010000000000010",
+ "10000010010000000010","10000010100000000010","10000010110000000010","10000011000000000010",
+ "10000011010000000010","10000011100000000010", others => "11111000010000001111" ));
+
+ type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel)
+ signal dflt_i : bit_2D := (others => (others => '1'));
+
+begin
+
+ Limit : process (CLK)
+ begin
+ if rising_edge(CLK) then
+
+ if (cal_Limit_reg <= cal_Limit_gen) then
+ cal_Limit <= cal_Limit_gen;
+ cal_Limit_set <= cal_Limit_gen;
+ else
+ cal_Limit <= cal_Limit_reg;
+ cal_Limit_set <= cal_Limit_reg;
+ end if;
+
+ end if;
+ end process;
+
+ Count : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then
+ if cnt_i < cal_Limit then
+ cnt_i <= cnt_i + 1;
+ chnl_cnt_out <= cnt_i + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ chnl_cnt_out <= to_unsigned(0,20);
+ dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
+ end if;
+ write_chnl_cnt <= '0';
+ use_old <= '0';
+ else -- new data
+ chnl_cnt_out <= cnt_i;
+ write_chnl_cnt <= '1';
+
+ if FPGA_next = FPGA_i and chnl_next = chnl_i then
+ use_old <= '1';
+ else
+ use_old <= '0';
+ end if;
+
+ if use_old = '0' then
+ if chnl_cnt_in < cal_Limit then
+ cnt_i <= chnl_cnt_in + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
+ end if;
+ else
+ if cnt_ii < cal_Limit then
+ cnt_i <= cnt_ii + 1;
+ else
+ cnt_i <= to_unsigned(0,20);
+ dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
+ end if;
+ end if;
+ end if; --new data
+
+ FPGA_out <= FPGA;
+ FPGA_i <= FPGA;
+ chnl_out <= chnl;
+ chnl_i <= chnl;
+ cnt_ii <= cnt_i;
+ FPGA_out_write <= FPGA_i;
+ chnl_out_write <= chnl_i;
+ FPGA_out_curr <= FPGA;
+ chnl_out_curr <= chnl;
+ else
+ write_chnl_cnt <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ Mem_next : process(CLK)--DIN_in
+ begin
+ if rising_edge(CLK) then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then -- old Data/ FPGA/CHNL
+ if cnt_i /= to_unsigned(0,20) then --next memory
+ if unsigned(DIN_in(21 downto 12)) > unsigned(max_next_i) then
+ max_next_i <= DIN_in(21 downto 12);
+ end if;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_i) then
+ min_next_i <= DIN_in(21 downto 12);
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if;
+ write_next <= '0';
+ min_next <= min_next_i;
+ max_next <= max_next_i;
+ else -- new data/FPGA/CHNL
+ write_next <= '1';
+ min_next <= min_next_i;
+ max_next <= max_next_i;
+ if use_old = '1' then
+ if cnt_ii /= to_unsigned(0,20) then
+ if unsigned(DIN_in(21 downto 12)) >= unsigned(max_next_ii) then
+ max_next_i <= DIN_in(21 downto 12);
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_ii) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_ii;
+ end if;
+ else
+ max_next_i <= max_next_ii;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_ii;
+ end if;
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if;
+ else -- fpga/=fpga_ii and chnl_iii /= chnl
+ if chnl_cnt_in /= to_unsigned(0,20) then --next memory
+ if unsigned(DIN_in(21 downto 12)) >= unsigned(max_next_in) then
+ max_next_i <= DIN_in(21 downto 12);
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_in;
+ end if;
+ else
+ max_next_i <= max_next_in;
+ if unsigned(DIN_in(21 downto 12)) < unsigned(min_next_in) then
+ min_next_i <= DIN_in(21 downto 12);
+ else
+ min_next_i <= min_next_in;
+ end if;
+ end if;
+ else
+ min_next_i <= DIN_in(21 downto 12);--"1111111111";
+ max_next_i <= DIN_in(21 downto 12);--"0000000000";
+ end if; --/= 0
+ end if;
+ end if;--new data
+
+ min_next_ii <= min_next_i;
+ max_next_ii <= max_next_i;
+
+ else
+ write_next <= '0';
+ end if;
+ end if;--rising_edge
+ end process;
+
+
+ Mem_curr : process(CLK)--DIN_in)
+ begin
+ if rising_edge(CLK) then
+ if dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) = '0' then
+ if Do_Cal_in = '1' then
+ if new_data = '0' then
+ if cnt_i /= to_unsigned(0,20) then
+ min_out <= min_curr_i;
+ max_out <= max_curr_i;
+ if (unsigned(min_curr_i) < unsigned(max_curr_i)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_i) - unsigned(min_curr_i));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ min_curr <= min_curr_i;
+ max_curr <= max_curr_i;
+ write_curr <= '0';
+ else
+ min_out <= min_next_i;
+ max_out <= max_next_i;
+ min_curr_i <= min_next_i;
+ max_curr_i <= max_next_i;
+ min_curr <= min_next_i;
+ max_curr <= max_next_i;
+ if (unsigned(min_next_i) < unsigned(max_next_i)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_i) - unsigned(min_next_i));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '1';
+ end if;
+
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ else -- new data
+ if use_old = '1' then
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ if cnt_ii = to_unsigned(0,20) then
+ write_curr <= '1';
+ min_curr_i <= min_next_ii;
+ max_curr_i <= max_next_ii;
+ min_out <= min_next_ii;
+ max_out <= max_next_ii;
+ min_curr <= min_next_ii;
+ max_curr <= max_next_ii;
+ if (unsigned(min_next_ii) < unsigned(max_next_ii)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_ii) - unsigned(min_next_ii));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ else
+ min_curr_i <= min_curr_ii;
+ max_curr_i <= max_curr_ii;
+ min_out <= min_curr_ii;
+ max_out <= max_curr_ii;
+ min_curr <= min_curr_ii;
+ max_curr <= max_curr_ii;
+ if (unsigned(min_curr_ii) < unsigned(max_curr_ii)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_ii) - unsigned(min_curr_ii));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '0';
+ end if;
+ else --use_old ='0'
+ --min_curr <= min_curr_i;
+ --max_curr <= max_curr_i;
+ if chnl_cnt_in = to_unsigned(0,20) then
+ write_curr <= '1';
+ min_curr_i <= min_next_in;
+ max_curr_i <= max_next_in;
+ min_out <= min_next_in;
+ max_out <= max_next_in;
+ min_curr <= min_next_in;
+ max_curr <= max_next_in;
+ if (unsigned(min_next_in) < unsigned(max_next_in)) then
+ Delta_i <= std_logic_vector(unsigned(max_next_in) - unsigned(min_next_in));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ else
+ min_curr_i <= min_curr_in;
+ max_curr_i <= max_curr_in;
+ min_out <= min_curr_in;
+ max_out <= max_curr_in;
+ min_curr <= min_curr_in;
+ max_curr <= max_curr_in;
+ if (unsigned(min_curr_in) < unsigned(max_curr_in)) then
+ Delta_i <= std_logic_vector(unsigned(max_curr_in) - unsigned(min_curr_in));
+ else
+ Delta_i <= "0110110100";
+ end if;
+ write_curr <= '0';
+ end if;
+ end if;
+ end if;
+ else -- no calibr
+ write_curr <= '0';
+ end if;
+ elsif dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) = '1' then
+ --FLASH
+ write_curr <= '1';
+ min_out <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_out <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ min_curr <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_curr <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ min_curr_i <= def_value(0,to_integer(unsigned(chnl)))( 9 downto 0);
+ max_curr_i <= def_value(0,to_integer(unsigned(chnl)))(19 downto 10);
+ Delta_i <= std_logic_vector(unsigned(def_value(0,to_integer(unsigned(chnl)))(19 downto 10)) - unsigned(def_value(0,to_integer(unsigned(chnl)))(9 downto 0)));
+ else
+ write_curr <= '0';
+ min_out <= "0000000100";
+ max_out <= "1000000000";
+ min_curr <= "0000000100";
+ max_curr <= "1000000000";
+ min_curr_i <= "0000000100";
+ max_curr_i <= "1000000000";
+ Delta_i <= "0111111011";--"0111111110";
+ end if;--default value
+
+ min_curr_ii <= min_curr_i;
+ max_curr_ii <= max_curr_i;
+
+ end if;--rising_edge
+ end process;
+
+ proc_Flash_input : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if Flash_flag = '1' then
+ def_value(0,to_integer(unsigned(BUS_Flash_value(27 downto 20))))( 19 downto 0) <= BUS_Flash_value(19 downto 0);
+
+ end if;
+ end if;
+ end process;
+
+
+ --synchronous output
+ proc_slope : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ Do_Cal_out <= Do_Cal_in;
+ end if;
+ end process;
+
+ Delta <= Delta_i;
+end Behavioral;
\ No newline at end of file
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity calc_output is
+ Port (
+ CLK : in std_logic;
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ --min_in : in std_logic_vector( 9 downto 0);
+ --max_in : in std_logic_vector( 9 downto 0);
+ do_cal_in : in std_logic;
+ overshoot_in : in std_logic := '0';
+ undershoot_in : in std_logic := '0';
+ slope : in std_logic_vector(11 downto 0);
+ factor : in std_logic_vector( 9 downto 0);
+
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ --min_out : out std_logic_vector( 9 downto 0);
+ --max_out : out std_logic_vector( 9 downto 0);
+ do_cal_out : out std_logic;
+ overshoot_out : out std_logic := '0';
+ undershoot_out : out std_logic := '0';
+ Cal_Data_out : out std_logic_vector(21 downto 0)
+ );
+end calc_output;
+
+architecture Behavioral of calc_output is
+
+ --type unsigned_2D is array (15 downto 0, 63 downto 0) of unsigned (19 downto 0); --(channel)
+ --signal cal_cnt_i : unsigned_2D := (others => (others => "00000000000000000000"));
+
+begin
+ cnt : process (CLK,factor,slope)
+ begin
+ if rising_edge(CLK) then
+
+ Cal_Data_out <= std_logic_vector( (unsigned(factor) * unsigned(slope)) + to_unsigned(500,9));
+
+
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ do_cal_out <= do_cal_in;
+
+ overshoot_out <= overshoot_in;
+ undershoot_out <= undershoot_in;
+
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: JLU Giessen
+-- Engineer: Adrian Weber
+--
+-- Create Date: 06.01.2017 13:32:05
+-- Module Name: Calibration - Behavioral
+-- Project Name: TDC Calibration
+-- Target Devices: TrbSc
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity Calibration is
+ Port (
+ CLK : in std_logic;
+ DIN : in READOUT_TX;
+ DOUT : out READOUT_TX;
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end Calibration;
+
+architecture Behavioral of Calibration is
+ signal Dout_int : std_logic_vector(21 downto 0);
+ signal DIN_i_Mem : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_i_Mem_b_r : std_logic;
+ signal DIN_i_Mem_data_w : std_logic;
+ signal DIN_i_Mem_data_f : std_logic;
+ signal Default_val_Mem : std_logic;
+ signal DIN_o_Lim : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_o_Lim_b_r : std_logic;
+ signal DIN_o_Lim_data_w : std_logic;
+ signal DIN_o_Lim_data_f : std_logic;
+ signal min_out_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal max_out_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal Delta_Lim : std_logic_vector( 9 downto 0) := "0110110100";
+ signal min_next_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal max_next_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal min_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal max_curr_Lim : std_logic_vector( 9 downto 0) := (others => '0');
+ signal FPGA_Lim : std_logic_vector( 3 downto 0) ;
+ signal chnl_Lim : std_logic_vector( 6 downto 0) := (others => '0');
+ signal do_cal_LIM : std_logic;
+ signal DIN_o_LUT : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_o_LUT_b_r : std_logic;
+ signal DIN_o_LUT_data_w : std_logic;
+ signal DIN_o_LUT_data_f : std_logic;
+ signal min_out_LUT : std_logic_vector( 9 downto 0) := (others => '0');
+ signal max_out_LUT : std_logic_vector( 9 downto 0) := (others => '1');
+ signal Delta_LUT : std_logic_vector( 9 downto 0) := (others => '0');
+ signal slope_LUT : std_logic_vector(11 downto 0) := (others => '0');
+ signal cal_flag_LUT : std_logic := '0';
+ signal cal_flag_LUT_out : std_logic := '0';
+ signal FPGA_in_LUT : std_logic_vector( 3 downto 0);
+ signal read_next : std_logic;
+ signal write_next : std_logic;
+ signal read_vld_next : std_logic;
+ signal write_vld_next : std_logic;
+ signal FPGA_next : std_logic_vector( 3 downto 0);
+ signal chnl_next : std_logic_vector( 6 downto 0);
+ signal min_next : std_logic_vector( 9 downto 0);
+ signal max_next : std_logic_vector( 9 downto 0);
+ signal min_in_next : std_logic_vector( 9 downto 0);
+ signal max_in_next : std_logic_vector( 9 downto 0);
+ signal read_curr : std_logic;
+ signal write_curr : std_logic;
+ signal FPGA_curr : std_logic_vector( 3 downto 0);
+ signal chnl_curr : std_logic_vector( 6 downto 0);
+ signal min_curr : std_logic_vector( 9 downto 0);
+ signal max_curr : std_logic_vector( 9 downto 0);
+ signal min_in_curr : std_logic_vector( 9 downto 0);
+ signal max_in_curr : std_logic_vector( 9 downto 0);
+ signal factor : std_logic_vector( 9 downto 0);
+ signal DIN_o_cnt : std_logic_vector(31 downto 0);
+ signal DIN_o_cnt_b_r : std_logic;
+ signal DIN_o_cnt_data_w : std_logic;
+ signal DIN_o_cnt_data_f : std_logic;
+ signal FPGA_o_cnt : std_logic_vector( 3 downto 0);
+ signal read_cal_cnt : std_logic;
+ signal read_dflt_cnt : std_logic;
+ signal chnl_read_cnt : std_logic_vector( 6 downto 0);
+ signal write_cal_cnt : std_logic;
+ signal write_dflt_cnt : std_logic;
+ signal dflt_cnt_in : std_logic;
+ signal dflt_cnt_out : std_logic;
+ signal cal_cnt_in : unsigned(19 downto 0);
+ signal cal_cnt_out : unsigned(19 downto 0);
+ signal FPGA_cnt_val : std_logic_vector( 3 downto 0);
+ signal chnl_cnt_val : std_logic_vector( 6 downto 0);
+ signal DIN_o_cnt_val : std_logic_vector(31 downto 0);
+ signal DIN_o_cnt_val_b_r : std_logic;
+ signal DIN_o_cnt_val_data_w : std_logic;
+ signal DIN_o_cnt_val_data_f : std_logic;
+ signal DIN_MemCurr_data : std_logic_vector(31 downto 0);
+ signal DIN_MemCurr_b_r : std_logic;
+ signal DIN_MemCurr_data_w : std_logic;
+ signal DIN_MemCurr_data_f : std_logic;
+ signal Do_Cal_read_cnt : std_logic;
+ signal Do_Cal_compare_old : std_logic;
+ signal DIN_out_data_compare_old : std_logic_vector(31 downto 0);
+ signal DIN_out_b_r_compare_old : std_logic;
+ signal DIN_out_data_w_compare_old : std_logic;
+ signal DIN_out_data_f_compare_old : std_logic;
+ signal read_compare_old : std_logic;
+ signal CHNL_out_compare_old : std_logic_vector( 6 downto 0);
+ signal FPGA_out_compare_old : std_logic_vector( 3 downto 0);
+ signal CHNL_out_Memory : std_logic_vector( 6 downto 0);
+ signal FPGA_out_Memory : std_logic_vector( 3 downto 0);
+ signal Do_Cal_Memory : std_logic;
+ signal write_chnl_cnt : std_logic;
+ signal new_data_Memory : std_logic;
+ signal chnl_out_write : std_logic_vector( 6 downto 0);
+ signal FPGA_out_write : std_logic_vector( 3 downto 0);
+ signal BUS_do_Cal : std_logic := '1';
+ signal overshoot_LUT : std_logic := '0';
+ signal undershoot_LUT : std_logic := '0';
+ signal Cal_Limit_reg : unsigned(19 downto 0) := "00011000011010100000";
+ signal cal_Limit_set : unsigned(19 downto 0);
+ signal Do_cal_CalcOut : std_logic := '0';
+ signal DIN_o_CalcOut : std_logic_vector(31 downto 0);
+ signal DIN_o_CalcOut_b_r : std_logic;
+ signal DIN_o_CalcOut_data_w : std_logic;
+ signal DIN_o_CalcOut_data_f : std_logic;
+ signal overshoot_CalcOut : std_logic := '0';
+ signal undershoot_CalcOut : std_logic := '0';
+ signal Bus_Chnl : std_logic_vector( 6 downto 0);
+ signal Bus_min : std_logic_vector( 9 downto 0);
+ signal Bus_max : std_logic_vector( 9 downto 0);
+ signal FPGA_out_curr : std_logic_vector( 3 downto 0);
+ signal chnl_out_curr : std_logic_vector( 6 downto 0);
+ signal BUS_Flash_value : std_logic_vector(27 downto 0);
+ signal Flash_flag : std_logic;
+
+begin
+
+--BUS Handler
+proc_reg : process begin
+ wait until rising_edge(CLK);
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.unknown <= '0';
+ Flash_flag <= '0';
+
+ if BUS_RX.write = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(11 downto 0) > x"006" and BUS_RX.addr(11 downto 0) < x"048" then
+ BUS_Flash_value <= std_logic_vector(unsigned(BUS_RX.addr(7 downto 0))-7) & BUS_RX.data(19 downto 10) & BUS_RX.data(9 downto 0);
+ Flash_flag <= '1';
+ else
+ case BUS_RX.addr(11 downto 0) is
+ when x"000" => BUS_do_Cal <= BUS_RX.data(0); -- change between w/ and w/o FPGA based Calibration
+ when x"001" => Cal_Limit_reg <= unsigned(BUS_RX.data(19 downto 0)); -- Set Maximum Value for Calibration Counter
+ when x"003" => Bus_Chnl <= BUS_RX.data(6 downto 0); -- set channel for Min/Max Output
+ when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+ end case;
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ case BUS_RX.addr(11 downto 0) is
+ when x"000" => BUS_TX.data(31 downto 1) <= "0000000000000000000000000000000";
+ BUS_TX.data(0) <= BUS_do_Cal;
+ when x"001" => BUS_TX.data(31 downto 20) <= "000000000000";
+ BUS_TX.data(19 downto 0) <= std_logic_vector(cal_Limit_set);
+ when x"004" => BUS_TX.data(31 downto 10) <= "0000000000000000000000";
+ BUS_TX.data( 9 downto 0) <= Bus_min;
+ when x"005" => BUS_TX.data(31 downto 10) <= "0000000000000000000000";
+ BUS_TX.data( 9 downto 0) <= Bus_max;
+ when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+ end case;
+ end if;
+end process;
+
+
+
+read_cntr : entity work.read_cnt
+ port map(
+ CLK => CLK,
+ chnl => chnl_read_cnt,
+ FPGA_out => FPGA_o_cnt,
+ DIN_in => DIN_i_Mem,
+ DIN_in_b_r => DIN_i_Mem_b_r,
+ DIN_in_data_w => DIN_i_Mem_data_w,
+ DIN_in_data_f => DIN_i_Mem_data_f,
+ DIN_out => DIN_o_cnt,
+ DIN_out_b_r => DIN_o_cnt_b_r,
+ DIN_out_data_w => DIN_o_cnt_data_w,
+ DIN_out_data_f => DIN_o_cnt_data_f,
+ Do_Cal => Do_Cal_read_cnt
+ );
+
+
+ ent_compare_old : entity work.compare_old
+ port map(
+ CLK => CLK,
+ DIN_in => DIN_o_cnt,
+ DIN_in_b_r => DIN_o_cnt_b_r,
+ DIN_in_data_w => DIN_o_cnt_data_w,
+ DIN_in_data_f => DIN_o_cnt_data_f,
+ FPGA_in => FPGA_o_cnt,
+ CHNL_in => chnl_read_cnt,
+ Do_Cal_in => Do_Cal_read_cnt,
+ CHNL_out => CHNL_out_compare_old,
+ FPGA_out => FPGA_out_compare_old,
+ DIN_out => DIN_out_data_compare_old,
+ DIN_out_b_r => DIN_out_b_r_compare_old,
+ DIN_out_data_w => DIN_out_data_w_compare_old,
+ DIN_out_data_f => DIN_out_data_f_compare_old,
+ Do_Cal_out => Do_Cal_compare_old,
+ read => read_compare_old
+ );
+
+ent_cnt_val : entity work.cnt_val
+ port map(
+ CLK => CLK,
+ read => read_compare_old,
+ write => write_chnl_cnt,
+ FPGA_read => FPGA_out_compare_old,
+ chnl_read => CHNL_out_compare_old,
+ FPGA_write => FPGA_out_write,
+ chnl_write => chnl_out_write,
+ cal_cnt => cal_cnt_in,
+ cal_cnt_out => cal_cnt_out,
+ DIN_in => DIN_out_data_compare_old,
+ DIN_in_b_r => DIN_out_b_r_compare_old,
+ DIN_in_data_w => DIN_out_data_w_compare_old,
+ DIN_in_data_f => DIN_out_data_f_compare_old,
+ DIN_out => DIN_o_cnt_val,
+ DIN_out_b_r => DIN_o_cnt_val_b_r,
+ DIN_out_data_w => DIN_o_cnt_val_data_w,
+ DIN_out_data_f => DIN_o_cnt_val_data_f
+ );
+
+ent_dflt_val : entity work.dflt_val
+ port map(
+ CLK => CLK,
+ read => read_compare_old,
+ FPGA_read => FPGA_out_compare_old,
+ chnl_read => CHNL_out_compare_old,
+ dflt_out => Default_val_Mem
+ );
+
+
+ Mem_next : entity work.Memory
+ port map(
+ CLK => CLK,
+ read => read_compare_old,
+ write => write_next,
+ FPGA_read => FPGA_out_compare_old,
+ chnl_read => CHNL_out_compare_old,
+ FPGA_write => FPGA_out_write,
+ chnl_write => chnl_out_write,
+ min => min_next_Lim,
+ max => max_next_Lim,
+ min_out => min_next,
+ max_out => max_next,
+ Do_Cal_in => Do_Cal_compare_old,
+ DIN_data => DIN_out_data_compare_old,
+ DIN_b_r => DIN_out_b_r_compare_old,
+ DIN_data_w => DIN_out_data_w_compare_old,
+ DIN_data_f => DIN_out_data_f_compare_old
+ );
+
+ Mem_curr : entity work.Memory_curr
+ port map(
+ CLK => CLK,
+ read => read_compare_old,
+ write => write_curr,
+ FPGA_read => FPGA_out_compare_old,
+ chnl_read => CHNL_out_compare_old,
+ FPGA_write => FPGA_out_curr,
+ chnl_write => chnl_out_curr,
+ min => min_curr_Lim,
+ max => max_curr_Lim,
+ min_out => min_curr,
+ max_out => max_curr,
+ Do_Cal_in => Do_Cal_compare_old,
+ DIN_data => DIN_out_data_compare_old,
+ DIN_b_r => DIN_out_b_r_compare_old,
+ DIN_data_w => DIN_out_data_w_compare_old,
+ DIN_data_f => DIN_out_data_f_compare_old,
+ DOUT_data => DIN_MemCurr_data,
+ DOUT_b_r => DIN_MemCurr_b_r,
+ DOUT_data_w => DIN_MemCurr_data_w,
+ DOUT_data_f => DIN_MemCurr_data_f,
+ FPGA_out => FPGA_out_Memory,
+ CHNL_out => CHNL_out_Memory,
+ Do_Cal_out => Do_Cal_Memory,
+ new_data => new_data_Memory
+ );
+
+ Cal_Limits : entity work.Cal_Limits_v2
+ generic map(
+ cal_Limit_gen => "00000010011100010000" -- 10.000
+ )
+ port map(
+ CLK => CLK,
+ cal_Limit_reg => Cal_Limit_reg,
+ DIN_in => DIN_MemCurr_data,
+ DIN_in_b_r => DIN_MemCurr_b_r,
+ DIN_in_data_w => DIN_MemCurr_data_w,
+ DIN_in_data_f => DIN_MemCurr_data_f,
+ min_curr_in => min_curr,
+ max_curr_in => max_curr,
+ min_next_in => min_next,
+ max_next_in => max_next,
+ FPGA => FPGA_out_Memory,
+ FPGA_next => FPGA_out_compare_old,
+ chnl => CHNL_out_Memory,
+ chnl_next => CHNL_out_compare_old,
+ Do_Cal_in => Do_Cal_Memory,
+ chnl_cnt_in => cal_cnt_out,
+ new_data => new_data_Memory,
+ write_curr => write_curr,
+ write_next => write_next,
+ min_next => min_next_Lim,
+ max_next => max_next_Lim,
+ min_curr => min_curr_Lim,
+ max_curr => max_curr_Lim,
+ min_out => min_out_Lim,
+ max_out => max_out_Lim,
+ Delta => Delta_Lim,
+ FPGA_out => FPGA_Lim,
+ chnl_out => chnl_Lim,
+ DIN_out => DIN_o_Lim,
+ DIN_out_b_r => DIN_o_Lim_b_r,
+ DIN_out_data_w => DIN_o_Lim_data_w,
+ DIN_out_data_f => DIN_o_Lim_data_f,
+ Do_Cal_out => do_cal_LIM,
+ chnl_cnt_out => cal_cnt_in,
+ write_chnl_cnt => write_chnl_cnt,
+ chnl_out_write => chnl_out_write,
+ FPGA_out_write => FPGA_out_write,
+ FPGA_out_curr => FPGA_out_curr,
+ chnl_out_curr => chnl_out_curr,
+ cal_Limit_set => cal_Limit_set,
+ BUS_Flash_value => BUS_Flash_value,
+ Flash_flag => Flash_flag
+ );
+
+ LUTs : entity work.LUT
+ port map(
+ CLK => CLK,
+ DIN_in => DIN_o_Lim,
+ DIN_in_b_r => DIN_o_Lim_b_r,
+ DIN_in_data_w => DIN_o_Lim_data_w,
+ DIN_in_data_f => DIN_o_Lim_data_f,
+ Delta => Delta_Lim,
+ min_in => min_out_Lim,
+ max_in => max_out_Lim,
+ do_cal_in => do_cal_LIM,
+ FPGA_in => FPGA_Lim,
+ chnl => chnl_Lim,
+ min_out => min_out_LUT,
+ max_out => max_out_LUT,
+ DIN_out => DIN_o_LUT,
+ DIN_out_b_r => DIN_o_LUT_b_r,
+ DIN_out_data_w => DIN_o_LUT_data_w,
+ DIN_out_data_f => DIN_o_LUT_data_f,
+ slope => slope_LUT,
+ do_cal_out => cal_flag_LUT_out,
+ factor => factor,
+ overshoot => overshoot_LUT,
+ undershoot => undershoot_LUT
+ );
+
+ Calc_Output : entity work.calc_output
+ port map(
+ CLK => CLK,
+ DIN_in => DIN_o_LUT,
+ DIN_in_b_r => DIN_o_LUT_b_r,
+ DIN_in_data_w => DIN_o_LUT_data_w,
+ DIN_in_data_f => DIN_o_LUT_data_f,
+ do_cal_in => cal_flag_LUT_out,
+ overshoot_in => overshoot_LUT,
+ undershoot_in => undershoot_LUT,
+ slope => slope_LUT,
+ factor => factor,
+ DIN_out => DIN_o_CalcOut,
+ DIN_out_b_r => DIN_o_CalcOut_b_r,
+ DIN_out_data_w => DIN_o_CalcOut_data_w,
+ DIN_out_data_f => DIN_o_CalcOut_data_f,
+ do_cal_out => Do_cal_CalcOut,
+ overshoot_out => overshoot_CalcOut,
+ undershoot_out => undershoot_CalcOut,
+ Cal_Data_out => Dout_int
+ );
+
+
+ DIN_i_Mem <= DIN.data;
+ DIN_i_Mem_b_r <= DIN.busy_release;
+ DIN_i_Mem_data_w <= DIN.data_write;
+ DIN_i_Mem_data_f <= DIN.data_finished;
+
+
+ fine_out : process (CLK, Do_cal_CalcOut, slope_LUT, factor)
+ begin
+ if rising_edge(CLK) then
+
+ if ((Do_cal_CalcOut = '1') and (BUS_do_Cal = '1')) then
+ DOUT.data(31 downto 22) <= DIN_o_CalcOut(31 downto 22);
+ DOUT.data(11 downto 0) <= DIN_o_CalcOut(11 downto 0);
+ if ((overshoot_CalcOut = '0') and (undershoot_CalcOut = '0')) then
+ DOUT.data(21 downto 12) <= Dout_int(19 downto 10);
+ elsif (undershoot_CalcOut = '1') and (overshoot_CalcOut = '0') then
+ DOUT.data(21 downto 12) <= "1111110010"; --1010
+ elsif (undershoot_CalcOut = '0') and (overshoot_CalcOut = '1') then
+ DOUT.data(21 downto 12) <= "1111110111"; --1015
+ else
+ DOUT.data(21 downto 12) <= "1111111100"; --1020
+ end if;
+ else
+ DOUT.data <= DIN_o_CalcOut;
+ end if;
+
+ DOUT.busy_release <= DIN_o_CalcOut_b_r;
+ DOUT.data_write <= DIN_o_CalcOut_data_w;
+ DOUT.data_finished <= DIN_o_CalcOut_data_f;
+ end if;
+ end process;
+
+
+ debug : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if unsigned(Bus_Chnl) = unsigned(chnl_Lim) then
+ Bus_min <= min_out_Lim;
+ Bus_max <= max_out_Lim;
+ end if;
+ end if;
+ end process;
+
+
+ TX_statusbits : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (DIN.busy_release = '1') then
+ DOUT.statusbits <= DIN.statusbits;
+ end if;
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.trb_net_std.all;
+
+entity LUT is
+ port (
+ CLK : in std_logic;
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ Delta : in std_logic_vector( 9 downto 0):="0110110100";
+ min_in : in std_logic_vector( 9 downto 0);
+ max_in : in std_logic_vector( 9 downto 0);
+ do_cal_in : in std_logic;
+ -- FPGA_in : in std_logic_vector( 3 downto 0);
+ -- chnl : in std_logic_vector( 6 downto 0);
+ min_out : out std_logic_vector( 9 downto 0);
+ max_out : out std_logic_vector( 9 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ slope : out std_logic_vector(11 downto 0);
+ do_cal_out : out std_logic;
+ factor : out std_logic_vector( 9 downto 0);
+ overshoot : out std_logic := '0';
+ undershoot : out std_logic := '0'
+ );
+end entity;
+
+architecture lut of LUT is
+ subtype lutin is std_logic_vector (11 downto 0);
+ subtype lutout is std_logic_vector (11 downto 0);
+ type lut is array (natural range 436 to 563) of lutout;
+
+ constant LUTslope: lut := (
+ "100100101101", "100100100111", "100100100010", "100100011101",
+ "100100010111", "100100010010", "100100001101", "100100001000",
+ "100100000010", "100011111101", "100011111000", "100011110011",
+ "100011101110", "100011101001", "100011100100", "100011011111",
+ "100011011001", "100011010100", "100011010000", "100011001011",
+ "100011000110", "100011000001", "100010111100", "100010110111",
+ "100010110010", "100010101101", "100010101000", "100010100100",
+ "100010011111", "100010011010", "100010010101", "100010010001",
+ "100010001100", "100010000111", "100010000011", "100001111110",
+ "100001111001", "100001110101", "100001110000", "100001101100",
+ "100001100111", "100001100011", "100001011110", "100001011010",
+ "100001010101", "100001010001", "100001001100", "100001001000",
+ "100001000100", "100000111111", "100000111011", "100000110111",
+ "100000110010", "100000101110", "100000101010", "100000100110",
+ "100000100001", "100000011101", "100000011001", "100000010101",
+ "100000010001", "100000001100", "100000001000", "100000000100",
+ "100000000000", "011111111100", "011111111000", "011111110100",
+ "011111110000", "011111101100", "011111101000", "011111100100",
+ "011111100000", "011111011100", "011111011000", "011111010100",
+ "011111010000", "011111001100", "011111001000", "011111000100",
+ "011111000000", "011110111101", "011110111001", "011110110101",
+ "011110110001", "011110101101", "011110101010", "011110100110",
+ "011110100010", "011110011110", "011110011011", "011110010111",
+ "011110010011", "011110010000", "011110001100", "011110001000",
+ "011110000101", "011110000001", "011101111110", "011101111010",
+ "011101110110", "011101110011", "011101101111", "011101101100",
+ "011101101000", "011101100101", "011101100001", "011101011110",
+ "011101011010", "011101010111", "011101010011", "011101010000",
+ "011101001101", "011101001001", "011101000110", "011101000010",
+ "011100111111", "011100111100", "011100111000", "011100110101",
+ "011100110010", "011100101110", "011100101011", "011100101000",
+ "011100100101", "011100100001", "011100011110", "011100011011"
+ );
+
+ signal DIN_in_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal DIN_out_i : std_logic_vector(31 downto 0) := (others => '0');
+ signal do_cal_out_i : std_logic := '0';
+
+begin
+
+ proc_slope : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if do_cal_in = '1' then
+ slope <= LUTslope( TO_INTEGER ( unsigned(Delta)));
+ end if;
+ min_out <= min_in;
+ max_out <= max_in;
+ do_cal_out_i <= do_cal_in;
+ end if;
+ end process;
+
+ proc_factor : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ --keep values in definition area of linear part
+ if (unsigned(DIN_in(21 downto 12)) < unsigned(min_in) ) then
+ factor <= (others => '0');
+ undershoot <= '1'; -- value is out of calibration range
+ overshoot <= '0';
+ elsif (unsigned(DIN_in(21 downto 12)) > unsigned(max_in) ) then
+ factor <= (others => '0');
+ overshoot <= '1'; -- value is out of calibration range
+ undershoot <= '0';
+ else
+ factor <= std_logic_vector(unsigned(DIN_in(21 downto 12)) - unsigned(min_in));
+ undershoot <= '0';
+ overshoot <= '0';
+ end if;
+
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ end if;
+ end process;
+
+ do_cal_out <= do_cal_out_i;
+
+end architecture;
\ No newline at end of file
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity Memory is
+ Port (
+ CLK : in std_logic;
+ read : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector(3 downto 0);
+ chnl_read : in std_logic_vector(6 downto 0);
+ FPGA_write : in std_logic_vector(3 downto 0);
+ chnl_write : in std_logic_vector(6 downto 0);
+ Min : in std_logic_vector(9 downto 0);
+ Max : in std_logic_vector(9 downto 0);
+ Do_Cal_in : in std_logic;
+ DIN_data : in std_logic_vector(31 downto 0);
+ DIN_b_r : in std_logic;
+ DIN_data_w : in std_logic;
+ DIN_data_f : in std_logic;
+ Min_out : out std_logic_vector(9 downto 0):= "1111111111";
+ Max_out : out std_logic_vector(9 downto 0):= "0000000000"
+ );
+end Memory;
+
+architecture Behavioral of Memory is
+
+ type array2D is array (3 downto 0, 14 downto 0) of std_logic_vector(9 downto 0); --(FPGA)(channel)
+ signal Max_Bin_i : array2D := (others => (others => ("0000000000")));
+ signal Min_Bin_i : array2D := (others => (others => ("1111111101")));
+
+begin
+
+ mem : process (CLK,read,write)
+ begin
+ if rising_edge(CLK) then
+
+ if (read = '1' and Do_Cal_in = '1') then --read
+ if (FPGA_read = FPGA_write) and (chnl_read = chnl_write) then
+ Max_out <= Max;
+ Min_out <= Min;
+ else
+ Max_out <= Max_Bin_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));
+ Min_out <= Min_Bin_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));
+ end if;
+ end if;
+ if (write = '1') then --write
+ Max_Bin_i(to_integer(unsigned(FPGA_write)),to_integer(unsigned(chnl_write))) <= Max;
+ Min_Bin_i(to_integer(unsigned(FPGA_write)),to_integer(unsigned(chnl_write))) <= Min;
+ end if;
+
+
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity Memory_curr is
+ Port (
+ CLK : in std_logic;
+ read : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector(3 downto 0);
+ chnl_read : in std_logic_vector(6 downto 0);
+ FPGA_write : in std_logic_vector(3 downto 0);
+ chnl_write : in std_logic_vector(6 downto 0);
+ Min : in std_logic_vector(9 downto 0);
+ Max : in std_logic_vector(9 downto 0);
+ Do_Cal_in : in std_logic;
+ DIN_data : in std_logic_vector(31 downto 0);
+ DIN_b_r : in std_logic;
+ DIN_data_w : in std_logic;
+ DIN_data_f : in std_logic;
+ Min_out : out std_logic_vector(9 downto 0):= "1111111111";
+ Max_out : out std_logic_vector(9 downto 0):= "0000000000";
+ new_data : out std_logic;
+ DOUT_data : out std_logic_vector(31 downto 0);
+ DOUT_b_r : out std_logic;
+ DOUT_data_w : out std_logic;
+ DOUT_data_f : out std_logic;
+ FPGA_out : out std_logic_vector(3 downto 0);
+ CHNL_out : out std_logic_vector(6 downto 0);
+ Do_Cal_out : out std_logic
+ );
+end Memory_curr;
+
+architecture Behavioral of Memory_curr is
+
+ type array2D is array (15 downto 0, 63 downto 0) of std_logic_vector(9 downto 0); --(FPGA)(channel)
+ signal Max_Bin_i : array2D := (others => (others => ("0000000010")));
+ signal Min_Bin_i : array2D := (others => (others => ("1001111110")));
+
+begin
+
+ mem : process (CLK,read,write)
+ begin
+ if rising_edge(CLK) then
+
+ if (read = '1' and Do_Cal_in = '1') then --read
+ --if (Do_Cal_in = '1') then --read
+ if (FPGA_read = FPGA_write) and (chnl_read = chnl_write) then
+ Max_out <= Max;
+ Min_out <= Min;
+ else
+ Max_out <= Max_Bin_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));
+ Min_out <= Min_Bin_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));
+ end if;
+ end if;
+ if (write = '1') then --write
+ Max_Bin_i(to_integer(unsigned(FPGA_write)),to_integer(unsigned(chnl_write))) <= Max;
+ Min_Bin_i(to_integer(unsigned(FPGA_write)),to_integer(unsigned(chnl_write))) <= Min;
+ end if;
+
+ DOUT_data <= DIN_data;
+ DOUT_b_r <= DIN_b_r;
+ DOUT_data_w <= DIN_data_w;
+ DOUT_data_f <= DIN_data_f;
+ new_data <= read;
+ FPGA_out <= FPGA_read;
+ CHNL_out <= chnl_read;
+ Do_Cal_out <= Do_Cal_in;
+
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity cnt_val is
+ Port (
+ CLK : in std_logic;
+ read : in std_logic;
+ write : in std_logic;
+ FPGA_read : in std_logic_vector( 3 downto 0);
+ chnl_read : in std_logic_vector( 6 downto 0);
+ FPGA_write : in std_logic_vector( 3 downto 0);
+ chnl_write : in std_logic_vector( 6 downto 0);
+ cal_cnt : in unsigned(19 downto 0);
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ cal_cnt_out : out unsigned(19 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic
+ );
+end cnt_val;
+
+architecture Behavioral of cnt_val is
+
+ type unsigned_2D is array (15 downto 0, 63 downto 0) of unsigned (19 downto 0); --(channel)
+ signal cal_cnt_i : unsigned_2D := (others => (others => "00000000000000000000"));
+
+begin
+ cnt : process (CLK,read,write)
+ begin
+ if rising_edge(CLK) then
+ if (read = '1') then --read
+ if (FPGA_read /= FPGA_write) or (chnl_read /= chnl_write) then
+ cal_cnt_out <= cal_cnt_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));
+ else
+ cal_cnt_out <= cal_cnt;-- if channel/fpage is same as 2 inputs before
+ end if;
+ end if;
+ if (write = '1') then --write
+ cal_cnt_i(to_integer(unsigned(FPGA_write)),to_integer(unsigned(chnl_write))) <= cal_cnt;
+ end if;
+
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity compare_old is
+ Port ( CLK : in std_logic;
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ FPGA_in : in std_Logic_vector( 3 downto 0);
+ CHNL_in : in std_logic_vector( 6 downto 0);
+ Do_Cal_in : in std_Logic;
+ CHNL_out : out std_logic_vector( 6 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ Do_Cal_out : out std_logic;
+ read : out std_logic := '0'
+ );
+end compare_old;
+
+architecture Behavioral of compare_old is
+
+ signal FPGA_i : std_logic_vector( 3 downto 0):="0010";
+ signal CHNL_i : std_logic_vector( 6 downto 0):="1111111";
+
+begin
+
+ rd_cnt : process(CLK)
+ begin
+ if rising_edge(CLK) then
+
+ if (Do_Cal_in = '1') then
+ if (FPGA_in = FPGA_i) and (CHNL_in = CHNL_i) then -- same channel and fpga as before, no need to reread
+ read <= '0';
+ FPGA_out <= FPGA_i;
+ CHNL_out <= CHNL_i;
+ else -- different fpga/channel -> read again!
+ read <= '1';
+ FPGA_i <= FPGA_in;
+ CHNL_i <= CHNL_in;
+ FPGA_out <= FPGA_in;
+ CHNL_out <= CHNL_in;
+ end if;
+ else
+ read <= '0';
+ FPGA_out <= "1111"; -- to avoid collisions
+ CHNL_out <= "1111111";
+ end if;
+ --loop through entity
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ Do_Cal_out <= Do_Cal_in;
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.NUMERIC_STD.ALL;\r
+\r
+entity dflt_val is\r
+ Port ( \r
+ CLK : in std_logic;\r
+ read : in std_logic;\r
+ --do_Cal : in std_logic;\r
+ FPGA_read : in std_logic_vector(3 downto 0);\r
+ chnl_read : in std_logic_vector(6 downto 0);\r
+ --FPGA_write : in std_logic_vector(3 downto 0);\r
+ --chnl_write : in std_logic_vector(6 downto 0);\r
+ dflt_out : out std_logic\r
+ );\r
+end dflt_val;\r
+\r
+architecture Behavioral of dflt_val is\r
+\r
+ type bit_2D is array (15 downto 0, 63 downto 0) of std_logic; --(channel)\r
+ signal dflt_i : bit_2D := (others => (others => '1'));\r
+ signal start : std_logic := '1';\r
+ \r
+begin\r
+ dflt_cnt : process (CLK)\r
+ begin\r
+ if rising_edge(CLK) then\r
+ if (read = '1') then --read\r
+ dflt_out <= dflt_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read)));\r
+ dflt_i(to_integer(unsigned(FPGA_read)),to_integer(unsigned(chnl_read))) <= '0';\r
+ else\r
+ dflt_out <= '0';\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity read_Memory is
+ generic (
+ calibration_value_max : unsigned(19 downto 0):="11111111111111111111"
+ );
+ Port (
+ CLK : in std_logic;
+ DIN : in std_logic_vector(31 downto 0);
+ DIN_b_r : in std_logic;
+ DIN_data_w : in std_logic;
+ DIN_data_f : in std_logic;
+ FPGA_in : in std_logic_vector( 3 downto 0);
+ chnl_in : in std_logic_vector(6 downto 0);
+ cal_cnt : in unsigned(19 downto 0);
+ dflt_cnt : in std_logic;
+ write_cal_cnt : out std_logic;
+ write_dflt_cnt : out std_logic;
+ cal_cnt_out : out unsigned(19 downto 0);
+ dflt_cnt_out : out std_logic;
+ read_next : out std_logic;
+ read_curr : out std_logic;
+ Cal_chng_flag : out std_logic;
+ do_cal : out std_logic;
+ FPGA : out std_logic_vector( 3 downto 0);
+ chnl : out std_logic_vector( 6 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ Default_val : out std_logic--;
+ --cal_cnt_dbug : out unsigned(19 downto 0)
+ );
+end read_Memory;
+
+architecture Behavioral of read_Memory is
+ -- type unsigned_2D is array (3 downto 0,6 downto 0) of unsigned (7 downto 0); --(channel)
+ --type bit_2D is array (3 downto 0,6 downto 0) of std_logic; --(channel)
+ --signal cal_cnt : unsigned_2D := (others => (others => "00000000"));
+ --signal FPGA_i : std_logic_vector(3 downto 0);
+ --signal Default_val_i : bit_2D := (others => (others => '1'));
+ signal dflt_cnt_last : std_logic;
+begin
+
+ Start_Calib : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if DIN(31) = '1' then
+ dflt_cnt_last <= dflt_cnt;
+ --Do Calibration
+ do_cal <= '1';
+
+ if cal_cnt = to_unsigned(0,20) then
+ --lese Wert aus Mem_next
+ if dflt_cnt = '1' then
+ Cal_chng_flag <= '0';
+ read_curr <= '0';
+ write_dflt_cnt <= '1'; -- gebe dflt_cnt auch die neue /alte adresse (FPGA und channel)
+ dflt_cnt_out <= '0';
+ Default_val <='1';
+ else
+ if dflt_cnt_last = '0' then
+ write_dflt_cnt <= '0';
+ Cal_chng_flag <= '1';
+ end if;
+ Default_val <='0';
+ read_curr <= '1';
+ end if;
+ read_next <= '1';
+ cal_cnt_out <= cal_cnt + 1 ;
+ elsif cal_cnt < calibration_value_max then
+ Default_val <='0';
+ Cal_chng_flag <= '0';
+ read_next <= '1';
+ read_curr <= '1';
+ cal_cnt_out <= cal_cnt + 1 ;
+ write_dflt_cnt <= '0';
+ else
+ Default_val <='0';
+ Cal_chng_flag <= '0';
+ read_next <= '1';
+ read_curr <= '1';
+ cal_cnt_out <= to_unsigned(0,20);--(others => '0');--"00000000000000000000";
+ write_dflt_cnt <= '1';
+ dflt_cnt_out <= '0';
+ end if;
+ write_cal_cnt <= '1';
+ chnl <= DIN(28 downto 22);
+
+ else -- DIN(31) = '0' -> no TDC
+ write_dflt_cnt <= '0';
+ do_cal <= '0';
+ read_next <= '0';
+ read_curr <= '0';
+ --FPGA_i <= DIN( 3 downto 0);
+ write_cal_cnt <= '0';
+ Default_val <='0';
+ Cal_chng_flag <= '0';
+ end if;--DIN(31)
+
+ DIN_out <= DIN;
+ DIN_out_b_r <= DIN_b_r;
+ DIN_out_data_w <= DIN_data_w;
+ DIN_out_data_f <= DIN_data_f;
+
+ FPGA <= FPGA_in;
+ end if; --rising_edge
+ end process;
+
+
+ --FPGA <= FPGA_i;
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity read_cnt is
+ Port ( CLK : in std_logic;
+ DIN_in : in std_logic_vector(31 downto 0);
+ DIN_in_b_r : in std_logic;
+ DIN_in_data_w : in std_logic;
+ DIN_in_data_f : in std_logic;
+ chnl : out std_logic_vector( 6 downto 0);
+ FPGA_out : out std_logic_vector( 3 downto 0);
+ DIN_out : out std_logic_vector(31 downto 0);
+ DIN_out_b_r : out std_logic;
+ DIN_out_data_w : out std_logic;
+ DIN_out_data_f : out std_logic;
+ Do_Cal : out std_logic
+ );
+end read_cnt;
+
+architecture Behavioral of read_cnt is
+
+ signal FPGA_i : std_logic_vector( 3 downto 0);
+
+begin
+
+ rd_cnt : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if DIN_in(31) = '1' then
+ chnl <= DIN_in(28 downto 22);
+ FPGA_out <= FPGA_i;
+ if DIN_in(21 downto 12) = "1111111111" then
+ Do_Cal <= '0';
+ else
+ Do_Cal <= '1';
+ end if;
+ --elsif DIN_in(31 downto 29) = "000" then -- TDC-Trailer
+ -- Do_Cal <= '0';
+ --elsif DIN_in(31 downto 29) = "001" then -- TDC_Header
+ -- Do_Cal <= '0';
+ --elsif DIN_in(31 downto 29) = "010" then -- DEBUG
+ -- Do_Cal <= '0';
+ --elsif DIN_in(31 downto 29) = "011" then -- EPOCH-Counter
+ -- Do_Cal <= '0';
+ else
+ FPGA_i <= "0000";
+
+ Do_Cal <= '0';
+ end if;
+ DIN_out <= DIN_in;
+ DIN_out_b_r <= DIN_in_b_r;
+ DIN_out_data_w <= DIN_in_data_w;
+ DIN_out_data_f <= DIN_in_data_f;
+ end if;
+ end process;
+
+end Behavioral;
--- /dev/null
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
+00000000000000000000000000000001 00000000000000000000000000000001
+10000000000000100001000000000000 10000000000000111110000000000000
+10000000000000100111000000000001 10000000000001001010000000000001
+10000000000001000010000000000010 10000000000001111110000000000010
+10000001100000000011000000000011 10000001100000000100000000000011
+10000000001000001100000000000001 10000000001111101000000000000001
+10000001100000000100000000000100 10000001100000000110000000000100
+10000001100000000001000000000001 10000001100000000000000000000001
+10000001100000000010000000000010 10000001100000000010000000000010
+10000001101000001010000000000011 10000001101111101000000000000011
+10000001100000001010000000000100 10000001100000010001000000000100
+10000001100000001110000000000101 10000001100000011001000000000101
+10000000000000000110000000000110 10000000000000001010000000000110
+10000000000000000111000000000111 10000000000000001100000000000111
+10000000000000001000000000000111 10000000000000001110000000000111
+10000001100000001001000000000111 10000001100000001111000000000111
+10000000000000001010000000000111 10000000000000010001000000000111
+10000001100000001011000000000111 10000001100000010011000000000111
+10000000000000001100000000000111 10000000000000010101000000000111
+10000001100000001101000000000111 10000001100000010111000000000111
+00000000000000000000000000000001 00000000000000000000000000000001
+10000000000000100001000000000000 10000000000000111110000000000000
+10000000000000100111000000000001 10000000000001000000000000000001
+10000000000001000010000000000010 10000000000001110100000000000010
+10000001100000000011000000000011 10000001100000000100000000000011
+10000000001000001100000000000001 10000000001111101000000000000001
+10000001100000000100000000000100 10000001100000000110000000000100
+10000001100000000001000000000001 10000001100000000000000000000001
+10000001100000000010000000000010 10000001100000000010000000000010
+10000001101000001010000000000011 10000001101111101000000000000011
+10000001100000001010000000000100 10000001100000010001000000000100
+10000001100000001110000000000101 10000001100000011001000000000101
+10000000000000000110000000000110 10000000000000000000000000000110
+10000000000000000111000000000111 10000000000000000000000000000111
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05.01.2017 14:31:03
+-- Design Name:
+-- Module Name: sim_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sim_tb is
+end sim_tb;
+
+architecture Behavioral of sim_tb is
+signal CLK ,Flag_Lim, Flag_LUT: std_logic := '0';
+signal DIN_i, DOUT_i : READOUT_TX;
+signal DIN_out_end: std_logic_vector(31 downto 0) := (others => '0');
+signal Fine, Delta, min_Cal : std_logic_vector(9 downto 0);
+signal DIN_out_Lim, DIN_out_LUT : std_logic_vector(31 downto 0);
+signal cal_cnt : unsigned(19 downto 0);
+signal min_curr_dbg, max_curr_dbg, min_next_dbg, max_next_dbg : std_logic_vector(9 downto 0);
+signal cal_cng_dbg,read_next_dbg,write_next_dbg,Dflt_cnt_dbg,Default_val_dbg,write_curr_dbg: std_logic;
+signal FPGA_dbg : std_logic_vector(3 downto 0);
+signal wrt_cal_cnt_dbg : std_logic;
+
+constant CLK_PERIOD : time := 20ns;
+
+begin
+--Input : entity work.input_env
+-- port map(
+-- CLK => CLK,
+-- DOUT => DIN_i
+-- );
+
+ Calibration : entity work.Calibration
+ port map(
+ CLK => CLK,
+ DIN => DIN_i,
+ DOUT => DOUT_i,
+ --Temp => temp,
+ Fine => Fine,
+ Delta => Delta,
+ Min_Cal => min_Cal,
+ Flag_Lim => Flag_Lim,
+ Flag_LUT => Flag_LUT,
+ DIN_out_Lim => DIN_out_Lim,
+ DIN_out_LUT => DIN_out_LUT,
+ cal_cnt_dbug => cal_cnt,
+ min_next_dbg => min_next_dbg,
+ max_next_dbg => max_next_dbg,
+ min_curr_dbg => min_curr_dbg,
+ max_curr_dbg => max_curr_dbg,
+ cal_cng_dbg => cal_cng_dbg,
+ read_next_dbg => read_next_dbg,
+ write_next_dbg => write_next_dbg,
+ FPGA_dbg => FPGA_dbg,
+ DIN_out_end => DIN_out_end,
+ Dflt_cnt_dbg => Dflt_cnt_dbg,
+ Default_val_dbg => Default_val_dbg,
+ write_curr_dbg => write_curr_dbg,
+ wrt_cal_cnt_dbg => wrt_cal_cnt_dbg
+ );
+
+ write : entity work.file_output
+ port map(
+ CLK => CLK,
+ x1 => DIN_out_end,
+ x2 => DOUT_i.data
+ );
+
+
+ CLK_PROC : process is
+ begin
+ CLK <= '1';
+ wait for CLK_PERIOD / 2;
+ CLK <= '0';
+ wait for CLK_PERIOD / 2;
+ end process;
+
+
+ proc_Cal : process is
+ begin
+ wait for 5 ns;
+ DIN_i.statusbits <= "00000000000000000000000000000001";
+ DIN_i.data <= "00000000000000000000000000000000";
+ DIN_i.data_write <= '1';
+ DIN_i.data_finished <= '0';
+ DIN_i.busy_release <= '1';
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "10000000001000000111000000000001";
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000000";
+ --wait for 20 ns;
+ DIN_i.data <= "10000000000000000010000000000010";
+ --wait for 20 ns;
+ --DIN_i <= "00000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000011000000000011";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000100000000000100";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000001000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000010000000000010";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000011000000000011";
+ wait for 20 ns;
+ DIN_i.data <= "00000000000000000000000000000000";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000100000000000100";
+ wait for 20 ns;
+ end process;
+
+
+end Behavioral;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05.01.2017 14:31:03
+-- Design Name:
+-- Module Name: sim_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sim_tb is
+end sim_tb;
+
+architecture Behavioral of sim_tb is
+signal CLK ,Flag_Lim, Flag_LUT: std_logic := '0';
+signal DIN_i, DOUT_i : READOUT_TX;
+signal DIN_out_end: std_logic_vector(31 downto 0) := (others => '0');
+signal Fine, Delta, min_Cal : std_logic_vector(9 downto 0);
+signal DIN_out_Lim, DIN_out_LUT : std_logic_vector(31 downto 0);
+signal cal_cntread_compare_old : unsigned(19 downto 0);
+signal min_curr_dbg, max_curr_dbg, min_next_dbg, max_next_dbg : std_logic_vector(9 downto 0);
+signal read_next_dbg,write_next_dbg,Default_val_dbg,write_curr_dbg : std_logic;
+signal FPGA_dbg : std_logic_vector(3 downto 0);
+signal wrt_cal_cnt_dbg,write_dflt_cnt_dbg : std_logic;
+signal cal_cnt : unsigned(19 downto 0);
+--signal cal_cng_dbg, Dflt_cnt_dbg : std_logic;
+
+constant CLK_PERIOD : time := 20 ns;
+
+signal BUS_RX : CTRLBUS_RX;
+
+begin
+--Input : entity work.input_env
+-- port map(
+-- CLK => CLK,
+-- DOUT => DIN_i
+-- );
+
+ Calibration : entity work.Calibration
+ port map(
+ CLK => CLK,
+ DIN => DIN_i,
+ DOUT => DOUT_i,
+ BUS_RX => BUS_RX,
+ BUS_TX => open
+ --Temp => temp,
+-- Fine => Fine,
+-- Delta => Delta,
+-- Min_Cal => min_Cal,
+-- Flag_Lim => Flag_Lim,
+-- Flag_LUT => Flag_LUT,
+-- DIN_out_Lim => DIN_out_Lim,
+-- DIN_out_LUT => DIN_out_LUT,
+-- cal_cnt_dbug => cal_cnt,
+-- min_next_dbg => min_next_dbg,
+-- max_next_dbg => max_next_dbg,
+-- min_curr_dbg => min_curr_dbg,
+-- max_curr_dbg => max_curr_dbg,
+-- --cal_cng_dbg => cal_cng_dbg,
+-- read_next_dbg => read_next_dbg,
+-- write_next_dbg => write_next_dbg,
+-- FPGA_dbg => FPGA_dbg,
+-- DIN_out_end => DIN_out_end,
+-- --Dflt_cnt_dbg => Dflt_cnt_dbg,
+-- Default_val_dbg => Default_val_dbg,
+-- write_curr_dbg => write_curr_dbg,
+-- wrt_cal_cnt_dbg => wrt_cal_cnt_dbg,
+-- write_dflt_cnt_dbg => write_dflt_cnt_dbg
+ );
+
+ write : entity work.file_output
+ port map(
+ CLK => CLK,
+ x1 => DIN_out_end,
+ x2 => DOUT_i.data
+ );
+
+
+ CLK_PROC : process is
+ begin
+ CLK <= '1';
+ wait for CLK_PERIOD / 2;
+ CLK <= '0';
+ wait for CLK_PERIOD / 2;
+ end process;
+
+
+ proc_Cal : process is
+ begin
+ wait for 5 ns;
+ DIN_i.statusbits <= "00000000000000000000000000000001";
+ DIN_i.data <= "00000000000000000000000000000001";
+ DIN_i.data_write <= '1';
+ DIN_i.data_finished <= '0';
+ DIN_i.busy_release <= '1';
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000100001000000000000"; --33
+ --wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000100111000000000001"; --39
+ --wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ wait for 20 ns;
+ DIN_i.data <= "10000000000001000010000000000010"; --66
+ --wait for 20 ns;
+ --DIN_i <= "00000000000000000000000000000000";
+ --wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ wait for 20 ns;
+ DIN_i.data <= "10000001100000000011000000000011"; --3
+ wait for 20 ns;
+
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000000001000001100000000000001"; --70
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000000100000000000100";--4
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ --DIN_i.data <= "10000000000111000000000000000000";
+ --wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000000001000000000001";--1
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000000010000000000010";--2
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001101000001010000000000011";--3
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000001010000000000100";--4
+ wait for 20 ns;
+ DIN_i.data <= "10000001100000001110000000000101";--5
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000000000000000110000000000110";--6
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000000111000000000111";--7
+ wait for 20 ns;
+ DIN_i.data <= "10000000000000001000000000000111";--8
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000001001000000000111";--9
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000000000000001010000000000111";--10
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000001011000000000111";--11
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000001";
+ --wait for 20 ns;
+ DIN_i.data <= "10000000000000001100000000000111";--12
+ wait for 20 ns;
+ --DIN_i.data <= "00000000000000000000000000000010";
+ --wait for 20 ns;
+ DIN_i.data <= "10000001100000001101000000000111";--13
+ wait for 20 ns;
+ end process;
+
+
+end Behavioral;
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--TDC settings
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 13; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
+ --ring buffer size: 32,64,96,128,dyn
+ constant TDC_DATA_FORMAT : integer := 0;
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F3CF";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"62";
+
+
+--set to 0 for backplane serdes, set to 3 for front SFP serdes
+ constant SERDES_NUM : integer := 3;
+
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 40;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 44;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"54", x"72", x"62", x"33", x"73", x"63", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ x"85",x"0a",
+ x"86",x"0a",
+ x"87",x"0a",
+ others => x"00");
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"95000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+ t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+config_compile_gsi.pl
\ No newline at end of file
--- /dev/null
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN1156C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3sc_tdctemplate"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -force_gsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3sc_tdctemplate.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
+add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
+add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
+
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+#TDC
+add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+
+
+add_file -vhdl -lib work "./trb3sc_tdctemplate.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+add_file -vhdl -lib work "../code/tdc_calib/Calibration.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/Cal_Limits.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/cnt_val.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/default_val.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/file_output.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/input_env.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/LUT.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/Memory.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/read_cnt.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/read_Memory.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/txt_util.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/compare_old.vhd"
+add_file -vhdl -lib work "../code/tdc_calib/Calc_output.vhd"
+
+
+
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.version.all;
+use work.config.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.tdc_components.all;
+use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.trb_net_gbe_components.all;
+use work.med_sync_define.all;
+
+entity trb3sc_tdctemplate is
+ port(
+ CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
+ CLK_CORE_PCLK : in std_logic; --Main Oscillator
+ CLK_EXT_PLL_LEFT : in std_logic; --External Clock
+ --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
+ --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
+ --CLK_CORE_PLL_LEFT : in std_logic; --not used
+ --CLK_CORE_PLL_RIGHT : in std_logic; --not used
+ --CLK_EXT_PCLK : in std_logic; --not used
+ --CLK_EXT_PLL_RIGHT : in std_logic; --not used
+
+ TRIG_LEFT : in std_logic; --Trigger Input
+ --TRIG_PLL : in std_logic; --not used
+ --TRIG_RIGHT : in std_logic; --not used
+
+ --Backplane, all lines
+ BACK_GPIO : inout std_logic_vector(15 downto 0);
+ BACK_LVDS : inout std_logic_vector(1 downto 0);
+ BACK_3V3 : inout std_logic_vector(3 downto 0);
+ --Backplane for slaves on trbv3scbp1
+-- BACK_GPIO : inout std_logic_vector(3 downto 0);
+
+ --AddOn Connector
+ --to be added
+
+ --KEL Connector
+ KEL : in std_logic_vector(40 downto 1);
+
+ --Additional IO
+ HDR_IO : inout std_logic_vector(10 downto 1);
+ RJ_IO : inout std_logic_vector(3 downto 0);
+ SPARE_IN : in std_logic_vector(1 downto 0);
+
+ --LED
+ LED_GREEN : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);
+ LED_RJ_RED : out std_logic_vector(1 downto 0);
+ LED_WHITE : out std_logic_vector(1 downto 0);
+ LED_SFP_GREEN : out std_logic_vector(1 downto 0);
+ LED_SFP_RED : out std_logic_vector(1 downto 0);
+
+ --SFP
+ SFP_LOS : in std_logic_vector(1 downto 0);
+ SFP_MOD0 : in std_logic_vector(1 downto 0);
+ SFP_MOD1 : inout std_logic_vector(1 downto 0) := (others => 'Z');
+ SFP_MOD2 : inout std_logic_vector(1 downto 0) := (others => 'Z');
+ SFP_TX_DIS : out std_logic_vector(1 downto 0) := (others => '0');
+
+ --Serdes switch
+ PCSSW_ENSMB : out std_logic;
+ PCSSW_EQ : out std_logic_vector(3 downto 0);
+ PCSSW_PE : out std_logic_vector(3 downto 0);
+ PCSSW : out std_logic_vector(7 downto 0);
+
+ --ADC
+ ADC_CLK : out std_logic;
+ ADC_CS : out std_logic;
+ ADC_DIN : out std_logic;
+ ADC_DOUT : in std_logic;
+
+ --Flash, 1-wire, Reload
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_IN : out std_logic;
+ FLASH_OUT : in std_logic;
+ PROGRAMN : out std_logic;
+ ENPIRION_CLOCK : out std_logic;
+ TEMPSENS : inout std_logic;
+
+ --Test Connectors
+ TEST_LINE : out std_logic_vector(15 downto 0)
+ );
+
+
+ attribute syn_useioff : boolean;
+ attribute syn_useioff of FLASH_CLK : signal is true;
+ attribute syn_useioff of FLASH_CS : signal is true;
+ attribute syn_useioff of FLASH_IN : signal is true;
+ attribute syn_useioff of FLASH_OUT : signal is true;
+ attribute syn_useioff of KEL : signal is false;
+
+ --Serdes: Backplane
+ --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane
+ --AddOn C2,C3,C0,C1,B0,B1,B2,D1(B3) Slave --,--,5,9,8,7,6,--
+ --SFP D0,B3(D1) D0: GbE, B3: TrbNet
+
+
+end entity;
+
+architecture trb3sc_arch of trb3sc_tdctemplate is
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+
+ signal time_counter : unsigned(31 downto 0) := (others => '0');
+ signal led : std_logic_vector(1 downto 0);
+ signal debug_clock_reset : std_logic_vector(31 downto 0);
+
+ --Media Interface
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+
+ --READOUT
+ signal readout_rx : READOUT_RX;
+ signal readout_tx_a : readout_tx_array_t(0 to 0);
+ signal tdc_cal_in : READOUT_TX;--READOUT_TX;
+
+ signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, bustdc_rx, buscalib_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, bustdc_tx, buscalib_tx, bus_master_in : CTRLBUS_TX;
+
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+
+ signal sed_error_i : std_logic;
+ signal bus_master_active : std_logic;
+
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
+
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+ signal trig_gen_out_i : std_logic_vector(3 downto 0);
+
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;
+ --TDC
+ signal hit_in_i : std_logic_vector(64 downto 1);
+ signal logic_analyser_i : std_logic_vector(15 downto 0);
+
+
+
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ attribute syn_keep of bussci_rx : signal is true;
+ attribute syn_preserve of bussci_rx : signal is true;
+ attribute syn_keep of bustools_rx : signal is true;
+ attribute syn_preserve of bustools_rx : signal is true;
+ attribute syn_keep of bustc_rx : signal is true;
+ attribute syn_preserve of bustc_rx : signal is true;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset Handling
+---------------------------------------------------------------------------
+ THE_CLOCK_RESET : entity work.clock_reset_handler
+ port map(
+ INT_CLK_IN => CLK_CORE_PCLK,
+ EXT_CLK_IN => CLK_EXT_PLL_LEFT,
+ NET_CLK_FULL_IN => med2int(0).clk_full,
+ NET_CLK_HALF_IN => med2int(0).clk_half,
+ RESET_FROM_NET => med2int(0).stat_op(13),
+
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+
+ FULL_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ REF_CLK_OUT => clk_full_osc,
+
+ ENPIRION_CLOCK => ENPIRION_CLOCK,
+ LED_RED_OUT => LED_RJ_RED,
+ LED_GREEN_OUT => LED_RJ_GREEN,
+ DEBUG_OUT => debug_clock_reset
+ );
+
+ pll_calibration : entity work.pll_in125_out33
+ port map (
+ CLK => CLK_SUPPL_PCLK,
+ CLKOP => clk_cal,
+ LOCK => open);
+
+-- GSR_N <= reset_i;
+
+---------------------------------------------------------------------------
+-- TrbNet Uplink
+---------------------------------------------------------------------------
+
+ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+ generic map(
+ SERDES_NUM => SERDES_NUM,
+ IS_SYNC_SLAVE => c_YES
+ )
+ port map(
+ CLK_REF_FULL => med2int(0).clk_full,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => sfp_prsnt_i,
+ SD_LOS_IN => sfp_los_i,
+ SD_TXDIS_OUT => sfp_txdis_i,
+ --Control Interface
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
+ -- Status and control port
+ STAT_DEBUG => med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+
+ SFP_TX_DIS(0) <= '1';
+ gen_sfp_con : if SERDES_NUM = 3 generate
+ sfp_los_i <= SFP_LOS(1);
+ sfp_prsnt_i <= SFP_MOD0(1);
+ SFP_TX_DIS(1) <= sfp_txdis_i;
+ end generate;
+ gen_bpl_con : if SERDES_NUM = 0 generate
+ sfp_los_i <= BACK_GPIO(1);
+ sfp_prsnt_i <= BACK_GPIO(1);
+ BACK_GPIO(0) <= sfp_txdis_i;
+ end generate;
+
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
+ generic map (
+ ADDRESS_MASK => x"FFFF",
+ BROADCAST_BITMASK => x"FF",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ TIMING_TRIGGER_RAW => c_YES,
+ --Configure data handler
+ DATA_INTERFACE_NUMBER => 1,
+ DATA_BUFFER_DEPTH => 10,
+ DATA_BUFFER_WIDTH => 32,
+ DATA_BUFFER_FULL_THRESH => 2**9+2,
+ TRG_RELEASE_AFTER_DATA => c_YES,
+ HEADER_BUFFER_DEPTH => 9,
+ HEADER_BUFFER_FULL_THRESH => 2**8
+ )
+
+ port map(
+ -- Misc
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
+
+ --Timing trigger in
+ TRG_TIMING_TRG_RECEIVED_IN => TRIG_LEFT,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx_a,
+
+ --Slow Control Port
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ ONEWIRE_INOUT => TEMPSENS,
+ --Timing registers
+ TIMERS_OUT => timer
+ );
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 5,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", 4 => x"e000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 12, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => bustdc_rx, --TDC config
+ BUS_RX(4) => buscalib_rx, --TDC Calibration
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => bustdc_tx,
+ BUS_TX(4) => buscalib_tx,
+
+ STAT_DEBUG => open
+ );
+
+
+
+---------------------------------------------------------------------------
+-- Control Tools
+---------------------------------------------------------------------------
+ THE_TOOLS : entity work.trb3sc_tools
+ port map(
+ CLK => clk_sys,
+ RESET => reset_i,
+
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_OUT,
+ FLASH_OUT => FLASH_IN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ --Header
+ HEADER_IO => HDR_IO,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ --ADC
+ ADC_CS => ADC_CS,
+ ADC_MOSI => ADC_DIN,
+ ADC_MISO => ADC_DOUT,
+ ADC_CLK => ADC_CLK,
+ --Trigger & Monitor
+ MONITOR_INPUTS(39 downto 0) => KEL(40 downto 1),
+ MONITOR_INPUTS(43 downto 40) => trig_gen_out_i,
+ TRIG_GEN_INPUTS => KEL(40 downto 1),
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+---------------------------------------------------------------------------
+-- Switches
+---------------------------------------------------------------------------
+--Serdes Select
+ PCSSW_ENSMB <= '0';
+ PCSSW_EQ <= x"0";
+ PCSSW_PE <= x"F";
+ PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
+
+---------------------------------------------------------------------------
+-- I/O
+---------------------------------------------------------------------------
+
+ RJ_IO(1 downto 0) <= "00";
+ RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);
+
+
+ BACK_GPIO(1 downto 0) <= (others => 'Z');
+ BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2);
+ BACK_GPIO(15 downto 4) <= (others => 'Z');
+
+ BACK_LVDS <= (others => '0');
+ BACK_3V3 <= (others => 'Z');
+
+
+---------------------------------------------------------------------------
+-- LCD Data to display
+---------------------------------------------------------------------------
+ lcd_data(15 downto 0) <= timer.network_address;
+ lcd_data(47 downto 16) <= timer.microsecond;
+ lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32));
+ lcd_data(95 downto 80) <= med2int(0).data;
+ lcd_data(111 downto 96) <= int2med(0).data;
+ lcd_data(115 downto 112) <= med2int(0).packet_num & med2int(0).dataready;
+ lcd_data(119 downto 116) <= int2med(0).packet_num & int2med(0).dataready;
+ lcd_data(511 downto 120) <= (others => '0');
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+ --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
+ LED_GREEN <= debug_clock_reset(0);
+ LED_ORANGE <= debug_clock_reset(1);
+ LED_RED <= not sed_error_i;
+ LED_YELLOW <= debug_clock_reset(2);
+ LED_WHITE(0) <= time_counter(26) and time_counter(19);
+ LED_WHITE(1) <= time_counter(20);
+ LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1'; --SFP Link Status
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) & '1'; --SFP RX/TX
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+ process
+ begin
+ wait until rising_edge(clk_sys);
+ time_counter <= time_counter + 1;
+ if reset_i = '1' then
+ time_counter <= (others => '0');
+ end if;
+ end process;
+
+
+--TEST_LINE <= med2int(0).dataready & int2med(0).dataready & med2int(0).data(6 downto 0) & int2med(0).data(6 downto 0);
+TEST_LINE <= med_stat_debug(15 downto 0);
+
+-------------------------------------------------------------------------------
+-- TDC
+-------------------------------------------------------------------------------
+ THE_TDC : TDC_record
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => clk_full_osc,
+ CLK_READOUT => clk_sys, -- Clock for the readout
+ REFERENCE_TIME => TRIG_LEFT, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+ -- Trigger signals from handler
+ BUSRDO_RX => readout_rx,
+ BUSRDO_TX => readout_tx_a(0),--tdc_cal_in,--readout_tx(0),
+ -- Slow control bus
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx,
+ -- Dubug signals
+ INFO_IN => timer,
+ LOGIC_ANALYSER_OUT => logic_analyser_i
+ );
+
+ -- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i(40 downto 1) <= KEL(40 downto 1);
+ end generate;
+
+ -- For ToT Measurements
+ gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+ Gen_Hit_In_Signals : for i in 1 to 20 generate
+ hit_in_i(i*2-1) <= KEL(i);
+ hit_in_i(i*2) <= not KEL(i);
+ end generate Gen_Hit_In_Signals;
+ end generate;
+
+
+ -------------------------------------------------------------------------------
+ --TDC Calibration
+ -------------------------------------------------------------------------------
+
+-- THE_TDC_Calibration : entity work.Calibration
+-- port map (
+-- CLK => clk_sys,
+-- DIN => tdc_cal_in,
+-- DOUT => readout_tx_a(0),
+-- BUS_RX => buscalib_rx,
+-- BUS_TX => buscalib_tx
+-- -- Debugging
+-- --Fine : out std_logic_vector(9 downto 0);
+-- --Delta : out std_logic_vector(9 downto 0);
+-- --Min_cal : out std_logic_vector(9 downto 0);
+-- --Flag_Lim : out std_logic;
+-- --Flag_LUT : out std_logic;
+-- --DIN_out_Lim : out std_logic_vector(31 downto 0);
+-- --DIN_out_LUT : out std_logic_vector(31 downto 0);
+-- --cal_cnt_dbug : out unsigned(7 downto 0);
+-- --min_next_dbg : out std_logic_vector(9 downto 0);
+-- --max_next_dbg : out std_logic_vector(9 downto 0);
+-- --min_curr_dbg : out std_logic_vector(9 downto 0);
+-- --max_curr_dbg : out std_logic_vector(9 downto 0);
+-- --cal_cng_dbg : out std_logic;
+-- --read_next_dbg : out std_logic;
+-- --write_next_dbg : out std_logic;
+-- --FPGA_dbg : out std_logic_vector(3 downto 0);
+-- --DIN_out_end : out std_logic_vector(31 downto 0);
+-- --Dflt_cnt_dbg : out std_logic;
+-- --Default_val_dbg : out std_logic;
+-- --write_curr_dbg : out std_logic
+-- );
+
+
+
+end architecture;
+
+
+
jspc29 / trb3sc.git / commitdiff