--- /dev/null
+SODA_SOURCE (0xF355)
+++++++++++++++++++++
+WRITE_REG:
+
+BE00 soda_cmd_word_S
+BE01 LEDregister_i
+
+READ_REG:
+
+BE00 soda_cmd_word_S
+BE01 super_burst_nr_S
+BE02 calib_register_S
+BE03 CTRL_STATUS_register_i
+
+control(read & write):
+CTRL_STATUS_register_i[3..0] : LEDs
+CTRL_STATUS_register_i[8] : dead_channel
+CTRL_STATUS_register_i[15] : reset errors
+status(read-only):
+CTRL_STATUS_register_i[17] : timeout-error
+CTRL_STATUS_register_i[18] : downstream-error
+CTRL_STATUS_register_i[31] : report error
+
+
+SODA_CLIENT (0xF356)
+++++++++++++++++++++
+WRITE_REG:
+
+BE00 LEDregister_i
+
+READ_REG:
+
+BE00 soda_cmd_word_S
+BE01 super_burst_nr_S
+BE02 LEDregister_i
+BE03 Debug_status
+BE04 Debug_RX_count
+BE05 Debug_TX_count
+BE06 Debug_SOS_count
+BE07 Debug_CMD_count
+
+
+
+
+DEBUG_STATUS(31) <= send_link_reset_i when rising_edge(SYSCLK);
+DEBUG_STATUS(30) <= '0';
+DEBUG_STATUS(29) <= internal_make_link_reset_out when rising_edge(SYSCLK);
+DEBUG_STATUS(28) <= '0';
+DEBUG_STATUS(27) <= '0';
+DEBUG_STATUS(26) <= rx_allow;
+DEBUG_STATUS(25) <= tx_allow;
+DEBUG_STATUS(24:20) <= (others => '0');
+DEBUG_STATUS(19:16) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
+DEBUG_STATUS(15:3) <= (others => '0');
+DEBUG_STATUS(2) <= CLK_EN;
+DEBUG_STATUS(1) <= CLEAR;
+DEBUG_STATUS(0) <= RESET;
+
+
+
+
SCI_ACK : out std_logic := '0';
SCI_NACK : out std_logic := '0';
-- Status and control port
--- STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
--- CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
+ STAT_OP : out t_HUB_WORD; --std_logic_vector (15 downto 0);
+ CTRL_OP : in t_HUB_WORD; --std_logic_vector (15 downto 0) := (others => '0');
STAT_DEBUG : out std_logic_vector (63 downto 0);
CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
);
<BaliProject version="3.2" title="ctsc" device="LFE3-150EA-8FN672C" default_implementation="ctsc">
<Options/>
<Implementation title="ctsc" dir="ctsc" description="ctsc" synthesis="synplify" default_strategy="Strategy1">
- <Options top="Cu_trb3_periph_soda_client"/>
+ <Options def_top="Cu_trb3_periph_soda_client" top="Cu_trb3_periph_soda_client"/>
<Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
- <Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
- <Options/>
- </Source>
</Implementation>
<Strategy name="Strategy1" file="soda_client1.sty"/>
</BaliProject>
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-12-03">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2015-01-08">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2064047666" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2085654093" Name="trb3_periph_sodaclient_LA0" ID="0">
<Setting>
<Clock SampleClk="rx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
</Bus>
<Sig Type="SIG" Name="clk_100_osc"/>
<Sig Type="SIG" Name="rx_half_clk"/>
+ <Bus Name="the_sync_link/sci_state">
+ <Sig Type="SIG" Name="the_sync_link/sci_state:0"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_state:1"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_state:2"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_state:3"/>
+ </Bus>
+ <Bus Name="the_sync_link/wa_position">
+ <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
+ </Bus>
+ <Bus Name="the_sync_link/sci_addr_i">
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:0"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:1"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:2"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:3"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:4"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:5"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:6"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:7"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_addr_i:8"/>
+ </Bus>
+ <Bus Name="the_sync_link/sci_data_in_i">
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:0"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:1"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:2"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:3"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:4"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:5"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:6"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:7"/>
+ </Bus>
+ <Bus Name="the_sync_link/sci_data_out_i">
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:0"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:1"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:2"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:3"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:4"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:5"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:6"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:7"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/sci_read_i"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_write_i"/>
+ <Bus Name="the_sync_link/sci_ch_i">
+ <Sig Type="SIG" Name="the_sync_link/sci_ch_i:0"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_ch_i:1"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_ch_i:2"/>
+ <Sig Type="SIG" Name="the_sync_link/sci_ch_i:3"/>
+ </Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/soda_cmd_valid_s,"/>
<TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
<TU Serialbits="0" Type="0" ID="4" Sig="general_reset_i,"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/sci_state[3:0],"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.0" title="soda_hub" device="LFE3-150EA-8FN672C" default_implementation="soda_hub">
+<BaliProject version="3.2" title="soda_hub" device="LFE3-150EA-8FN672C" default_implementation="soda_hub">
<Options>
<Option name="HDL type" value="VHDL"/>
</Options>
-rvl_alias "rxup_full_clk" "the_hub_sync_uplink/rx_full_clk_out";
-RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk";
-RVL_ALIAS "clk_raw_internal" "the_hub_sync_downlink/oscclk";
-RVL_ALIAS "reveal_ist_577" "the_hub_sync_downlink/the_serdes/rx_full_clk_ch0";
+rvl_alias "rxup_full_clk" "rxup_full_clk";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
+BLOCK JTAGPATHS ;
#################################################################
# Basic Settings
#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
+# SYSCONFIG MCCLK_FREQ = 2.5;
# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
#################################################################
# Clock I/O
#################################################################
-#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-#LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";s
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-#LOCATE COMP "CLK_GPLL_LEFT" SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
+#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
+#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
+#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
+#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
+DEFINE PORT GROUP "CLK_group" "*CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
#################################################################
# To central FPGA
#################################################################
-#LOCATE COMP "FPGA5_COMM_0" SITE "AD4";
-#LOCATE COMP "FPGA5_COMM_1" SITE "AE3";
-#LOCATE COMP "FPGA5_COMM_2" SITE "AA7";
-#LOCATE COMP "FPGA5_COMM_3" SITE "AB7";
-#LOCATE COMP "FPGA5_COMM_4" SITE "AD3";
-#LOCATE COMP "FPGA5_COMM_5" SITE "AC4";
-#LOCATE COMP "FPGA5_COMM_6" SITE "AE2";
-#LOCATE COMP "FPGA5_COMM_7" SITE "AF3";
-#LOCATE COMP "FPGA5_COMM_8" SITE "AE4";
-#LOCATE COMP "FPGA5_COMM_9" SITE "AF4";
-#LOCATE COMP "FPGA5_COMM_10" SITE "V10";
-#LOCATE COMP "FPGA5_COMM_11" SITE "W10";
-#DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
#terminated differential pair to pads
LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25;
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
#################################################################
# LED
#################################################################
#################################################################
LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber !
-#REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ; No longer present in copper
-#LOCATE UGROUP "THE_SYNC_LINK/media_uplink_group" REGION "UPLINK_REGION" ;
+
MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only
#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-#USE SECONDARY NET "THE_SYNC_LINK/sci_read_i" ;
-#USE SECONDARY NET "THE_SYNC_LINK/sci_write_i" ;
-#USE PRIMARY NET "THE_HUB_SYNC_DOWNLINK/soda_rxdn_clock_full[1]" ;
-USE PRIMARY NET "clk_raw_internal_c" ;
-USE PRIMARY NET "clk_soda_i" ;
-USE PRIMARY NET "clk_sys_internal_c" ;
MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
+
+## IOBUF ALLPORTS ;
+USE PRIMARY NET "clk_200_osc" ;
+USE PRIMARY NET "clk_100_osc" ;
+USE PRIMARY NET "rxup_full_clk" ;
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
+FREQUENCY NET "rxup_full_clk" 100.000000 MHz ;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-08-27">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2015-01-07">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2050424539" Name="trb3_periph_sodahub_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2085538867" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
<Clock SampleClk="rxup_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="64"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
<Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:3"/>
</Bus>
<Sig Type="SIG" Name="a_soda_hub/\channel(0)\/packet_builder/start_of_superburst"/>
+ <Bus Name="the_hub_sync_downlink/rx_allow_q">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_allow_q:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_allow_q">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_allow_q:3"/>
+ </Bus>
<Bus Name="a_soda_hub/\channel(0)\/packet_builder/super_burst_nr_in">
<Sig Type="SIG" Name="a_soda_hub/\channel(0)\/packet_builder/super_burst_nr_in:0"/>
<Sig Type="SIG" Name="a_soda_hub/\channel(0)\/packet_builder/super_burst_nr_in:1"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_half_clk_out"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_half_clk_out"/>
+ <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/rx_k">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/rx_dlm">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/rx_dlm_word[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_k">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_dlm">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_dlm_word[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:7"/>
+ </Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
-<ispXCF version="3.1.0">
+<ispXCF version="3.3.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140827.bit</File>
- <FileTime>08/27/14 15:46:45</FileTime>
- <JedecChecksum>N/A</JedecChecksum>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20150107.bit</File>
+ <FileTime>01/07/15 13:15:28</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140827.bit</File>
- <FileTime>08/27/14 15:00:59</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20150108.bit</File>
+ <FileTime>01/07/15 16:18:12</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140827.bit</File>
- <FileTime>08/27/14 09:49:24</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20141126.bit</File>
+ <FileTime>11/25/14 14:12:00</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
jspc29 / soda.git / commitdiff