16 & trg. counter mismatch & The internal trigger number does not match the received trigger number. Set by trigger interface or user. \\
17 & timing trg missing & A LVL1 trigger has been received which needs a timing trigger, but no timing trigger was seen. Set by trigger interface or user. \\
18 & multiple timing trg & There were two signals on the timing input but only one LVL1 trigger \\
-19 & t.b.d. & Not yet defined \\
+19 & severe front-end error & The front-end shows a severe error that requires external aid \\
20 & buffers half full & The event data buffers are filled halfway. Set by user. \\
21 & buffers almost full & The event data buffers are almost full. Set by user. \\
22 & not configured & Frontend is not configured correctly to handle triggers, an initilization is needed. Set by user. \\
-23 & frontend error & Parts of the connected frontend are not behaving correctly: no response, not synchronized, token missing...\\
+23 & frontend error & Parts of the connected frontend are not behaving correctly: no response, not synchronized, token missing... The error is either not permanent or can be handled internally\\
24 & spike detected & A spike was detected on the timing trigger input. \\
25 & trigger timeout & The delay between timing trigger and LVL1 trigger was longer than expected \\
26 - 31 & t.b.d. & Not yet defined \\
Words & 0x0B & Bit 23 -- 0: Number of words given to data handler & 1\\
Invalid Trg. & 0x0C & Bit 15 -- 0: Number of invalid triggers received & 1 \\
Multiple Trg. & 0x0D & Bit 15 -- 0: Number of multiple triggers received & 1 \\
-Spikes Trg. & 0x0E & Bit 15 -- 0: Number of spikes on CMS received & 1 \\
+Spikes Trg. & 0x0E & Bit 15 -- 0: Number of spikes on CMS (synchronous) received & 1 \\
Spurious Trg. & 0x0F & Bit 15 -- 0: Number of spurious triggers received & 1 \\
Idle Time & 0x10 & Bit 23 -- 0: Idle time of the trigger handler state machine in ${{\mu}s}$ & \\
Init Time & 0x11 & Bit 23 -- 0: Time the OEP spent for reinitalizations in ${{\mu}s}$ & \\
Calib Time & 0x12 & Bit 23 -- 0: Time the OEP spent with calibration in ${{\mu}s}$ & \\
Readout Time & 0x13 & Bit 23 -- 0: Time while reading data from TDC in ${{\mu}s}$ & \\
Waiting Time & 0x14 & Bit 23 -- 0: Time spent with various small waits in ${{\mu}s}$ & \\
+Real Spikes CMS & 0x15 & Bit 23 -- 0: Number of spikes on CMS (asynchrous) & \\
Dummy Word & 0x1E & Dummy data word. Sent in every event when selected by CCR2 Bit 22 (see table \ref{MDCCommonCtrlReg2}). Bit 23 -- 16: Lower 8 bit of trigger number. Bit 11 -- 0: Word counter & \\
Debug Word & 0x1F & Debug word. Sent in every event when selected by CCR2 Bit 30 (see table \ref{MDCCommonCtrlReg2}). Bit 15 -- 0: Trigger number & \\
\hline
\begin{table}
\begin{center}
-\begin{tabular}{|c|c|}
+\begin{tabularx}{\textwidth}{cXcccc}
\hline
-\textbf{Bits} & \textbf{Description} \\
+\textbf{Bits} & \textbf{Description} & \textbf{EP} & \textbf{EPF} & \textbf{U} & \textbf{RST} \\
\hline\hline
-31 -- 20 & temperature \\
-19 -- 16 & reserved \\
-15 & Link error (e.g. code violation) \\
-14 & Single Event Upset detected \\
-13 & Timing Trigger Input \\
-12 & Last event sent on IPU is broken\\
-11 & Severe problem in event data buffer / IPU request handler\\
-10 & IPU requested event partially not found / data missing\\
-9 & IPU Event not found\\
-8 & Timing trigger missing\\
-7 & Frontend error\\
-6 & Frontend not configured\\
-5 & IPU channel counter mismatch \\
-4 & LVL1 trigger counter mismatch \\
-3 & note flag\\
-2 & warning flag \\
-1 & error flag \\
-0 & serious error flag \\
+31 -- 20 & temperature & & & & \\
+19 -- 16 & reserved & & & & \\
+15 & Link error (e.g. code violation) & X & - & - & 4 \\
+14 & Single Event Upset detected & o & & & \\
+13 & Timing Trigger Input & X & - & - & n/a \\
+12 & Last event sent on IPU is broken & o & & & \\
+11 & Severe problem in event data buffer / IPU request handler & o & X & X & 4 \\
+10 & IPU requested event partially not found / data missing & o & X & X & 4 \\
+9 & IPU Event not found & o & X & X & 4 \\
+8 & Timing trigger missing & X & - & - & 4 \\
+7 & Frontend error & o & o & X & \\
+6 & Frontend not configured & o & X & X & n/a \\
+5 & IPU channel counter mismatch & o & o & o & \\
+4 & LVL1 trigger counter mismatch & X & - & - & n/a \\
+3 & note flag & o & o & X & n/a \\
+2 & warning flag & o & o & X & n/a \\
+1 & error flag & o & o & X & n/a \\
+0 & serious error flag & o & o & X & n/a \\
\hline
-\end{tabular}
-\caption{Common Status Register 0 (CSR0)}
+\end{tabularx}
+\caption{Common Status Register 0 (CSR0). X: entity changes value, -: entity not allowed to change, o:entity may change but doesn't. EP: Endpoint, EPF: Endpoint full handler, U: User, RST: reset signal}
\label{CommonStatReg0}
\end{center}
\end{table}
13 & multiple timing triggers found \\
12 & trigger number match \\
11 & timeout found \\
-10 -- 4 & reserved \\
+10 -- 8 & reserved \\
+7 & wrong polarity \\
+6 & spurious trigger\\
+5 & missing trigger\\
+4 & short timing trigger\\
3 -- 0 & Status of LVL1 handler state machine. 0: idle, 1: timing trigger found, 3: LVL1 trigger received, 5: bad combination of timing trigger and LVL1 trigger, 7: done.\\
\hline
\end{tabularx}
\textbf{Bits} & \textbf{Description} \\
\hline\hline
31 -- 16 & Number of spurious triggers (i.e. timing triggers preceeding a timing triggerless trigger) \\
-15 -- 0 & Number of spikes seen on the timing trigger input \\
+15 -- 0 & Number of spikes seen on the timing trigger input (sampled with system clock) \\
\hline
\end{tabularx}
\caption{Common Status Register 7 (CSR7): LVL1 handler statistics 2}
\end{center}
\end{table}
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Bits} & \textbf{Description} \\
+\hline\hline
+31 -- 16 & reserved \\
+15 -- 0 & Number of spikes seen on the timing trigger input using asynchronous circuitry\\
+\hline
+\end{tabularx}
+\caption{Common Status Register 8 (CSR8): LVL1 handler statistics 3}
+\label{CommonStatReg8}
+\end{center}
+\end{table}
+
\begin{table}
\begin{center}
jspc29 / daqdocu.git / commitdiff
