Removed the CompileVersion field in favor of a larger ImplementedFeatures list generic

diff --git a/trb_net16_endpoint_hades_cts.vhd b/trb_net16_endpoint_hades_cts.vhd
index b464e95890d7084165f8f744890dd01a163eaf9b..b7890dfb4936dd02e252a4fa7ad0f8641db5e0b8 100644 (file)
--- a/trb_net16_endpoint_hades_cts.vhd
+++ b/trb_net16_endpoint_hades_cts.vhd
@@ -34,7 +34,7 @@ entity trb_net16_endpoint_hades_cts is
     REGIO_INIT_BOARD_INFO    : std_logic_vector(31 downto 0) := x"0000_0000";
     REGIO_INIT_ENDPOINT_ID   : std_logic_vector(15 downto 0) := x"0001";
     REGIO_COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
+    REGIO_INCLUDED_FEATURES  : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"50000000";
     REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
@@ -640,7 +640,7 @@ begin
       INIT_BOARD_INFO    => REGIO_INIT_BOARD_INFO,
       INIT_UNIQUE_ID     => REGIO_INIT_UNIQUE_ID,
       COMPILE_TIME       => REGIO_COMPILE_TIME,
-      COMPILE_VERSION    => REGIO_COMPILE_VERSION,
+      INCLUDED_FEATURES  => REGIO_INCLUDED_FEATURES,
       HARDWARE_VERSION   => REGIO_HARDWARE_VERSION,
       CLOCK_FREQ         => CLOCK_FREQUENCY
       )
@@ -781,4 +781,4 @@ begin
 
   STAT_DEBUG_1 <= (others => '0');
 
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd
index ba5d9c0b6e8f05935fa49cbb5db4d434b13542be..1576456ebed6b7a5658b04f77772184a9854e15e 100644 (file)
--- a/trb_net16_endpoint_hades_full.vhd
+++ b/trb_net16_endpoint_hades_full.vhd
@@ -43,7 +43,7 @@ entity trb_net16_endpoint_hades_full is
     REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
     REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(63 downto 0) := (others => '0');
+    REGIO_INCLUDED_FEATURES      : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
@@ -578,7 +578,7 @@ begin
               INIT_UNIQUE_ID     => REGIO_INIT_UNIQUE_ID,
               INIT_ENDPOINT_ID   => REGIO_INIT_ENDPOINT_ID,
               COMPILE_TIME       => REGIO_COMPILE_TIME,
-              COMPILE_VERSION    => REGIO_COMPILE_VERSION,
+              INCLUDED_FEATURES  => REGIO_INCLUDED_FEATURES,
               HARDWARE_VERSION   => REGIO_HARDWARE_VERSION,
               CLOCK_FREQ         => CLOCK_FREQUENCY
               )

diff --git a/trb_net16_endpoint_sctrl.vhd b/trb_net16_endpoint_sctrl.vhd
index cf987c573be8e182012a02e17ee15eabb191de76..56a2a186d04ae324600010edde3dd79c352861e8 100644 (file)
--- a/trb_net16_endpoint_sctrl.vhd
+++ b/trb_net16_endpoint_sctrl.vhd
@@ -34,7 +34,7 @@ entity trb_net16_endpoint_sctrl is
     REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
     REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_COMPILE_VERSION        : std_logic_vector(63 downto 0) := (others => '0');
+    REGIO_INCLUDED_FEATURES      : std_logic_vector(63 downto 0) := (others => '0');
     REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
@@ -569,7 +569,7 @@ begin
               INIT_UNIQUE_ID     => REGIO_INIT_UNIQUE_ID,
               INIT_ENDPOINT_ID   => REGIO_INIT_ENDPOINT_ID,
               COMPILE_TIME       => REGIO_COMPILE_TIME,
-              COMPILE_VERSION    => REGIO_COMPILE_VERSION,
+              INCLUDED_FEATURES  => REGIO_INCLUDED_FEATURES,
               HARDWARE_VERSION   => REGIO_HARDWARE_VERSION,
               CLOCK_FREQ         => CLOCK_FREQUENCY
               )

diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd
index df6aa64824c6756eb90369d4e1cdc3f157390431..bfb7f4734c7d1a1d78f22b9e1a6dc865b97d67d2 100644 (file)
--- a/trb_net16_hub_base.vhd
+++ b/trb_net16_hub_base.vhd
@@ -28,7 +28,7 @@ entity trb_net16_hub_base is
                                          x"00000000_00000000_00007077_00000000" &
                                          x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
@@ -1052,7 +1052,7 @@ end generate;
       INIT_UNIQUE_ID     => INIT_UNIQUE_ID,
       INIT_ENDPOINT_ID   => INIT_ENDPOINT_ID,
       COMPILE_TIME       => COMPILE_TIME,
-      COMPILE_VERSION    => COMPILE_VERSION,
+      INCLUDED_FEATURES  => INCLUDED_FEATURES,
       HARDWARE_VERSION   => HARDWARE_VERSION,
       CLOCK_FREQ         => CLOCK_FREQUENCY
       )

diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd
index 37cf57be35382d892197333ff18628d386476d95..12ee9a8f7f98bd59e6d75cc56f440c275cff19f1 100644 (file)
--- a/trb_net16_hub_func.vhd
+++ b/trb_net16_hub_func.vhd
@@ -101,7 +101,7 @@ package trb_net16_hub_func is
                                          x"00000000_00000000_000050FF_00000000" &
                                          x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0)  := x"0001";
     USE_VAR_ENDPOINT_ID     : integer range c_NO to c_YES := c_NO;
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
@@ -206,7 +206,7 @@ component trb_net16_hub_streaming_port is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -602,7 +602,7 @@ component trb_net16_hub_streaming_port_sctrl is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -712,7 +712,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F3C0";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"9000CE00";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0005";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";

diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd
index 073aab08e3d9bd7f401ddd373028a1a923a8fc37..e76593b5583f3e04d1c786b5953aa74e03e2d1d2 100644 (file)
--- a/trb_net16_hub_streaming_port.vhd
+++ b/trb_net16_hub_streaming_port.vhd
@@ -22,7 +22,7 @@ entity trb_net16_hub_streaming_port is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -230,7 +230,7 @@ begin
       INIT_ADDRESS               => INIT_ADDRESS,
       INIT_UNIQUE_ID             => INIT_UNIQUE_ID,
       COMPILE_TIME               => COMPILE_TIME,
-      COMPILE_VERSION            => COMPILE_VERSION,
+      INCLUDED_FEATURES          => INCLUDED_FEATURES,
       HARDWARE_VERSION           => HARDWARE_VERSION,
       HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK,
       CLOCK_FREQUENCY            => CLOCK_FREQUENCY,

diff --git a/trb_net16_hub_streaming_port_sctrl.vhd b/trb_net16_hub_streaming_port_sctrl.vhd
index 2b272884a3b8f687af3f395bf444b7ab361e47b8..3d77640d831501f31448cb98af6db46c1b3c4c37 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl.vhd
+++ b/trb_net16_hub_streaming_port_sctrl.vhd
@@ -35,7 +35,7 @@ entity trb_net16_hub_streaming_port_sctrl is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F004";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"12345678";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0001";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -264,7 +264,7 @@ begin
       INIT_ADDRESS               => INIT_ADDRESS,
       INIT_UNIQUE_ID             => INIT_UNIQUE_ID,
       COMPILE_TIME               => COMPILE_TIME,
-      COMPILE_VERSION            => COMPILE_VERSION,
+      INCLUDED_FEATURES          => INCLUDED_FEATURES,
       HARDWARE_VERSION           => HARDWARE_VERSION,
       HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK,
       CLOCK_FREQUENCY            => CLOCK_FREQUENCY,

diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd
index 3620663de20f7e38cd52aa451b9478cf349acbdf..4b537ff8198fc7dc2ff8eed54505e5b2a9921224 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_cts.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd
@@ -51,7 +51,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is
     INIT_ADDRESS            : std_logic_vector(15 downto 0) := x"F3C0";
     INIT_UNIQUE_ID          : std_logic_vector(63 downto 0) := (others => '0');
     COMPILE_TIME            : std_logic_vector(31 downto 0) := x"00000000";
-    COMPILE_VERSION         : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES       : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION        : std_logic_vector(31 downto 0) := x"9000CE00";
     INIT_ENDPOINT_ID        : std_logic_vector(15 downto 0) := x"0005";
     BROADCAST_BITMASK       : std_logic_vector(7 downto 0)  := x"7E";
@@ -426,7 +426,7 @@ begin
       INIT_UNIQUE_ID             => INIT_UNIQUE_ID,
       INIT_CTRL_REGS             => INIT_CTRL_REGS,
       COMPILE_TIME               => COMPILE_TIME,
-      COMPILE_VERSION            => COMPILE_VERSION,
+      INCLUDED_FEATURES          => INCLUDED_FEATURES,
       HARDWARE_VERSION           => HARDWARE_VERSION,
       HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK,
       CLOCK_FREQUENCY            => CLOCK_FREQUENCY,

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 779375bd26d44a97721a05eddaf748e38f909d96..0777d40b38f683ade66bacb27ecb387dc6c8f660 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -20,13 +20,13 @@ entity trb_net16_regIO is
     USED_CTRL_REGS     : std_logic_vector(2**(4)-1 downto 0)   := (others => '1');
     --set to 0 for each unused bit in a register
     USED_CTRL_BITMASK  : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
-    USE_DAT_PORT        : integer range 0 to 1 := c_YES;  --internal data port
-    INIT_ADDRESS     : std_logic_vector(15 downto 0) := x"FFFF";
-    INIT_UNIQUE_ID   : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-    INIT_BOARD_INFO  : std_logic_vector(31 downto 0) := x"1111_2222";
-    INIT_ENDPOINT_ID : std_logic_vector(15 downto 0)  := x"0001";
+    USE_DAT_PORT       : integer range 0 to 1 := c_YES;  --internal data port
+    INIT_ADDRESS       : std_logic_vector(15 downto 0) := x"FFFF";
+    INIT_UNIQUE_ID     : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
+    INIT_BOARD_INFO    : std_logic_vector(31 downto 0) := x"1111_2222";
+    INIT_ENDPOINT_ID   : std_logic_vector(15 downto 0)  := x"0001";
     COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";  --not used any more!
-    COMPILE_VERSION    : std_logic_vector(63 downto 0) := (others => '0');
+    INCLUDED_FEATURES  : std_logic_vector(63 downto 0) := (others => '0');
     HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
     CLOCK_FREQ         : integer range 1 to 200 := 100 --MHz
     );
@@ -931,12 +931,12 @@ begin
     generic map(
       INIT0 => COMPILE_TIME_LIB(15 downto 0),
       INIT1 => COMPILE_TIME_LIB(31 downto 16),
-      INIT2 => COMPILE_VERSION(15 downto 0),
-      INIT3 => COMPILE_VERSION(31 downto 16),
+      INIT2 => INCLUDED_FEATURES(15 downto 0),
+      INIT3 => INCLUDED_FEATURES(31 downto 16),
       INIT4 => HARDWARE_VERSION(15 downto 0),
       INIT5 => HARDWARE_VERSION(31 downto 16),
-      INIT6 => COMPILE_VERSION(47 downto 32),
-      INIT7 => COMPILE_VERSION(63 downto 48)
+      INIT6 => INCLUDED_FEATURES(47 downto 32),
+      INIT7 => INCLUDED_FEATURES(63 downto 48)
       )
     port map(
       CLK     => CLK,

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index 60d623aa536c1df2b59e0512d0ed63e45206e028..b9089c91d160c8c1bbf73ce29c9e6b87620c234d 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -506,6 +506,24 @@ package trb_net_components is
       DEBUG_OUT      : out std_logic_vector (31 downto 0)\r
       );\r
   end component;\r
+  \r
+  \r
+component bus_register_handler is\r
+  generic (\r
+    BUS_LENGTH : integer range 0 to 64 := 2);\r
+  port (\r
+    RESET            : in  std_logic;\r
+    CLK              : in  std_logic;\r
+--\r
+    DATA_IN          : in  std_logic_vector_array_32(0 to BUS_LENGTH);\r
+    READ_EN_IN       : in  std_logic;\r
+    WRITE_EN_IN      : in  std_logic;\r
+    ADDR_IN          : in  std_logic_vector(6 downto 0);\r
+    DATA_OUT         : out std_logic_vector(31 downto 0);\r
+    DATAREADY_OUT    : out std_logic;\r
+    UNKNOWN_ADDR_OUT : out std_logic\r
+    );\r
+end component;  \r
 \r
   component trb_net_CRC is\r
     port(\r
@@ -615,7 +633,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)          := x"1111_2222";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)          := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)          := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)          := (others => '0');\r
+      REGIO_INCLUDED_FEATURES   : std_logic_vector(63 downto 0)          := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)          := x"12345678";\r
       REGIO_USE_1WIRE_INTERFACE : integer                                := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES            := c_NO;\r
@@ -746,7 +764,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)      := x"1111_2222";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)      := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)      := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)      := (others => '0');\r
+      REGIO_INCLUDED_FEATURES   : std_logic_vector(63 downto 0)      := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)      := x"12345678";\r
       REGIO_USE_1WIRE_INTERFACE : integer                            := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES        := c_NO;\r
@@ -886,7 +904,7 @@ package trb_net_components is
       REGIO_INIT_BOARD_INFO     : std_logic_vector(31 downto 0)          := x"0000_0000";\r
       REGIO_INIT_ENDPOINT_ID    : std_logic_vector(15 downto 0)          := x"0001";\r
       REGIO_COMPILE_TIME        : std_logic_vector(31 downto 0)          := x"00000000";\r
-      REGIO_COMPILE_VERSION     : std_logic_vector(63 downto 0)          := (others => '0');\r
+      REGIO_INCLUDED_FEATURES   : std_logic_vector(63 downto 0)          := (others => '0');\r
       REGIO_HARDWARE_VERSION    : std_logic_vector(31 downto 0)          := x"50000000";\r
       REGIO_USE_1WIRE_INTERFACE : integer                                := c_YES;  --c_YES,c_NO,c_MONITOR\r
       REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES            := c_NO;\r
@@ -2554,7 +2572,7 @@ package trb_net_components is
       INIT_BOARD_INFO   : std_logic_vector(31 downto 0)          := x"1111_2222";\r
       INIT_ENDPOINT_ID  : std_logic_vector(15 downto 0)          := x"0001";\r
       COMPILE_TIME      : std_logic_vector(31 downto 0)          := x"00000000";\r
-      COMPILE_VERSION   : std_logic_vector(63 downto 0)          := (others => '0');\r
+      INCLUDED_FEATURES : std_logic_vector(63 downto 0)          := (others => '0');\r
       HARDWARE_VERSION  : std_logic_vector(31 downto 0)          := x"12345678";\r
       CLOCK_FREQ        : integer range 1 to 200                 := 100  --MHz\r
       );\r

diff --git a/trb_net_std.vhd b/trb_net_std.vhd
index 58921a9569255745037111da739626c6dbc97f2f..df73da50310f4df8fb5090f44e02f07168880531 100644 (file)
--- a/trb_net_std.vhd
+++ b/trb_net_std.vhd
@@ -149,6 +149,12 @@ package trb_net_std is
   --constant VERSION_NUMBER_TIME  : std_logic_vector(31 downto 0)   := conv_std_logic_vector(1234567890,32);
 
 
+  type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0);
+  type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0);
+  type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0);
+  type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0);
+  type std_logic_vector_array_8  is array (integer range <>) of std_logic_vector(7 downto 0);
+
 
 
 --function declarations