CTS: Upgrade to TDCv1.5

diff --git a/cts/tdc_release b/cts/tdc_release
index 5ecb3546789253f8697c776d4e41466a410da4f0..660503024f2a9a147b987afcc6738cad83f6b500 120000 (symlink)
--- a/cts/tdc_release
+++ b/cts/tdc_release
@@ -1 +1 @@
-../tdc_releases/tdc_v1.4
\ No newline at end of file
+../tdc_releases/tdc_v1.5
\ No newline at end of file

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index e9dd156818daf9e1b162f8838a52664b043d3e5b..c5e3d44321708e8a6449784fa8352e6bf1a87a0d 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -233,6 +233,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd"
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../base/cores/pll_in125_out20.vhd"
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
 add_file -vhdl -lib work "source/cts_pkg.vhd"
 add_file -vhdl -lib work "source/cts_fifo.vhd"

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index d63380871e7e9cb3d6a2a5c92c4ea9f8717225ea..3effa893210e767927829d4c2a07da6dee709698 100644 (file)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -172,6 +172,8 @@ architecture trb3_central_arch of trb3_central is
 
   signal clk_100_i   : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
   signal clk_200_i   : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+  signal clk_125_i   : std_logic; --125 MHz, via Clock Manager and bypassed PLL
+  signal clk_20_i    : std_logic; --clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL
   signal pll_lock    : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
   signal clear_i     : std_logic;
   signal reset_i     : std_logic;
@@ -587,6 +589,15 @@ THE_MAIN_PLL : pll_in200_out100
     LOCK   => pll_lock
     );
 
+-- generates hits for calibration uncorrelated with tdc clk
+THE_CALIBRATION_PLL : pll_in125_out20
+       port map (
+               CLK   => CLK_GPLL_RIGHT,
+               CLKOP => clk_20_i,
+               CLKOK => clk_125_i,
+               LOCK  => open);
+
+  
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (SFP)
@@ -894,7 +905,7 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard
   port map( 
          CLK                         => clk_100_i,
          TEST_CLK                    => '0',
-         CLK_125_IN                  => CLK_GPLL_RIGHT,
+         CLK_125_IN                  => clk_125_i,
          RESET                       => reset_i,
          GSR_N                       => gsr_n,
          --Debug
@@ -1237,6 +1248,7 @@ gen_TDC : if INCLUDE_TDC = c_YES generate
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => cts_trigger_out,  -- Reference time input
       HIT_IN                => trigger_in_buf_i,  -- Channel start signals
+      HIT_CALIBRATION       => clk_20_i,    -- Hits for calibrating the TDC
       TRG_WIN_PRE           => tdc_ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => tdc_ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --