TX_CD_OUT : out std_logic;\r
-- DLM stuff\r
DLM_DATA_IN : in std_logic_vector(7 downto 0);\r
- DLM_INJECT_IN : in std_logic\r
+ DLM_INJECT_IN : in std_logic;\r
+ --\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
);\r
end entity inserter;\r
\r
\r
signal inject_k : std_logic;\r
signal inject_d : std_logic;\r
- \r
- signal phy_cd_q : std_logic;\r
- signal phy_k_q : std_logic;\r
- signal phy_d_q : std_logic_vector(7 downto 0);\r
+\r
+ -- 9 = CD, 8 = K, 7..0 = D\r
+ signal delay_qqq : std_logic_vector(9 downto 0);\r
+ signal delay_qq : std_logic_vector(9 downto 0);\r
+ signal delay_q : std_logic_vector(9 downto 0);\r
\r
signal idle_x : std_logic;\r
signal idle_int : std_logic;\r
signal drop_req_x : std_logic;\r
\r
signal ins_cnt : unsigned(2 downto 0);\r
-\r
+ \r
begin\r
\r
+ DEBUG_OUT(0) <= drop_req_x;\r
+ DEBUG_OUT(1) <= idle_int;\r
+ DEBUG_OUT(2) <= fifo_wr_x;\r
+ DEBUG_OUT(3) <= fifo_rd_x;\r
+ DEBUG_OUT(4) <= fifo_empty_x;\r
+ DEBUG_OUT(5) <= remove_x;\r
+ DEBUG_OUT(6) <= remove_int;\r
+ DEBUG_OUT(7) <= inject_k;\r
+ DEBUG_OUT(8) <= inject_d;\r
+ \r
+ DEBUG_OUT(15 downto 9) <= (others => '0');\r
+\r
-- Syncing and delaying signals for /IT recognition\r
THE_SYNC_PROC: process( CLK )\r
begin\r
if( rising_edge(CLK) ) then\r
- phy_d_q <= PHY_D_IN;\r
- phy_k_q <= PHY_K_IN;\r
- phy_cd_q <= PHY_CD_IN;\r
+ -- third stage\r
+ delay_qqq <= delay_qq;\r
+ -- second stage\r
+ delay_qq <= delay_q;\r
+ -- first stage\r
+ delay_q(7 downto 0) <= PHY_D_IN;\r
+ delay_q(8) <= PHY_K_IN;\r
+ delay_q(9) <= PHY_CD_IN;\r
+ -- sync\r
idle_int <= idle_x;\r
remove_int <= remove_x;\r
end if;\r
end process THE_SYNC_PROC;\r
\r
- -- we have an /I/ candidate for dropping\r
- idle_x <= '1' when ((phy_d_q = x"bc") and (phy_k_q = '1') and (phy_cd_q = '0') and\r
- (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) \r
+ -- we have an /I/ candidate for dropping (in the input and first stage)\r
+ idle_x <= '1' when ((delay_q(7 downto 0) = x"bc") and (delay_q(8) = '1') and (delay_q(9) = '0') and\r
+ (PHY_D_IN = x"50") and (PHY_K_IN = '0') and (PHY_CD_IN = '0')) \r
else '0';\r
\r
-- insert counter\r
if( rising_edge(CLK) ) then\r
if ( RESET = '1' ) then\r
ins_cnt <= (others => '0');\r
- elsif( (DLM_INJECT_IN = '1') and (remove_x = '0') ) then\r
+ elsif( (DLM_INJECT_IN = '1') and (remove_x = '0') ) then -- maybe inject_d ?\r
ins_cnt <= ins_cnt + 1;\r
- elsif( (DLM_INJECT_IN = '0') and (remove_x = '1') ) then\r
+ elsif( (DLM_INJECT_IN = '0') and (remove_x = '1') ) then -- maybe inject_d ?\r
ins_cnt <= ins_cnt - 1;\r
end if;\r
end if;\r
-- FIFO\r
THE_FIFO: fifo_inserter\r
port map(\r
- DATA(9) => phy_cd_q,\r
- DATA(8) => phy_k_q,\r
- DATA(7 downto 0) => phy_d_q,\r
- CLOCK => CLK,\r
- WREN => fifo_wr_x,\r
- RDEN => fifo_rd_x,\r
- RESET => RESET,\r
- Q(9) => tx_cd_int,\r
- Q(8) => tx_k_int,\r
- Q(7 downto 0) => tx_d_int, \r
- EMPTY => open,\r
- FULL => open,\r
- ALMOSTEMPTY => fifo_empty_x\r
+ DATA => delay_qqq,\r
+ CLOCK => CLK,\r
+ WREN => fifo_wr_x,\r
+ RDEN => fifo_rd_x,\r
+ RESET => RESET,\r
+ Q(9) => tx_cd_int,\r
+ Q(8) => tx_k_int,\r
+ Q(7 downto 0) => tx_d_int, \r
+ EMPTY => open,\r
+ FULL => open,\r
+ ALMOSTEMPTY => fifo_empty_x\r
);\r
\r
--\r
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-
-entity remover is
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- -- SerDes output
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+\r
+entity remover is\r
+ port(\r
+ CLK : in std_logic;\r
+ RESET : in std_logic;\r
+ -- SerDes output\r
RX_D_IN : in std_logic_vector(7 downto 0);\r
- RX_K_IN : in std_logic;
+ RX_K_IN : in std_logic;\r
-- PHY input\r
- PHY_D_OUT : out std_logic_vector(7 downto 0);
+ PHY_D_OUT : out std_logic_vector(7 downto 0);\r
PHY_K_OUT : out std_logic;\r
-- DLM stuff\r
DLM_DATA_OUT : out std_logic_vector(7 downto 0);\r
- DLM_FOUND_OUT : out std_logic
- );
-end entity remover;
-
-architecture remover_arch of remover is
-
--- Components
- component fifo_remover
- port(
- DATA : in std_logic_vector(8 downto 0);
- CLOCK : in std_logic;
- WREN : in std_logic;
- RDEN : in std_logic;
- RESET : in std_logic;
- WCNT : out std_logic_vector(4 downto 0);
- Q : out std_logic_vector(8 downto 0);
+ DLM_FOUND_OUT : out std_logic;\r
+ --\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity remover;\r
+\r
+architecture remover_arch of remover is\r
+\r
+-- Components\r
+ component fifo_remover\r
+ port(\r
+ DATA : in std_logic_vector(8 downto 0);\r
+ CLOCK : in std_logic;\r
+ WREN : in std_logic;\r
+ RDEN : in std_logic;\r
+ RESET : in std_logic;\r
+ Q : out std_logic_vector(8 downto 0);\r
+ WCNT : out std_logic_vector(4 downto 0);\r
+ EMPTY : out std_logic;\r
FULL : out std_logic;\r
ALMOSTFULL : out std_logic\r
- );
- end component fifo_remover;
-
--- state machine signals
- type state_t is (FILL, IDLE, ONE, TWO, THREE);
- signal STATE, NEXT_STATE : state_t;
-
--- Signals
- signal dlm_found_x : std_logic;
- signal dlm_found : std_logic;
+ );\r
+ end component fifo_remover;\r
+\r
+-- state machine signals\r
+ type state_t is (FILL, IDLE, ONE, TWO, THREE);\r
+ signal STATE, NEXT_STATE : state_t;\r
+\r
+-- Signals\r
+ signal dlm_found_x : std_logic;\r
+ signal dlm_found : std_logic;\r
signal fifo_wr_x : std_logic;\r
signal fifofull : std_logic;\r
- signal phy_k_fifo : std_logic;
- signal phy_d_fifo : std_logic_vector(7 downto 0);
+ signal fifoempty : std_logic;\r
+ signal phy_k_fifo : std_logic;\r
+ signal phy_d_fifo : std_logic_vector(7 downto 0);\r
signal fifo_rd_x : std_logic;\r
- signal replace_k_x : std_logic;
- signal replace_k : std_logic;
- signal replace_d_x : std_logic;
- signal replace_d : std_logic;
+ signal replace_k_x : std_logic;\r
+ signal replace_k : std_logic;\r
+ signal replace_d_x : std_logic;\r
+ signal replace_d : std_logic;\r
signal dlm_data_int : std_logic_vector(7 downto 0);\r
-
-begin
+\r
+begin\r
+\r
+ DEBUG_OUT(0) <= dlm_found;\r
+ DEBUG_OUT(1) <= fifo_wr_x;\r
+ DEBUG_OUT(2) <= replace_k;\r
+ DEBUG_OUT(3) <= replace_d;\r
+ DEBUG_OUT(4) <= fifofull;\r
+ DEBUG_OUT(5) <= fifoempty;\r
+ DEBUG_OUT(15 downto 6) <= (others => '0');\r
\r
-- DLM komma detected in data stream\r
dlm_found_x <= '1' when ((RX_K_IN = '1') and (RX_D_IN = x"dc")) else '0';\r
DLM_DATA_OUT <= dlm_data_int;\r
\r
-- write signal for FIFO\r
- fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1';
+ fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1';\r
\r
-- FIFO\r
THE_FIFO: fifo_remover\r
- port map(
+ port map(\r
DATA(8) => RX_K_IN,\r
DATA(7 downto 0) => RX_D_IN,\r
CLOCK => CLK,\r
- WREN => fifo_wr_x,
- RDEN => fifo_rd_x,
- RESET => RESET,
- Q(8) => phy_k_fifo,
+ WREN => fifo_wr_x,\r
+ RDEN => fifo_rd_x,\r
+ RESET => RESET,\r
+ Q(8) => phy_k_fifo,\r
Q(7 downto 0) => phy_d_fifo,\r
- WCNT => open,
+ WCNT => open,\r
+ EMPTY => fifoempty,\r
FULL => open,\r
- ALMOSTFULL => fifofull
- );
+ ALMOSTFULL => fifofull\r
+ );\r
\r
-- read signal for FIFO\r
fifo_rd_x <= '0' when (STATE = FILL) or\r
PHY_K_OUT <= '1' when (replace_k = '1') else\r
'0' when (replace_d = '1') else\r
phy_k_fifo;\r
-
- -- data to PHY, multiplexed
+\r
+ -- data to PHY, multiplexed\r
PHY_D_OUT <= x"bc" when (replace_k = '1') else\r
x"50" when (replace_d = '1') else\r
- phy_d_fifo;
-\r
- -----------------------------------------------------------
- -- statemachine: clocked process
- -----------------------------------------------------------
- THE_FSM: process( CLK )
- begin
- if( rising_edge(CLK) ) then
- if( RESET = '1' ) then
+ phy_d_fifo;\r
+\r
+ -----------------------------------------------------------\r
+ -- statemachine: clocked process\r
+ -----------------------------------------------------------\r
+ THE_FSM: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( RESET = '1' ) then\r
STATE <= FILL;\r
replace_k <= '0';\r
- replace_d <= '0';
- else
- STATE <= NEXT_STATE;
- replace_k <= replace_k_x;
- replace_d <= replace_d_x;
- end if;
- end if;
- end process THE_FSM;
-
+ replace_d <= '0';\r
+ else\r
+ STATE <= NEXT_STATE;\r
+ replace_k <= replace_k_x;\r
+ replace_d <= replace_d_x;\r
+ end if;\r
+ end if;\r
+ end process THE_FSM;\r
+\r
+ -----------------------------------------------------------\r
+ -- staemachine: transitions\r
-----------------------------------------------------------\r
- -- staemachine: transitions
- -----------------------------------------------------------
- THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull )
+ THE_STATE_TRANSITIONS: process( STATE, RX_D_IN, RX_K_IN, phy_k_fifo, phy_d_fifo, fifofull )\r
begin\r
replace_k_x <= '0';\r
replace_d_x <= '0';\r
-
+\r
case STATE is\r
when FILL =>\r
if( (RX_K_IN = '1') and (RX_D_IN = x"bc") and (fifofull = '1') ) then\r
end if;\r
\r
when ONE =>\r
- if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then
+ if( (phy_k_fifo = '0') and (phy_d_fifo = x"50")) then\r
NEXT_STATE <= TWO;\r
- replace_k_x <= '1';
- else
- NEXT_STATE <= IDLE;
- end if;
+ replace_k_x <= '1';\r
+ else\r
+ NEXT_STATE <= IDLE;\r
+ end if;\r
\r
when TWO =>\r
NEXT_STATE <= THREE;\r
when THREE =>\r
if( fifofull = '0' ) then\r
NEXT_STATE <= TWO;\r
- replace_k_x <= '1';
+ replace_k_x <= '1';\r
else\r
NEXT_STATE <= IDLE;\r
end if;\r
-
- when others =>
- NEXT_STATE <= IDLE;
- end case;
- end process THE_STATE_TRANSITIONS;
-
-end architecture;
+\r
+ when others =>\r
+ NEXT_STATE <= IDLE;\r
+ end case;\r
+ end process THE_STATE_TRANSITIONS;\r
+\r
+end architecture;\r
signal rx_bsm : std_logic_vector(3 downto 0);
+ signal remover_dbg : std_logic_vector(15 downto 0);
+ signal inserter_dbg : std_logic_vector(15 downto 0);
+
-- -- just a check to see if something goes wrong....
-- attribute HGROUP : string;
-- attribute HGROUP of gbe_med_fifo_arch : architecture is "media_interface_group";
D_OUT(1) => rx_serdes_rst_q
);
+-- -- RX PATH
-- -- "Good" debugging pins
+-- debug(7 downto 0) <= sd_rx_data_src;
+-- debug(15 downto 8) <= sd_rx_data_dst;
+-- debug(16) <= sd_rx_kcntl_src(0);
+-- debug(17) <= sd_rx_kcntl_dst(0);
+-- debug(18) <= sd_rx_disp_error(0);
+-- debug(19) <= sd_rx_cv_error(0);
+-- -- "Bad" debugging pins
+-- debug(20) <= remover_dbg(0);
+-- debug(21) <= remover_dbg(1);
+-- debug(22) <= remover_dbg(2);
+-- debug(23) <= remover_dbg(3);
+-- debug(24) <= remover_dbg(4);
+-- debug(25) <= remover_dbg(5);
+-- debug(26) <= pcs_rx_en;
+-- debug(27) <= pcs_rx_er;
+-- debug(28) <= mac_rx_wr;
+-- debug(29) <= mac_rx_eof;
+-- debug(30) <= mac_rx_err;
+-- debug(31) <= '0';
+-- debug(32) <= sd_rx_clk;
+-- debug(33) <= CLK_125;
+
+ -- TX PATH
+ -- "Good" debugging pins
debug(7 downto 0) <= sd_tx_data_src;
debug(15 downto 8) <= sd_tx_data_dst;
debug(16) <= sd_tx_kcntl_src(0);
debug(18) <= sd_tx_correct_disp_src(0);
debug(19) <= sd_tx_correct_disp_dst(0);
-- "Bad" debugging pins
- debug(20) <= DLM_INJECT_IN;
- debug(21) <= '0';
- debug(22) <= '0';
- debug(23) <= '0';
- debug(24) <= '0';
- debug(25) <= '0';
- debug(26) <= '0';
- debug(27) <= '0';
- debug(28) <= '0';
- debug(29) <= '0';
+ debug(20) <= inserter_dbg(0);
+ debug(21) <= inserter_dbg(1);
+ debug(22) <= inserter_dbg(2);
+ debug(23) <= inserter_dbg(3);
+ debug(24) <= inserter_dbg(4);
+ debug(25) <= inserter_dbg(5);
+ debug(26) <= inserter_dbg(6);
+ debug(27) <= inserter_dbg(7);
+ debug(28) <= inserter_dbg(8);
+ debug(29) <= pcs_tx_en;
debug(30) <= '0';
debug(31) <= '0';
debug(32) <= sd_rx_clk;
TX_CD_OUT => sd_tx_correct_disp_dst(0),
-- DLM stuff
DLM_DATA_IN => DLM_DATA_IN,
- DLM_INJECT_IN => DLM_INJECT_IN
+ DLM_INJECT_IN => DLM_INJECT_IN,
+ --
+ DEBUG_OUT => inserter_dbg
);
THE_EVE: entity remover
PHY_K_OUT => sd_rx_kcntl_dst(0),
-- DLM stuff
DLM_DATA_OUT => DLM_DATA_OUT,
- DLM_FOUND_OUT => DLM_FOUND_OUT
+ DLM_FOUND_OUT => DLM_FOUND_OUT,
+ --
+ DEBUG_OUT => remover_dbg
);
------------------------------------------------------------
------------------------------------------------------------
jspc29 / trbnet.git / commitdiff