cleanups

diff --git a/gbe_trb/base/gather_ports.vhd b/gbe_trb/base/gather_ports.vhd
index 9ee21b736afc550d18d414c180c6992bb54c4f27..478cc9d258c87296fab5d9997f00b01614b9ce50 100644 (file)
--- a/gbe_trb/base/gather_ports.vhd
+++ b/gbe_trb/base/gather_ports.vhd
@@ -13,6 +13,7 @@ entity gather_ports is
     FRAME_REQ_OUT       : out std_logic_vector(15 downto 0);\r
     FRAME_ACK_IN        : in  std_logic_vector(15 downto 0) := (others => '0');\r
     PORT_SELECT_OUT     : out std_logic_vector(15 downto 0);\r
+    PORT_MUX_OUT        : out std_logic_vector(3 downto 0);\r
     CYCLE_DONE_OUT      : out std_logic;\r
     --\r
     DEBUG               : out std_logic_vector(15 downto 0)\r
@@ -36,6 +37,9 @@ architecture gather_ports_arch of gather_ports is
   signal select_ports           : std_logic_vector(15 downto 0);\r
   signal req_ports              : std_logic_vector(15 downto 0);\r
 \r
+  signal next_mux_x             : std_logic_vector(3 downto 0);\r
+  signal mux_ports              : std_logic_vector(3 downto 0);\r
+\r
 begin\r
 \r
   -- we need to start a gather cycle if any src port has frames available\r
@@ -65,8 +69,10 @@ begin
     if( rising_edge(CLK) ) then\r
       if( RESET = '1' ) then\r
         select_ports <= (others => '0');\r
+        mux_ports    <= (others => '0');\r
       else\r
         select_ports <= next_port_x;\r
+        mux_ports    <= next_mux_x;\r
       end if;\r
     end if;\r
   end process THE_SELECT_PORT_PROC;\r
@@ -85,38 +91,55 @@ begin
   begin\r
     if   ( stored_ports(0) = '1' ) then\r
       next_port_x <= x"0001";\r
+      next_mux_x  <= x"0";\r
     elsif( stored_ports(1) = '1' ) then\r
       next_port_x <= x"0002";\r
+      next_mux_x  <= x"1";\r
     elsif( stored_ports(2) = '1' ) then\r
       next_port_x <= x"0004";\r
+      next_mux_x  <= x"2";\r
     elsif( stored_ports(3) = '1' ) then\r
       next_port_x <= x"0008";\r
+      next_mux_x  <= x"3";\r
     elsif( stored_ports(4) = '1' ) then\r
       next_port_x <= x"0010";\r
+      next_mux_x  <= x"4";\r
     elsif( stored_ports(5) = '1' ) then\r
       next_port_x <= x"0020";\r
+      next_mux_x  <= x"5";\r
     elsif( stored_ports(6) = '1' ) then\r
       next_port_x <= x"0040";\r
+      next_mux_x  <= x"6";\r
     elsif( stored_ports(7) = '1' ) then\r
       next_port_x <= x"0080";\r
+      next_mux_x  <= x"7";\r
     elsif( stored_ports(8) = '1' ) then\r
       next_port_x <= x"0100";\r
+      next_mux_x  <= x"8";\r
     elsif( stored_ports(9) = '1' ) then\r
       next_port_x <= x"0200";\r
+      next_mux_x  <= x"9";\r
     elsif( stored_ports(10) = '1' ) then\r
       next_port_x <= x"0400";\r
+      next_mux_x  <= x"a";\r
     elsif( stored_ports(11) = '1' ) then\r
       next_port_x <= x"0800";\r
+      next_mux_x  <= x"b";\r
     elsif( stored_ports(12) = '1' ) then\r
       next_port_x <= x"1000";\r
+      next_mux_x  <= x"c";\r
     elsif( stored_ports(13) = '1' ) then\r
       next_port_x <= x"2000";\r
+      next_mux_x  <= x"d";\r
     elsif( stored_ports(14) = '1' ) then\r
       next_port_x <= x"4000";\r
+      next_mux_x  <= x"e";\r
     elsif( stored_ports(15) = '1' ) then\r
       next_port_x <= x"8000";\r
+      next_mux_x  <= x"f";\r
     else\r
       next_port_x <= x"0000";\r
+      next_mux_x  <= x"0";\r
     end if;\r
   end process THE_NEXT_PORT_PROC;\r
 \r

diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd
index 13375d8985e7dbfb6c6fe036055bcdee8e44e46d..4e74f0a6e55ec099306c3596eef450ed5d585ca5 100644 (file)
--- a/gbe_trb/base/gbe_wrapper_fifo.vhd
+++ b/gbe_trb/base/gbe_wrapper_fifo.vhd
@@ -79,10 +79,10 @@ entity gbe_wrapper_fifo is
     -- IP configuration       
     BUS_IP_RX                 : in  CTRLBUS_RX;
     BUS_IP_TX                 : out CTRLBUS_TX;
-    -- Registers config       
+    -- Registers config
     BUS_REG_RX                : in  CTRLBUS_RX;
     BUS_REG_TX                : out CTRLBUS_TX;
-    -- Forwarder              
+    -- Forwarder
     FWD_DST_MAC_IN            : in  std_logic_vector(47 downto 0) := (others => '0');
     FWD_DST_IP_IN             : in  std_logic_vector(31 downto 0) := (others => '0');
     FWD_DST_UDP_IN            : in  std_logic_vector(15 downto 0) := (others => '0');
@@ -273,17 +273,16 @@ begin
     MAC_READY_CONF_IN        => LINK_ACTIVE_IN,
     MAC_RECONF_OUT           => open,
     MAC_AN_READY_IN          => PCS_AN_READY_IN,
-----    
-    MAC_RX_DATA_IN           => MAC_RX_DATA_IN, --FIFO_DATA_IN(7 downto 0),
-    MAC_RX_WRITE_IN          => MAC_RX_WRITE_IN, --rx_fifo_wr,
-    MAC_RX_EOF_IN            => MAC_RX_EOF_IN, --FIFO_DATA_IN(8),
-    MAC_RX_ERROR_IN          => MAC_RX_ERROR_IN, --'0',
-----
+    -- MAC RX stuff    
+    MAC_RX_DATA_IN           => MAC_RX_DATA_IN,
+    MAC_RX_WRITE_IN          => MAC_RX_WRITE_IN,
+    MAC_RX_EOF_IN            => MAC_RX_EOF_IN,
+    MAC_RX_ERROR_IN          => MAC_RX_ERROR_IN,
     -- FIFO TX stuff
     FT_TX_DATA_OUT           => ft_tx_data,
     FT_TX_WR_OUT             => ft_tx_wr,
     FT_TX_FIFOFULL_IN        => ft_tx_fifofull,
-----
+    --
     CTS_NUMBER_IN            => mlt_cts_number,
     CTS_CODE_IN              => mlt_cts_code,
     CTS_INFORMATION_IN       => mlt_cts_information,