\r
-COMMERCIAL ;\r
-BLOCK RESETPATHS ;\r
-BLOCK ASYNCPATHS ;\r
\r
-#########################################\r
-# Constraints\r
-#########################################\r
- IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
-\r
- FREQUENCY PORT CLK_F1_TO_F2_P 100.000000 MHz ;\r
- FREQUENCY PORT CLK_F2_TO_F1_P 100.000000 MHz ;\r
-\r
- LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_1/THE_SERDES/PCSC_INST" SITE "LLPCS" ;\r
- LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_2/THE_SERDES/PCSC_INST" SITE "LRPCS" ;\r
- LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_3/THE_SERDES/PCSC_INST" SITE "URPCS" ;\r
- LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_4/THE_SERDES/PCSC_INST" SITE "ULPCS" ;\r
+IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;\r
\r
#########################################\r
# Clock & Reset\r
#########################################\r
- LOCATE COMP "CLK_F2_TO_F1_P" SITE "AC30";\r
- LOCATE COMP "CLK_F2_TO_F1_N" SITE "AC29";\r
- LOCATE COMP "CLK_F1_TO_F2_P" SITE "N1";\r
- LOCATE COMP "CLK_F1_TO_F2_N" SITE "P1";\r
+ LOCATE COMP "CLK_F2_TO_F1" SITE "AC30";\r
+ LOCATE COMP "CLK_F1_TO_F2" SITE "N1";\r
+\r
+ IOBUF PORT "CLK_F1_TO_F2" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
+ IOBUF PORT "CLK_F2_TO_F1" IO_TYPE=LVDS25 PULLMODE=NONE ;\r
\r
LOCATE COMP "ADDON_RESET" SITE "C17";\r
LOCATE COMP "RESET_N" SITE "B17";\r
LOCATE COMP "ADO_TTL_44" SITE "AF18";\r
LOCATE COMP "ADO_TTL_45" SITE "AJ15";\r
LOCATE COMP "ADO_TTL_46" SITE "AG16"; #occupied by 1-wire monitor\r
- DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ;\r
- IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
+# DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ;\r
+\r
\r
\r
#########################################\r
LOCATE COMP "FS_PE_14" SITE "E13";\r
LOCATE COMP "FS_PE_15" SITE "J12";\r
LOCATE COMP "FS_PE_16" SITE "H10";\r
- DEFINE PORT GROUP "fs_pe_group" "FS_PE*" ;\r
- IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
+# DEFINE PORT GROUP "fs_pe_group" "FS_PE*" ;\r
+# IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
\r
#########################################\r
# LED\r
LOCATE COMP "SFP_LED_ORANGE_18" SITE "AH17";\r
LOCATE COMP "SFP_LED_ORANGE_19" SITE "D23";\r
LOCATE COMP "SFP_LED_ORANGE_20" SITE "D26";\r
- DEFINE PORT GROUP "sfp_led_group" "SFP_LED*" ;\r
- IOBUF GROUP "sfp_led_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
+# DEFINE PORT GROUP "sfp_led_group" "SFP_LED*" ;\r
+# IOBUF GROUP "sfp_led_group" IO_TYPE=LVTTL33 PULLMODE=NONE ;\r
\r
#########################################\r
# SFP Control Signals\r
DEFINE PORT GROUP "sfp_los_group" "SFP_LOS*" ;\r
IOBUF GROUP "sfp_los_group" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
\r
- LOCATE COMP "TX_DIS_17" SITE "AF19";\r
- LOCATE COMP "TX_DIS_18" SITE "AE20";\r
- LOCATE COMP "TX_DIS_19" SITE "AD18";\r
- LOCATE COMP "TX_DIS_20" SITE "AC20";\r
- DEFINE PORT GROUP "tx_dis_group" "TX_DIS*" ;\r
+ LOCATE COMP "SFP_DIS_17" SITE "AF19";\r
+ LOCATE COMP "SFP_DIS_18" SITE "AE20";\r
+ LOCATE COMP "SFP_DIS_19" SITE "AD18";\r
+ LOCATE COMP "SFP_DIS_20" SITE "AC20";\r
+ DEFINE PORT GROUP "tx_dis_group" "SFP_DIS*" ;\r
IOBUF GROUP "tx_dis_group" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
\r
#not supported by transceivers\r
# Onewire Monitor\r
#########################################\r
LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "AG16"; #former ADO_TTL(46)\r
- IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=12 ;\r
+ IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
\r
#########################################\r
# Test Connectors\r
-- Internal direction port
- FEE_INIT_DATAREADY_OUT : out std_logic;
FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ FEE_INIT_DATAREADY_OUT : out std_logic;
FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
FEE_INIT_READ_IN : in std_logic;
- FEE_REPLY_DATAREADY_IN : in std_logic;
FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ FEE_REPLY_DATAREADY_IN : in std_logic;
FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
FEE_REPLY_READ_OUT : out std_logic;
- CTS_INIT_DATAREADY_IN : in std_logic;
CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ CTS_INIT_DATAREADY_IN : in std_logic;
CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
CTS_INIT_READ_OUT : out std_logic;
- CTS_REPLY_DATAREADY_OUT : out std_logic;
CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ CTS_REPLY_DATAREADY_OUT : out std_logic;
CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
CTS_REPLY_READ_IN : in std_logic;
- IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
- IPU_CODE_OUT : out std_logic_vector (7 downto 0);
- IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
- IPU_START_READOUT_OUT: out std_logic;
+ --Event information coming from CTS
+ IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ IPU_CODE_OUT : out std_logic_vector (7 downto 0);
+ IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_START_READOUT_OUT : out std_logic;
+ --Answer sent to CTS
APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
APL_CTS_DATAREADY_IN : in std_logic;
APL_FEE_READ_IN : in std_logic;
-- APL Control port
- APL_RUN_OUT : out std_logic;
- APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
-
+ APL_CTS_RUN_OUT : out std_logic;
+ APL_FEE_RUN_OUT : out std_logic;
+ MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ CTRL_SEQNR_RESET : in std_logic;
);
-end entity;
\ No newline at end of file
+end entity;
+
+architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming is
+
+ signal APL_CTS_TARGET_ADDRESS : std_logic_vector(15 downto 0);
+ signal APL_CTS_DATA_OUT : std_logic_vector(15 downto 0);
+ signal APL_CTS_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
+ signal APL_CTS_DATAREADY_OUT : std_logic;
+ signal APL_CTS_READ_IN : std_logic;
+ signal APL_CTS_SEQNR_OUT : std_logic_vector(7 downto 0);
+
+ signal APL_FEE_DTYPE_IN : std_logic_vector(3 downto 0);
+ signal APL_FEE_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal APL_FEE_SEND_IN : std_logic;
+
+
+
+
+begin
+
+-------------------------------------------------------------------------------
+--Application Interface, receiving request from CTS
+-------------------------------------------------------------------------------
+ THE_CTS_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_PASSIVE,
+ FIFO_TO_INT_DEPTH => FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(1),
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => APL_CTS_DATA_IN,
+ APL_PACKET_NUM_IN => APL_CTS_PACKET_NUM_IN,
+ APL_DATAREADY_IN => APL_CTS_DATAREADY_IN,
+ APL_READ_OUT => APL_CTS_READ_OUT,
+ APL_SHORT_TRANSFER_IN => APL_CTS_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => APL_CTS_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_CTS_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_CTS_SEND_IN,
+ APL_TARGET_ADDRESS_IN => APL_CTS_TARGET_ADDRESS,
+ -- Receiver port
+ APL_DATA_OUT => APL_CTS_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_CTS_PACKET_NUM_OUT,
+ APL_TYP_OUT => open,
+ APL_DATAREADY_OUT => APL_CTS_DATAREADY_OUT,
+ APL_READ_IN => APL_CTS_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_CTS_RUN_OUT,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_CTS_SEQNR_OUT,
+ APL_LENGTH_IN => APL_CTS_LENGTH_IN,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => CTS_REPLY_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => CTS_REPLY_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT=> CTS_REPLY_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => CTS_REPLY_READ_IN,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => (others => '0'),
+ INT_MASTER_READ_OUT => '0',
+ INT_SLAVE_DATAREADY_OUT => '0'
+ INT_SLAVE_DATA_OUT => (others => '0'),
+ INT_SLAVE_PACKET_NUM_OUT => (others => '0'),
+ INT_SLAVE_READ_IN => '0',
+ INT_SLAVE_DATAREADY_IN => CTS_INIT_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => CTS_INIT_DATA_IN,
+ INT_SLAVE_PACKET_NUM_IN=> CTS_INIT_PACKET_NUM_IN,
+ INT_SLAVE_READ_OUT => CTS_INIT_READ_OUT,
+ -- Status and control port
+ CTRL_SEQNR_RESET => CTRL_SEQNR_RESET,
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+
+
+
+-------------------------------------------------------------------------------
+--Application Interface, sending request to FEE
+-------------------------------------------------------------------------------
+
+ THE_FEE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_ACTIVE,
+ FIFO_TO_INT_DEPTH => FIFO_BRAM,
+ FIFO_TO_APL_DEPTH => FIFO_BRAM,
+ FORCE_REPLY => cfg_FORCE_REPLY(1),
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS=> c_YES,
+ BROADCAST_BITMASK => x"FF"
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ -- APL Transmitter port
+ APL_DATA_IN => (others => '0'),
+ APL_PACKET_NUM_IN => (others => '0'),
+ APL_DATAREADY_IN => '0',
+ APL_READ_OUT => open,
+ APL_SHORT_TRANSFER_IN => '1',
+ APL_DTYPE_IN => APL_FEE_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => APL_FEE_ERROR_PATTERN_IN,
+ APL_SEND_IN => APL_FEE_SEND_IN,
+ APL_TARGET_ADDRESS_IN => (others => '1'),
+ -- Receiver port
+ APL_DATA_OUT => APL_FEE_DATA_OUT,
+ APL_PACKET_NUM_OUT=> APL_FEE_PACKET_NUM_OUT,
+ APL_TYP_OUT => APL_FEE_TYP_OUT,
+ APL_DATAREADY_OUT => APL_FEE_DATAREADY_OUT,
+ APL_READ_IN => APL_FEE_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => APL_FEE_RUN_OUT,
+ APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
+ APL_SEQNR_OUT => APL_FEE_SEQNR_OUT,
+ APL_LENGTH_IN => APL_FEE_LENGTH_IN,
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => FEE_INIT_DATAREADY_OUT,
+ INT_MASTER_DATA_OUT => FEE_INIT_DATA_OUT,
+ INT_MASTER_PACKET_NUM_OUT=> FEE_INIT_PACKET_NUM_OUT,
+ INT_MASTER_READ_IN => FEE_INIT_READ_IN,
+ INT_MASTER_DATAREADY_IN => '0',
+ INT_MASTER_DATA_IN => (others => '0'),
+ INT_MASTER_PACKET_NUM_IN => (others => '0'),
+ INT_MASTER_READ_OUT => '0',
+ INT_SLAVE_DATAREADY_OUT => '0'
+ INT_SLAVE_DATA_OUT => (others => '0'),
+ INT_SLAVE_PACKET_NUM_OUT => (others => '0'),
+ INT_SLAVE_READ_IN => '0',
+ INT_SLAVE_DATAREADY_IN => FEE_REPLY_DATAREADY_IN,
+ INT_SLAVE_DATA_IN => FEE_REPLY_DATA_IN,
+ INT_SLAVE_PACKET_NUM_IN=> FEE_REPLY_PACKET_NUM_IN,
+ INT_SLAVE_READ_OUT => FEE_REPLY_READ_OUT,
+ -- Status and control port
+ CTRL_SEQNR_RESET => CTRL_SEQNR_RESET,
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+-------------------------------------------------------------------------------
+--Reading CTS data, forwarding to FEE
+-------------------------------------------------------------------------------
+
+
+ PROC_FSM_FORWARD_CTS_REQUEST : process(CLK)
+ begin
+ APL_CTS_READ_IN <= '1';
+ APL_FEE_SEND_IN <= '0';
+ if APL_CTS_DATAREADY_OUT = '1' then
+ case APL_CTS_PACKET_NUM_OUT is
+ when c_F1 =>
+ APL_FEE_ERROR_PATTERN_IN(31 downto 16) <= APL_CTS_DATA_OUT;
+ when c_F2 =>
+ APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= APL_CTS_DATA_OUT;
+ when c_F3 =>
+ APL_FEE_SEQNR_IN <= APL_CTS_DATA_OUT(11 downto 4);
+ APL_FEE_DTYPE_IN <= APL_CTS_DATA_OUT(3 downto 0);
+ APL_FEE_SEND_IN <= '1';
+ IPU_START_READOUT_OUT <= '1';
+ when others =>
+ null;
+ end case;
+ end if;
+ if APL_CTS_RUN_OUT = '0' then
+ IPU_START_READOUT_OUT <= '0';
+ end if;
+ end process;
+
+ IPU_NUMBER_OUT <= APL_FEE_ERROR_PATTERN_IN(15 downto 0);
+ IPU_CODE_OUT <= APL_FEE_ERROR_PATTERN_IN(23 downto 16);
+ IPU_INFORMATION_OUT <= APL_FEE_ERROR_PATTERN_IN(31 downto 24);
+
+
+
+
+end architecture;
\ No newline at end of file
--Information received with request
IPU_NUMBER_OUT : out std_logic_vector (15 downto 0);
IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0);
+ IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0);
--start strobe
IPU_START_READOUT_OUT: out std_logic;
--detector data, equipped with DHDR
signal ipu_read_before : std_logic;
signal second_word_waiting : std_logic;
signal last_second_word_waiting : std_logic;
+ signal make_compare : std_logic;
+ signal mismatch_number : std_logic;
+ signal mismatch_random : std_logic;
+ signal mismatch_type : std_logic;
+ signal mismatch_length : std_logic;
begin
- IPU_NUMBER_OUT <= buf_NUMBER;
- IPU_START_READOUT_OUT <= buf_START_READOUT;
- IPU_READ_OUT <= buf_IPU_READ;
- IPU_INFORMATION_OUT <= buf_INFORMATION;
PROC_STATE_MACHINE : process(CLK)
begin
else
buf_API_READ_OUT <= '1';
first_ipu_read <= '0';
- --make_compare <= '0';
+ make_compare <= '0';
+ update_buffers <= '0';
case state is
when START =>
buf_API_SEND_OUT <= '0';
- update_buffers <= '0';
buf_START_READOUT <= '0';
if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' and API_TYP_IN = TYPE_TRM then
case API_PACKET_NUM_IN is
end if;
when MAKE_DHDR => -- send DHDR packet
- update_buffers <= '0';
buf_API_SEND_OUT <= '1';
buf_API_DATAREADY_OUT <= '1';
- --make_compare <= '1';
+ make_compare <= '1';
if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then
dhdr_counter <= dhdr_counter + 1;
case dhdr_counter is
end process;
buf_IPU_READ <= '1' when API_READ_IN = '1' and waiting_word = '0' and second_word_waiting = '0' and (state = READING or first_ipu_read = '1') else '0';
---
+
+
+---------------------------------------------------------------------
+--second half of 32bit word has to be sent
+---------------------------------------------------------------------
+
PROC_second_word : process(waiting_word, buf_API_DATAREADY_OUT, API_READ_IN, last_second_word_waiting, RESET)
begin
if RESET = '1' then
end if;
end process;
+
+---------------------------------------------------------------------
+--store length and error pattern input
+---------------------------------------------------------------------
PROC_buffer_inputs : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+---------------------------------------------------------------------
+--store ipu data
+---------------------------------------------------------------------
PROC_store_IPU_input : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+---------------------------------------------------------------------
+--User finished readout yet?
+---------------------------------------------------------------------
PROC_get_end_of_data : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+---------------------------------------------------------------------
+--Gen. Packet Number
+---------------------------------------------------------------------
PROC_packet_num : process(CLK)
begin
if rising_edge(CLK) then
end if;
end process;
+---------------------------------------------------------------------
+--Connect Outputs
+---------------------------------------------------------------------
+
API_ERROR_PATTERN_OUT <= buf_IPU_ERROR_PATTERN_IN;
API_LENGTH_OUT <= buf_IPU_LENGTH_IN+2;
API_READ_OUT <= buf_API_READ_OUT;
API_SHORT_TRANSFER_OUT<= '0';
API_DTYPE_OUT <= buf_TYPE;
+ IPU_NUMBER_OUT <= buf_NUMBER;
+ IPU_START_READOUT_OUT <= buf_START_READOUT;
+ IPU_READ_OUT <= buf_IPU_READ;
+ IPU_INFORMATION_OUT <= buf_INFORMATION;
+ IPU_READOUT_TYPE_OUT <= buf_TYPE;
-
+---------------------------------------------------------------------
+--Debugging
+---------------------------------------------------------------------
STAT_DEBUG <= (others => '0');
state_bits(0) <= '1' when state = START else '0';
jspc29 / trbnet.git / commitdiff