not tested.
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_18x1k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:27:25\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=1024\r
+Width=18\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_18x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 1024 -width 18 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:27:25 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_18x1k_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(9 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(10 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x1k_oreg;
+
+architecture Structure of fifo_18x1k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal rptr_10: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co4_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal co4_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal co4_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x1k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "18";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 18,
+ DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vlo,
+ ADW3=>scuba_vlo, ADW4=>wptr_0, ADW5=>wptr_1, ADW6=>wptr_2,
+ ADW7=>wptr_3, ADW8=>wptr_4, ADW9=>wptr_5, ADW10=>wptr_6,
+ ADW11=>wptr_7, ADW12=>wptr_8, ADW13=>wptr_9, CEW=>wren_i,
+ CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>rptr_0, ADR5=>rptr_1,
+ ADR6=>rptr_2, ADR7=>rptr_3, ADR8=>rptr_4, ADR9=>rptr_5,
+ ADR10=>rptr_6, ADR11=>rptr_7, ADR12=>rptr_8, ADR13=>rptr_9,
+ CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2),
+ DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7),
+ DO8=>Q(8), DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12),
+ DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16),
+ DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_57: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_55: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_44: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>scuba_vlo, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>open, NC0=>ifcount_10);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>scuba_vlo, PC0=>wcount_10, CO=>co5_1,
+ NC1=>open, NC0=>iwcount_10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>scuba_vlo, PC0=>rcount_10, CO=>co5_2,
+ NC1=>open, NC0=>ircount_10);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co4_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_10);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_18x1k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_18x256_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:26:44\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=256\r
+Width=18\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_18x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 256 -width 18 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:26:44 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_18x256_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x256_oreg;
+
+architecture Structure of fifo_18x256_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal rptr_8: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co3_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal co3_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal co3_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x256_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "18";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_8, B=>rptr_8, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 18,
+ DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vlo,
+ ADW3=>scuba_vlo, ADW4=>wptr_0, ADW5=>wptr_1, ADW6=>wptr_2,
+ ADW7=>wptr_3, ADW8=>wptr_4, ADW9=>wptr_5, ADW10=>wptr_6,
+ ADW11=>wptr_7, ADW12=>scuba_vlo, ADW13=>scuba_vlo,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>rptr_0, ADR5=>rptr_1, ADR6=>rptr_2, ADR7=>rptr_3,
+ ADR8=>rptr_4, ADR9=>rptr_5, ADR10=>rptr_6, ADR11=>rptr_7,
+ ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3),
+ DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8),
+ DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12),
+ DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16),
+ DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_47: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_45: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_36: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>scuba_vlo, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>open, NC0=>ifcount_8);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co3_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>scuba_vlo, PC0=>wcount_8, CO=>co4_1,
+ NC1=>open, NC0=>iwcount_8);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>scuba_vlo, PC0=>rcount_8, CO=>co4_2,
+ NC1=>open, NC0=>ircount_8);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co3_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_8);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_18x256_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_18x2k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:27:53\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=2048\r
+Width=18\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_18x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 2048 -width 18 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:27:53 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_18x2k_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(10 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(11 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x2k_oreg;
+
+architecture Structure of fifo_18x2k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal rptr_11: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co4_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal wcount_10: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_18x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_18x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "9";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0),
+ DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
+ DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>scuba_vlo, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(9), DO1=>Q(10), DO2=>Q(11), DO3=>Q(12),
+ DO4=>Q(13), DO5=>Q(14), DO6=>Q(15), DO7=>Q(16), DO8=>Q(17),
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_62: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_60: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_48: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i_inv,
+ B0=>wren_i, CI=>co4_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_1,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_2,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_10, B1=>scuba_vlo,
+ B0=>rptr_10, BI=>co4_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_11, S0=>wcnt_sub_10);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>scuba_vlo,
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_18x2k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_18x512_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:27:04\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=512\r
+Width=18\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_18x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 512 -width 18 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:27:04 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_18x512_oreg is
+ port (
+ Data: in std_logic_vector(17 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(8 downto 0);
+ Q: out std_logic_vector(17 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_18x512_oreg;
+
+architecture Structure of fifo_18x512_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal rptr_9: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co3_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal wcount_8: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_18x512_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wptr_0, ADW6=>wptr_1,
+ ADW7=>wptr_2, ADW8=>wptr_3, ADW9=>wptr_4, ADW10=>wptr_5,
+ ADW11=>wptr_6, ADW12=>wptr_7, ADW13=>wptr_8, CEW=>wren_i,
+ CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
+ ADR13=>rptr_8, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open,
+ DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open,
+ DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_52: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_50: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_40: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i_inv, B0=>wren_i,
+ CI=>co3_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_1,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_2,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_8, B1=>scuba_vlo,
+ B0=>rptr_8, BI=>co3_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_9, S0=>wcnt_sub_8);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>scuba_vlo,
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_18x512_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x16k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:25:20\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=16384\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x16k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 16384 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:25:20 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x16k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(13 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(14 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x16k_oreg;
+
+architecture Structure of fifo_36x16k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal rden_cr0: std_logic;
+ signal rden_cr0_1: std_logic;
+ signal rden_cr0_2: std_logic;
+ signal rden_cr0_3: std_logic;
+ signal rden_cr0_4: std_logic;
+ signal rden_cr0_5: std_logic;
+ signal rden_cr0_6: std_logic;
+ signal rden_cr0_7: std_logic;
+ signal rden_cr0_8: std_logic;
+ signal rden_cr0_9: std_logic;
+ signal rden_cr0_10: std_logic;
+ signal rden_cr0_11: std_logic;
+ signal rden_cr0_12: std_logic;
+ signal rden_cr0_13: std_logic;
+ signal rden_cr0_14: std_logic;
+ signal rden_cr0_15: std_logic;
+ signal rden_cr0_16: std_logic;
+ signal rden_cr0_17: std_logic;
+ signal rden_cr0_18: std_logic;
+ signal rden_cr0_19: std_logic;
+ signal rden_cr0_20: std_logic;
+ signal rden_cr0_21: std_logic;
+ signal rden_cr0_22: std_logic;
+ signal rden_cr0_23: std_logic;
+ signal rden_cr0_24: std_logic;
+ signal rden_cr0_25: std_logic;
+ signal rden_cr0_26: std_logic;
+ signal rden_cr0_27: std_logic;
+ signal rden_cr0_28: std_logic;
+ signal rden_cr0_29: std_logic;
+ signal rden_cr0_30: std_logic;
+ signal rden_cr0_31: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal wptr_14: std_logic;
+ signal rptr_14: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal rptr_13_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co5: std_logic;
+ signal ifcount_14: std_logic;
+ signal co7: std_logic;
+ signal co6: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co6_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co6_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_14: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5_3: std_logic;
+ signal iwcount_14: std_logic;
+ signal co7_1: std_logic;
+ signal wcount_14: std_logic;
+ signal co6_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal co5_4: std_logic;
+ signal ircount_14: std_logic;
+ signal co7_2: std_logic;
+ signal rcount_14: std_logic;
+ signal co6_4: std_logic;
+ signal mdout1_7_0: std_logic;
+ signal mdout1_6_0: std_logic;
+ signal mdout1_5_0: std_logic;
+ signal mdout1_4_0: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_7_1: std_logic;
+ signal mdout1_6_1: std_logic;
+ signal mdout1_5_1: std_logic;
+ signal mdout1_4_1: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_7_2: std_logic;
+ signal mdout1_6_2: std_logic;
+ signal mdout1_5_2: std_logic;
+ signal mdout1_4_2: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_7_3: std_logic;
+ signal mdout1_6_3: std_logic;
+ signal mdout1_5_3: std_logic;
+ signal mdout1_4_3: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_7_4: std_logic;
+ signal mdout1_6_4: std_logic;
+ signal mdout1_5_4: std_logic;
+ signal mdout1_4_4: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_7_5: std_logic;
+ signal mdout1_6_5: std_logic;
+ signal mdout1_5_5: std_logic;
+ signal mdout1_4_5: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_7_6: std_logic;
+ signal mdout1_6_6: std_logic;
+ signal mdout1_5_6: std_logic;
+ signal mdout1_4_6: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_7_7: std_logic;
+ signal mdout1_6_7: std_logic;
+ signal mdout1_5_7: std_logic;
+ signal mdout1_4_7: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_7_8: std_logic;
+ signal mdout1_6_8: std_logic;
+ signal mdout1_5_8: std_logic;
+ signal mdout1_4_8: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_7_9: std_logic;
+ signal mdout1_6_9: std_logic;
+ signal mdout1_5_9: std_logic;
+ signal mdout1_4_9: std_logic;
+ signal mdout1_3_9: std_logic;
+ signal mdout1_2_9: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_7_10: std_logic;
+ signal mdout1_6_10: std_logic;
+ signal mdout1_5_10: std_logic;
+ signal mdout1_4_10: std_logic;
+ signal mdout1_3_10: std_logic;
+ signal mdout1_2_10: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_7_11: std_logic;
+ signal mdout1_6_11: std_logic;
+ signal mdout1_5_11: std_logic;
+ signal mdout1_4_11: std_logic;
+ signal mdout1_3_11: std_logic;
+ signal mdout1_2_11: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_7_12: std_logic;
+ signal mdout1_6_12: std_logic;
+ signal mdout1_5_12: std_logic;
+ signal mdout1_4_12: std_logic;
+ signal mdout1_3_12: std_logic;
+ signal mdout1_2_12: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_7_13: std_logic;
+ signal mdout1_6_13: std_logic;
+ signal mdout1_5_13: std_logic;
+ signal mdout1_4_13: std_logic;
+ signal mdout1_3_13: std_logic;
+ signal mdout1_2_13: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_7_14: std_logic;
+ signal mdout1_6_14: std_logic;
+ signal mdout1_5_14: std_logic;
+ signal mdout1_4_14: std_logic;
+ signal mdout1_3_14: std_logic;
+ signal mdout1_2_14: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_7_15: std_logic;
+ signal mdout1_6_15: std_logic;
+ signal mdout1_5_15: std_logic;
+ signal mdout1_4_15: std_logic;
+ signal mdout1_3_15: std_logic;
+ signal mdout1_2_15: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_7_16: std_logic;
+ signal mdout1_6_16: std_logic;
+ signal mdout1_5_16: std_logic;
+ signal mdout1_4_16: std_logic;
+ signal mdout1_3_16: std_logic;
+ signal mdout1_2_16: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal mdout1_7_17: std_logic;
+ signal mdout1_6_17: std_logic;
+ signal mdout1_5_17: std_logic;
+ signal mdout1_4_17: std_logic;
+ signal mdout1_3_17: std_logic;
+ signal mdout1_2_17: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal mdout1_7_18: std_logic;
+ signal mdout1_6_18: std_logic;
+ signal mdout1_5_18: std_logic;
+ signal mdout1_4_18: std_logic;
+ signal mdout1_3_18: std_logic;
+ signal mdout1_2_18: std_logic;
+ signal mdout1_1_18: std_logic;
+ signal mdout1_0_18: std_logic;
+ signal mdout1_7_19: std_logic;
+ signal mdout1_6_19: std_logic;
+ signal mdout1_5_19: std_logic;
+ signal mdout1_4_19: std_logic;
+ signal mdout1_3_19: std_logic;
+ signal mdout1_2_19: std_logic;
+ signal mdout1_1_19: std_logic;
+ signal mdout1_0_19: std_logic;
+ signal mdout1_7_20: std_logic;
+ signal mdout1_6_20: std_logic;
+ signal mdout1_5_20: std_logic;
+ signal mdout1_4_20: std_logic;
+ signal mdout1_3_20: std_logic;
+ signal mdout1_2_20: std_logic;
+ signal mdout1_1_20: std_logic;
+ signal mdout1_0_20: std_logic;
+ signal mdout1_7_21: std_logic;
+ signal mdout1_6_21: std_logic;
+ signal mdout1_5_21: std_logic;
+ signal mdout1_4_21: std_logic;
+ signal mdout1_3_21: std_logic;
+ signal mdout1_2_21: std_logic;
+ signal mdout1_1_21: std_logic;
+ signal mdout1_0_21: std_logic;
+ signal mdout1_7_22: std_logic;
+ signal mdout1_6_22: std_logic;
+ signal mdout1_5_22: std_logic;
+ signal mdout1_4_22: std_logic;
+ signal mdout1_3_22: std_logic;
+ signal mdout1_2_22: std_logic;
+ signal mdout1_1_22: std_logic;
+ signal mdout1_0_22: std_logic;
+ signal mdout1_7_23: std_logic;
+ signal mdout1_6_23: std_logic;
+ signal mdout1_5_23: std_logic;
+ signal mdout1_4_23: std_logic;
+ signal mdout1_3_23: std_logic;
+ signal mdout1_2_23: std_logic;
+ signal mdout1_1_23: std_logic;
+ signal mdout1_0_23: std_logic;
+ signal mdout1_7_24: std_logic;
+ signal mdout1_6_24: std_logic;
+ signal mdout1_5_24: std_logic;
+ signal mdout1_4_24: std_logic;
+ signal mdout1_3_24: std_logic;
+ signal mdout1_2_24: std_logic;
+ signal mdout1_1_24: std_logic;
+ signal mdout1_0_24: std_logic;
+ signal mdout1_7_25: std_logic;
+ signal mdout1_6_25: std_logic;
+ signal mdout1_5_25: std_logic;
+ signal mdout1_4_25: std_logic;
+ signal mdout1_3_25: std_logic;
+ signal mdout1_2_25: std_logic;
+ signal mdout1_1_25: std_logic;
+ signal mdout1_0_25: std_logic;
+ signal mdout1_7_26: std_logic;
+ signal mdout1_6_26: std_logic;
+ signal mdout1_5_26: std_logic;
+ signal mdout1_4_26: std_logic;
+ signal mdout1_3_26: std_logic;
+ signal mdout1_2_26: std_logic;
+ signal mdout1_1_26: std_logic;
+ signal mdout1_0_26: std_logic;
+ signal mdout1_7_27: std_logic;
+ signal mdout1_6_27: std_logic;
+ signal mdout1_5_27: std_logic;
+ signal mdout1_4_27: std_logic;
+ signal mdout1_3_27: std_logic;
+ signal mdout1_2_27: std_logic;
+ signal mdout1_1_27: std_logic;
+ signal mdout1_0_27: std_logic;
+ signal mdout1_7_28: std_logic;
+ signal mdout1_6_28: std_logic;
+ signal mdout1_5_28: std_logic;
+ signal mdout1_4_28: std_logic;
+ signal mdout1_3_28: std_logic;
+ signal mdout1_2_28: std_logic;
+ signal mdout1_1_28: std_logic;
+ signal mdout1_0_28: std_logic;
+ signal mdout1_7_29: std_logic;
+ signal mdout1_6_29: std_logic;
+ signal mdout1_5_29: std_logic;
+ signal mdout1_4_29: std_logic;
+ signal mdout1_3_29: std_logic;
+ signal mdout1_2_29: std_logic;
+ signal mdout1_1_29: std_logic;
+ signal mdout1_0_29: std_logic;
+ signal mdout1_7_30: std_logic;
+ signal mdout1_6_30: std_logic;
+ signal mdout1_5_30: std_logic;
+ signal mdout1_4_30: std_logic;
+ signal mdout1_3_30: std_logic;
+ signal mdout1_2_30: std_logic;
+ signal mdout1_1_30: std_logic;
+ signal mdout1_0_30: std_logic;
+ signal mdout1_7_31: std_logic;
+ signal mdout1_6_31: std_logic;
+ signal mdout1_5_31: std_logic;
+ signal mdout1_4_31: std_logic;
+ signal mdout1_3_31: std_logic;
+ signal mdout1_2_31: std_logic;
+ signal mdout1_1_31: std_logic;
+ signal mdout1_0_31: std_logic;
+ signal mdout1_7_32: std_logic;
+ signal mdout1_6_32: std_logic;
+ signal mdout1_5_32: std_logic;
+ signal mdout1_4_32: std_logic;
+ signal mdout1_3_32: std_logic;
+ signal mdout1_2_32: std_logic;
+ signal mdout1_1_32: std_logic;
+ signal mdout1_0_32: std_logic;
+ signal mdout1_7_33: std_logic;
+ signal mdout1_6_33: std_logic;
+ signal mdout1_5_33: std_logic;
+ signal mdout1_4_33: std_logic;
+ signal mdout1_3_33: std_logic;
+ signal mdout1_2_33: std_logic;
+ signal mdout1_1_33: std_logic;
+ signal mdout1_0_33: std_logic;
+ signal mdout1_7_34: std_logic;
+ signal mdout1_6_34: std_logic;
+ signal mdout1_5_34: std_logic;
+ signal mdout1_4_34: std_logic;
+ signal mdout1_3_34: std_logic;
+ signal mdout1_2_34: std_logic;
+ signal mdout1_1_34: std_logic;
+ signal mdout1_0_34: std_logic;
+ signal rptr_13_ff2: std_logic;
+ signal rptr_12_ff2: std_logic;
+ signal rptr_11_ff2: std_logic;
+ signal mdout1_7_35: std_logic;
+ signal mdout1_6_35: std_logic;
+ signal mdout1_5_35: std_logic;
+ signal mdout1_4_35: std_logic;
+ signal mdout1_3_35: std_logic;
+ signal mdout1_2_35: std_logic;
+ signal mdout1_1_35: std_logic;
+ signal mdout1_0_35: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_11: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal co5_5: std_logic;
+ signal rptr_12: std_logic;
+ signal rptr_13: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal wcnt_sub_14: std_logic;
+ signal co6_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal co6_6: std_logic;
+ signal wcnt_reg_14: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX81
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; SD1: in std_logic;
+ SD2: in std_logic; SD3: in std_logic; Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_17 : label is "0x3232";
+ attribute initval of LUT4_16 : label is "0x3232";
+ attribute initval of LUT4_15 : label is "0xfffe";
+ attribute initval of LUT4_14 : label is "0xfffe";
+ attribute initval of LUT4_13 : label is "0xfffe";
+ attribute initval of LUT4_12 : label is "0xfffe";
+ attribute initval of LUT4_11 : label is "0xfffe";
+ attribute initval of LUT4_10 : label is "0xfffe";
+ attribute initval of LUT4_9 : label is "0xfffe";
+ attribute initval of LUT4_8 : label is "0xfffe";
+ attribute initval of LUT4_7 : label is "0xfffe";
+ attribute initval of LUT4_6 : label is "0xfffe";
+ attribute initval of LUT4_5 : label is "0xfffe";
+ attribute initval of LUT4_4 : label is "0xfffe";
+ attribute initval of LUT4_3 : label is "0xfffe";
+ attribute initval of LUT4_2 : label is "0xfffe";
+ attribute initval of LUT4_1 : label is "0xfffe";
+ attribute initval of LUT4_0 : label is "0xfffe";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_31 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_31 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_31 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_31 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_31 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_31 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_31 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_31 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_31 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_30 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_30 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_30 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_1_30 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_30 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_30 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_30 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_30 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_30 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_29 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_29 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_29 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_2_29 : label is "0b000";
+ attribute GSR of pdp_ram_0_2_29 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_29 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_29 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_29 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_29 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_28 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_28 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_3_28 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_3_28 : label is "0b000";
+ attribute GSR of pdp_ram_0_3_28 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_28 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_3_28 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_3_28 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_3_28 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_27 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_27 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_0_27 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_1_0_27 : label is "0b001";
+ attribute GSR of pdp_ram_1_0_27 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_27 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_0_27 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_0_27 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_0_27 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_26 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_26 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_1_26 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_1_1_26 : label is "0b001";
+ attribute GSR of pdp_ram_1_1_26 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_1_26 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_1_26 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_1_26 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_1_26 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_2_25 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_2_25 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_2_25 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_1_2_25 : label is "0b001";
+ attribute GSR of pdp_ram_1_2_25 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_2_25 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_2_25 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_2_25 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_2_25 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_3_24 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_3_24 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_3_24 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_1_3_24 : label is "0b001";
+ attribute GSR of pdp_ram_1_3_24 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_3_24 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_3_24 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_3_24 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_3_24 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_23 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_23 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_0_23 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_2_0_23 : label is "0b010";
+ attribute GSR of pdp_ram_2_0_23 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_23 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_0_23 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_0_23 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_0_23 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_22 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_22 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_1_22 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_2_1_22 : label is "0b010";
+ attribute GSR of pdp_ram_2_1_22 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_1_22 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_1_22 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_1_22 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_1_22 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_2_21 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_2_21 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_2_21 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_2_2_21 : label is "0b010";
+ attribute GSR of pdp_ram_2_2_21 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_2_21 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_2_21 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_2_21 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_2_21 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_3_20 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_3_20 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_3_20 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_2_3_20 : label is "0b010";
+ attribute GSR of pdp_ram_2_3_20 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_3_20 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_3_20 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_3_20 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_3_20 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_19 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_19 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_0_19 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_0_19 : label is "0b011";
+ attribute GSR of pdp_ram_3_0_19 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_19 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_0_19 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_0_19 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_0_19 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_18 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_18 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_1_18 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_1_18 : label is "0b011";
+ attribute GSR of pdp_ram_3_1_18 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_1_18 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_1_18 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_1_18 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_1_18 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_2_17 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_2_17 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_2_17 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_2_17 : label is "0b011";
+ attribute GSR of pdp_ram_3_2_17 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_2_17 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_2_17 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_2_17 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_2_17 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_3_16 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_3_16 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_3_16 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_3_16 : label is "0b011";
+ attribute GSR of pdp_ram_3_3_16 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_3_16 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_3_16 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_3_16 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_3_16 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_0_15 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_0_15 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_0_15 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_4_0_15 : label is "0b100";
+ attribute GSR of pdp_ram_4_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_0_15 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_0_15 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_0_15 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_0_15 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_1_14 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_1_14 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_1_14 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_4_1_14 : label is "0b100";
+ attribute GSR of pdp_ram_4_1_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_1_14 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_1_14 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_1_14 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_1_14 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_2_13 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_2_13 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_2_13 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_4_2_13 : label is "0b100";
+ attribute GSR of pdp_ram_4_2_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_2_13 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_2_13 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_2_13 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_2_13 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_3_12 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_3_12 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_3_12 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_4_3_12 : label is "0b100";
+ attribute GSR of pdp_ram_4_3_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_3_12 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_3_12 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_3_12 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_3_12 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_0_11 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_0_11 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_0_11 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_5_0_11 : label is "0b101";
+ attribute GSR of pdp_ram_5_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_0_11 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_0_11 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_0_11 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_0_11 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_1_10 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_1_10 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_1_10 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_5_1_10 : label is "0b101";
+ attribute GSR of pdp_ram_5_1_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_1_10 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_1_10 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_1_10 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_1_10 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_2_9 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_2_9 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_2_9 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_5_2_9 : label is "0b101";
+ attribute GSR of pdp_ram_5_2_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_2_9 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_2_9 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_2_9 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_2_9 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_3_8 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_3_8 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_3_8 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_5_3_8 : label is "0b101";
+ attribute GSR of pdp_ram_5_3_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_3_8 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_3_8 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_3_8 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_3_8 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_0_7 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_0_7 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_0_7 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_6_0_7 : label is "0b110";
+ attribute GSR of pdp_ram_6_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_0_7 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_0_7 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_0_7 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_1_6 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_1_6 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_1_6 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_6_1_6 : label is "0b110";
+ attribute GSR of pdp_ram_6_1_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_1_6 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_1_6 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_1_6 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_1_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_2_5 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_2_5 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_2_5 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_6_2_5 : label is "0b110";
+ attribute GSR of pdp_ram_6_2_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_2_5 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_2_5 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_2_5 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_2_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_3_4 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_3_4 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_3_4 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_6_3_4 : label is "0b110";
+ attribute GSR of pdp_ram_6_3_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_3_4 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_3_4 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_3_4 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_3_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_0_3 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_0_3 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_0_3 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_7_0_3 : label is "0b111";
+ attribute GSR of pdp_ram_7_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_0_3 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_0_3 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_0_3 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_1_2 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_1_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_1_2 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_7_1_2 : label is "0b111";
+ attribute GSR of pdp_ram_7_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_1_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_1_2 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_1_2 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_2_1 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_2_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_2_1 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_7_2_1 : label is "0b111";
+ attribute GSR of pdp_ram_7_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_2_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_2_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_2_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_3_0 : label is "fifo_36x16k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_3_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_3_0 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_7_3_0 : label is "0b111";
+ attribute GSR of pdp_ram_7_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_3_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_3_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_3_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_3_0 : label is "9";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t21: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t20: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t19: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t18: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_1);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_2);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_3);
+
+ AND2_t17: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_4);
+
+ AND2_t16: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_5);
+
+ AND2_t15: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_6);
+
+ AND2_t14: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_7);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_9);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_10);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_11);
+
+ AND2_t13: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_12);
+
+ AND2_t12: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_13);
+
+ AND2_t11: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_14);
+
+ AND2_t10: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_15);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_16);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_17);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_18);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_19);
+
+ AND2_t9: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_20);
+
+ AND2_t8: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_21);
+
+ AND2_t7: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_22);
+
+ AND2_t6: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_23);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_24);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_25);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_26);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0xfffe")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rden_i_inv, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rden_cr0_27);
+
+ AND2_t5: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_28);
+
+ AND2_t4: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_29);
+
+ AND2_t3: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_30);
+
+ AND2_t2: AND2
+ port map (A=>rden_i, B=>rptr_11, Z=>rden_cr0_31);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_14, B=>rptr_14, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_31: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_cr0,
+ CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset, DO0=>mdout1_0_0,
+ DO1=>mdout1_0_1, DO2=>mdout1_0_2, DO3=>mdout1_0_3,
+ DO4=>mdout1_0_4, DO5=>mdout1_0_5, DO6=>mdout1_0_6,
+ DO7=>mdout1_0_7, DO8=>mdout1_0_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_30: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_1, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_0_9, DO1=>mdout1_0_10, DO2=>mdout1_0_11,
+ DO3=>mdout1_0_12, DO4=>mdout1_0_13, DO5=>mdout1_0_14,
+ DO6=>mdout1_0_15, DO7=>mdout1_0_16, DO8=>mdout1_0_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_0_2_29: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_2, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_0_18, DO1=>mdout1_0_19, DO2=>mdout1_0_20,
+ DO3=>mdout1_0_21, DO4=>mdout1_0_22, DO5=>mdout1_0_23,
+ DO6=>mdout1_0_24, DO7=>mdout1_0_25, DO8=>mdout1_0_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_0_3_28: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_3, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_0_27, DO1=>mdout1_0_28, DO2=>mdout1_0_29,
+ DO3=>mdout1_0_30, DO4=>mdout1_0_31, DO5=>mdout1_0_32,
+ DO6=>mdout1_0_33, DO7=>mdout1_0_34, DO8=>mdout1_0_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_1_0_27: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_4, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_1_0, DO1=>mdout1_1_1, DO2=>mdout1_1_2,
+ DO3=>mdout1_1_3, DO4=>mdout1_1_4, DO5=>mdout1_1_5,
+ DO6=>mdout1_1_6, DO7=>mdout1_1_7, DO8=>mdout1_1_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_1_1_26: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_5, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_1_9, DO1=>mdout1_1_10, DO2=>mdout1_1_11,
+ DO3=>mdout1_1_12, DO4=>mdout1_1_13, DO5=>mdout1_1_14,
+ DO6=>mdout1_1_15, DO7=>mdout1_1_16, DO8=>mdout1_1_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_1_2_25: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_6, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_1_18, DO1=>mdout1_1_19, DO2=>mdout1_1_20,
+ DO3=>mdout1_1_21, DO4=>mdout1_1_22, DO5=>mdout1_1_23,
+ DO6=>mdout1_1_24, DO7=>mdout1_1_25, DO8=>mdout1_1_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_1_3_24: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_7, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_1_27, DO1=>mdout1_1_28, DO2=>mdout1_1_29,
+ DO3=>mdout1_1_30, DO4=>mdout1_1_31, DO5=>mdout1_1_32,
+ DO6=>mdout1_1_33, DO7=>mdout1_1_34, DO8=>mdout1_1_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_2_0_23: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_8, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_2_0, DO1=>mdout1_2_1, DO2=>mdout1_2_2,
+ DO3=>mdout1_2_3, DO4=>mdout1_2_4, DO5=>mdout1_2_5,
+ DO6=>mdout1_2_6, DO7=>mdout1_2_7, DO8=>mdout1_2_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_2_1_22: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_9, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_2_9, DO1=>mdout1_2_10, DO2=>mdout1_2_11,
+ DO3=>mdout1_2_12, DO4=>mdout1_2_13, DO5=>mdout1_2_14,
+ DO6=>mdout1_2_15, DO7=>mdout1_2_16, DO8=>mdout1_2_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_2_2_21: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_10, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_2_18, DO1=>mdout1_2_19, DO2=>mdout1_2_20,
+ DO3=>mdout1_2_21, DO4=>mdout1_2_22, DO5=>mdout1_2_23,
+ DO6=>mdout1_2_24, DO7=>mdout1_2_25, DO8=>mdout1_2_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_2_3_20: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_11, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_2_27, DO1=>mdout1_2_28, DO2=>mdout1_2_29,
+ DO3=>mdout1_2_30, DO4=>mdout1_2_31, DO5=>mdout1_2_32,
+ DO6=>mdout1_2_33, DO7=>mdout1_2_34, DO8=>mdout1_2_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_3_0_19: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_12, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_3_0, DO1=>mdout1_3_1, DO2=>mdout1_3_2,
+ DO3=>mdout1_3_3, DO4=>mdout1_3_4, DO5=>mdout1_3_5,
+ DO6=>mdout1_3_6, DO7=>mdout1_3_7, DO8=>mdout1_3_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_3_1_18: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_13, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_3_9, DO1=>mdout1_3_10, DO2=>mdout1_3_11,
+ DO3=>mdout1_3_12, DO4=>mdout1_3_13, DO5=>mdout1_3_14,
+ DO6=>mdout1_3_15, DO7=>mdout1_3_16, DO8=>mdout1_3_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_3_2_17: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_14, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_3_18, DO1=>mdout1_3_19, DO2=>mdout1_3_20,
+ DO3=>mdout1_3_21, DO4=>mdout1_3_22, DO5=>mdout1_3_23,
+ DO6=>mdout1_3_24, DO7=>mdout1_3_25, DO8=>mdout1_3_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_3_3_16: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_15, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_3_27, DO1=>mdout1_3_28, DO2=>mdout1_3_29,
+ DO3=>mdout1_3_30, DO4=>mdout1_3_31, DO5=>mdout1_3_32,
+ DO6=>mdout1_3_33, DO7=>mdout1_3_34, DO8=>mdout1_3_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_4_0_15: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "100", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_16, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_4_0, DO1=>mdout1_4_1, DO2=>mdout1_4_2,
+ DO3=>mdout1_4_3, DO4=>mdout1_4_4, DO5=>mdout1_4_5,
+ DO6=>mdout1_4_6, DO7=>mdout1_4_7, DO8=>mdout1_4_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_4_1_14: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "100", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_17, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_4_9, DO1=>mdout1_4_10, DO2=>mdout1_4_11,
+ DO3=>mdout1_4_12, DO4=>mdout1_4_13, DO5=>mdout1_4_14,
+ DO6=>mdout1_4_15, DO7=>mdout1_4_16, DO8=>mdout1_4_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_4_2_13: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "100", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_18, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_4_18, DO1=>mdout1_4_19, DO2=>mdout1_4_20,
+ DO3=>mdout1_4_21, DO4=>mdout1_4_22, DO5=>mdout1_4_23,
+ DO6=>mdout1_4_24, DO7=>mdout1_4_25, DO8=>mdout1_4_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_4_3_12: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "100", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_19, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_4_27, DO1=>mdout1_4_28, DO2=>mdout1_4_29,
+ DO3=>mdout1_4_30, DO4=>mdout1_4_31, DO5=>mdout1_4_32,
+ DO6=>mdout1_4_33, DO7=>mdout1_4_34, DO8=>mdout1_4_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_5_0_11: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "101", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_20, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_5_0, DO1=>mdout1_5_1, DO2=>mdout1_5_2,
+ DO3=>mdout1_5_3, DO4=>mdout1_5_4, DO5=>mdout1_5_5,
+ DO6=>mdout1_5_6, DO7=>mdout1_5_7, DO8=>mdout1_5_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_5_1_10: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "101", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_21, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_5_9, DO1=>mdout1_5_10, DO2=>mdout1_5_11,
+ DO3=>mdout1_5_12, DO4=>mdout1_5_13, DO5=>mdout1_5_14,
+ DO6=>mdout1_5_15, DO7=>mdout1_5_16, DO8=>mdout1_5_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_5_2_9: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "101", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_22, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_5_18, DO1=>mdout1_5_19, DO2=>mdout1_5_20,
+ DO3=>mdout1_5_21, DO4=>mdout1_5_22, DO5=>mdout1_5_23,
+ DO6=>mdout1_5_24, DO7=>mdout1_5_25, DO8=>mdout1_5_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_5_3_8: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "101", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_23, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_5_27, DO1=>mdout1_5_28, DO2=>mdout1_5_29,
+ DO3=>mdout1_5_30, DO4=>mdout1_5_31, DO5=>mdout1_5_32,
+ DO6=>mdout1_5_33, DO7=>mdout1_5_34, DO8=>mdout1_5_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_6_0_7: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "110", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_24, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_6_0, DO1=>mdout1_6_1, DO2=>mdout1_6_2,
+ DO3=>mdout1_6_3, DO4=>mdout1_6_4, DO5=>mdout1_6_5,
+ DO6=>mdout1_6_6, DO7=>mdout1_6_7, DO8=>mdout1_6_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_6_1_6: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "110", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_25, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_6_9, DO1=>mdout1_6_10, DO2=>mdout1_6_11,
+ DO3=>mdout1_6_12, DO4=>mdout1_6_13, DO5=>mdout1_6_14,
+ DO6=>mdout1_6_15, DO7=>mdout1_6_16, DO8=>mdout1_6_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_6_2_5: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "110", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_26, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_6_18, DO1=>mdout1_6_19, DO2=>mdout1_6_20,
+ DO3=>mdout1_6_21, DO4=>mdout1_6_22, DO5=>mdout1_6_23,
+ DO6=>mdout1_6_24, DO7=>mdout1_6_25, DO8=>mdout1_6_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_6_3_4: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "110", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_27, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_6_27, DO1=>mdout1_6_28, DO2=>mdout1_6_29,
+ DO3=>mdout1_6_30, DO4=>mdout1_6_31, DO5=>mdout1_6_32,
+ DO6=>mdout1_6_33, DO7=>mdout1_6_34, DO8=>mdout1_6_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_7_0_3: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "111", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_28, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_7_0, DO1=>mdout1_7_1, DO2=>mdout1_7_2,
+ DO3=>mdout1_7_3, DO4=>mdout1_7_4, DO5=>mdout1_7_5,
+ DO6=>mdout1_7_6, DO7=>mdout1_7_7, DO8=>mdout1_7_8, DO9=>open,
+ DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>open, DO19=>open,
+ DO20=>open, DO21=>open, DO22=>open, DO23=>open, DO24=>open,
+ DO25=>open, DO26=>open, DO27=>open, DO28=>open, DO29=>open,
+ DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open,
+ DO35=>open);
+
+ pdp_ram_7_1_2: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "111", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_29, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_7_9, DO1=>mdout1_7_10, DO2=>mdout1_7_11,
+ DO3=>mdout1_7_12, DO4=>mdout1_7_13, DO5=>mdout1_7_14,
+ DO6=>mdout1_7_15, DO7=>mdout1_7_16, DO8=>mdout1_7_17,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_7_2_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "111", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_30, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_7_18, DO1=>mdout1_7_19, DO2=>mdout1_7_20,
+ DO3=>mdout1_7_21, DO4=>mdout1_7_22, DO5=>mdout1_7_23,
+ DO6=>mdout1_7_24, DO7=>mdout1_7_25, DO8=>mdout1_7_26,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_7_3_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "111", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>wptr_13, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_cr0_31, CSR1=>rptr_12, CSR2=>rptr_13, RST=>Reset,
+ DO0=>mdout1_7_27, DO1=>mdout1_7_28, DO2=>mdout1_7_29,
+ DO3=>mdout1_7_30, DO4=>mdout1_7_31, DO5=>mdout1_7_32,
+ DO6=>mdout1_7_33, DO7=>mdout1_7_34, DO8=>mdout1_7_35,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_14);
+
+ FF_83: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_82: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_81: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_66: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_14);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_14);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_13);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_14);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_13_ff);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff2);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff2);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_13_ff2);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC1=>fcount_13, PC0=>fcount_12, CON=>cnt_con,
+ CO=>co6, NC1=>ifcount_13, NC0=>ifcount_12);
+
+ bdcnt_bctr_7: CB2
+ port map (CI=>co6, PC1=>scuba_vlo, PC0=>fcount_14, CON=>cnt_con,
+ CO=>co7, NC1=>open, NC0=>ifcount_14);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co5_1, LE=>co6_1);
+
+ e_cmp_7: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_14, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co6_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i, B0=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>wren_i, B0=>wren_i,
+ CI=>co5_2, GE=>co6_2);
+
+ g_cmp_7: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_14, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co6_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_3,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC1=>wcount_13, PC0=>wcount_12, CO=>co6_3,
+ NC1=>iwcount_13, NC0=>iwcount_12);
+
+ w_ctr_7: CU2
+ port map (CI=>co6_3, PC1=>scuba_vlo, PC0=>wcount_14, CO=>co7_1,
+ NC1=>open, NC0=>iwcount_14);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_4,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC1=>rcount_13, PC0=>rcount_12, CO=>co6_4,
+ NC1=>ircount_13, NC0=>ircount_12);
+
+ r_ctr_7: CU2
+ port map (CI=>co6_4, PC1=>scuba_vlo, PC0=>rcount_14, CO=>co7_2,
+ NC1=>open, NC0=>ircount_14);
+
+ mux_35: MUX81
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(0));
+
+ mux_34: MUX81
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(1));
+
+ mux_33: MUX81
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(2));
+
+ mux_32: MUX81
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(3));
+
+ mux_31: MUX81
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(4));
+
+ mux_30: MUX81
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(5));
+
+ mux_29: MUX81
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(6));
+
+ mux_28: MUX81
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(7));
+
+ mux_27: MUX81
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(8));
+
+ mux_26: MUX81
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
+ D6=>mdout1_6_9, D7=>mdout1_7_9, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(9));
+
+ mux_25: MUX81
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
+ D6=>mdout1_6_10, D7=>mdout1_7_10, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(10));
+
+ mux_24: MUX81
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
+ D6=>mdout1_6_11, D7=>mdout1_7_11, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(11));
+
+ mux_23: MUX81
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
+ D6=>mdout1_6_12, D7=>mdout1_7_12, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(12));
+
+ mux_22: MUX81
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
+ D6=>mdout1_6_13, D7=>mdout1_7_13, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(13));
+
+ mux_21: MUX81
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
+ D6=>mdout1_6_14, D7=>mdout1_7_14, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(14));
+
+ mux_20: MUX81
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
+ D6=>mdout1_6_15, D7=>mdout1_7_15, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(15));
+
+ mux_19: MUX81
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
+ D6=>mdout1_6_16, D7=>mdout1_7_16, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(16));
+
+ mux_18: MUX81
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
+ D6=>mdout1_6_17, D7=>mdout1_7_17, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(17));
+
+ mux_17: MUX81
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
+ D6=>mdout1_6_18, D7=>mdout1_7_18, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(18));
+
+ mux_16: MUX81
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
+ D6=>mdout1_6_19, D7=>mdout1_7_19, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(19));
+
+ mux_15: MUX81
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
+ D6=>mdout1_6_20, D7=>mdout1_7_20, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(20));
+
+ mux_14: MUX81
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
+ D6=>mdout1_6_21, D7=>mdout1_7_21, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(21));
+
+ mux_13: MUX81
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
+ D6=>mdout1_6_22, D7=>mdout1_7_22, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(22));
+
+ mux_12: MUX81
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
+ D6=>mdout1_6_23, D7=>mdout1_7_23, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(23));
+
+ mux_11: MUX81
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
+ D6=>mdout1_6_24, D7=>mdout1_7_24, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(24));
+
+ mux_10: MUX81
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
+ D6=>mdout1_6_25, D7=>mdout1_7_25, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(25));
+
+ mux_9: MUX81
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
+ D6=>mdout1_6_26, D7=>mdout1_7_26, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(26));
+
+ mux_8: MUX81
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
+ D6=>mdout1_6_27, D7=>mdout1_7_27, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(27));
+
+ mux_7: MUX81
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
+ D6=>mdout1_6_28, D7=>mdout1_7_28, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(28));
+
+ mux_6: MUX81
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
+ D6=>mdout1_6_29, D7=>mdout1_7_29, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(29));
+
+ mux_5: MUX81
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
+ D6=>mdout1_6_30, D7=>mdout1_7_30, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(30));
+
+ mux_4: MUX81
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
+ D6=>mdout1_6_31, D7=>mdout1_7_31, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(31));
+
+ mux_3: MUX81
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
+ D6=>mdout1_6_32, D7=>mdout1_7_32, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(32));
+
+ mux_2: MUX81
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
+ D6=>mdout1_6_33, D7=>mdout1_7_33, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(33));
+
+ mux_1: MUX81
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
+ D6=>mdout1_6_34, D7=>mdout1_7_34, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(34));
+
+ mux_0: MUX81
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
+ D6=>mdout1_6_35, D7=>mdout1_7_35, SD1=>rptr_11_ff2,
+ SD2=>rptr_12_ff2, SD3=>rptr_13_ff2, Z=>Q(35));
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcount_11, A0=>wcount_10, B1=>rptr_11, B0=>rptr_10,
+ BI=>co4_5, BOUT1=>co5_5, BOUT0=>open, S1=>wcnt_sub_11,
+ S0=>wcnt_sub_10);
+
+ wcnt_6: FSUB2
+ port map (A1=>wcount_13, A0=>wcount_12, B1=>rptr_13, B0=>rptr_12,
+ BI=>co5_5, BOUT1=>co6_5, BOUT0=>open, S1=>wcnt_sub_13,
+ S0=>wcnt_sub_12);
+
+ wcnt_7: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co6_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_14);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>AmFullThresh(11),
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>co5_6);
+
+ af_set_cmp_6: AGEB2
+ port map (A1=>wcnt_reg_13, A0=>wcnt_reg_12, B1=>AmFullThresh(13),
+ B0=>AmFullThresh(12), CI=>co5_6, GE=>co6_6);
+
+ af_set_cmp_7: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_14, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co6_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ WCNT(14) <= fcount_14;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x16k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX81 use entity SCM.MUX81(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x1k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:23:41\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=1024\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x1k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 1024 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:23:41 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x1k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(9 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(10 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x1k_oreg;
+
+architecture Structure of fifo_36x1k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal rptr_10: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co4_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_10: std_logic;
+ signal co4_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal co4_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal co4_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_36x1k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "18";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "18";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_36x1k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "18";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "18";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_10, B=>rptr_10, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 18,
+ DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vlo,
+ ADW3=>scuba_vlo, ADW4=>wptr_0, ADW5=>wptr_1, ADW6=>wptr_2,
+ ADW7=>wptr_3, ADW8=>wptr_4, ADW9=>wptr_5, ADW10=>wptr_6,
+ ADW11=>wptr_7, ADW12=>wptr_8, ADW13=>wptr_9, CEW=>wren_i,
+ CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>rptr_0, ADR5=>rptr_1,
+ ADR6=>rptr_2, ADR7=>rptr_3, ADR8=>rptr_4, ADR9=>rptr_5,
+ ADR10=>rptr_6, ADR11=>rptr_7, ADR12=>rptr_8, ADR13=>rptr_9,
+ CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2),
+ DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7),
+ DO8=>Q(8), DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12),
+ DO13=>Q(13), DO14=>Q(14), DO15=>Q(15), DO16=>Q(16),
+ DO17=>Q(17), DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 18,
+ DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>Data(27), DI10=>Data(28),
+ DI11=>Data(29), DI12=>Data(30), DI13=>Data(31),
+ DI14=>Data(32), DI15=>Data(33), DI16=>Data(34),
+ DI17=>Data(35), DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vhi, ADW1=>scuba_vhi,
+ ADW2=>scuba_vlo, ADW3=>scuba_vlo, ADW4=>wptr_0, ADW5=>wptr_1,
+ ADW6=>wptr_2, ADW7=>wptr_3, ADW8=>wptr_4, ADW9=>wptr_5,
+ ADW10=>wptr_6, ADW11=>wptr_7, ADW12=>wptr_8, ADW13=>wptr_9,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>rptr_0, ADR5=>rptr_1, ADR6=>rptr_2, ADR7=>rptr_3,
+ ADR8=>rptr_4, ADR9=>rptr_5, ADR10=>rptr_6, ADR11=>rptr_7,
+ ADR12=>rptr_8, ADR13=>rptr_9, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22),
+ DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27),
+ DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31),
+ DO14=>Q(32), DO15=>Q(33), DO16=>Q(34), DO17=>Q(35),
+ DO18=>open, DO19=>open, DO20=>open, DO21=>open, DO22=>open,
+ DO23=>open, DO24=>open, DO25=>open, DO26=>open, DO27=>open,
+ DO28=>open, DO29=>open, DO30=>open, DO31=>open, DO32=>open,
+ DO33=>open, DO34=>open, DO35=>open);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_57: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_55: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_44: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>scuba_vlo, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>open, NC0=>ifcount_10);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>scuba_vlo, PC0=>wcount_10, CO=>co5_1,
+ NC1=>open, NC0=>iwcount_10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>scuba_vlo, PC0=>rcount_10, CO=>co5_2,
+ NC1=>open, NC0=>ircount_10);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co4_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_10);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x1k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x256_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:20:48\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=256\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x256_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 256 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:20:48 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x256_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(7 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(8 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x256_oreg;
+
+architecture Structure of fifo_36x256_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal rptr_8: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co3_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal co3_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal co3_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x256_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_8, B=>rptr_8, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wptr_0, ADW6=>wptr_1,
+ ADW7=>wptr_2, ADW8=>wptr_3, ADW9=>wptr_4, ADW10=>wptr_5,
+ ADW11=>wptr_6, ADW12=>wptr_7, ADW13=>scuba_vlo, CEW=>wren_i,
+ CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
+ ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_47: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_45: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_36: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>scuba_vlo, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>open, NC0=>ifcount_8);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co3_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>scuba_vlo, PC0=>wcount_8, CO=>co4_1,
+ NC1=>open, NC0=>iwcount_8);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>scuba_vlo, PC0=>rcount_8, CO=>co4_2,
+ NC1=>open, NC0=>ircount_8);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co3_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_8);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x256_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x2k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:24:10\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=2048\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x2k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 2048 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:24:10 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x2k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(10 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(11 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x2k_oreg;
+
+architecture Structure of fifo_36x2k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal rptr_11: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co4_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co4_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal wcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co5_2: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal wcount_10: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_36x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_3 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_3 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_3 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_3 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_3 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_2 : label is "fifo_36x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_2 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_1_2 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_2 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_2 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_1 : label is "fifo_36x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_1 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_2_1 : label is "0b000";
+ attribute GSR of pdp_ram_0_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_0 : label is "fifo_36x2k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_3_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_3_0 : label is "0b000";
+ attribute GSR of pdp_ram_0_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_3_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_3_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_3_0 : label is "9";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_3: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vlo,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(0),
+ DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5),
+ DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_2: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>scuba_vlo, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(9), DO1=>Q(10), DO2=>Q(11), DO3=>Q(12),
+ DO4=>Q(13), DO5=>Q(14), DO6=>Q(15), DO7=>Q(16), DO8=>Q(17),
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_0_2_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>scuba_vlo, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21),
+ DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26),
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_0_3_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>scuba_vlo, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>Q(27), DO1=>Q(28), DO2=>Q(29), DO3=>Q(30),
+ DO4=>Q(31), DO5=>Q(32), DO6=>Q(33), DO7=>Q(34), DO8=>Q(35),
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_62: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_60: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_48: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i_inv,
+ B0=>wren_i, CI=>co4_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_1,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_2,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_10, B1=>scuba_vlo,
+ B0=>rptr_10, BI=>co4_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_11, S0=>wcnt_sub_10);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>scuba_vlo,
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x2k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x32k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:25:43\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=32768\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x32k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 32768 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:25:44 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x32k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(14 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x32k_oreg;
+
+architecture Structure of fifo_36x32k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal wptr_14_inv: std_logic;
+ signal rptr_14_inv: std_logic;
+ signal wptr_13_inv: std_logic;
+ signal rptr_13_inv: std_logic;
+ signal wptr_12_inv: std_logic;
+ signal rptr_12_inv: std_logic;
+ signal wptr_11_inv: std_logic;
+ signal rptr_11_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal dec1_r10: std_logic;
+ signal dec0_p00: std_logic;
+ signal dec3_r10: std_logic;
+ signal dec2_p00: std_logic;
+ signal dec5_r10: std_logic;
+ signal dec4_p00: std_logic;
+ signal dec7_r10: std_logic;
+ signal dec6_p00: std_logic;
+ signal dec9_r11: std_logic;
+ signal dec8_p01: std_logic;
+ signal dec11_r11: std_logic;
+ signal dec10_p01: std_logic;
+ signal dec13_r11: std_logic;
+ signal dec12_p01: std_logic;
+ signal dec15_r11: std_logic;
+ signal dec14_p01: std_logic;
+ signal dec17_r12: std_logic;
+ signal dec16_p02: std_logic;
+ signal dec19_r12: std_logic;
+ signal dec18_p02: std_logic;
+ signal dec21_r12: std_logic;
+ signal dec20_p02: std_logic;
+ signal dec23_r12: std_logic;
+ signal dec22_p02: std_logic;
+ signal dec25_r13: std_logic;
+ signal dec24_p03: std_logic;
+ signal dec27_r13: std_logic;
+ signal dec26_p03: std_logic;
+ signal dec29_r13: std_logic;
+ signal dec28_p03: std_logic;
+ signal dec31_r13: std_logic;
+ signal dec30_p03: std_logic;
+ signal dec33_r14: std_logic;
+ signal dec32_p04: std_logic;
+ signal dec35_r14: std_logic;
+ signal dec34_p04: std_logic;
+ signal dec37_r14: std_logic;
+ signal dec36_p04: std_logic;
+ signal dec39_r14: std_logic;
+ signal dec38_p04: std_logic;
+ signal dec41_r15: std_logic;
+ signal dec40_p05: std_logic;
+ signal dec43_r15: std_logic;
+ signal dec42_p05: std_logic;
+ signal dec45_r15: std_logic;
+ signal dec44_p05: std_logic;
+ signal dec47_r15: std_logic;
+ signal dec46_p05: std_logic;
+ signal dec49_r16: std_logic;
+ signal dec48_p06: std_logic;
+ signal dec51_r16: std_logic;
+ signal dec50_p06: std_logic;
+ signal dec53_r16: std_logic;
+ signal dec52_p06: std_logic;
+ signal dec55_r16: std_logic;
+ signal dec54_p06: std_logic;
+ signal dec57_r17: std_logic;
+ signal dec56_p07: std_logic;
+ signal dec59_r17: std_logic;
+ signal dec58_p07: std_logic;
+ signal dec61_r17: std_logic;
+ signal dec60_p07: std_logic;
+ signal dec63_r17: std_logic;
+ signal dec62_p07: std_logic;
+ signal dec65_r18: std_logic;
+ signal dec64_p08: std_logic;
+ signal dec67_r18: std_logic;
+ signal dec66_p08: std_logic;
+ signal dec69_r18: std_logic;
+ signal dec68_p08: std_logic;
+ signal dec71_r18: std_logic;
+ signal dec70_p08: std_logic;
+ signal dec73_r19: std_logic;
+ signal dec72_p09: std_logic;
+ signal dec75_r19: std_logic;
+ signal dec74_p09: std_logic;
+ signal dec77_r19: std_logic;
+ signal dec76_p09: std_logic;
+ signal dec79_r19: std_logic;
+ signal dec78_p09: std_logic;
+ signal dec81_r110: std_logic;
+ signal dec80_p010: std_logic;
+ signal dec83_r110: std_logic;
+ signal dec82_p010: std_logic;
+ signal dec85_r110: std_logic;
+ signal dec84_p010: std_logic;
+ signal dec87_r110: std_logic;
+ signal dec86_p010: std_logic;
+ signal dec89_r111: std_logic;
+ signal dec88_p011: std_logic;
+ signal dec91_r111: std_logic;
+ signal dec90_p011: std_logic;
+ signal dec93_r111: std_logic;
+ signal dec92_p011: std_logic;
+ signal dec95_r111: std_logic;
+ signal dec94_p011: std_logic;
+ signal dec97_r112: std_logic;
+ signal dec96_p012: std_logic;
+ signal dec99_r112: std_logic;
+ signal dec98_p012: std_logic;
+ signal dec101_r112: std_logic;
+ signal dec100_p012: std_logic;
+ signal dec103_r112: std_logic;
+ signal dec102_p012: std_logic;
+ signal dec105_r113: std_logic;
+ signal dec104_p013: std_logic;
+ signal dec107_r113: std_logic;
+ signal dec106_p013: std_logic;
+ signal dec109_r113: std_logic;
+ signal dec108_p013: std_logic;
+ signal dec111_r113: std_logic;
+ signal dec110_p013: std_logic;
+ signal dec113_r114: std_logic;
+ signal dec112_p014: std_logic;
+ signal dec115_r114: std_logic;
+ signal dec114_p014: std_logic;
+ signal dec117_r114: std_logic;
+ signal dec116_p014: std_logic;
+ signal dec119_r114: std_logic;
+ signal dec118_p014: std_logic;
+ signal dec121_r115: std_logic;
+ signal dec120_p015: std_logic;
+ signal dec123_r115: std_logic;
+ signal dec122_p015: std_logic;
+ signal dec125_r115: std_logic;
+ signal dec124_p015: std_logic;
+ signal dec127_r115: std_logic;
+ signal dec126_p015: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal wptr_14: std_logic;
+ signal wptr_15: std_logic;
+ signal rptr_15: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal rptr_13_ff: std_logic;
+ signal rptr_14_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co5: std_logic;
+ signal ifcount_14: std_logic;
+ signal ifcount_15: std_logic;
+ signal co7: std_logic;
+ signal co6: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co6_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co6_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_14: std_logic;
+ signal fcount_15: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5_3: std_logic;
+ signal iwcount_14: std_logic;
+ signal iwcount_15: std_logic;
+ signal co7_1: std_logic;
+ signal wcount_15: std_logic;
+ signal co6_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal co5_4: std_logic;
+ signal ircount_14: std_logic;
+ signal ircount_15: std_logic;
+ signal co7_2: std_logic;
+ signal rcount_14: std_logic;
+ signal rcount_15: std_logic;
+ signal co6_4: std_logic;
+ signal mdout1_15_0: std_logic;
+ signal mdout1_14_0: std_logic;
+ signal mdout1_13_0: std_logic;
+ signal mdout1_12_0: std_logic;
+ signal mdout1_11_0: std_logic;
+ signal mdout1_10_0: std_logic;
+ signal mdout1_9_0: std_logic;
+ signal mdout1_8_0: std_logic;
+ signal mdout1_7_0: std_logic;
+ signal mdout1_6_0: std_logic;
+ signal mdout1_5_0: std_logic;
+ signal mdout1_4_0: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_15_1: std_logic;
+ signal mdout1_14_1: std_logic;
+ signal mdout1_13_1: std_logic;
+ signal mdout1_12_1: std_logic;
+ signal mdout1_11_1: std_logic;
+ signal mdout1_10_1: std_logic;
+ signal mdout1_9_1: std_logic;
+ signal mdout1_8_1: std_logic;
+ signal mdout1_7_1: std_logic;
+ signal mdout1_6_1: std_logic;
+ signal mdout1_5_1: std_logic;
+ signal mdout1_4_1: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_15_2: std_logic;
+ signal mdout1_14_2: std_logic;
+ signal mdout1_13_2: std_logic;
+ signal mdout1_12_2: std_logic;
+ signal mdout1_11_2: std_logic;
+ signal mdout1_10_2: std_logic;
+ signal mdout1_9_2: std_logic;
+ signal mdout1_8_2: std_logic;
+ signal mdout1_7_2: std_logic;
+ signal mdout1_6_2: std_logic;
+ signal mdout1_5_2: std_logic;
+ signal mdout1_4_2: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_15_3: std_logic;
+ signal mdout1_14_3: std_logic;
+ signal mdout1_13_3: std_logic;
+ signal mdout1_12_3: std_logic;
+ signal mdout1_11_3: std_logic;
+ signal mdout1_10_3: std_logic;
+ signal mdout1_9_3: std_logic;
+ signal mdout1_8_3: std_logic;
+ signal mdout1_7_3: std_logic;
+ signal mdout1_6_3: std_logic;
+ signal mdout1_5_3: std_logic;
+ signal mdout1_4_3: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_15_4: std_logic;
+ signal mdout1_14_4: std_logic;
+ signal mdout1_13_4: std_logic;
+ signal mdout1_12_4: std_logic;
+ signal mdout1_11_4: std_logic;
+ signal mdout1_10_4: std_logic;
+ signal mdout1_9_4: std_logic;
+ signal mdout1_8_4: std_logic;
+ signal mdout1_7_4: std_logic;
+ signal mdout1_6_4: std_logic;
+ signal mdout1_5_4: std_logic;
+ signal mdout1_4_4: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_15_5: std_logic;
+ signal mdout1_14_5: std_logic;
+ signal mdout1_13_5: std_logic;
+ signal mdout1_12_5: std_logic;
+ signal mdout1_11_5: std_logic;
+ signal mdout1_10_5: std_logic;
+ signal mdout1_9_5: std_logic;
+ signal mdout1_8_5: std_logic;
+ signal mdout1_7_5: std_logic;
+ signal mdout1_6_5: std_logic;
+ signal mdout1_5_5: std_logic;
+ signal mdout1_4_5: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_15_6: std_logic;
+ signal mdout1_14_6: std_logic;
+ signal mdout1_13_6: std_logic;
+ signal mdout1_12_6: std_logic;
+ signal mdout1_11_6: std_logic;
+ signal mdout1_10_6: std_logic;
+ signal mdout1_9_6: std_logic;
+ signal mdout1_8_6: std_logic;
+ signal mdout1_7_6: std_logic;
+ signal mdout1_6_6: std_logic;
+ signal mdout1_5_6: std_logic;
+ signal mdout1_4_6: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_15_7: std_logic;
+ signal mdout1_14_7: std_logic;
+ signal mdout1_13_7: std_logic;
+ signal mdout1_12_7: std_logic;
+ signal mdout1_11_7: std_logic;
+ signal mdout1_10_7: std_logic;
+ signal mdout1_9_7: std_logic;
+ signal mdout1_8_7: std_logic;
+ signal mdout1_7_7: std_logic;
+ signal mdout1_6_7: std_logic;
+ signal mdout1_5_7: std_logic;
+ signal mdout1_4_7: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_15_8: std_logic;
+ signal mdout1_14_8: std_logic;
+ signal mdout1_13_8: std_logic;
+ signal mdout1_12_8: std_logic;
+ signal mdout1_11_8: std_logic;
+ signal mdout1_10_8: std_logic;
+ signal mdout1_9_8: std_logic;
+ signal mdout1_8_8: std_logic;
+ signal mdout1_7_8: std_logic;
+ signal mdout1_6_8: std_logic;
+ signal mdout1_5_8: std_logic;
+ signal mdout1_4_8: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_15_9: std_logic;
+ signal mdout1_14_9: std_logic;
+ signal mdout1_13_9: std_logic;
+ signal mdout1_12_9: std_logic;
+ signal mdout1_11_9: std_logic;
+ signal mdout1_10_9: std_logic;
+ signal mdout1_9_9: std_logic;
+ signal mdout1_8_9: std_logic;
+ signal mdout1_7_9: std_logic;
+ signal mdout1_6_9: std_logic;
+ signal mdout1_5_9: std_logic;
+ signal mdout1_4_9: std_logic;
+ signal mdout1_3_9: std_logic;
+ signal mdout1_2_9: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_15_10: std_logic;
+ signal mdout1_14_10: std_logic;
+ signal mdout1_13_10: std_logic;
+ signal mdout1_12_10: std_logic;
+ signal mdout1_11_10: std_logic;
+ signal mdout1_10_10: std_logic;
+ signal mdout1_9_10: std_logic;
+ signal mdout1_8_10: std_logic;
+ signal mdout1_7_10: std_logic;
+ signal mdout1_6_10: std_logic;
+ signal mdout1_5_10: std_logic;
+ signal mdout1_4_10: std_logic;
+ signal mdout1_3_10: std_logic;
+ signal mdout1_2_10: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_15_11: std_logic;
+ signal mdout1_14_11: std_logic;
+ signal mdout1_13_11: std_logic;
+ signal mdout1_12_11: std_logic;
+ signal mdout1_11_11: std_logic;
+ signal mdout1_10_11: std_logic;
+ signal mdout1_9_11: std_logic;
+ signal mdout1_8_11: std_logic;
+ signal mdout1_7_11: std_logic;
+ signal mdout1_6_11: std_logic;
+ signal mdout1_5_11: std_logic;
+ signal mdout1_4_11: std_logic;
+ signal mdout1_3_11: std_logic;
+ signal mdout1_2_11: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_15_12: std_logic;
+ signal mdout1_14_12: std_logic;
+ signal mdout1_13_12: std_logic;
+ signal mdout1_12_12: std_logic;
+ signal mdout1_11_12: std_logic;
+ signal mdout1_10_12: std_logic;
+ signal mdout1_9_12: std_logic;
+ signal mdout1_8_12: std_logic;
+ signal mdout1_7_12: std_logic;
+ signal mdout1_6_12: std_logic;
+ signal mdout1_5_12: std_logic;
+ signal mdout1_4_12: std_logic;
+ signal mdout1_3_12: std_logic;
+ signal mdout1_2_12: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_15_13: std_logic;
+ signal mdout1_14_13: std_logic;
+ signal mdout1_13_13: std_logic;
+ signal mdout1_12_13: std_logic;
+ signal mdout1_11_13: std_logic;
+ signal mdout1_10_13: std_logic;
+ signal mdout1_9_13: std_logic;
+ signal mdout1_8_13: std_logic;
+ signal mdout1_7_13: std_logic;
+ signal mdout1_6_13: std_logic;
+ signal mdout1_5_13: std_logic;
+ signal mdout1_4_13: std_logic;
+ signal mdout1_3_13: std_logic;
+ signal mdout1_2_13: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_15_14: std_logic;
+ signal mdout1_14_14: std_logic;
+ signal mdout1_13_14: std_logic;
+ signal mdout1_12_14: std_logic;
+ signal mdout1_11_14: std_logic;
+ signal mdout1_10_14: std_logic;
+ signal mdout1_9_14: std_logic;
+ signal mdout1_8_14: std_logic;
+ signal mdout1_7_14: std_logic;
+ signal mdout1_6_14: std_logic;
+ signal mdout1_5_14: std_logic;
+ signal mdout1_4_14: std_logic;
+ signal mdout1_3_14: std_logic;
+ signal mdout1_2_14: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_15_15: std_logic;
+ signal mdout1_14_15: std_logic;
+ signal mdout1_13_15: std_logic;
+ signal mdout1_12_15: std_logic;
+ signal mdout1_11_15: std_logic;
+ signal mdout1_10_15: std_logic;
+ signal mdout1_9_15: std_logic;
+ signal mdout1_8_15: std_logic;
+ signal mdout1_7_15: std_logic;
+ signal mdout1_6_15: std_logic;
+ signal mdout1_5_15: std_logic;
+ signal mdout1_4_15: std_logic;
+ signal mdout1_3_15: std_logic;
+ signal mdout1_2_15: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_15_16: std_logic;
+ signal mdout1_14_16: std_logic;
+ signal mdout1_13_16: std_logic;
+ signal mdout1_12_16: std_logic;
+ signal mdout1_11_16: std_logic;
+ signal mdout1_10_16: std_logic;
+ signal mdout1_9_16: std_logic;
+ signal mdout1_8_16: std_logic;
+ signal mdout1_7_16: std_logic;
+ signal mdout1_6_16: std_logic;
+ signal mdout1_5_16: std_logic;
+ signal mdout1_4_16: std_logic;
+ signal mdout1_3_16: std_logic;
+ signal mdout1_2_16: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal mdout1_15_17: std_logic;
+ signal mdout1_14_17: std_logic;
+ signal mdout1_13_17: std_logic;
+ signal mdout1_12_17: std_logic;
+ signal mdout1_11_17: std_logic;
+ signal mdout1_10_17: std_logic;
+ signal mdout1_9_17: std_logic;
+ signal mdout1_8_17: std_logic;
+ signal mdout1_7_17: std_logic;
+ signal mdout1_6_17: std_logic;
+ signal mdout1_5_17: std_logic;
+ signal mdout1_4_17: std_logic;
+ signal mdout1_3_17: std_logic;
+ signal mdout1_2_17: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal mdout1_15_18: std_logic;
+ signal mdout1_14_18: std_logic;
+ signal mdout1_13_18: std_logic;
+ signal mdout1_12_18: std_logic;
+ signal mdout1_11_18: std_logic;
+ signal mdout1_10_18: std_logic;
+ signal mdout1_9_18: std_logic;
+ signal mdout1_8_18: std_logic;
+ signal mdout1_7_18: std_logic;
+ signal mdout1_6_18: std_logic;
+ signal mdout1_5_18: std_logic;
+ signal mdout1_4_18: std_logic;
+ signal mdout1_3_18: std_logic;
+ signal mdout1_2_18: std_logic;
+ signal mdout1_1_18: std_logic;
+ signal mdout1_0_18: std_logic;
+ signal mdout1_15_19: std_logic;
+ signal mdout1_14_19: std_logic;
+ signal mdout1_13_19: std_logic;
+ signal mdout1_12_19: std_logic;
+ signal mdout1_11_19: std_logic;
+ signal mdout1_10_19: std_logic;
+ signal mdout1_9_19: std_logic;
+ signal mdout1_8_19: std_logic;
+ signal mdout1_7_19: std_logic;
+ signal mdout1_6_19: std_logic;
+ signal mdout1_5_19: std_logic;
+ signal mdout1_4_19: std_logic;
+ signal mdout1_3_19: std_logic;
+ signal mdout1_2_19: std_logic;
+ signal mdout1_1_19: std_logic;
+ signal mdout1_0_19: std_logic;
+ signal mdout1_15_20: std_logic;
+ signal mdout1_14_20: std_logic;
+ signal mdout1_13_20: std_logic;
+ signal mdout1_12_20: std_logic;
+ signal mdout1_11_20: std_logic;
+ signal mdout1_10_20: std_logic;
+ signal mdout1_9_20: std_logic;
+ signal mdout1_8_20: std_logic;
+ signal mdout1_7_20: std_logic;
+ signal mdout1_6_20: std_logic;
+ signal mdout1_5_20: std_logic;
+ signal mdout1_4_20: std_logic;
+ signal mdout1_3_20: std_logic;
+ signal mdout1_2_20: std_logic;
+ signal mdout1_1_20: std_logic;
+ signal mdout1_0_20: std_logic;
+ signal mdout1_15_21: std_logic;
+ signal mdout1_14_21: std_logic;
+ signal mdout1_13_21: std_logic;
+ signal mdout1_12_21: std_logic;
+ signal mdout1_11_21: std_logic;
+ signal mdout1_10_21: std_logic;
+ signal mdout1_9_21: std_logic;
+ signal mdout1_8_21: std_logic;
+ signal mdout1_7_21: std_logic;
+ signal mdout1_6_21: std_logic;
+ signal mdout1_5_21: std_logic;
+ signal mdout1_4_21: std_logic;
+ signal mdout1_3_21: std_logic;
+ signal mdout1_2_21: std_logic;
+ signal mdout1_1_21: std_logic;
+ signal mdout1_0_21: std_logic;
+ signal mdout1_15_22: std_logic;
+ signal mdout1_14_22: std_logic;
+ signal mdout1_13_22: std_logic;
+ signal mdout1_12_22: std_logic;
+ signal mdout1_11_22: std_logic;
+ signal mdout1_10_22: std_logic;
+ signal mdout1_9_22: std_logic;
+ signal mdout1_8_22: std_logic;
+ signal mdout1_7_22: std_logic;
+ signal mdout1_6_22: std_logic;
+ signal mdout1_5_22: std_logic;
+ signal mdout1_4_22: std_logic;
+ signal mdout1_3_22: std_logic;
+ signal mdout1_2_22: std_logic;
+ signal mdout1_1_22: std_logic;
+ signal mdout1_0_22: std_logic;
+ signal mdout1_15_23: std_logic;
+ signal mdout1_14_23: std_logic;
+ signal mdout1_13_23: std_logic;
+ signal mdout1_12_23: std_logic;
+ signal mdout1_11_23: std_logic;
+ signal mdout1_10_23: std_logic;
+ signal mdout1_9_23: std_logic;
+ signal mdout1_8_23: std_logic;
+ signal mdout1_7_23: std_logic;
+ signal mdout1_6_23: std_logic;
+ signal mdout1_5_23: std_logic;
+ signal mdout1_4_23: std_logic;
+ signal mdout1_3_23: std_logic;
+ signal mdout1_2_23: std_logic;
+ signal mdout1_1_23: std_logic;
+ signal mdout1_0_23: std_logic;
+ signal mdout1_15_24: std_logic;
+ signal mdout1_14_24: std_logic;
+ signal mdout1_13_24: std_logic;
+ signal mdout1_12_24: std_logic;
+ signal mdout1_11_24: std_logic;
+ signal mdout1_10_24: std_logic;
+ signal mdout1_9_24: std_logic;
+ signal mdout1_8_24: std_logic;
+ signal mdout1_7_24: std_logic;
+ signal mdout1_6_24: std_logic;
+ signal mdout1_5_24: std_logic;
+ signal mdout1_4_24: std_logic;
+ signal mdout1_3_24: std_logic;
+ signal mdout1_2_24: std_logic;
+ signal mdout1_1_24: std_logic;
+ signal mdout1_0_24: std_logic;
+ signal mdout1_15_25: std_logic;
+ signal mdout1_14_25: std_logic;
+ signal mdout1_13_25: std_logic;
+ signal mdout1_12_25: std_logic;
+ signal mdout1_11_25: std_logic;
+ signal mdout1_10_25: std_logic;
+ signal mdout1_9_25: std_logic;
+ signal mdout1_8_25: std_logic;
+ signal mdout1_7_25: std_logic;
+ signal mdout1_6_25: std_logic;
+ signal mdout1_5_25: std_logic;
+ signal mdout1_4_25: std_logic;
+ signal mdout1_3_25: std_logic;
+ signal mdout1_2_25: std_logic;
+ signal mdout1_1_25: std_logic;
+ signal mdout1_0_25: std_logic;
+ signal mdout1_15_26: std_logic;
+ signal mdout1_14_26: std_logic;
+ signal mdout1_13_26: std_logic;
+ signal mdout1_12_26: std_logic;
+ signal mdout1_11_26: std_logic;
+ signal mdout1_10_26: std_logic;
+ signal mdout1_9_26: std_logic;
+ signal mdout1_8_26: std_logic;
+ signal mdout1_7_26: std_logic;
+ signal mdout1_6_26: std_logic;
+ signal mdout1_5_26: std_logic;
+ signal mdout1_4_26: std_logic;
+ signal mdout1_3_26: std_logic;
+ signal mdout1_2_26: std_logic;
+ signal mdout1_1_26: std_logic;
+ signal mdout1_0_26: std_logic;
+ signal mdout1_15_27: std_logic;
+ signal mdout1_14_27: std_logic;
+ signal mdout1_13_27: std_logic;
+ signal mdout1_12_27: std_logic;
+ signal mdout1_11_27: std_logic;
+ signal mdout1_10_27: std_logic;
+ signal mdout1_9_27: std_logic;
+ signal mdout1_8_27: std_logic;
+ signal mdout1_7_27: std_logic;
+ signal mdout1_6_27: std_logic;
+ signal mdout1_5_27: std_logic;
+ signal mdout1_4_27: std_logic;
+ signal mdout1_3_27: std_logic;
+ signal mdout1_2_27: std_logic;
+ signal mdout1_1_27: std_logic;
+ signal mdout1_0_27: std_logic;
+ signal mdout1_15_28: std_logic;
+ signal mdout1_14_28: std_logic;
+ signal mdout1_13_28: std_logic;
+ signal mdout1_12_28: std_logic;
+ signal mdout1_11_28: std_logic;
+ signal mdout1_10_28: std_logic;
+ signal mdout1_9_28: std_logic;
+ signal mdout1_8_28: std_logic;
+ signal mdout1_7_28: std_logic;
+ signal mdout1_6_28: std_logic;
+ signal mdout1_5_28: std_logic;
+ signal mdout1_4_28: std_logic;
+ signal mdout1_3_28: std_logic;
+ signal mdout1_2_28: std_logic;
+ signal mdout1_1_28: std_logic;
+ signal mdout1_0_28: std_logic;
+ signal mdout1_15_29: std_logic;
+ signal mdout1_14_29: std_logic;
+ signal mdout1_13_29: std_logic;
+ signal mdout1_12_29: std_logic;
+ signal mdout1_11_29: std_logic;
+ signal mdout1_10_29: std_logic;
+ signal mdout1_9_29: std_logic;
+ signal mdout1_8_29: std_logic;
+ signal mdout1_7_29: std_logic;
+ signal mdout1_6_29: std_logic;
+ signal mdout1_5_29: std_logic;
+ signal mdout1_4_29: std_logic;
+ signal mdout1_3_29: std_logic;
+ signal mdout1_2_29: std_logic;
+ signal mdout1_1_29: std_logic;
+ signal mdout1_0_29: std_logic;
+ signal mdout1_15_30: std_logic;
+ signal mdout1_14_30: std_logic;
+ signal mdout1_13_30: std_logic;
+ signal mdout1_12_30: std_logic;
+ signal mdout1_11_30: std_logic;
+ signal mdout1_10_30: std_logic;
+ signal mdout1_9_30: std_logic;
+ signal mdout1_8_30: std_logic;
+ signal mdout1_7_30: std_logic;
+ signal mdout1_6_30: std_logic;
+ signal mdout1_5_30: std_logic;
+ signal mdout1_4_30: std_logic;
+ signal mdout1_3_30: std_logic;
+ signal mdout1_2_30: std_logic;
+ signal mdout1_1_30: std_logic;
+ signal mdout1_0_30: std_logic;
+ signal mdout1_15_31: std_logic;
+ signal mdout1_14_31: std_logic;
+ signal mdout1_13_31: std_logic;
+ signal mdout1_12_31: std_logic;
+ signal mdout1_11_31: std_logic;
+ signal mdout1_10_31: std_logic;
+ signal mdout1_9_31: std_logic;
+ signal mdout1_8_31: std_logic;
+ signal mdout1_7_31: std_logic;
+ signal mdout1_6_31: std_logic;
+ signal mdout1_5_31: std_logic;
+ signal mdout1_4_31: std_logic;
+ signal mdout1_3_31: std_logic;
+ signal mdout1_2_31: std_logic;
+ signal mdout1_1_31: std_logic;
+ signal mdout1_0_31: std_logic;
+ signal mdout1_15_32: std_logic;
+ signal mdout1_14_32: std_logic;
+ signal mdout1_13_32: std_logic;
+ signal mdout1_12_32: std_logic;
+ signal mdout1_11_32: std_logic;
+ signal mdout1_10_32: std_logic;
+ signal mdout1_9_32: std_logic;
+ signal mdout1_8_32: std_logic;
+ signal mdout1_7_32: std_logic;
+ signal mdout1_6_32: std_logic;
+ signal mdout1_5_32: std_logic;
+ signal mdout1_4_32: std_logic;
+ signal mdout1_3_32: std_logic;
+ signal mdout1_2_32: std_logic;
+ signal mdout1_1_32: std_logic;
+ signal mdout1_0_32: std_logic;
+ signal mdout1_15_33: std_logic;
+ signal mdout1_14_33: std_logic;
+ signal mdout1_13_33: std_logic;
+ signal mdout1_12_33: std_logic;
+ signal mdout1_11_33: std_logic;
+ signal mdout1_10_33: std_logic;
+ signal mdout1_9_33: std_logic;
+ signal mdout1_8_33: std_logic;
+ signal mdout1_7_33: std_logic;
+ signal mdout1_6_33: std_logic;
+ signal mdout1_5_33: std_logic;
+ signal mdout1_4_33: std_logic;
+ signal mdout1_3_33: std_logic;
+ signal mdout1_2_33: std_logic;
+ signal mdout1_1_33: std_logic;
+ signal mdout1_0_33: std_logic;
+ signal mdout1_15_34: std_logic;
+ signal mdout1_14_34: std_logic;
+ signal mdout1_13_34: std_logic;
+ signal mdout1_12_34: std_logic;
+ signal mdout1_11_34: std_logic;
+ signal mdout1_10_34: std_logic;
+ signal mdout1_9_34: std_logic;
+ signal mdout1_8_34: std_logic;
+ signal mdout1_7_34: std_logic;
+ signal mdout1_6_34: std_logic;
+ signal mdout1_5_34: std_logic;
+ signal mdout1_4_34: std_logic;
+ signal mdout1_3_34: std_logic;
+ signal mdout1_2_34: std_logic;
+ signal mdout1_1_34: std_logic;
+ signal mdout1_0_34: std_logic;
+ signal rptr_14_ff2: std_logic;
+ signal rptr_13_ff2: std_logic;
+ signal rptr_12_ff2: std_logic;
+ signal rptr_11_ff2: std_logic;
+ signal mdout1_15_35: std_logic;
+ signal mdout1_14_35: std_logic;
+ signal mdout1_13_35: std_logic;
+ signal mdout1_12_35: std_logic;
+ signal mdout1_11_35: std_logic;
+ signal mdout1_10_35: std_logic;
+ signal mdout1_9_35: std_logic;
+ signal mdout1_8_35: std_logic;
+ signal mdout1_7_35: std_logic;
+ signal mdout1_6_35: std_logic;
+ signal mdout1_5_35: std_logic;
+ signal mdout1_4_35: std_logic;
+ signal mdout1_3_35: std_logic;
+ signal mdout1_2_35: std_logic;
+ signal mdout1_1_35: std_logic;
+ signal mdout1_0_35: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_11: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal co5_5: std_logic;
+ signal rptr_12: std_logic;
+ signal rptr_13: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal wcnt_sub_14: std_logic;
+ signal wcnt_sub_15: std_logic;
+ signal co6_5: std_logic;
+ signal rptr_14: std_logic;
+ signal wcount_14: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal co6_6: std_logic;
+ signal wcnt_reg_14: std_logic;
+ signal wcnt_reg_15: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX161
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; D4: in std_logic; D5: in std_logic;
+ D6: in std_logic; D7: in std_logic; D8: in std_logic;
+ D9: in std_logic; D10: in std_logic; D11: in std_logic;
+ D12: in std_logic; D13: in std_logic; D14: in std_logic;
+ D15: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ SD3: in std_logic; SD4: in std_logic; Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_129 : label is "0x3232";
+ attribute initval of LUT4_128 : label is "0x3232";
+ attribute initval of LUT4_127 : label is "0x8000";
+ attribute initval of LUT4_126 : label is "0x8000";
+ attribute initval of LUT4_125 : label is "0x8000";
+ attribute initval of LUT4_124 : label is "0x8000";
+ attribute initval of LUT4_123 : label is "0x8000";
+ attribute initval of LUT4_122 : label is "0x8000";
+ attribute initval of LUT4_121 : label is "0x8000";
+ attribute initval of LUT4_120 : label is "0x8000";
+ attribute initval of LUT4_119 : label is "0x8000";
+ attribute initval of LUT4_118 : label is "0x8000";
+ attribute initval of LUT4_117 : label is "0x8000";
+ attribute initval of LUT4_116 : label is "0x8000";
+ attribute initval of LUT4_115 : label is "0x8000";
+ attribute initval of LUT4_114 : label is "0x8000";
+ attribute initval of LUT4_113 : label is "0x8000";
+ attribute initval of LUT4_112 : label is "0x8000";
+ attribute initval of LUT4_111 : label is "0x8000";
+ attribute initval of LUT4_110 : label is "0x8000";
+ attribute initval of LUT4_109 : label is "0x8000";
+ attribute initval of LUT4_108 : label is "0x8000";
+ attribute initval of LUT4_107 : label is "0x8000";
+ attribute initval of LUT4_106 : label is "0x8000";
+ attribute initval of LUT4_105 : label is "0x8000";
+ attribute initval of LUT4_104 : label is "0x8000";
+ attribute initval of LUT4_103 : label is "0x8000";
+ attribute initval of LUT4_102 : label is "0x8000";
+ attribute initval of LUT4_101 : label is "0x8000";
+ attribute initval of LUT4_100 : label is "0x8000";
+ attribute initval of LUT4_99 : label is "0x8000";
+ attribute initval of LUT4_98 : label is "0x8000";
+ attribute initval of LUT4_97 : label is "0x8000";
+ attribute initval of LUT4_96 : label is "0x8000";
+ attribute initval of LUT4_95 : label is "0x8000";
+ attribute initval of LUT4_94 : label is "0x8000";
+ attribute initval of LUT4_93 : label is "0x8000";
+ attribute initval of LUT4_92 : label is "0x8000";
+ attribute initval of LUT4_91 : label is "0x8000";
+ attribute initval of LUT4_90 : label is "0x8000";
+ attribute initval of LUT4_89 : label is "0x8000";
+ attribute initval of LUT4_88 : label is "0x8000";
+ attribute initval of LUT4_87 : label is "0x8000";
+ attribute initval of LUT4_86 : label is "0x8000";
+ attribute initval of LUT4_85 : label is "0x8000";
+ attribute initval of LUT4_84 : label is "0x8000";
+ attribute initval of LUT4_83 : label is "0x8000";
+ attribute initval of LUT4_82 : label is "0x8000";
+ attribute initval of LUT4_81 : label is "0x8000";
+ attribute initval of LUT4_80 : label is "0x8000";
+ attribute initval of LUT4_79 : label is "0x8000";
+ attribute initval of LUT4_78 : label is "0x8000";
+ attribute initval of LUT4_77 : label is "0x8000";
+ attribute initval of LUT4_76 : label is "0x8000";
+ attribute initval of LUT4_75 : label is "0x8000";
+ attribute initval of LUT4_74 : label is "0x8000";
+ attribute initval of LUT4_73 : label is "0x8000";
+ attribute initval of LUT4_72 : label is "0x8000";
+ attribute initval of LUT4_71 : label is "0x8000";
+ attribute initval of LUT4_70 : label is "0x8000";
+ attribute initval of LUT4_69 : label is "0x8000";
+ attribute initval of LUT4_68 : label is "0x8000";
+ attribute initval of LUT4_67 : label is "0x8000";
+ attribute initval of LUT4_66 : label is "0x8000";
+ attribute initval of LUT4_65 : label is "0x8000";
+ attribute initval of LUT4_64 : label is "0x8000";
+ attribute initval of LUT4_63 : label is "0x8000";
+ attribute initval of LUT4_62 : label is "0x8000";
+ attribute initval of LUT4_61 : label is "0x8000";
+ attribute initval of LUT4_60 : label is "0x8000";
+ attribute initval of LUT4_59 : label is "0x8000";
+ attribute initval of LUT4_58 : label is "0x8000";
+ attribute initval of LUT4_57 : label is "0x8000";
+ attribute initval of LUT4_56 : label is "0x8000";
+ attribute initval of LUT4_55 : label is "0x8000";
+ attribute initval of LUT4_54 : label is "0x8000";
+ attribute initval of LUT4_53 : label is "0x8000";
+ attribute initval of LUT4_52 : label is "0x8000";
+ attribute initval of LUT4_51 : label is "0x8000";
+ attribute initval of LUT4_50 : label is "0x8000";
+ attribute initval of LUT4_49 : label is "0x8000";
+ attribute initval of LUT4_48 : label is "0x8000";
+ attribute initval of LUT4_47 : label is "0x8000";
+ attribute initval of LUT4_46 : label is "0x8000";
+ attribute initval of LUT4_45 : label is "0x8000";
+ attribute initval of LUT4_44 : label is "0x8000";
+ attribute initval of LUT4_43 : label is "0x8000";
+ attribute initval of LUT4_42 : label is "0x8000";
+ attribute initval of LUT4_41 : label is "0x8000";
+ attribute initval of LUT4_40 : label is "0x8000";
+ attribute initval of LUT4_39 : label is "0x8000";
+ attribute initval of LUT4_38 : label is "0x8000";
+ attribute initval of LUT4_37 : label is "0x8000";
+ attribute initval of LUT4_36 : label is "0x8000";
+ attribute initval of LUT4_35 : label is "0x8000";
+ attribute initval of LUT4_34 : label is "0x8000";
+ attribute initval of LUT4_33 : label is "0x8000";
+ attribute initval of LUT4_32 : label is "0x8000";
+ attribute initval of LUT4_31 : label is "0x8000";
+ attribute initval of LUT4_30 : label is "0x8000";
+ attribute initval of LUT4_29 : label is "0x8000";
+ attribute initval of LUT4_28 : label is "0x8000";
+ attribute initval of LUT4_27 : label is "0x8000";
+ attribute initval of LUT4_26 : label is "0x8000";
+ attribute initval of LUT4_25 : label is "0x8000";
+ attribute initval of LUT4_24 : label is "0x8000";
+ attribute initval of LUT4_23 : label is "0x8000";
+ attribute initval of LUT4_22 : label is "0x8000";
+ attribute initval of LUT4_21 : label is "0x8000";
+ attribute initval of LUT4_20 : label is "0x8000";
+ attribute initval of LUT4_19 : label is "0x8000";
+ attribute initval of LUT4_18 : label is "0x8000";
+ attribute initval of LUT4_17 : label is "0x8000";
+ attribute initval of LUT4_16 : label is "0x8000";
+ attribute initval of LUT4_15 : label is "0x8000";
+ attribute initval of LUT4_14 : label is "0x8000";
+ attribute initval of LUT4_13 : label is "0x8000";
+ attribute initval of LUT4_12 : label is "0x8000";
+ attribute initval of LUT4_11 : label is "0x8000";
+ attribute initval of LUT4_10 : label is "0x8000";
+ attribute initval of LUT4_9 : label is "0x8000";
+ attribute initval of LUT4_8 : label is "0x8000";
+ attribute initval of LUT4_7 : label is "0x8000";
+ attribute initval of LUT4_6 : label is "0x8000";
+ attribute initval of LUT4_5 : label is "0x8000";
+ attribute initval of LUT4_4 : label is "0x8000";
+ attribute initval of LUT4_3 : label is "0x8000";
+ attribute initval of LUT4_2 : label is "0x8000";
+ attribute initval of LUT4_1 : label is "0x8000";
+ attribute initval of LUT4_0 : label is "0x8000";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_63 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_63 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_63 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_0_0_63 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_63 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_63 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_63 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_63 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_63 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_62 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_62 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_62 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_0_1_62 : label is "0b001";
+ attribute GSR of pdp_ram_0_1_62 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_62 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_62 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_62 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_62 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_61 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_61 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_61 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_0_2_61 : label is "0b001";
+ attribute GSR of pdp_ram_0_2_61 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_61 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_61 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_61 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_61 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_60 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_60 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_3_60 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_0_3_60 : label is "0b001";
+ attribute GSR of pdp_ram_0_3_60 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_60 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_3_60 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_3_60 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_3_60 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_59 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_59 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_0_59 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_0_59 : label is "0b001";
+ attribute GSR of pdp_ram_1_0_59 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_59 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_0_59 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_0_59 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_0_59 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_58 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_58 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_1_58 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_1_58 : label is "0b001";
+ attribute GSR of pdp_ram_1_1_58 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_1_58 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_1_58 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_1_58 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_1_58 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_2_57 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_2_57 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_2_57 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_2_57 : label is "0b001";
+ attribute GSR of pdp_ram_1_2_57 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_2_57 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_2_57 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_2_57 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_2_57 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_3_56 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_3_56 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_3_56 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_3_56 : label is "0b001";
+ attribute GSR of pdp_ram_1_3_56 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_3_56 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_3_56 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_3_56 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_3_56 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_55 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_55 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_0_55 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_2_0_55 : label is "0b001";
+ attribute GSR of pdp_ram_2_0_55 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_55 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_0_55 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_0_55 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_0_55 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_54 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_54 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_1_54 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_2_1_54 : label is "0b001";
+ attribute GSR of pdp_ram_2_1_54 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_1_54 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_1_54 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_1_54 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_1_54 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_2_53 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_2_53 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_2_53 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_2_2_53 : label is "0b001";
+ attribute GSR of pdp_ram_2_2_53 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_2_53 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_2_53 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_2_53 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_2_53 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_3_52 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_3_52 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_3_52 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_2_3_52 : label is "0b001";
+ attribute GSR of pdp_ram_2_3_52 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_3_52 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_3_52 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_3_52 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_3_52 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_51 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_51 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_0_51 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_0_51 : label is "0b001";
+ attribute GSR of pdp_ram_3_0_51 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_51 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_0_51 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_0_51 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_0_51 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_50 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_50 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_1_50 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_1_50 : label is "0b001";
+ attribute GSR of pdp_ram_3_1_50 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_1_50 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_1_50 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_1_50 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_1_50 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_2_49 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_2_49 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_2_49 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_2_49 : label is "0b001";
+ attribute GSR of pdp_ram_3_2_49 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_2_49 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_2_49 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_2_49 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_2_49 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_3_48 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_3_48 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_3_48 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_3_3_48 : label is "0b001";
+ attribute GSR of pdp_ram_3_3_48 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_3_48 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_3_48 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_3_48 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_3_48 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_0_47 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_0_47 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_0_47 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_4_0_47 : label is "0b001";
+ attribute GSR of pdp_ram_4_0_47 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_0_47 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_0_47 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_0_47 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_0_47 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_1_46 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_1_46 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_1_46 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_4_1_46 : label is "0b001";
+ attribute GSR of pdp_ram_4_1_46 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_1_46 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_1_46 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_1_46 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_1_46 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_2_45 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_2_45 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_2_45 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_4_2_45 : label is "0b001";
+ attribute GSR of pdp_ram_4_2_45 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_2_45 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_2_45 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_2_45 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_2_45 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_4_3_44 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_4_3_44 : label is "";
+ attribute CSDECODE_R of pdp_ram_4_3_44 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_4_3_44 : label is "0b001";
+ attribute GSR of pdp_ram_4_3_44 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_4_3_44 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_4_3_44 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_4_3_44 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_4_3_44 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_0_43 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_0_43 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_0_43 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_5_0_43 : label is "0b001";
+ attribute GSR of pdp_ram_5_0_43 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_0_43 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_0_43 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_0_43 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_0_43 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_1_42 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_1_42 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_1_42 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_5_1_42 : label is "0b001";
+ attribute GSR of pdp_ram_5_1_42 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_1_42 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_1_42 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_1_42 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_1_42 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_2_41 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_2_41 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_2_41 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_5_2_41 : label is "0b001";
+ attribute GSR of pdp_ram_5_2_41 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_2_41 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_2_41 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_2_41 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_2_41 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_5_3_40 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_5_3_40 : label is "";
+ attribute CSDECODE_R of pdp_ram_5_3_40 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_5_3_40 : label is "0b001";
+ attribute GSR of pdp_ram_5_3_40 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_5_3_40 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_5_3_40 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_5_3_40 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_5_3_40 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_0_39 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_0_39 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_0_39 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_6_0_39 : label is "0b001";
+ attribute GSR of pdp_ram_6_0_39 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_0_39 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_0_39 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_0_39 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_0_39 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_1_38 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_1_38 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_1_38 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_6_1_38 : label is "0b001";
+ attribute GSR of pdp_ram_6_1_38 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_1_38 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_1_38 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_1_38 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_1_38 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_2_37 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_2_37 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_2_37 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_6_2_37 : label is "0b001";
+ attribute GSR of pdp_ram_6_2_37 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_2_37 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_2_37 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_2_37 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_2_37 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_6_3_36 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_6_3_36 : label is "";
+ attribute CSDECODE_R of pdp_ram_6_3_36 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_6_3_36 : label is "0b001";
+ attribute GSR of pdp_ram_6_3_36 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_6_3_36 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_6_3_36 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_6_3_36 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_6_3_36 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_0_35 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_0_35 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_0_35 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_7_0_35 : label is "0b001";
+ attribute GSR of pdp_ram_7_0_35 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_0_35 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_0_35 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_0_35 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_0_35 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_1_34 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_1_34 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_1_34 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_7_1_34 : label is "0b001";
+ attribute GSR of pdp_ram_7_1_34 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_1_34 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_1_34 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_1_34 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_1_34 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_2_33 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_2_33 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_2_33 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_7_2_33 : label is "0b001";
+ attribute GSR of pdp_ram_7_2_33 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_2_33 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_2_33 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_2_33 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_2_33 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_7_3_32 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_7_3_32 : label is "";
+ attribute CSDECODE_R of pdp_ram_7_3_32 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_7_3_32 : label is "0b001";
+ attribute GSR of pdp_ram_7_3_32 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_7_3_32 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_7_3_32 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_7_3_32 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_7_3_32 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_8_0_31 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_0_31 : label is "";
+ attribute CSDECODE_R of pdp_ram_8_0_31 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_8_0_31 : label is "0b001";
+ attribute GSR of pdp_ram_8_0_31 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_0_31 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_8_0_31 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_8_0_31 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_8_0_31 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_8_1_30 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_1_30 : label is "";
+ attribute CSDECODE_R of pdp_ram_8_1_30 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_8_1_30 : label is "0b001";
+ attribute GSR of pdp_ram_8_1_30 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_1_30 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_8_1_30 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_8_1_30 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_8_1_30 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_8_2_29 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_2_29 : label is "";
+ attribute CSDECODE_R of pdp_ram_8_2_29 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_8_2_29 : label is "0b001";
+ attribute GSR of pdp_ram_8_2_29 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_2_29 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_8_2_29 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_8_2_29 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_8_2_29 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_8_3_28 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_8_3_28 : label is "";
+ attribute CSDECODE_R of pdp_ram_8_3_28 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_8_3_28 : label is "0b001";
+ attribute GSR of pdp_ram_8_3_28 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_8_3_28 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_8_3_28 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_8_3_28 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_8_3_28 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_9_0_27 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_0_27 : label is "";
+ attribute CSDECODE_R of pdp_ram_9_0_27 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_9_0_27 : label is "0b001";
+ attribute GSR of pdp_ram_9_0_27 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_0_27 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_9_0_27 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_9_0_27 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_9_0_27 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_9_1_26 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_1_26 : label is "";
+ attribute CSDECODE_R of pdp_ram_9_1_26 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_9_1_26 : label is "0b001";
+ attribute GSR of pdp_ram_9_1_26 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_1_26 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_9_1_26 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_9_1_26 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_9_1_26 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_9_2_25 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_2_25 : label is "";
+ attribute CSDECODE_R of pdp_ram_9_2_25 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_9_2_25 : label is "0b001";
+ attribute GSR of pdp_ram_9_2_25 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_2_25 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_9_2_25 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_9_2_25 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_9_2_25 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_9_3_24 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_9_3_24 : label is "";
+ attribute CSDECODE_R of pdp_ram_9_3_24 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_9_3_24 : label is "0b001";
+ attribute GSR of pdp_ram_9_3_24 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_9_3_24 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_9_3_24 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_9_3_24 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_9_3_24 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_10_0_23 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_0_23 : label is "";
+ attribute CSDECODE_R of pdp_ram_10_0_23 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_10_0_23 : label is "0b001";
+ attribute GSR of pdp_ram_10_0_23 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_0_23 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_10_0_23 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_10_0_23 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_10_0_23 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_10_1_22 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_1_22 : label is "";
+ attribute CSDECODE_R of pdp_ram_10_1_22 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_10_1_22 : label is "0b001";
+ attribute GSR of pdp_ram_10_1_22 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_1_22 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_10_1_22 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_10_1_22 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_10_1_22 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_10_2_21 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_2_21 : label is "";
+ attribute CSDECODE_R of pdp_ram_10_2_21 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_10_2_21 : label is "0b001";
+ attribute GSR of pdp_ram_10_2_21 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_2_21 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_10_2_21 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_10_2_21 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_10_2_21 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_10_3_20 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_10_3_20 : label is "";
+ attribute CSDECODE_R of pdp_ram_10_3_20 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_10_3_20 : label is "0b001";
+ attribute GSR of pdp_ram_10_3_20 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_10_3_20 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_10_3_20 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_10_3_20 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_10_3_20 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_11_0_19 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_0_19 : label is "";
+ attribute CSDECODE_R of pdp_ram_11_0_19 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_11_0_19 : label is "0b001";
+ attribute GSR of pdp_ram_11_0_19 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_0_19 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_11_0_19 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_11_0_19 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_11_0_19 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_11_1_18 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_1_18 : label is "";
+ attribute CSDECODE_R of pdp_ram_11_1_18 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_11_1_18 : label is "0b001";
+ attribute GSR of pdp_ram_11_1_18 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_1_18 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_11_1_18 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_11_1_18 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_11_1_18 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_11_2_17 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_2_17 : label is "";
+ attribute CSDECODE_R of pdp_ram_11_2_17 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_11_2_17 : label is "0b001";
+ attribute GSR of pdp_ram_11_2_17 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_2_17 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_11_2_17 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_11_2_17 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_11_2_17 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_11_3_16 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_11_3_16 : label is "";
+ attribute CSDECODE_R of pdp_ram_11_3_16 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_11_3_16 : label is "0b001";
+ attribute GSR of pdp_ram_11_3_16 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_11_3_16 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_11_3_16 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_11_3_16 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_11_3_16 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_12_0_15 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_0_15 : label is "";
+ attribute CSDECODE_R of pdp_ram_12_0_15 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_12_0_15 : label is "0b001";
+ attribute GSR of pdp_ram_12_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_0_15 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_12_0_15 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_12_0_15 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_12_0_15 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_12_1_14 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_1_14 : label is "";
+ attribute CSDECODE_R of pdp_ram_12_1_14 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_12_1_14 : label is "0b001";
+ attribute GSR of pdp_ram_12_1_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_1_14 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_12_1_14 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_12_1_14 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_12_1_14 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_12_2_13 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_2_13 : label is "";
+ attribute CSDECODE_R of pdp_ram_12_2_13 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_12_2_13 : label is "0b001";
+ attribute GSR of pdp_ram_12_2_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_2_13 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_12_2_13 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_12_2_13 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_12_2_13 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_12_3_12 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_12_3_12 : label is "";
+ attribute CSDECODE_R of pdp_ram_12_3_12 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_12_3_12 : label is "0b001";
+ attribute GSR of pdp_ram_12_3_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_12_3_12 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_12_3_12 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_12_3_12 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_12_3_12 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_13_0_11 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_0_11 : label is "";
+ attribute CSDECODE_R of pdp_ram_13_0_11 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_13_0_11 : label is "0b001";
+ attribute GSR of pdp_ram_13_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_0_11 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_13_0_11 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_13_0_11 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_13_0_11 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_13_1_10 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_1_10 : label is "";
+ attribute CSDECODE_R of pdp_ram_13_1_10 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_13_1_10 : label is "0b001";
+ attribute GSR of pdp_ram_13_1_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_1_10 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_13_1_10 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_13_1_10 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_13_1_10 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_13_2_9 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_2_9 : label is "";
+ attribute CSDECODE_R of pdp_ram_13_2_9 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_13_2_9 : label is "0b001";
+ attribute GSR of pdp_ram_13_2_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_2_9 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_13_2_9 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_13_2_9 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_13_2_9 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_13_3_8 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_13_3_8 : label is "";
+ attribute CSDECODE_R of pdp_ram_13_3_8 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_13_3_8 : label is "0b001";
+ attribute GSR of pdp_ram_13_3_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_13_3_8 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_13_3_8 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_13_3_8 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_13_3_8 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_14_0_7 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_0_7 : label is "";
+ attribute CSDECODE_R of pdp_ram_14_0_7 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_14_0_7 : label is "0b001";
+ attribute GSR of pdp_ram_14_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_0_7 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_14_0_7 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_14_0_7 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_14_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_14_1_6 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_1_6 : label is "";
+ attribute CSDECODE_R of pdp_ram_14_1_6 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_14_1_6 : label is "0b001";
+ attribute GSR of pdp_ram_14_1_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_1_6 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_14_1_6 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_14_1_6 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_14_1_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_14_2_5 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_2_5 : label is "";
+ attribute CSDECODE_R of pdp_ram_14_2_5 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_14_2_5 : label is "0b001";
+ attribute GSR of pdp_ram_14_2_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_2_5 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_14_2_5 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_14_2_5 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_14_2_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_14_3_4 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_14_3_4 : label is "";
+ attribute CSDECODE_R of pdp_ram_14_3_4 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_14_3_4 : label is "0b001";
+ attribute GSR of pdp_ram_14_3_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_14_3_4 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_14_3_4 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_14_3_4 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_14_3_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_15_0_3 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_0_3 : label is "";
+ attribute CSDECODE_R of pdp_ram_15_0_3 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_15_0_3 : label is "0b001";
+ attribute GSR of pdp_ram_15_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_0_3 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_15_0_3 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_15_0_3 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_15_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_15_1_2 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_1_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_15_1_2 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_15_1_2 : label is "0b001";
+ attribute GSR of pdp_ram_15_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_1_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_15_1_2 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_15_1_2 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_15_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_15_2_1 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_2_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_15_2_1 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_15_2_1 : label is "0b001";
+ attribute GSR of pdp_ram_15_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_2_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_15_2_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_15_2_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_15_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_15_3_0 : label is "fifo_36x32k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_15_3_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_15_3_0 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_15_3_0 : label is "0b001";
+ attribute GSR of pdp_ram_15_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_15_3_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_15_3_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_15_3_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_15_3_0 : label is "9";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_12: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_11: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_10: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_9: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_129: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_128: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ INV_8: INV
+ port map (A=>wptr_11, Z=>wptr_11_inv);
+
+ INV_7: INV
+ port map (A=>wptr_12, Z=>wptr_12_inv);
+
+ INV_6: INV
+ port map (A=>wptr_13, Z=>wptr_13_inv);
+
+ INV_5: INV
+ port map (A=>wptr_14, Z=>wptr_14_inv);
+
+ LUT4_127: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec0_p00);
+
+ INV_4: INV
+ port map (A=>rptr_11, Z=>rptr_11_inv);
+
+ INV_3: INV
+ port map (A=>rptr_12, Z=>rptr_12_inv);
+
+ INV_2: INV
+ port map (A=>rptr_13, Z=>rptr_13_inv);
+
+ INV_1: INV
+ port map (A=>rptr_14, Z=>rptr_14_inv);
+
+ LUT4_126: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec1_r10);
+
+ LUT4_125: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec2_p00);
+
+ LUT4_124: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec3_r10);
+
+ LUT4_123: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec4_p00);
+
+ LUT4_122: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec5_r10);
+
+ LUT4_121: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec6_p00);
+
+ LUT4_120: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec7_r10);
+
+ LUT4_119: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec8_p01);
+
+ LUT4_118: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec9_r11);
+
+ LUT4_117: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec10_p01);
+
+ LUT4_116: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec11_r11);
+
+ LUT4_115: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec12_p01);
+
+ LUT4_114: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec13_r11);
+
+ LUT4_113: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec14_p01);
+
+ LUT4_112: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec15_r11);
+
+ LUT4_111: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec16_p02);
+
+ LUT4_110: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec17_r12);
+
+ LUT4_109: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec18_p02);
+
+ LUT4_108: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec19_r12);
+
+ LUT4_107: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec20_p02);
+
+ LUT4_106: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec21_r12);
+
+ LUT4_105: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec22_p02);
+
+ LUT4_104: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec23_r12);
+
+ LUT4_103: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec24_p03);
+
+ LUT4_102: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec25_r13);
+
+ LUT4_101: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec26_p03);
+
+ LUT4_100: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec27_r13);
+
+ LUT4_99: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec28_p03);
+
+ LUT4_98: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec29_r13);
+
+ LUT4_97: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14_inv, DO0=>dec30_p03);
+
+ LUT4_96: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14_inv, DO0=>dec31_r13);
+
+ LUT4_95: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec32_p04);
+
+ LUT4_94: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec33_r14);
+
+ LUT4_93: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec34_p04);
+
+ LUT4_92: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec35_r14);
+
+ LUT4_91: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec36_p04);
+
+ LUT4_90: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec37_r14);
+
+ LUT4_89: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec38_p04);
+
+ LUT4_88: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec39_r14);
+
+ LUT4_87: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec40_p05);
+
+ LUT4_86: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec41_r15);
+
+ LUT4_85: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec42_p05);
+
+ LUT4_84: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec43_r15);
+
+ LUT4_83: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec44_p05);
+
+ LUT4_82: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec45_r15);
+
+ LUT4_81: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec46_p05);
+
+ LUT4_80: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec47_r15);
+
+ LUT4_79: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec48_p06);
+
+ LUT4_78: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec49_r16);
+
+ LUT4_77: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec50_p06);
+
+ LUT4_76: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec51_r16);
+
+ LUT4_75: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec52_p06);
+
+ LUT4_74: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec53_r16);
+
+ LUT4_73: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec54_p06);
+
+ LUT4_72: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec55_r16);
+
+ LUT4_71: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec56_p07);
+
+ LUT4_70: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec57_r17);
+
+ LUT4_69: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec58_p07);
+
+ LUT4_68: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec59_r17);
+
+ LUT4_67: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec60_p07);
+
+ LUT4_66: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec61_r17);
+
+ LUT4_65: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14_inv, DO0=>dec62_p07);
+
+ LUT4_64: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14_inv, DO0=>dec63_r17);
+
+ LUT4_63: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec64_p08);
+
+ LUT4_62: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec65_r18);
+
+ LUT4_61: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec66_p08);
+
+ LUT4_60: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec67_r18);
+
+ LUT4_59: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec68_p08);
+
+ LUT4_58: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec69_r18);
+
+ LUT4_57: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec70_p08);
+
+ LUT4_56: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec71_r18);
+
+ LUT4_55: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec72_p09);
+
+ LUT4_54: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec73_r19);
+
+ LUT4_53: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec74_p09);
+
+ LUT4_52: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec75_r19);
+
+ LUT4_51: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec76_p09);
+
+ LUT4_50: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec77_r19);
+
+ LUT4_49: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec78_p09);
+
+ LUT4_48: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec79_r19);
+
+ LUT4_47: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec80_p010);
+
+ LUT4_46: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec81_r110);
+
+ LUT4_45: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec82_p010);
+
+ LUT4_44: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec83_r110);
+
+ LUT4_43: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec84_p010);
+
+ LUT4_42: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec85_r110);
+
+ LUT4_41: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec86_p010);
+
+ LUT4_40: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec87_r110);
+
+ LUT4_39: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec88_p011);
+
+ LUT4_38: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec89_r111);
+
+ LUT4_37: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec90_p011);
+
+ LUT4_36: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec91_r111);
+
+ LUT4_35: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec92_p011);
+
+ LUT4_34: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec93_r111);
+
+ LUT4_33: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13_inv,
+ AD0=>wptr_14, DO0=>dec94_p011);
+
+ LUT4_32: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13_inv,
+ AD0=>rptr_14, DO0=>dec95_r111);
+
+ LUT4_31: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec96_p012);
+
+ LUT4_30: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec97_r112);
+
+ LUT4_29: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec98_p012);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec99_r112);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec100_p012);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec101_r112);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec102_p012);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec103_r112);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec104_p013);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec105_r113);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec106_p013);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec107_r113);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec108_p013);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec109_r113);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12_inv, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec110_p013);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12_inv, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec111_r113);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec112_p014);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec113_r114);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec114_p014);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec115_r114);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec116_p014);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec117_r114);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11_inv, AD2=>wptr_12, AD1=>wptr_13,
+ AD0=>wptr_14, DO0=>dec118_p014);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11_inv, AD2=>rptr_12, AD1=>rptr_13,
+ AD0=>rptr_14, DO0=>dec119_r114);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>dec120_p015);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>dec121_r115);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>dec122_p015);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>dec123_r115);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>dec124_p015);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>dec125_r115);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wptr_12, AD1=>wptr_13, AD0=>wptr_14,
+ DO0=>dec126_p015);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x8000")
+ -- synopsys translate_on
+ port map (AD3=>rptr_11, AD2=>rptr_12, AD1=>rptr_13, AD0=>rptr_14,
+ DO0=>dec127_r115);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_15, B=>rptr_15, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_63: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec0_p00,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec1_r10,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_0_0,
+ DO1=>mdout1_0_1, DO2=>mdout1_0_2, DO3=>mdout1_0_3,
+ DO4=>mdout1_0_4, DO5=>mdout1_0_5, DO6=>mdout1_0_6,
+ DO7=>mdout1_0_7, DO8=>mdout1_0_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_62: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec2_p00, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec3_r10, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_9, DO1=>mdout1_0_10,
+ DO2=>mdout1_0_11, DO3=>mdout1_0_12, DO4=>mdout1_0_13,
+ DO5=>mdout1_0_14, DO6=>mdout1_0_15, DO7=>mdout1_0_16,
+ DO8=>mdout1_0_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_2_61: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec4_p00, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec5_r10, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_18, DO1=>mdout1_0_19,
+ DO2=>mdout1_0_20, DO3=>mdout1_0_21, DO4=>mdout1_0_22,
+ DO5=>mdout1_0_23, DO6=>mdout1_0_24, DO7=>mdout1_0_25,
+ DO8=>mdout1_0_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_3_60: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec6_p00, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec7_r10, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_27, DO1=>mdout1_0_28,
+ DO2=>mdout1_0_29, DO3=>mdout1_0_30, DO4=>mdout1_0_31,
+ DO5=>mdout1_0_32, DO6=>mdout1_0_33, DO7=>mdout1_0_34,
+ DO8=>mdout1_0_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_0_59: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec8_p01,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec9_r11,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_1_0,
+ DO1=>mdout1_1_1, DO2=>mdout1_1_2, DO3=>mdout1_1_3,
+ DO4=>mdout1_1_4, DO5=>mdout1_1_5, DO6=>mdout1_1_6,
+ DO7=>mdout1_1_7, DO8=>mdout1_1_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_1_58: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec10_p01, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec11_r11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_9, DO1=>mdout1_1_10,
+ DO2=>mdout1_1_11, DO3=>mdout1_1_12, DO4=>mdout1_1_13,
+ DO5=>mdout1_1_14, DO6=>mdout1_1_15, DO7=>mdout1_1_16,
+ DO8=>mdout1_1_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_2_57: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec12_p01, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec13_r11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_18, DO1=>mdout1_1_19,
+ DO2=>mdout1_1_20, DO3=>mdout1_1_21, DO4=>mdout1_1_22,
+ DO5=>mdout1_1_23, DO6=>mdout1_1_24, DO7=>mdout1_1_25,
+ DO8=>mdout1_1_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_3_56: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec14_p01, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec15_r11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_27, DO1=>mdout1_1_28,
+ DO2=>mdout1_1_29, DO3=>mdout1_1_30, DO4=>mdout1_1_31,
+ DO5=>mdout1_1_32, DO6=>mdout1_1_33, DO7=>mdout1_1_34,
+ DO8=>mdout1_1_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_0_55: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec16_p02,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec17_r12,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_2_0,
+ DO1=>mdout1_2_1, DO2=>mdout1_2_2, DO3=>mdout1_2_3,
+ DO4=>mdout1_2_4, DO5=>mdout1_2_5, DO6=>mdout1_2_6,
+ DO7=>mdout1_2_7, DO8=>mdout1_2_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_1_54: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec18_p02, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec19_r12, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_2_9, DO1=>mdout1_2_10,
+ DO2=>mdout1_2_11, DO3=>mdout1_2_12, DO4=>mdout1_2_13,
+ DO5=>mdout1_2_14, DO6=>mdout1_2_15, DO7=>mdout1_2_16,
+ DO8=>mdout1_2_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_2_53: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec20_p02, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec21_r12, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_2_18, DO1=>mdout1_2_19,
+ DO2=>mdout1_2_20, DO3=>mdout1_2_21, DO4=>mdout1_2_22,
+ DO5=>mdout1_2_23, DO6=>mdout1_2_24, DO7=>mdout1_2_25,
+ DO8=>mdout1_2_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_3_52: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec22_p02, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec23_r12, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_2_27, DO1=>mdout1_2_28,
+ DO2=>mdout1_2_29, DO3=>mdout1_2_30, DO4=>mdout1_2_31,
+ DO5=>mdout1_2_32, DO6=>mdout1_2_33, DO7=>mdout1_2_34,
+ DO8=>mdout1_2_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_0_51: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec24_p03,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec25_r13,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_3_0,
+ DO1=>mdout1_3_1, DO2=>mdout1_3_2, DO3=>mdout1_3_3,
+ DO4=>mdout1_3_4, DO5=>mdout1_3_5, DO6=>mdout1_3_6,
+ DO7=>mdout1_3_7, DO8=>mdout1_3_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_1_50: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec26_p03, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec27_r13, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_3_9, DO1=>mdout1_3_10,
+ DO2=>mdout1_3_11, DO3=>mdout1_3_12, DO4=>mdout1_3_13,
+ DO5=>mdout1_3_14, DO6=>mdout1_3_15, DO7=>mdout1_3_16,
+ DO8=>mdout1_3_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_2_49: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec28_p03, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec29_r13, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_3_18, DO1=>mdout1_3_19,
+ DO2=>mdout1_3_20, DO3=>mdout1_3_21, DO4=>mdout1_3_22,
+ DO5=>mdout1_3_23, DO6=>mdout1_3_24, DO7=>mdout1_3_25,
+ DO8=>mdout1_3_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_3_48: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec30_p03, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec31_r13, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_3_27, DO1=>mdout1_3_28,
+ DO2=>mdout1_3_29, DO3=>mdout1_3_30, DO4=>mdout1_3_31,
+ DO5=>mdout1_3_32, DO6=>mdout1_3_33, DO7=>mdout1_3_34,
+ DO8=>mdout1_3_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_4_0_47: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec32_p04,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec33_r14,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_4_0,
+ DO1=>mdout1_4_1, DO2=>mdout1_4_2, DO3=>mdout1_4_3,
+ DO4=>mdout1_4_4, DO5=>mdout1_4_5, DO6=>mdout1_4_6,
+ DO7=>mdout1_4_7, DO8=>mdout1_4_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_4_1_46: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec34_p04, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec35_r14, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_4_9, DO1=>mdout1_4_10,
+ DO2=>mdout1_4_11, DO3=>mdout1_4_12, DO4=>mdout1_4_13,
+ DO5=>mdout1_4_14, DO6=>mdout1_4_15, DO7=>mdout1_4_16,
+ DO8=>mdout1_4_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_4_2_45: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec36_p04, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec37_r14, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_4_18, DO1=>mdout1_4_19,
+ DO2=>mdout1_4_20, DO3=>mdout1_4_21, DO4=>mdout1_4_22,
+ DO5=>mdout1_4_23, DO6=>mdout1_4_24, DO7=>mdout1_4_25,
+ DO8=>mdout1_4_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_4_3_44: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec38_p04, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec39_r14, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_4_27, DO1=>mdout1_4_28,
+ DO2=>mdout1_4_29, DO3=>mdout1_4_30, DO4=>mdout1_4_31,
+ DO5=>mdout1_4_32, DO6=>mdout1_4_33, DO7=>mdout1_4_34,
+ DO8=>mdout1_4_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_5_0_43: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec40_p05,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec41_r15,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_5_0,
+ DO1=>mdout1_5_1, DO2=>mdout1_5_2, DO3=>mdout1_5_3,
+ DO4=>mdout1_5_4, DO5=>mdout1_5_5, DO6=>mdout1_5_6,
+ DO7=>mdout1_5_7, DO8=>mdout1_5_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_5_1_42: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec42_p05, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec43_r15, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_5_9, DO1=>mdout1_5_10,
+ DO2=>mdout1_5_11, DO3=>mdout1_5_12, DO4=>mdout1_5_13,
+ DO5=>mdout1_5_14, DO6=>mdout1_5_15, DO7=>mdout1_5_16,
+ DO8=>mdout1_5_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_5_2_41: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec44_p05, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec45_r15, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_5_18, DO1=>mdout1_5_19,
+ DO2=>mdout1_5_20, DO3=>mdout1_5_21, DO4=>mdout1_5_22,
+ DO5=>mdout1_5_23, DO6=>mdout1_5_24, DO7=>mdout1_5_25,
+ DO8=>mdout1_5_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_5_3_40: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec46_p05, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec47_r15, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_5_27, DO1=>mdout1_5_28,
+ DO2=>mdout1_5_29, DO3=>mdout1_5_30, DO4=>mdout1_5_31,
+ DO5=>mdout1_5_32, DO6=>mdout1_5_33, DO7=>mdout1_5_34,
+ DO8=>mdout1_5_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_6_0_39: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec48_p06,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec49_r16,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_6_0,
+ DO1=>mdout1_6_1, DO2=>mdout1_6_2, DO3=>mdout1_6_3,
+ DO4=>mdout1_6_4, DO5=>mdout1_6_5, DO6=>mdout1_6_6,
+ DO7=>mdout1_6_7, DO8=>mdout1_6_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_6_1_38: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec50_p06, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec51_r16, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_6_9, DO1=>mdout1_6_10,
+ DO2=>mdout1_6_11, DO3=>mdout1_6_12, DO4=>mdout1_6_13,
+ DO5=>mdout1_6_14, DO6=>mdout1_6_15, DO7=>mdout1_6_16,
+ DO8=>mdout1_6_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_6_2_37: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec52_p06, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec53_r16, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_6_18, DO1=>mdout1_6_19,
+ DO2=>mdout1_6_20, DO3=>mdout1_6_21, DO4=>mdout1_6_22,
+ DO5=>mdout1_6_23, DO6=>mdout1_6_24, DO7=>mdout1_6_25,
+ DO8=>mdout1_6_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_6_3_36: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec54_p06, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec55_r16, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_6_27, DO1=>mdout1_6_28,
+ DO2=>mdout1_6_29, DO3=>mdout1_6_30, DO4=>mdout1_6_31,
+ DO5=>mdout1_6_32, DO6=>mdout1_6_33, DO7=>mdout1_6_34,
+ DO8=>mdout1_6_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_7_0_35: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec56_p07,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec57_r17,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_7_0,
+ DO1=>mdout1_7_1, DO2=>mdout1_7_2, DO3=>mdout1_7_3,
+ DO4=>mdout1_7_4, DO5=>mdout1_7_5, DO6=>mdout1_7_6,
+ DO7=>mdout1_7_7, DO8=>mdout1_7_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_7_1_34: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec58_p07, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec59_r17, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_7_9, DO1=>mdout1_7_10,
+ DO2=>mdout1_7_11, DO3=>mdout1_7_12, DO4=>mdout1_7_13,
+ DO5=>mdout1_7_14, DO6=>mdout1_7_15, DO7=>mdout1_7_16,
+ DO8=>mdout1_7_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_7_2_33: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec60_p07, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec61_r17, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_7_18, DO1=>mdout1_7_19,
+ DO2=>mdout1_7_20, DO3=>mdout1_7_21, DO4=>mdout1_7_22,
+ DO5=>mdout1_7_23, DO6=>mdout1_7_24, DO7=>mdout1_7_25,
+ DO8=>mdout1_7_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_7_3_32: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec62_p07, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec63_r17, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_7_27, DO1=>mdout1_7_28,
+ DO2=>mdout1_7_29, DO3=>mdout1_7_30, DO4=>mdout1_7_31,
+ DO5=>mdout1_7_32, DO6=>mdout1_7_33, DO7=>mdout1_7_34,
+ DO8=>mdout1_7_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_8_0_31: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec64_p08,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec65_r18,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_8_0,
+ DO1=>mdout1_8_1, DO2=>mdout1_8_2, DO3=>mdout1_8_3,
+ DO4=>mdout1_8_4, DO5=>mdout1_8_5, DO6=>mdout1_8_6,
+ DO7=>mdout1_8_7, DO8=>mdout1_8_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_8_1_30: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec66_p08, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec67_r18, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_8_9, DO1=>mdout1_8_10,
+ DO2=>mdout1_8_11, DO3=>mdout1_8_12, DO4=>mdout1_8_13,
+ DO5=>mdout1_8_14, DO6=>mdout1_8_15, DO7=>mdout1_8_16,
+ DO8=>mdout1_8_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_8_2_29: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec68_p08, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec69_r18, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_8_18, DO1=>mdout1_8_19,
+ DO2=>mdout1_8_20, DO3=>mdout1_8_21, DO4=>mdout1_8_22,
+ DO5=>mdout1_8_23, DO6=>mdout1_8_24, DO7=>mdout1_8_25,
+ DO8=>mdout1_8_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_8_3_28: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec70_p08, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec71_r18, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_8_27, DO1=>mdout1_8_28,
+ DO2=>mdout1_8_29, DO3=>mdout1_8_30, DO4=>mdout1_8_31,
+ DO5=>mdout1_8_32, DO6=>mdout1_8_33, DO7=>mdout1_8_34,
+ DO8=>mdout1_8_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_9_0_27: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec72_p09,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>dec73_r19,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_9_0,
+ DO1=>mdout1_9_1, DO2=>mdout1_9_2, DO3=>mdout1_9_3,
+ DO4=>mdout1_9_4, DO5=>mdout1_9_5, DO6=>mdout1_9_6,
+ DO7=>mdout1_9_7, DO8=>mdout1_9_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_9_1_26: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec74_p09, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec75_r19, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_9_9, DO1=>mdout1_9_10,
+ DO2=>mdout1_9_11, DO3=>mdout1_9_12, DO4=>mdout1_9_13,
+ DO5=>mdout1_9_14, DO6=>mdout1_9_15, DO7=>mdout1_9_16,
+ DO8=>mdout1_9_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_9_2_25: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec76_p09, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec77_r19, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_9_18, DO1=>mdout1_9_19,
+ DO2=>mdout1_9_20, DO3=>mdout1_9_21, DO4=>mdout1_9_22,
+ DO5=>mdout1_9_23, DO6=>mdout1_9_24, DO7=>mdout1_9_25,
+ DO8=>mdout1_9_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_9_3_24: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec78_p09, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec79_r19, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_9_27, DO1=>mdout1_9_28,
+ DO2=>mdout1_9_29, DO3=>mdout1_9_30, DO4=>mdout1_9_31,
+ DO5=>mdout1_9_32, DO6=>mdout1_9_33, DO7=>mdout1_9_34,
+ DO8=>mdout1_9_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_10_0_23: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec80_p010,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec81_r110, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_10_0, DO1=>mdout1_10_1, DO2=>mdout1_10_2,
+ DO3=>mdout1_10_3, DO4=>mdout1_10_4, DO5=>mdout1_10_5,
+ DO6=>mdout1_10_6, DO7=>mdout1_10_7, DO8=>mdout1_10_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_10_1_22: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec82_p010, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec83_r110, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_10_9, DO1=>mdout1_10_10,
+ DO2=>mdout1_10_11, DO3=>mdout1_10_12, DO4=>mdout1_10_13,
+ DO5=>mdout1_10_14, DO6=>mdout1_10_15, DO7=>mdout1_10_16,
+ DO8=>mdout1_10_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_10_2_21: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec84_p010, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec85_r110, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_10_18, DO1=>mdout1_10_19,
+ DO2=>mdout1_10_20, DO3=>mdout1_10_21, DO4=>mdout1_10_22,
+ DO5=>mdout1_10_23, DO6=>mdout1_10_24, DO7=>mdout1_10_25,
+ DO8=>mdout1_10_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_10_3_20: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec86_p010, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec87_r110, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_10_27, DO1=>mdout1_10_28,
+ DO2=>mdout1_10_29, DO3=>mdout1_10_30, DO4=>mdout1_10_31,
+ DO5=>mdout1_10_32, DO6=>mdout1_10_33, DO7=>mdout1_10_34,
+ DO8=>mdout1_10_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_11_0_19: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec88_p011,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec89_r111, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_11_0, DO1=>mdout1_11_1, DO2=>mdout1_11_2,
+ DO3=>mdout1_11_3, DO4=>mdout1_11_4, DO5=>mdout1_11_5,
+ DO6=>mdout1_11_6, DO7=>mdout1_11_7, DO8=>mdout1_11_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_11_1_18: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec90_p011, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec91_r111, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_11_9, DO1=>mdout1_11_10,
+ DO2=>mdout1_11_11, DO3=>mdout1_11_12, DO4=>mdout1_11_13,
+ DO5=>mdout1_11_14, DO6=>mdout1_11_15, DO7=>mdout1_11_16,
+ DO8=>mdout1_11_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_11_2_17: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec92_p011, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec93_r111, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_11_18, DO1=>mdout1_11_19,
+ DO2=>mdout1_11_20, DO3=>mdout1_11_21, DO4=>mdout1_11_22,
+ DO5=>mdout1_11_23, DO6=>mdout1_11_24, DO7=>mdout1_11_25,
+ DO8=>mdout1_11_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_11_3_16: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec94_p011, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec95_r111, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_11_27, DO1=>mdout1_11_28,
+ DO2=>mdout1_11_29, DO3=>mdout1_11_30, DO4=>mdout1_11_31,
+ DO5=>mdout1_11_32, DO6=>mdout1_11_33, DO7=>mdout1_11_34,
+ DO8=>mdout1_11_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_12_0_15: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec96_p012,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec97_r112, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_12_0, DO1=>mdout1_12_1, DO2=>mdout1_12_2,
+ DO3=>mdout1_12_3, DO4=>mdout1_12_4, DO5=>mdout1_12_5,
+ DO6=>mdout1_12_6, DO7=>mdout1_12_7, DO8=>mdout1_12_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_12_1_14: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec98_p012, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec99_r112, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_12_9, DO1=>mdout1_12_10,
+ DO2=>mdout1_12_11, DO3=>mdout1_12_12, DO4=>mdout1_12_13,
+ DO5=>mdout1_12_14, DO6=>mdout1_12_15, DO7=>mdout1_12_16,
+ DO8=>mdout1_12_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_12_2_13: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec100_p012, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec101_r112, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_12_18,
+ DO1=>mdout1_12_19, DO2=>mdout1_12_20, DO3=>mdout1_12_21,
+ DO4=>mdout1_12_22, DO5=>mdout1_12_23, DO6=>mdout1_12_24,
+ DO7=>mdout1_12_25, DO8=>mdout1_12_26, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_12_3_12: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec102_p012, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec103_r112, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_12_27,
+ DO1=>mdout1_12_28, DO2=>mdout1_12_29, DO3=>mdout1_12_30,
+ DO4=>mdout1_12_31, DO5=>mdout1_12_32, DO6=>mdout1_12_33,
+ DO7=>mdout1_12_34, DO8=>mdout1_12_35, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_13_0_11: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec104_p013,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec105_r113, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_13_0, DO1=>mdout1_13_1, DO2=>mdout1_13_2,
+ DO3=>mdout1_13_3, DO4=>mdout1_13_4, DO5=>mdout1_13_5,
+ DO6=>mdout1_13_6, DO7=>mdout1_13_7, DO8=>mdout1_13_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_13_1_10: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec106_p013, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec107_r113, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_13_9,
+ DO1=>mdout1_13_10, DO2=>mdout1_13_11, DO3=>mdout1_13_12,
+ DO4=>mdout1_13_13, DO5=>mdout1_13_14, DO6=>mdout1_13_15,
+ DO7=>mdout1_13_16, DO8=>mdout1_13_17, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_13_2_9: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec108_p013, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec109_r113, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_13_18,
+ DO1=>mdout1_13_19, DO2=>mdout1_13_20, DO3=>mdout1_13_21,
+ DO4=>mdout1_13_22, DO5=>mdout1_13_23, DO6=>mdout1_13_24,
+ DO7=>mdout1_13_25, DO8=>mdout1_13_26, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_13_3_8: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec110_p013, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec111_r113, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_13_27,
+ DO1=>mdout1_13_28, DO2=>mdout1_13_29, DO3=>mdout1_13_30,
+ DO4=>mdout1_13_31, DO5=>mdout1_13_32, DO6=>mdout1_13_33,
+ DO7=>mdout1_13_34, DO8=>mdout1_13_35, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_14_0_7: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec112_p014,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec113_r114, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_14_0, DO1=>mdout1_14_1, DO2=>mdout1_14_2,
+ DO3=>mdout1_14_3, DO4=>mdout1_14_4, DO5=>mdout1_14_5,
+ DO6=>mdout1_14_6, DO7=>mdout1_14_7, DO8=>mdout1_14_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_14_1_6: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec114_p014, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec115_r114, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_14_9,
+ DO1=>mdout1_14_10, DO2=>mdout1_14_11, DO3=>mdout1_14_12,
+ DO4=>mdout1_14_13, DO5=>mdout1_14_14, DO6=>mdout1_14_15,
+ DO7=>mdout1_14_16, DO8=>mdout1_14_17, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_14_2_5: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec116_p014, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec117_r114, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_14_18,
+ DO1=>mdout1_14_19, DO2=>mdout1_14_20, DO3=>mdout1_14_21,
+ DO4=>mdout1_14_22, DO5=>mdout1_14_23, DO6=>mdout1_14_24,
+ DO7=>mdout1_14_25, DO8=>mdout1_14_26, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_14_3_4: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec118_p014, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec119_r114, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_14_27,
+ DO1=>mdout1_14_28, DO2=>mdout1_14_29, DO3=>mdout1_14_30,
+ DO4=>mdout1_14_31, DO5=>mdout1_14_32, DO6=>mdout1_14_33,
+ DO7=>mdout1_14_34, DO8=>mdout1_14_35, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_15_0_3: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>dec120_p015,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock,
+ CSR0=>dec121_r115, CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset,
+ DO0=>mdout1_15_0, DO1=>mdout1_15_1, DO2=>mdout1_15_2,
+ DO3=>mdout1_15_3, DO4=>mdout1_15_4, DO5=>mdout1_15_5,
+ DO6=>mdout1_15_6, DO7=>mdout1_15_7, DO8=>mdout1_15_8,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>open,
+ DO19=>open, DO20=>open, DO21=>open, DO22=>open, DO23=>open,
+ DO24=>open, DO25=>open, DO26=>open, DO27=>open, DO28=>open,
+ DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open,
+ DO34=>open, DO35=>open);
+
+ pdp_ram_15_1_2: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec122_p015, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec123_r115, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_15_9,
+ DO1=>mdout1_15_10, DO2=>mdout1_15_11, DO3=>mdout1_15_12,
+ DO4=>mdout1_15_13, DO5=>mdout1_15_14, DO6=>mdout1_15_15,
+ DO7=>mdout1_15_16, DO8=>mdout1_15_17, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_15_2_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec124_p015, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec125_r115, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_15_18,
+ DO1=>mdout1_15_19, DO2=>mdout1_15_20, DO3=>mdout1_15_21,
+ DO4=>mdout1_15_22, DO5=>mdout1_15_23, DO6=>mdout1_15_24,
+ DO7=>mdout1_15_25, DO8=>mdout1_15_26, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_15_3_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>dec126_p015, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>dec127_r115, CSR1=>rden_i,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_15_27,
+ DO1=>mdout1_15_28, DO2=>mdout1_15_29, DO3=>mdout1_15_30,
+ DO4=>mdout1_15_31, DO5=>mdout1_15_32, DO6=>mdout1_15_33,
+ DO7=>mdout1_15_34, DO8=>mdout1_15_35, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_14, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_14);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_15, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_15);
+
+ FF_90: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_89: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_88: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_15);
+
+ FF_72: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_14);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_15);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_14);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_15, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_15);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_13);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_14, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_14);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_15, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_15);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_13_ff);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_14, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_14_ff);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff2);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff2);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_13_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_13_ff2);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_14_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_14_ff2);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_14, CK=>Clock, CD=>Reset, Q=>wcnt_reg_14);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_15, CK=>Clock, CD=>Reset, Q=>wcnt_reg_15);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC1=>fcount_13, PC0=>fcount_12, CON=>cnt_con,
+ CO=>co6, NC1=>ifcount_13, NC0=>ifcount_12);
+
+ bdcnt_bctr_7: CB2
+ port map (CI=>co6, PC1=>fcount_15, PC0=>fcount_14, CON=>cnt_con,
+ CO=>co7, NC1=>ifcount_15, NC0=>ifcount_14);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co5_1, LE=>co6_1);
+
+ e_cmp_7: ALEB2
+ port map (A1=>fcount_15, A0=>fcount_14, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co6_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i, B0=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>wren_i, B0=>wren_i,
+ CI=>co5_2, GE=>co6_2);
+
+ g_cmp_7: AGEB2
+ port map (A1=>fcount_15, A0=>fcount_14, B1=>wren_i_inv,
+ B0=>wren_i, CI=>co6_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_3,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC1=>wcount_13, PC0=>wcount_12, CO=>co6_3,
+ NC1=>iwcount_13, NC0=>iwcount_12);
+
+ w_ctr_7: CU2
+ port map (CI=>co6_3, PC1=>wcount_15, PC0=>wcount_14, CO=>co7_1,
+ NC1=>iwcount_15, NC0=>iwcount_14);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_4,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC1=>rcount_13, PC0=>rcount_12, CO=>co6_4,
+ NC1=>ircount_13, NC0=>ircount_12);
+
+ r_ctr_7: CU2
+ port map (CI=>co6_4, PC1=>rcount_15, PC0=>rcount_14, CO=>co7_2,
+ NC1=>ircount_15, NC0=>ircount_14);
+
+ mux_35: MUX161
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, D4=>mdout1_4_0, D5=>mdout1_5_0,
+ D6=>mdout1_6_0, D7=>mdout1_7_0, D8=>mdout1_8_0,
+ D9=>mdout1_9_0, D10=>mdout1_10_0, D11=>mdout1_11_0,
+ D12=>mdout1_12_0, D13=>mdout1_13_0, D14=>mdout1_14_0,
+ D15=>mdout1_15_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(0));
+
+ mux_34: MUX161
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, D4=>mdout1_4_1, D5=>mdout1_5_1,
+ D6=>mdout1_6_1, D7=>mdout1_7_1, D8=>mdout1_8_1,
+ D9=>mdout1_9_1, D10=>mdout1_10_1, D11=>mdout1_11_1,
+ D12=>mdout1_12_1, D13=>mdout1_13_1, D14=>mdout1_14_1,
+ D15=>mdout1_15_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(1));
+
+ mux_33: MUX161
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, D4=>mdout1_4_2, D5=>mdout1_5_2,
+ D6=>mdout1_6_2, D7=>mdout1_7_2, D8=>mdout1_8_2,
+ D9=>mdout1_9_2, D10=>mdout1_10_2, D11=>mdout1_11_2,
+ D12=>mdout1_12_2, D13=>mdout1_13_2, D14=>mdout1_14_2,
+ D15=>mdout1_15_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(2));
+
+ mux_32: MUX161
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, D4=>mdout1_4_3, D5=>mdout1_5_3,
+ D6=>mdout1_6_3, D7=>mdout1_7_3, D8=>mdout1_8_3,
+ D9=>mdout1_9_3, D10=>mdout1_10_3, D11=>mdout1_11_3,
+ D12=>mdout1_12_3, D13=>mdout1_13_3, D14=>mdout1_14_3,
+ D15=>mdout1_15_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(3));
+
+ mux_31: MUX161
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, D4=>mdout1_4_4, D5=>mdout1_5_4,
+ D6=>mdout1_6_4, D7=>mdout1_7_4, D8=>mdout1_8_4,
+ D9=>mdout1_9_4, D10=>mdout1_10_4, D11=>mdout1_11_4,
+ D12=>mdout1_12_4, D13=>mdout1_13_4, D14=>mdout1_14_4,
+ D15=>mdout1_15_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(4));
+
+ mux_30: MUX161
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, D4=>mdout1_4_5, D5=>mdout1_5_5,
+ D6=>mdout1_6_5, D7=>mdout1_7_5, D8=>mdout1_8_5,
+ D9=>mdout1_9_5, D10=>mdout1_10_5, D11=>mdout1_11_5,
+ D12=>mdout1_12_5, D13=>mdout1_13_5, D14=>mdout1_14_5,
+ D15=>mdout1_15_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(5));
+
+ mux_29: MUX161
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, D4=>mdout1_4_6, D5=>mdout1_5_6,
+ D6=>mdout1_6_6, D7=>mdout1_7_6, D8=>mdout1_8_6,
+ D9=>mdout1_9_6, D10=>mdout1_10_6, D11=>mdout1_11_6,
+ D12=>mdout1_12_6, D13=>mdout1_13_6, D14=>mdout1_14_6,
+ D15=>mdout1_15_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(6));
+
+ mux_28: MUX161
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, D4=>mdout1_4_7, D5=>mdout1_5_7,
+ D6=>mdout1_6_7, D7=>mdout1_7_7, D8=>mdout1_8_7,
+ D9=>mdout1_9_7, D10=>mdout1_10_7, D11=>mdout1_11_7,
+ D12=>mdout1_12_7, D13=>mdout1_13_7, D14=>mdout1_14_7,
+ D15=>mdout1_15_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(7));
+
+ mux_27: MUX161
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, D4=>mdout1_4_8, D5=>mdout1_5_8,
+ D6=>mdout1_6_8, D7=>mdout1_7_8, D8=>mdout1_8_8,
+ D9=>mdout1_9_8, D10=>mdout1_10_8, D11=>mdout1_11_8,
+ D12=>mdout1_12_8, D13=>mdout1_13_8, D14=>mdout1_14_8,
+ D15=>mdout1_15_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(8));
+
+ mux_26: MUX161
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, D4=>mdout1_4_9, D5=>mdout1_5_9,
+ D6=>mdout1_6_9, D7=>mdout1_7_9, D8=>mdout1_8_9,
+ D9=>mdout1_9_9, D10=>mdout1_10_9, D11=>mdout1_11_9,
+ D12=>mdout1_12_9, D13=>mdout1_13_9, D14=>mdout1_14_9,
+ D15=>mdout1_15_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(9));
+
+ mux_25: MUX161
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, D4=>mdout1_4_10, D5=>mdout1_5_10,
+ D6=>mdout1_6_10, D7=>mdout1_7_10, D8=>mdout1_8_10,
+ D9=>mdout1_9_10, D10=>mdout1_10_10, D11=>mdout1_11_10,
+ D12=>mdout1_12_10, D13=>mdout1_13_10, D14=>mdout1_14_10,
+ D15=>mdout1_15_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(10));
+
+ mux_24: MUX161
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, D4=>mdout1_4_11, D5=>mdout1_5_11,
+ D6=>mdout1_6_11, D7=>mdout1_7_11, D8=>mdout1_8_11,
+ D9=>mdout1_9_11, D10=>mdout1_10_11, D11=>mdout1_11_11,
+ D12=>mdout1_12_11, D13=>mdout1_13_11, D14=>mdout1_14_11,
+ D15=>mdout1_15_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(11));
+
+ mux_23: MUX161
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, D4=>mdout1_4_12, D5=>mdout1_5_12,
+ D6=>mdout1_6_12, D7=>mdout1_7_12, D8=>mdout1_8_12,
+ D9=>mdout1_9_12, D10=>mdout1_10_12, D11=>mdout1_11_12,
+ D12=>mdout1_12_12, D13=>mdout1_13_12, D14=>mdout1_14_12,
+ D15=>mdout1_15_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(12));
+
+ mux_22: MUX161
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, D4=>mdout1_4_13, D5=>mdout1_5_13,
+ D6=>mdout1_6_13, D7=>mdout1_7_13, D8=>mdout1_8_13,
+ D9=>mdout1_9_13, D10=>mdout1_10_13, D11=>mdout1_11_13,
+ D12=>mdout1_12_13, D13=>mdout1_13_13, D14=>mdout1_14_13,
+ D15=>mdout1_15_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(13));
+
+ mux_21: MUX161
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, D4=>mdout1_4_14, D5=>mdout1_5_14,
+ D6=>mdout1_6_14, D7=>mdout1_7_14, D8=>mdout1_8_14,
+ D9=>mdout1_9_14, D10=>mdout1_10_14, D11=>mdout1_11_14,
+ D12=>mdout1_12_14, D13=>mdout1_13_14, D14=>mdout1_14_14,
+ D15=>mdout1_15_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(14));
+
+ mux_20: MUX161
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, D4=>mdout1_4_15, D5=>mdout1_5_15,
+ D6=>mdout1_6_15, D7=>mdout1_7_15, D8=>mdout1_8_15,
+ D9=>mdout1_9_15, D10=>mdout1_10_15, D11=>mdout1_11_15,
+ D12=>mdout1_12_15, D13=>mdout1_13_15, D14=>mdout1_14_15,
+ D15=>mdout1_15_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(15));
+
+ mux_19: MUX161
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, D4=>mdout1_4_16, D5=>mdout1_5_16,
+ D6=>mdout1_6_16, D7=>mdout1_7_16, D8=>mdout1_8_16,
+ D9=>mdout1_9_16, D10=>mdout1_10_16, D11=>mdout1_11_16,
+ D12=>mdout1_12_16, D13=>mdout1_13_16, D14=>mdout1_14_16,
+ D15=>mdout1_15_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(16));
+
+ mux_18: MUX161
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, D4=>mdout1_4_17, D5=>mdout1_5_17,
+ D6=>mdout1_6_17, D7=>mdout1_7_17, D8=>mdout1_8_17,
+ D9=>mdout1_9_17, D10=>mdout1_10_17, D11=>mdout1_11_17,
+ D12=>mdout1_12_17, D13=>mdout1_13_17, D14=>mdout1_14_17,
+ D15=>mdout1_15_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(17));
+
+ mux_17: MUX161
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, D4=>mdout1_4_18, D5=>mdout1_5_18,
+ D6=>mdout1_6_18, D7=>mdout1_7_18, D8=>mdout1_8_18,
+ D9=>mdout1_9_18, D10=>mdout1_10_18, D11=>mdout1_11_18,
+ D12=>mdout1_12_18, D13=>mdout1_13_18, D14=>mdout1_14_18,
+ D15=>mdout1_15_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(18));
+
+ mux_16: MUX161
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, D4=>mdout1_4_19, D5=>mdout1_5_19,
+ D6=>mdout1_6_19, D7=>mdout1_7_19, D8=>mdout1_8_19,
+ D9=>mdout1_9_19, D10=>mdout1_10_19, D11=>mdout1_11_19,
+ D12=>mdout1_12_19, D13=>mdout1_13_19, D14=>mdout1_14_19,
+ D15=>mdout1_15_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(19));
+
+ mux_15: MUX161
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, D4=>mdout1_4_20, D5=>mdout1_5_20,
+ D6=>mdout1_6_20, D7=>mdout1_7_20, D8=>mdout1_8_20,
+ D9=>mdout1_9_20, D10=>mdout1_10_20, D11=>mdout1_11_20,
+ D12=>mdout1_12_20, D13=>mdout1_13_20, D14=>mdout1_14_20,
+ D15=>mdout1_15_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(20));
+
+ mux_14: MUX161
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, D4=>mdout1_4_21, D5=>mdout1_5_21,
+ D6=>mdout1_6_21, D7=>mdout1_7_21, D8=>mdout1_8_21,
+ D9=>mdout1_9_21, D10=>mdout1_10_21, D11=>mdout1_11_21,
+ D12=>mdout1_12_21, D13=>mdout1_13_21, D14=>mdout1_14_21,
+ D15=>mdout1_15_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(21));
+
+ mux_13: MUX161
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, D4=>mdout1_4_22, D5=>mdout1_5_22,
+ D6=>mdout1_6_22, D7=>mdout1_7_22, D8=>mdout1_8_22,
+ D9=>mdout1_9_22, D10=>mdout1_10_22, D11=>mdout1_11_22,
+ D12=>mdout1_12_22, D13=>mdout1_13_22, D14=>mdout1_14_22,
+ D15=>mdout1_15_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(22));
+
+ mux_12: MUX161
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, D4=>mdout1_4_23, D5=>mdout1_5_23,
+ D6=>mdout1_6_23, D7=>mdout1_7_23, D8=>mdout1_8_23,
+ D9=>mdout1_9_23, D10=>mdout1_10_23, D11=>mdout1_11_23,
+ D12=>mdout1_12_23, D13=>mdout1_13_23, D14=>mdout1_14_23,
+ D15=>mdout1_15_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(23));
+
+ mux_11: MUX161
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, D4=>mdout1_4_24, D5=>mdout1_5_24,
+ D6=>mdout1_6_24, D7=>mdout1_7_24, D8=>mdout1_8_24,
+ D9=>mdout1_9_24, D10=>mdout1_10_24, D11=>mdout1_11_24,
+ D12=>mdout1_12_24, D13=>mdout1_13_24, D14=>mdout1_14_24,
+ D15=>mdout1_15_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(24));
+
+ mux_10: MUX161
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, D4=>mdout1_4_25, D5=>mdout1_5_25,
+ D6=>mdout1_6_25, D7=>mdout1_7_25, D8=>mdout1_8_25,
+ D9=>mdout1_9_25, D10=>mdout1_10_25, D11=>mdout1_11_25,
+ D12=>mdout1_12_25, D13=>mdout1_13_25, D14=>mdout1_14_25,
+ D15=>mdout1_15_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(25));
+
+ mux_9: MUX161
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, D4=>mdout1_4_26, D5=>mdout1_5_26,
+ D6=>mdout1_6_26, D7=>mdout1_7_26, D8=>mdout1_8_26,
+ D9=>mdout1_9_26, D10=>mdout1_10_26, D11=>mdout1_11_26,
+ D12=>mdout1_12_26, D13=>mdout1_13_26, D14=>mdout1_14_26,
+ D15=>mdout1_15_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(26));
+
+ mux_8: MUX161
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, D4=>mdout1_4_27, D5=>mdout1_5_27,
+ D6=>mdout1_6_27, D7=>mdout1_7_27, D8=>mdout1_8_27,
+ D9=>mdout1_9_27, D10=>mdout1_10_27, D11=>mdout1_11_27,
+ D12=>mdout1_12_27, D13=>mdout1_13_27, D14=>mdout1_14_27,
+ D15=>mdout1_15_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(27));
+
+ mux_7: MUX161
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, D4=>mdout1_4_28, D5=>mdout1_5_28,
+ D6=>mdout1_6_28, D7=>mdout1_7_28, D8=>mdout1_8_28,
+ D9=>mdout1_9_28, D10=>mdout1_10_28, D11=>mdout1_11_28,
+ D12=>mdout1_12_28, D13=>mdout1_13_28, D14=>mdout1_14_28,
+ D15=>mdout1_15_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(28));
+
+ mux_6: MUX161
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, D4=>mdout1_4_29, D5=>mdout1_5_29,
+ D6=>mdout1_6_29, D7=>mdout1_7_29, D8=>mdout1_8_29,
+ D9=>mdout1_9_29, D10=>mdout1_10_29, D11=>mdout1_11_29,
+ D12=>mdout1_12_29, D13=>mdout1_13_29, D14=>mdout1_14_29,
+ D15=>mdout1_15_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(29));
+
+ mux_5: MUX161
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, D4=>mdout1_4_30, D5=>mdout1_5_30,
+ D6=>mdout1_6_30, D7=>mdout1_7_30, D8=>mdout1_8_30,
+ D9=>mdout1_9_30, D10=>mdout1_10_30, D11=>mdout1_11_30,
+ D12=>mdout1_12_30, D13=>mdout1_13_30, D14=>mdout1_14_30,
+ D15=>mdout1_15_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(30));
+
+ mux_4: MUX161
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, D4=>mdout1_4_31, D5=>mdout1_5_31,
+ D6=>mdout1_6_31, D7=>mdout1_7_31, D8=>mdout1_8_31,
+ D9=>mdout1_9_31, D10=>mdout1_10_31, D11=>mdout1_11_31,
+ D12=>mdout1_12_31, D13=>mdout1_13_31, D14=>mdout1_14_31,
+ D15=>mdout1_15_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(31));
+
+ mux_3: MUX161
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, D4=>mdout1_4_32, D5=>mdout1_5_32,
+ D6=>mdout1_6_32, D7=>mdout1_7_32, D8=>mdout1_8_32,
+ D9=>mdout1_9_32, D10=>mdout1_10_32, D11=>mdout1_11_32,
+ D12=>mdout1_12_32, D13=>mdout1_13_32, D14=>mdout1_14_32,
+ D15=>mdout1_15_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(32));
+
+ mux_2: MUX161
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, D4=>mdout1_4_33, D5=>mdout1_5_33,
+ D6=>mdout1_6_33, D7=>mdout1_7_33, D8=>mdout1_8_33,
+ D9=>mdout1_9_33, D10=>mdout1_10_33, D11=>mdout1_11_33,
+ D12=>mdout1_12_33, D13=>mdout1_13_33, D14=>mdout1_14_33,
+ D15=>mdout1_15_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(33));
+
+ mux_1: MUX161
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, D4=>mdout1_4_34, D5=>mdout1_5_34,
+ D6=>mdout1_6_34, D7=>mdout1_7_34, D8=>mdout1_8_34,
+ D9=>mdout1_9_34, D10=>mdout1_10_34, D11=>mdout1_11_34,
+ D12=>mdout1_12_34, D13=>mdout1_13_34, D14=>mdout1_14_34,
+ D15=>mdout1_15_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(34));
+
+ mux_0: MUX161
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, D4=>mdout1_4_35, D5=>mdout1_5_35,
+ D6=>mdout1_6_35, D7=>mdout1_7_35, D8=>mdout1_8_35,
+ D9=>mdout1_9_35, D10=>mdout1_10_35, D11=>mdout1_11_35,
+ D12=>mdout1_12_35, D13=>mdout1_13_35, D14=>mdout1_14_35,
+ D15=>mdout1_15_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ SD3=>rptr_13_ff2, SD4=>rptr_14_ff2, Z=>Q(35));
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcount_11, A0=>wcount_10, B1=>rptr_11, B0=>rptr_10,
+ BI=>co4_5, BOUT1=>co5_5, BOUT0=>open, S1=>wcnt_sub_11,
+ S0=>wcnt_sub_10);
+
+ wcnt_6: FSUB2
+ port map (A1=>wcount_13, A0=>wcount_12, B1=>rptr_13, B0=>rptr_12,
+ BI=>co5_5, BOUT1=>co6_5, BOUT0=>open, S1=>wcnt_sub_13,
+ S0=>wcnt_sub_12);
+
+ wcnt_7: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_14, B1=>scuba_vlo,
+ B0=>rptr_14, BI=>co6_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_15, S0=>wcnt_sub_14);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>AmFullThresh(11),
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>co5_6);
+
+ af_set_cmp_6: AGEB2
+ port map (A1=>wcnt_reg_13, A0=>wcnt_reg_12, B1=>AmFullThresh(13),
+ B0=>AmFullThresh(12), CI=>co5_6, GE=>co6_6);
+
+ af_set_cmp_7: AGEB2
+ port map (A1=>wcnt_reg_15, A0=>wcnt_reg_14, B1=>scuba_vlo,
+ B0=>AmFullThresh(14), CI=>co6_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ WCNT(14) <= fcount_14;
+ WCNT(15) <= fcount_15;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x32k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX161 use entity SCM.MUX161(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x4k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:24:32\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=4096\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x4k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 4096 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:24:32 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x4k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(11 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(12 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x4k_oreg;
+
+architecture Structure of fifo_36x4k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal rptr_12: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co5_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co5_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_12: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal co6_1: std_logic;
+ signal wcount_12: std_logic;
+ signal co5_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal ircount_12: std_logic;
+ signal co6_2: std_logic;
+ signal rcount_12: std_logic;
+ signal co5_4: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal mdout1_1_18: std_logic;
+ signal mdout1_0_18: std_logic;
+ signal mdout1_1_19: std_logic;
+ signal mdout1_0_19: std_logic;
+ signal mdout1_1_20: std_logic;
+ signal mdout1_0_20: std_logic;
+ signal mdout1_1_21: std_logic;
+ signal mdout1_0_21: std_logic;
+ signal mdout1_1_22: std_logic;
+ signal mdout1_0_22: std_logic;
+ signal mdout1_1_23: std_logic;
+ signal mdout1_0_23: std_logic;
+ signal mdout1_1_24: std_logic;
+ signal mdout1_0_24: std_logic;
+ signal mdout1_1_25: std_logic;
+ signal mdout1_0_25: std_logic;
+ signal mdout1_1_26: std_logic;
+ signal mdout1_0_26: std_logic;
+ signal mdout1_1_27: std_logic;
+ signal mdout1_0_27: std_logic;
+ signal mdout1_1_28: std_logic;
+ signal mdout1_0_28: std_logic;
+ signal mdout1_1_29: std_logic;
+ signal mdout1_0_29: std_logic;
+ signal mdout1_1_30: std_logic;
+ signal mdout1_0_30: std_logic;
+ signal mdout1_1_31: std_logic;
+ signal mdout1_0_31: std_logic;
+ signal mdout1_1_32: std_logic;
+ signal mdout1_0_32: std_logic;
+ signal mdout1_1_33: std_logic;
+ signal mdout1_0_33: std_logic;
+ signal mdout1_1_34: std_logic;
+ signal mdout1_0_34: std_logic;
+ signal rptr_11_ff2: std_logic;
+ signal mdout1_1_35: std_logic;
+ signal mdout1_0_35: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_11: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal co5_5: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX21
+ port (D0: in std_logic; D1: in std_logic; SD: in std_logic;
+ Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_7 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_7 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_7 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_0_0_7 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_7 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_7 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_7 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_6 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_6 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_6 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_0_1_6 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_6 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_6 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_6 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_5 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_5 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_5 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_0_2_5 : label is "0b000";
+ attribute GSR of pdp_ram_0_2_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_5 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_5 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_5 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_4 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_4 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_3_4 : label is "0b010";
+ attribute CSDECODE_W of pdp_ram_0_3_4 : label is "0b000";
+ attribute GSR of pdp_ram_0_3_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_4 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_3_4 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_3_4 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_3_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_3 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_3 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_0_3 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_0_3 : label is "0b001";
+ attribute GSR of pdp_ram_1_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_3 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_0_3 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_0_3 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_2 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_1_2 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_1_2 : label is "0b001";
+ attribute GSR of pdp_ram_1_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_1_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_1_2 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_1_2 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_2_1 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_2_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_2_1 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_2_1 : label is "0b001";
+ attribute GSR of pdp_ram_1_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_2_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_2_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_2_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_3_0 : label is "fifo_36x4k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_3_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_3_0 : label is "0b011";
+ attribute CSDECODE_W of pdp_ram_1_3_0 : label is "0b001";
+ attribute GSR of pdp_ram_1_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_3_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_3_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_3_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_3_0 : label is "9";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_12, B=>rptr_12, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_7: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_0_0,
+ DO1=>mdout1_0_1, DO2=>mdout1_0_2, DO3=>mdout1_0_3,
+ DO4=>mdout1_0_4, DO5=>mdout1_0_5, DO6=>mdout1_0_6,
+ DO7=>mdout1_0_7, DO8=>mdout1_0_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_6: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_9, DO1=>mdout1_0_10,
+ DO2=>mdout1_0_11, DO3=>mdout1_0_12, DO4=>mdout1_0_13,
+ DO5=>mdout1_0_14, DO6=>mdout1_0_15, DO7=>mdout1_0_16,
+ DO8=>mdout1_0_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_2_5: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_18, DO1=>mdout1_0_19,
+ DO2=>mdout1_0_20, DO3=>mdout1_0_21, DO4=>mdout1_0_22,
+ DO5=>mdout1_0_23, DO6=>mdout1_0_24, DO7=>mdout1_0_25,
+ DO8=>mdout1_0_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_3_4: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "010", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_0_27, DO1=>mdout1_0_28,
+ DO2=>mdout1_0_29, DO3=>mdout1_0_30, DO4=>mdout1_0_31,
+ DO5=>mdout1_0_32, DO6=>mdout1_0_33, DO7=>mdout1_0_34,
+ DO8=>mdout1_0_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_0_3: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rden_i, CSR2=>scuba_vlo, RST=>Reset, DO0=>mdout1_1_0,
+ DO1=>mdout1_1_1, DO2=>mdout1_1_2, DO3=>mdout1_1_3,
+ DO4=>mdout1_1_4, DO5=>mdout1_1_5, DO6=>mdout1_1_6,
+ DO7=>mdout1_1_7, DO8=>mdout1_1_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_1_2: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_9, DO1=>mdout1_1_10,
+ DO2=>mdout1_1_11, DO3=>mdout1_1_12, DO4=>mdout1_1_13,
+ DO5=>mdout1_1_14, DO6=>mdout1_1_15, DO7=>mdout1_1_16,
+ DO8=>mdout1_1_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_2_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_18, DO1=>mdout1_1_19,
+ DO2=>mdout1_1_20, DO3=>mdout1_1_21, DO4=>mdout1_1_22,
+ DO5=>mdout1_1_23, DO6=>mdout1_1_24, DO7=>mdout1_1_25,
+ DO8=>mdout1_1_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_3_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "011", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rden_i, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>mdout1_1_27, DO1=>mdout1_1_28,
+ DO2=>mdout1_1_29, DO3=>mdout1_1_30, DO4=>mdout1_1_31,
+ DO5=>mdout1_1_32, DO6=>mdout1_1_33, DO7=>mdout1_1_34,
+ DO8=>mdout1_1_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_69: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_68: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_67: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_54: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff2);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC1=>scuba_vlo, PC0=>fcount_12, CON=>cnt_con,
+ CO=>co6, NC1=>open, NC0=>ifcount_12);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A1=>scuba_vlo, A0=>fcount_12, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i, B0=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A1=>scuba_vlo, A0=>fcount_12, B1=>scuba_vlo,
+ B0=>wren_i_inv, CI=>co5_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_3,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC1=>scuba_vlo, PC0=>wcount_12, CO=>co6_1,
+ NC1=>open, NC0=>iwcount_12);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_4,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC1=>scuba_vlo, PC0=>rcount_12, CO=>co6_2,
+ NC1=>open, NC0=>ircount_12);
+
+ mux_35: MUX21
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, SD=>rptr_11_ff2,
+ Z=>Q(0));
+
+ mux_34: MUX21
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, SD=>rptr_11_ff2,
+ Z=>Q(1));
+
+ mux_33: MUX21
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, SD=>rptr_11_ff2,
+ Z=>Q(2));
+
+ mux_32: MUX21
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, SD=>rptr_11_ff2,
+ Z=>Q(3));
+
+ mux_31: MUX21
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, SD=>rptr_11_ff2,
+ Z=>Q(4));
+
+ mux_30: MUX21
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, SD=>rptr_11_ff2,
+ Z=>Q(5));
+
+ mux_29: MUX21
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, SD=>rptr_11_ff2,
+ Z=>Q(6));
+
+ mux_28: MUX21
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, SD=>rptr_11_ff2,
+ Z=>Q(7));
+
+ mux_27: MUX21
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, SD=>rptr_11_ff2,
+ Z=>Q(8));
+
+ mux_26: MUX21
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, SD=>rptr_11_ff2,
+ Z=>Q(9));
+
+ mux_25: MUX21
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, SD=>rptr_11_ff2,
+ Z=>Q(10));
+
+ mux_24: MUX21
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, SD=>rptr_11_ff2,
+ Z=>Q(11));
+
+ mux_23: MUX21
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, SD=>rptr_11_ff2,
+ Z=>Q(12));
+
+ mux_22: MUX21
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, SD=>rptr_11_ff2,
+ Z=>Q(13));
+
+ mux_21: MUX21
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, SD=>rptr_11_ff2,
+ Z=>Q(14));
+
+ mux_20: MUX21
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, SD=>rptr_11_ff2,
+ Z=>Q(15));
+
+ mux_19: MUX21
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, SD=>rptr_11_ff2,
+ Z=>Q(16));
+
+ mux_18: MUX21
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, SD=>rptr_11_ff2,
+ Z=>Q(17));
+
+ mux_17: MUX21
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, SD=>rptr_11_ff2,
+ Z=>Q(18));
+
+ mux_16: MUX21
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, SD=>rptr_11_ff2,
+ Z=>Q(19));
+
+ mux_15: MUX21
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, SD=>rptr_11_ff2,
+ Z=>Q(20));
+
+ mux_14: MUX21
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, SD=>rptr_11_ff2,
+ Z=>Q(21));
+
+ mux_13: MUX21
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, SD=>rptr_11_ff2,
+ Z=>Q(22));
+
+ mux_12: MUX21
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, SD=>rptr_11_ff2,
+ Z=>Q(23));
+
+ mux_11: MUX21
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, SD=>rptr_11_ff2,
+ Z=>Q(24));
+
+ mux_10: MUX21
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, SD=>rptr_11_ff2,
+ Z=>Q(25));
+
+ mux_9: MUX21
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, SD=>rptr_11_ff2,
+ Z=>Q(26));
+
+ mux_8: MUX21
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, SD=>rptr_11_ff2,
+ Z=>Q(27));
+
+ mux_7: MUX21
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, SD=>rptr_11_ff2,
+ Z=>Q(28));
+
+ mux_6: MUX21
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, SD=>rptr_11_ff2,
+ Z=>Q(29));
+
+ mux_5: MUX21
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, SD=>rptr_11_ff2,
+ Z=>Q(30));
+
+ mux_4: MUX21
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, SD=>rptr_11_ff2,
+ Z=>Q(31));
+
+ mux_3: MUX21
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, SD=>rptr_11_ff2,
+ Z=>Q(32));
+
+ mux_2: MUX21
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, SD=>rptr_11_ff2,
+ Z=>Q(33));
+
+ mux_1: MUX21
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, SD=>rptr_11_ff2,
+ Z=>Q(34));
+
+ mux_0: MUX21
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, SD=>rptr_11_ff2,
+ Z=>Q(35));
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcount_11, A0=>wcount_10, B1=>rptr_11, B0=>rptr_10,
+ BI=>co4_5, BOUT1=>co5_5, BOUT0=>open, S1=>wcnt_sub_11,
+ S0=>wcnt_sub_10);
+
+ wcnt_6: FSUB2
+ port map (A1=>scuba_vlo, A0=>wcnt_sub_msb, B1=>scuba_vlo,
+ B0=>scuba_vlo, BI=>co5_5, BOUT1=>open, BOUT0=>open, S1=>open,
+ S0=>wcnt_sub_12);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>AmFullThresh(11),
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>co5_6);
+
+ af_set_cmp_6: AGEB2
+ port map (A1=>scuba_vlo, A0=>wcnt_reg_12, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co5_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x4k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX21 use entity SCM.MUX21(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x512_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:23:09\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=512\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x512_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 512 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:23:09 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x512_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(8 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x512_oreg;
+
+architecture Structure of fifo_36x512_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal rptr_9: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co3_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal wcount_8: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x512_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_9, B=>rptr_9, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wptr_0, ADW6=>wptr_1,
+ ADW7=>wptr_2, ADW8=>wptr_3, ADW9=>wptr_4, ADW10=>wptr_5,
+ ADW11=>wptr_6, ADW12=>wptr_7, ADW13=>wptr_8, CEW=>wren_i,
+ CLKW=>Clock, WE=>scuba_vhi, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2, ADR8=>rptr_3,
+ ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6, ADR12=>rptr_7,
+ ADR13=>rptr_8, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_52: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_50: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_40: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i_inv, B0=>wren_i,
+ CI=>co3_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_1,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_2,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_8, B1=>scuba_vlo,
+ B0=>rptr_8, BI=>co3_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_9, S0=>wcnt_sub_8);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>scuba_vlo,
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x512_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]\r
+Family=latticescm\r
+PartType=LFSCM3GA40EP1\r
+PartName=LFSCM3GA40EP1-7FF1020C\r
+SpeedGrade=-7\r
+Package=FFBGA1020\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=FIFO\r
+CoreRevision=4.8\r
+ModuleName=fifo_36x8k_oreg\r
+SourceFormat=Schematic/VHDL\r
+ParameterFileVersion=1.0\r
+Date=06/29/2010\r
+Time=10:24:57\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+FIFOImp=EBR Based\r
+Depth=8192\r
+Width=36\r
+regout=1\r
+CtrlByRdEn=0\r
+EmpFlg=0\r
+PeMode=Static - Dual Threshold\r
+PeAssert=10\r
+PeDeassert=12\r
+FullFlg=1\r
+PfMode=Dynamic - Single Threshold\r
+PfAssert=508\r
+PfDeassert=506\r
+RDataCount=1\r
+EnECC=0\r
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v80_SP1_Build
+-- Module Version: 4.8
+--X:\Programme\ispTOOLS_80\ispfpga\bin\nt\scuba.exe -w -n fifo_36x8k_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 8192 -width 36 -regout -no_enable -pe -1 -pf 0 -fill -e
+
+-- Tue Jun 29 10:24:57 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo_36x8k_oreg is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmFullThresh: in std_logic_vector(12 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(13 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_36x8k_oreg;
+
+architecture Structure of fifo_36x8k_oreg is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal rptr_13: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co5_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co5_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co6_1: std_logic;
+ signal wcount_13: std_logic;
+ signal co5_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal rcount_10: std_logic;
+ signal rcount_11: std_logic;
+ signal co4_4: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co6_2: std_logic;
+ signal rcount_12: std_logic;
+ signal rcount_13: std_logic;
+ signal co5_4: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_3_9: std_logic;
+ signal mdout1_2_9: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_3_10: std_logic;
+ signal mdout1_2_10: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_3_11: std_logic;
+ signal mdout1_2_11: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_3_12: std_logic;
+ signal mdout1_2_12: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_3_13: std_logic;
+ signal mdout1_2_13: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_3_14: std_logic;
+ signal mdout1_2_14: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_3_15: std_logic;
+ signal mdout1_2_15: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_3_16: std_logic;
+ signal mdout1_2_16: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal mdout1_3_17: std_logic;
+ signal mdout1_2_17: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal mdout1_3_18: std_logic;
+ signal mdout1_2_18: std_logic;
+ signal mdout1_1_18: std_logic;
+ signal mdout1_0_18: std_logic;
+ signal mdout1_3_19: std_logic;
+ signal mdout1_2_19: std_logic;
+ signal mdout1_1_19: std_logic;
+ signal mdout1_0_19: std_logic;
+ signal mdout1_3_20: std_logic;
+ signal mdout1_2_20: std_logic;
+ signal mdout1_1_20: std_logic;
+ signal mdout1_0_20: std_logic;
+ signal mdout1_3_21: std_logic;
+ signal mdout1_2_21: std_logic;
+ signal mdout1_1_21: std_logic;
+ signal mdout1_0_21: std_logic;
+ signal mdout1_3_22: std_logic;
+ signal mdout1_2_22: std_logic;
+ signal mdout1_1_22: std_logic;
+ signal mdout1_0_22: std_logic;
+ signal mdout1_3_23: std_logic;
+ signal mdout1_2_23: std_logic;
+ signal mdout1_1_23: std_logic;
+ signal mdout1_0_23: std_logic;
+ signal mdout1_3_24: std_logic;
+ signal mdout1_2_24: std_logic;
+ signal mdout1_1_24: std_logic;
+ signal mdout1_0_24: std_logic;
+ signal mdout1_3_25: std_logic;
+ signal mdout1_2_25: std_logic;
+ signal mdout1_1_25: std_logic;
+ signal mdout1_0_25: std_logic;
+ signal mdout1_3_26: std_logic;
+ signal mdout1_2_26: std_logic;
+ signal mdout1_1_26: std_logic;
+ signal mdout1_0_26: std_logic;
+ signal mdout1_3_27: std_logic;
+ signal mdout1_2_27: std_logic;
+ signal mdout1_1_27: std_logic;
+ signal mdout1_0_27: std_logic;
+ signal mdout1_3_28: std_logic;
+ signal mdout1_2_28: std_logic;
+ signal mdout1_1_28: std_logic;
+ signal mdout1_0_28: std_logic;
+ signal mdout1_3_29: std_logic;
+ signal mdout1_2_29: std_logic;
+ signal mdout1_1_29: std_logic;
+ signal mdout1_0_29: std_logic;
+ signal mdout1_3_30: std_logic;
+ signal mdout1_2_30: std_logic;
+ signal mdout1_1_30: std_logic;
+ signal mdout1_0_30: std_logic;
+ signal mdout1_3_31: std_logic;
+ signal mdout1_2_31: std_logic;
+ signal mdout1_1_31: std_logic;
+ signal mdout1_0_31: std_logic;
+ signal mdout1_3_32: std_logic;
+ signal mdout1_2_32: std_logic;
+ signal mdout1_1_32: std_logic;
+ signal mdout1_0_32: std_logic;
+ signal mdout1_3_33: std_logic;
+ signal mdout1_2_33: std_logic;
+ signal mdout1_1_33: std_logic;
+ signal mdout1_0_33: std_logic;
+ signal mdout1_3_34: std_logic;
+ signal mdout1_2_34: std_logic;
+ signal mdout1_1_34: std_logic;
+ signal mdout1_0_34: std_logic;
+ signal rptr_12_ff2: std_logic;
+ signal rptr_11_ff2: std_logic;
+ signal mdout1_3_35: std_logic;
+ signal mdout1_2_35: std_logic;
+ signal mdout1_1_35: std_logic;
+ signal mdout1_0_35: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal cnt_con: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal co0_5: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal co1_5: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal co2_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal co3_5: std_logic;
+ signal rptr_8: std_logic;
+ signal rptr_9: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal co4_5: std_logic;
+ signal rptr_10: std_logic;
+ signal rptr_11: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal co5_5: std_logic;
+ signal rptr_12: std_logic;
+ signal wcount_12: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component MUX41
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ Z: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FADD2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; COUT1: out std_logic;
+ COUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component FSUB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; BI: in std_logic; BOUT1: out std_logic;
+ BOUT0: out std_logic; S1: out std_logic;
+ S0: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_15 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_0_0_15 : label is "0b000";
+ attribute GSR of pdp_ram_0_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_15 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_15 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_15 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_15 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_14 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_14 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_14 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_0_1_14 : label is "0b000";
+ attribute GSR of pdp_ram_0_1_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_14 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_14 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_14 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_14 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_13 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_13 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_2_13 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_0_2_13 : label is "0b000";
+ attribute GSR of pdp_ram_0_2_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_13 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_2_13 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_2_13 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_2_13 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_12 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_12 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_3_12 : label is "0b100";
+ attribute CSDECODE_W of pdp_ram_0_3_12 : label is "0b000";
+ attribute GSR of pdp_ram_0_3_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_12 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_3_12 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_3_12 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_0_3_12 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_11 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_11 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_0_11 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_1_0_11 : label is "0b001";
+ attribute GSR of pdp_ram_1_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_11 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_0_11 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_0_11 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_0_11 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_10 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_10 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_1_10 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_1_1_10 : label is "0b001";
+ attribute GSR of pdp_ram_1_1_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_1_10 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_1_10 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_1_10 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_1_10 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_2_9 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_2_9 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_2_9 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_1_2_9 : label is "0b001";
+ attribute GSR of pdp_ram_1_2_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_2_9 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_2_9 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_2_9 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_2_9 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_3_8 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_3_8 : label is "";
+ attribute CSDECODE_R of pdp_ram_1_3_8 : label is "0b101";
+ attribute CSDECODE_W of pdp_ram_1_3_8 : label is "0b001";
+ attribute GSR of pdp_ram_1_3_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_3_8 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_1_3_8 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_1_3_8 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_1_3_8 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_7 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_7 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_0_7 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_2_0_7 : label is "0b010";
+ attribute GSR of pdp_ram_2_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_7 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_0_7 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_0_7 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_6 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_6 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_1_6 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_2_1_6 : label is "0b010";
+ attribute GSR of pdp_ram_2_1_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_1_6 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_1_6 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_1_6 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_1_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_2_5 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_2_5 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_2_5 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_2_2_5 : label is "0b010";
+ attribute GSR of pdp_ram_2_2_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_2_5 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_2_5 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_2_5 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_2_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_3_4 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_3_4 : label is "";
+ attribute CSDECODE_R of pdp_ram_2_3_4 : label is "0b110";
+ attribute CSDECODE_W of pdp_ram_2_3_4 : label is "0b010";
+ attribute GSR of pdp_ram_2_3_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_3_4 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_2_3_4 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_2_3_4 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_2_3_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_3 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_3 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_0_3 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_3_0_3 : label is "0b011";
+ attribute GSR of pdp_ram_3_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_3 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_0_3 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_0_3 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_2 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_2 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_1_2 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_3_1_2 : label is "0b011";
+ attribute GSR of pdp_ram_3_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_1_2 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_1_2 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_1_2 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_2_1 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_2_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_2_1 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_3_2_1 : label is "0b011";
+ attribute GSR of pdp_ram_3_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_2_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_2_1 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_2_1 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_3_0 : label is "fifo_36x8k_oreg.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_3_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_3_3_0 : label is "0b111";
+ attribute CSDECODE_W of pdp_ram_3_3_0 : label is "0b011";
+ attribute GSR of pdp_ram_3_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_3_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_3_3_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_3_3_0 : label is "9";
+ attribute DATA_WIDTH_W of pdp_ram_3_3_0 : label is "9";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t5: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_4: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t4: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_3: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t3: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t2: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_2: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_1: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t1: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb);
+
+ pdp_ram_0_0_15: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rptr_12, CSR2=>rden_i, RST=>Reset, DO0=>mdout1_0_0,
+ DO1=>mdout1_0_1, DO2=>mdout1_0_2, DO3=>mdout1_0_3,
+ DO4=>mdout1_0_4, DO5=>mdout1_0_5, DO6=>mdout1_0_6,
+ DO7=>mdout1_0_7, DO8=>mdout1_0_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_1_14: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_0_9, DO1=>mdout1_0_10,
+ DO2=>mdout1_0_11, DO3=>mdout1_0_12, DO4=>mdout1_0_13,
+ DO5=>mdout1_0_14, DO6=>mdout1_0_15, DO7=>mdout1_0_16,
+ DO8=>mdout1_0_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_2_13: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_0_18, DO1=>mdout1_0_19,
+ DO2=>mdout1_0_20, DO3=>mdout1_0_21, DO4=>mdout1_0_22,
+ DO5=>mdout1_0_23, DO6=>mdout1_0_24, DO7=>mdout1_0_25,
+ DO8=>mdout1_0_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_0_3_12: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "100", CSDECODE_W=> "000", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_0_27, DO1=>mdout1_0_28,
+ DO2=>mdout1_0_29, DO3=>mdout1_0_30, DO4=>mdout1_0_31,
+ DO5=>mdout1_0_32, DO6=>mdout1_0_33, DO7=>mdout1_0_34,
+ DO8=>mdout1_0_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_0_11: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rptr_12, CSR2=>rden_i, RST=>Reset, DO0=>mdout1_1_0,
+ DO1=>mdout1_1_1, DO2=>mdout1_1_2, DO3=>mdout1_1_3,
+ DO4=>mdout1_1_4, DO5=>mdout1_1_5, DO6=>mdout1_1_6,
+ DO7=>mdout1_1_7, DO8=>mdout1_1_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_1_10: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_1_9, DO1=>mdout1_1_10,
+ DO2=>mdout1_1_11, DO3=>mdout1_1_12, DO4=>mdout1_1_13,
+ DO5=>mdout1_1_14, DO6=>mdout1_1_15, DO7=>mdout1_1_16,
+ DO8=>mdout1_1_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_2_9: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_1_18, DO1=>mdout1_1_19,
+ DO2=>mdout1_1_20, DO3=>mdout1_1_21, DO4=>mdout1_1_22,
+ DO5=>mdout1_1_23, DO6=>mdout1_1_24, DO7=>mdout1_1_25,
+ DO8=>mdout1_1_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_1_3_8: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "101", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_1_27, DO1=>mdout1_1_28,
+ DO2=>mdout1_1_29, DO3=>mdout1_1_30, DO4=>mdout1_1_31,
+ DO5=>mdout1_1_32, DO6=>mdout1_1_33, DO7=>mdout1_1_34,
+ DO8=>mdout1_1_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_0_7: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rptr_12, CSR2=>rden_i, RST=>Reset, DO0=>mdout1_2_0,
+ DO1=>mdout1_2_1, DO2=>mdout1_2_2, DO3=>mdout1_2_3,
+ DO4=>mdout1_2_4, DO5=>mdout1_2_5, DO6=>mdout1_2_6,
+ DO7=>mdout1_2_7, DO8=>mdout1_2_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_1_6: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_2_9, DO1=>mdout1_2_10,
+ DO2=>mdout1_2_11, DO3=>mdout1_2_12, DO4=>mdout1_2_13,
+ DO5=>mdout1_2_14, DO6=>mdout1_2_15, DO7=>mdout1_2_16,
+ DO8=>mdout1_2_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_2_5: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_2_18, DO1=>mdout1_2_19,
+ DO2=>mdout1_2_20, DO3=>mdout1_2_21, DO4=>mdout1_2_22,
+ DO5=>mdout1_2_23, DO6=>mdout1_2_24, DO7=>mdout1_2_25,
+ DO8=>mdout1_2_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_2_3_4: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "110", CSDECODE_W=> "010", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_2_27, DO1=>mdout1_2_28,
+ DO2=>mdout1_2_29, DO3=>mdout1_2_30, DO4=>mdout1_2_31,
+ DO5=>mdout1_2_32, DO6=>mdout1_2_33, DO7=>mdout1_2_34,
+ DO8=>mdout1_2_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_0_3: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>scuba_vlo, ADW1=>scuba_vlo,
+ ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1, ADW5=>wptr_2,
+ ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5, ADW9=>wptr_6,
+ ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9, ADW13=>wptr_10,
+ CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi, CSW0=>wptr_11,
+ CSW1=>wptr_12, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>rptr_0, ADR4=>rptr_1,
+ ADR5=>rptr_2, ADR6=>rptr_3, ADR7=>rptr_4, ADR8=>rptr_5,
+ ADR9=>rptr_6, ADR10=>rptr_7, ADR11=>rptr_8, ADR12=>rptr_9,
+ ADR13=>rptr_10, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rptr_11,
+ CSR1=>rptr_12, CSR2=>rden_i, RST=>Reset, DO0=>mdout1_3_0,
+ DO1=>mdout1_3_1, DO2=>mdout1_3_2, DO3=>mdout1_3_3,
+ DO4=>mdout1_3_4, DO5=>mdout1_3_5, DO6=>mdout1_3_6,
+ DO7=>mdout1_3_7, DO8=>mdout1_3_8, DO9=>open, DO10=>open,
+ DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open,
+ DO16=>open, DO17=>open, DO18=>open, DO19=>open, DO20=>open,
+ DO21=>open, DO22=>open, DO23=>open, DO24=>open, DO25=>open,
+ DO26=>open, DO27=>open, DO28=>open, DO29=>open, DO30=>open,
+ DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_1_2: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(9), DI1=>Data(10), DI2=>Data(11),
+ DI3=>Data(12), DI4=>Data(13), DI5=>Data(14), DI6=>Data(15),
+ DI7=>Data(16), DI8=>Data(17), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_3_9, DO1=>mdout1_3_10,
+ DO2=>mdout1_3_11, DO3=>mdout1_3_12, DO4=>mdout1_3_13,
+ DO5=>mdout1_3_14, DO6=>mdout1_3_15, DO7=>mdout1_3_16,
+ DO8=>mdout1_3_17, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_2_1: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(18), DI1=>Data(19), DI2=>Data(20),
+ DI3=>Data(21), DI4=>Data(22), DI5=>Data(23), DI6=>Data(24),
+ DI7=>Data(25), DI8=>Data(26), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_3_18, DO1=>mdout1_3_19,
+ DO2=>mdout1_3_20, DO3=>mdout1_3_21, DO4=>mdout1_3_22,
+ DO5=>mdout1_3_23, DO6=>mdout1_3_24, DO7=>mdout1_3_25,
+ DO8=>mdout1_3_26, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ pdp_ram_3_3_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "111", CSDECODE_W=> "011", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 9,
+ DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(27), DI1=>Data(28), DI2=>Data(29),
+ DI3=>Data(30), DI4=>Data(31), DI5=>Data(32), DI6=>Data(33),
+ DI7=>Data(34), DI8=>Data(35), DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>scuba_vlo,
+ ADW1=>scuba_vlo, ADW2=>scuba_vlo, ADW3=>wptr_0, ADW4=>wptr_1,
+ ADW5=>wptr_2, ADW6=>wptr_3, ADW7=>wptr_4, ADW8=>wptr_5,
+ ADW9=>wptr_6, ADW10=>wptr_7, ADW11=>wptr_8, ADW12=>wptr_9,
+ ADW13=>wptr_10, CEW=>wren_i, CLKW=>Clock, WE=>scuba_vhi,
+ CSW0=>wptr_11, CSW1=>wptr_12, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>rptr_0, ADR4=>rptr_1, ADR5=>rptr_2, ADR6=>rptr_3,
+ ADR7=>rptr_4, ADR8=>rptr_5, ADR9=>rptr_6, ADR10=>rptr_7,
+ ADR11=>rptr_8, ADR12=>rptr_9, ADR13=>rptr_10, CER=>scuba_vhi,
+ CLKR=>Clock, CSR0=>rptr_11, CSR1=>rptr_12, CSR2=>rden_i,
+ RST=>Reset, DO0=>mdout1_3_27, DO1=>mdout1_3_28,
+ DO2=>mdout1_3_29, DO3=>mdout1_3_30, DO4=>mdout1_3_31,
+ DO5=>mdout1_3_32, DO6=>mdout1_3_33, DO7=>mdout1_3_34,
+ DO8=>mdout1_3_35, DO9=>open, DO10=>open, DO11=>open,
+ DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>open, DO19=>open, DO20=>open, DO21=>open,
+ DO22=>open, DO23=>open, DO24=>open, DO25=>open, DO26=>open,
+ DO27=>open, DO28=>open, DO29=>open, DO30=>open, DO31=>open,
+ DO32=>open, DO33=>open, DO34=>open, DO35=>open);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_76: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_75: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_74: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_60: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_13);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff2);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12_ff, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff2);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC1=>fcount_11, PC0=>fcount_10, CON=>cnt_con,
+ CO=>co5, NC1=>ifcount_11, NC0=>ifcount_10);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC1=>fcount_13, PC0=>fcount_12, CON=>cnt_con,
+ CO=>co6, NC1=>ifcount_13, NC0=>ifcount_12);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i, B0=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A1=>fcount_11, A0=>fcount_10, B1=>wren_i, B0=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A1=>fcount_13, A0=>fcount_12, B1=>wren_i_inv,
+ B0=>wren_i, CI=>co5_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_3,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC1=>wcount_11, PC0=>wcount_10, CO=>co5_3,
+ NC1=>iwcount_11, NC0=>iwcount_10);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC1=>wcount_13, PC0=>wcount_12, CO=>co6_1,
+ NC1=>iwcount_13, NC0=>iwcount_12);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_4,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC1=>rcount_11, PC0=>rcount_10, CO=>co5_4,
+ NC1=>ircount_11, NC0=>ircount_10);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC1=>rcount_13, PC0=>rcount_12, CO=>co6_2,
+ NC1=>ircount_13, NC0=>ircount_12);
+
+ mux_35: MUX41
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(0));
+
+ mux_34: MUX41
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(1));
+
+ mux_33: MUX41
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(2));
+
+ mux_32: MUX41
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(3));
+
+ mux_31: MUX41
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(4));
+
+ mux_30: MUX41
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(5));
+
+ mux_29: MUX41
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(6));
+
+ mux_28: MUX41
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(7));
+
+ mux_27: MUX41
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(8));
+
+ mux_26: MUX41
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2, Z=>Q(9));
+
+ mux_25: MUX41
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(10));
+
+ mux_24: MUX41
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(11));
+
+ mux_23: MUX41
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(12));
+
+ mux_22: MUX41
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(13));
+
+ mux_21: MUX41
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(14));
+
+ mux_20: MUX41
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(15));
+
+ mux_19: MUX41
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(16));
+
+ mux_18: MUX41
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(17));
+
+ mux_17: MUX41
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(18));
+
+ mux_16: MUX41
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(19));
+
+ mux_15: MUX41
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(20));
+
+ mux_14: MUX41
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(21));
+
+ mux_13: MUX41
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(22));
+
+ mux_12: MUX41
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(23));
+
+ mux_11: MUX41
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(24));
+
+ mux_10: MUX41
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(25));
+
+ mux_9: MUX41
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(26));
+
+ mux_8: MUX41
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(27));
+
+ mux_7: MUX41
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(28));
+
+ mux_6: MUX41
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(29));
+
+ mux_5: MUX41
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(30));
+
+ mux_4: MUX41
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(31));
+
+ mux_3: MUX41
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(32));
+
+ mux_2: MUX41
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(33));
+
+ mux_1: MUX41
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(34));
+
+ mux_0: MUX41
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, SD1=>rptr_11_ff2, SD2=>rptr_12_ff2,
+ Z=>Q(35));
+
+ wcnt_0: FSUB2
+ port map (A1=>wcount_1, A0=>wcount_0, B1=>rptr_1, B0=>rptr_0,
+ BI=>cnt_con, BOUT1=>co0_5, BOUT0=>open, S1=>wcnt_sub_1,
+ S0=>wcnt_sub_0);
+
+ wcnt_1: FSUB2
+ port map (A1=>wcount_3, A0=>wcount_2, B1=>rptr_3, B0=>rptr_2,
+ BI=>co0_5, BOUT1=>co1_5, BOUT0=>open, S1=>wcnt_sub_3,
+ S0=>wcnt_sub_2);
+
+ wcnt_2: FSUB2
+ port map (A1=>wcount_5, A0=>wcount_4, B1=>rptr_5, B0=>rptr_4,
+ BI=>co1_5, BOUT1=>co2_5, BOUT0=>open, S1=>wcnt_sub_5,
+ S0=>wcnt_sub_4);
+
+ wcnt_3: FSUB2
+ port map (A1=>wcount_7, A0=>wcount_6, B1=>rptr_7, B0=>rptr_6,
+ BI=>co2_5, BOUT1=>co3_5, BOUT0=>open, S1=>wcnt_sub_7,
+ S0=>wcnt_sub_6);
+
+ wcnt_4: FSUB2
+ port map (A1=>wcount_9, A0=>wcount_8, B1=>rptr_9, B0=>rptr_8,
+ BI=>co3_5, BOUT1=>co4_5, BOUT0=>open, S1=>wcnt_sub_9,
+ S0=>wcnt_sub_8);
+
+ wcnt_5: FSUB2
+ port map (A1=>wcount_11, A0=>wcount_10, B1=>rptr_11, B0=>rptr_10,
+ BI=>co4_5, BOUT1=>co5_5, BOUT0=>open, S1=>wcnt_sub_11,
+ S0=>wcnt_sub_10);
+
+ wcnt_6: FSUB2
+ port map (A1=>wcnt_sub_msb, A0=>wcount_12, B1=>scuba_vlo,
+ B0=>rptr_12, BI=>co5_5, BOUT1=>open, BOUT0=>open,
+ S1=>wcnt_sub_13, S0=>wcnt_sub_12);
+
+ af_set_cmp_0: AGEB2
+ port map (A1=>wcnt_reg_1, A0=>wcnt_reg_0, B1=>AmFullThresh(1),
+ B0=>AmFullThresh(0), CI=>wren_i, GE=>co0_6);
+
+ af_set_cmp_1: AGEB2
+ port map (A1=>wcnt_reg_3, A0=>wcnt_reg_2, B1=>AmFullThresh(3),
+ B0=>AmFullThresh(2), CI=>co0_6, GE=>co1_6);
+
+ af_set_cmp_2: AGEB2
+ port map (A1=>wcnt_reg_5, A0=>wcnt_reg_4, B1=>AmFullThresh(5),
+ B0=>AmFullThresh(4), CI=>co1_6, GE=>co2_6);
+
+ af_set_cmp_3: AGEB2
+ port map (A1=>wcnt_reg_7, A0=>wcnt_reg_6, B1=>AmFullThresh(7),
+ B0=>AmFullThresh(6), CI=>co2_6, GE=>co3_6);
+
+ af_set_cmp_4: AGEB2
+ port map (A1=>wcnt_reg_9, A0=>wcnt_reg_8, B1=>AmFullThresh(9),
+ B0=>AmFullThresh(8), CI=>co3_6, GE=>co4_6);
+
+ af_set_cmp_5: AGEB2
+ port map (A1=>wcnt_reg_11, A0=>wcnt_reg_10, B1=>AmFullThresh(11),
+ B0=>AmFullThresh(10), CI=>co4_6, GE=>co5_6);
+
+ af_set_cmp_6: AGEB2
+ port map (A1=>wcnt_reg_13, A0=>wcnt_reg_12, B1=>scuba_vlo,
+ B0=>AmFullThresh(12), CI=>co5_6, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a0: FADD2
+ port map (A1=>scuba_vlo, A0=>scuba_vlo, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>af_set_c, COUT1=>open, COUT0=>open,
+ S1=>open, S0=>af_set);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo_36x8k_oreg is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:MUX41 use entity SCM.MUX41(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FADD2 use entity SCM.FADD2(V); end for;
+ for all:FSUB2 use entity SCM.FSUB2(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3BX use entity SCM.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
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