--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 01/02/2007
+-- Description: this entity initializes trigger_handle_tld.
+-- It controls if ROC1 has been written correctly after trigger begrun
+-- This entity receive the request of data from the TRB and distribute the
+-- trigger internally to others entity.
+--
+-- This code has not optimized yet.
+-- 01/09/2007 I added INIT_TDC_READOUT_OUT and INIT_TDC_READOUT_OUT ports
+--
+--
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity common_stop_generator is
+ generic (width : integer := 5);
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ A_CMS_OUT : out std_logic; --common stop to all buses
+ A_RDO_IN : in std_logic; --ready FROM first motherboard
+ TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger
+
+ INIT_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); --to all buses
+ INIT_TRIGGER_HANDLE_TLD_OUT : out std_logic_vector(3 downto 0);
+
+ ROC1_WRITTEN_IN : in std_logic;
+ CAL1_WRITTEN_IN : in std_logic;
+
+ ENABLE_MODE_LINE_OUT : out std_logic_vector(3 downto 0);
+ ENABLE_A_ADD_DATA_OUT : out std_logic --'1'(mdc_addon to MBs)
+ );
+end common_stop_generator;
+
+architecture behavioral of common_stop_generator is
+
+ type state_type is (idle_state, common_stop_out_state,
+ wait_state, normal_trigger_state,
+ begrun_trigger_out_state,
+ wait_roc1_written, wait_token_back_state,
+ roc1_written_state, pull_down_cms, reinit_roc1_state,
+ stop_state, calibration_trigger_state,
+--calibration state
+ calibration_readout_0, calibration_readout_1,
+ calibration_readout_2, calibration_readout_3,
+ wait_cal1_written);
+
+ signal current_state, next_state : state_type;
+ signal reg_a_cms, next_a_cms : std_logic;
+ signal time_counter : std_logic_vector(15 downto 0);
+ signal time_counter_2 : std_logic_vector(15 downto 0);
+
+ signal counter_reset : std_logic;
+ signal reg_enable_mode_line, next_enable_mode_line : std_logic_vector(3 downto 0);
+
+ signal reg_token_to_trb, next_token_to_trb : std_logic;
+ signal reg_init_trigger_handle_tld_i, next_init_trigger_handle_tld_i : std_logic_vector(3 downto 0);
+
+ signal reg_init_tdc_readout, next_init_tdc_readout : std_logic_vector(3 downto 0);
+
+ signal reg_enable_a_add_data_i, next_enable_a_add_data_i : std_logic;
+ signal reset_all_counters : std_logic;
+ signal reg_succesful_reinit_roc1, next_succesful_reinit_roc1 : std_logic;
+ signal no_token_number : std_logic_vector(63 downto 0);
+ signal reset_no_token_number, roc_written_i : std_logic;
+ signal bus_0_roc1_written_i, bus_1_roc1_written_i : std_logic;
+
+ constant time_limit : std_logic_vector(width - 1 downto 0) := (others => '1');
+
+begin -- behavioral
+
+ REGISTER_ADDR_DATA_MODE : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_a_cms <= '0';
+ reg_token_to_trb <= '0';
+ reg_init_tdc_readout <= (others => '0');
+ reg_init_trigger_handle_tld_i <= (others => '0');
+ reg_enable_a_add_data_i <= '0';
+ reg_succesful_reinit_roc1 <= '0';
+ else
+ current_state <= next_state;
+ reg_a_cms <= next_a_cms;
+ reg_enable_mode_line <= next_enable_mode_line;
+ reg_token_to_trb <= next_token_to_trb;
+ reg_init_tdc_readout <= next_init_tdc_readout;
+ reg_init_trigger_handle_tld_i <= next_init_trigger_handle_tld_i;
+ reg_enable_a_add_data_i <= next_enable_a_add_data_i;
+ reg_succesful_reinit_roc1 <= next_succesful_reinit_roc1;
+ end if;
+ end if;
+ end process REGISTER_ADDR_DATA_MODE;
+
+-- TOKEN_TO_TRB <= reg_token_to_trb;
+ A_CMS_OUT <= reg_a_cms;
+
+ INIT_TDC_READOUT_OUT <= reg_init_tdc_readout;
+ INIT_TRIGGER_HANDLE_TLD_OUT <= reg_init_trigger_handle_tld_i;
+
+ ENABLE_A_ADD_DATA_OUT <= reg_enable_a_add_data_i;
+ ENABLE_MODE_LINE_OUT <= reg_enable_mode_line;
+
+-- SUCCESFUL_REINIT_ROC1_OUT <= reg_succesful_reinit_roc1; --when (no_token_number >= x"0000000000000001") else '0';
+
+ process (current_state, time_counter,
+ time_counter_2,
+ TRIGGER_TYPE_IN, roc_written_i,
+ ROC1_WRITTEN_IN, A_RDO_IN, CAL1_WRITTEN_IN)
+ begin
+ reset_all_counters <= '0';
+ next_init_trigger_handle_tld_i <= (others => '0');
+ -- next_init_trb_interface_i <= '0';
+ next_init_tdc_readout <= (others => '0');
+ next_enable_mode_line <= (others => '0');
+ next_enable_a_add_data_i <= '0';
+ next_token_to_trb <= '0';
+ next_a_cms <= '0';
+ next_succesful_reinit_roc1 <= '0';
+
+ case current_state is
+
+ when idle_state =>
+ --DEBUG_REGISTER <= "0000";
+ reset_all_counters <= '1';
+ next_a_cms <= '0';
+ if TRIGGER_TYPE_IN = x"D" then
+ next_state <= begrun_trigger_out_state;
+ elsif TRIGGER_TYPE_IN = x"1" then
+ next_state <= common_stop_out_state;
+ elsif TRIGGER_TYPE_IN = x"C" then
+ next_state <= calibration_trigger_state;
+ else
+ next_state <= idle_state;
+ end if;
+
+--here I generate the CMS
+ when common_stop_out_state =>
+ --DEBUG_REGISTER <= "001";
+ reset_all_counters <= '0';
+ next_enable_mode_line <= x"1";
+ --next_init_trb_interface_i <= '1';
+ next_init_tdc_readout <= x"1";
+ next_a_cms <= '1';
+ next_state <= normal_trigger_state;
+-------------------------------------------------------------------------------
+-- here I add delay between CMS and token
+-------------------------------------------------------------------------------
+ when wait_state =>
+ -- DEBUG_REGISTER <= "010";
+ reset_all_counters <= '0';
+ next_a_cms <= '1'; --mantain cms up
+ next_enable_mode_line <= x"1";
+ if time_counter_2 >= "0000000001111111" then
+--ok 25MHz
+ --if time_counter_2 >= "0000000000000100" then --oep
+ next_state <= normal_trigger_state;
+ else
+ next_state <= wait_state;
+ end if;
+-------------------------------------------------------------------------------
+--here I send the token
+-------------------------------------------------------------------------------
+ when normal_trigger_state =>
+ -- DEBUG_REGISTER <= "011";
+ reset_all_counters <= '0';
+ next_a_cms <= '1'; --mantain cms up
+ next_enable_mode_line <= x"1";
+ next_init_trigger_handle_tld_i <= x"1"; --this sends token
+ -- next_init_trb_interface_i <= '0'; --I prepare the readout
+--here I size the width at 320 ns
+ if time_counter > "0000000000011111" then -- time_limit then
+--ok 25MHz
+-- if time_counter > "0000000000001100" then -- oep
+ next_state <= wait_token_back_state;
+ else
+ next_state <= normal_trigger_state;
+ end if;
+
+ when wait_token_back_state =>
+ reset_all_counters <= '0';
+ next_a_cms <= '0'; --'1'; --mantain cms up
+ next_enable_mode_line <= x"1";
+ if A_RDO_IN = '1' then --real token back or request to reinit
+ next_state <= idle_state;
+ else
+ next_state <= wait_token_back_state;
+ end if;
+-------------------------------------------------------------------------------
+-- BEGRUN TRIGGER
+-------------------------------------------------------------------------------
+ when begrun_trigger_out_state =>
+ --DEBUG_REGISTER <= "100";
+ reset_all_counters <= '0';
+ next_enable_mode_line <= x"D";
+ next_enable_a_add_data_i <= '1'; --mux for config. (mdc_addon to MBs)
+ next_init_trigger_handle_tld_i <= x"D";
+ next_state <= wait_roc1_written;
+
+ when wait_roc1_written =>
+ -- DEBUG_REGISTER <= "101";
+ reset_all_counters <= '0';
+ next_enable_mode_line <= x"D";
+ next_enable_a_add_data_i <= '1'; --mux for config. (mdc_addon to MBs)
+ if ROC1_WRITTEN_IN = '1' then
+ next_token_to_trb <= '1'; --token to trb simulated:)
+ next_state <= roc1_written_state;
+ else
+ next_state <= wait_roc1_written;
+ end if;
+
+ when roc1_written_state =>
+ reset_all_counters <= '0';
+ next_token_to_trb <= '0'; --token to trb simulated:)
+ next_state <= idle_state;
+--! next_state <= normal_trigger_state;
+-------------------------------------------------------------------------------
+-- CALIBRATION TRIGGER
+-------------------------------------------------------------------------------
+ when calibration_trigger_state => --here like begrun
+ next_enable_mode_line <= x"D";
+ next_enable_a_add_data_i <= '1';
+ next_init_trigger_handle_tld_i <= x"2"; --start calibration
+ next_state <= wait_cal1_written;
+
+ when wait_cal1_written =>
+ next_enable_mode_line <= x"D";
+ next_enable_a_add_data_i <= '1';
+-- CAL1_WRITTEN = '1' means the CAL1 has been loaded and I can start the
+-- readout as usual WITHOUT CMS signal
+ if CAL1_WRITTEN_IN = '1' then
+ next_state <= calibration_readout_0; --readout starts
+ else
+ next_state <= wait_cal1_written;
+ end if;
+-------------------------------------------------------------------------------
+--Readout the calibration data
+-------------------------------------------------------------------------------
+ when calibration_readout_0 =>
+ reset_all_counters <= '0';
+ next_enable_mode_line <= x"1";
+ -- next_init_trb_interface_i <= '1';
+ next_init_tdc_readout <= x"9";
+ next_a_cms <= '0';
+ next_state <= calibration_readout_2;
+-- when calibration_readout_1 =>
+-- reset_all_counters <= '0';
+-- next_a_cms <= '0';
+-- next_enable_mode_line <= x"1";
+-- if calibration_counter_0 >= "0000000001111111" then
+-- next_state <= calibration_readout_2;
+-- else
+-- next_state <= calibration_readout_1;
+-- end if;
+-------------------------------------------------------------------------------
+--here I send the token
+-------------------------------------------------------------------------------
+ when calibration_readout_2 =>
+ reset_all_counters <= '0';
+ next_a_cms <= '0';
+ next_enable_mode_line <= x"1";
+ next_init_trigger_handle_tld_i <= x"1"; --this sends token
+ -- next_init_trb_interface_i <= '0';
+ next_state <= calibration_readout_3;
+-- if time_counter_1 > "0000000000011111" then -- time_limit then
+-- next_state <= calibration_readout_3;
+-- else
+-- next_state <= calibration_readout_2;
+-- end if;
+
+ when calibration_readout_3 =>
+ reset_all_counters <= '0';
+ next_a_cms <= '0';
+ next_enable_mode_line <= x"1";
+ if A_RDO_IN = '1' then
+ next_state <= idle_state;
+ else
+ next_state <= calibration_readout_3;
+ end if;
+
+ when others =>
+ next_state <= idle_state;
+ end case;
+ end process;
+
+-------------------------------------------------------------------------------
+--purpose: this counter is used to generate the common stop 800ns before the token
+--and to tune the cms length (320ns)
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_all_counters = '1' then
+ time_counter <= (others => '0');
+ elsif (current_state = normal_trigger_state) then
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+--counter used in wait_state: delay between CMS and token
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_all_counters = '1' then
+ time_counter_2 <= (others => '0');
+ elsif (current_state = wait_state) then
+ time_counter_2 <= time_counter_2 + 1;
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+--I count number of token I do NOT receive from MB
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_no_token_number = '1' then
+ no_token_number <= (others => '0');
+ elsif (current_state = reinit_roc1_state) then
+ no_token_number <= no_token_number + 1;
+ else
+ no_token_number <= no_token_number;
+ end if;
+ end if;
+ end process;
+
+ reset_no_token_number <= '0'; --test
+end behavioral;
+
+
+
+
+
+
+
+
+
+
my $SPEEDGRADE="5";
#create full lpf file
-system("cp ../cvs/trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf");
+system("cp ../trbnet/pinout/mdc_oep3.lpf workdir/mdc_oepb.lpf");
system("cat constraints.lpf >> workdir/mdc_oepb.lpf");
#generate timestamp
#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t" -f "$TOPNAME.p3t" "$tpmap.ncd" "$TOPNAME.ncd"|;
$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
-#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f ../$TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
execute($c);
# # IOR IO Timing Report
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_12bit is
+ Port ( QOUT : out std_logic_vector(11 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLR : in std_logic);
+end counter_12bit;
+
+architecture Behavioral of counter_12bit is
+
+signal counter: std_logic_vector (11 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if rising_edge(CLK) then
+ if CLR = '1' or RESET = '1' then
+ counter <= ( others => '0');
+ elsif UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+ end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_4bit is
+ Port ( QOUT : out std_logic_vector(3 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLR : in std_logic);
+end counter_4bit;
+
+architecture Behavioral of counter_4bit is
+
+signal counter: std_logic_vector (3 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if rising_edge(CLK) then
+ if CLR = '1' or RESET = '1' then
+ counter <= ( others => '0');
+ elsif UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+ end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity counter_8bit is
+ Port ( QOUT : out std_logic_vector(7 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLR : in std_logic);
+end counter_8bit;
+
+architecture Behavioral of counter_8bit is
+
+signal counter: std_logic_vector (7 downto 0);
+
+begin
+
+ process (CLR, UP, CLK)
+
+ begin
+ if rising_edge(CLK) then
+ if CLR = '1' or RESET = '1' then
+ counter <= ( others => '0');
+ elsif UP = '1' then
+ counter <= counter + 1;
+ else
+ counter <= counter;
+ end if;
+ end if;
+ end process;
+
+QOUT <= counter;
+
+end Behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+
+--library synplify;
+--use synplify.attributes.all;
+
+
+entity edge_to_pulse is
+
+ port (
+ CLOCK : in std_logic;
+ ENABLE_CLK_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+
+end edge_to_pulse;
+
+architecture arch_edge_to_pulse of edge_to_pulse is
+ signal signal_sync : std_logic;
+ signal old_sync : std_logic;
+ type state is (idle, high, wait_for_low); -- state
+ signal current_state, next_state : state;
+
+begin -- arch_edge_to_pulse
+
+ fsm : process (CLOCK)
+ begin -- process fsm
+ if (rising_edge(CLOCK)) then
+ if ENABLE_CLK_IN = '1' then
+ current_state <= next_state;
+ signal_sync <= SIGNAL_IN;
+ end if;
+ end if;
+ end process fsm;
+
+
+ fsm_comb : process (current_state, signal_sync)
+ begin -- process fsm_comb
+ case current_state is
+ when idle =>
+ PULSE_OUT <= '0';
+ if signal_sync = '1' then
+ next_state <= high;
+ else
+ next_state <= idle;
+ end if;
+
+ when high =>
+ PULSE_OUT <= '1';
+ next_state <= wait_for_low;
+-- when wait_for_low_1 =>
+-- pulse <= '1';
+-- next_state <= wait_for_low;
+ when wait_for_low =>
+ PULSE_OUT <= '0';
+ if signal_sync = '0' then
+ next_state <= idle;
+ else
+ next_state <= wait_for_low;
+ end if;
+ when others =>
+ next_state <= idle;
+ end case;
+ end process fsm_comb;
+
+
+end arch_edge_to_pulse;
+
+
+
+-- library IEEE;
+-- use IEEE.STD_LOGIC_1164.all;
+
+-- package support is
+
+-- component f_divider
+-- generic (
+-- cnt : integer);
+-- port (
+-- clk : in std_logic;
+-- ena_cnt : in std_logic;
+-- f_div : out std_logic);
+-- end component;
+
+-- component edge_to_pulse
+-- port (
+-- clock : in std_logic;
+-- en_clk : in std_logic;
+-- signal_in : in std_logic;
+-- pulse : out std_logic);
+-- end component;
+
+
+-- end support;
+
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.5
+--/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -no_enable -pe 0 -pf 0 -fill -e
+
+-- Wed May 13 09:18:51 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_8192depth_36width_dual_thresh is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ AmEmptyThresh: in std_logic_vector(12 downto 0);
+ AmFullThresh: in std_logic_vector(12 downto 0);
+ Q: out std_logic_vector(35 downto 0);
+ WCNT: out std_logic_vector(13 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_8192depth_36width_dual_thresh;
+
+architecture Structure of fifo_8192depth_36width_dual_thresh is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw: std_logic;
+ signal rcnt_reg_12_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal rptr_13: std_logic;
+ signal rcnt_reg_13: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co3: std_logic;
+ signal ifcount_10: std_logic;
+ signal ifcount_11: std_logic;
+ signal co4: std_logic;
+ signal ifcount_12: std_logic;
+ signal ifcount_13: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal cmp_ci: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal co4_1: std_logic;
+ signal co5_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_2: std_logic;
+ signal fcount_10: std_logic;
+ signal fcount_11: std_logic;
+ signal co5_2: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_12: std_logic;
+ signal fcount_13: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4_3: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co6_1: std_logic;
+ signal wcount_13: std_logic;
+ signal co5_3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_4: std_logic;
+ signal ircount_10: std_logic;
+ signal ircount_11: std_logic;
+ signal co4_4: std_logic;
+ signal ircount_12: std_logic;
+ signal ircount_13: std_logic;
+ signal co6_2: std_logic;
+ signal rcount_13: std_logic;
+ signal co5_4: std_logic;
+ signal mdout1_3_0: std_logic;
+ signal mdout1_2_0: std_logic;
+ signal mdout1_1_0: std_logic;
+ signal mdout1_0_0: std_logic;
+ signal mdout1_3_1: std_logic;
+ signal mdout1_2_1: std_logic;
+ signal mdout1_1_1: std_logic;
+ signal mdout1_0_1: std_logic;
+ signal mdout1_3_2: std_logic;
+ signal mdout1_2_2: std_logic;
+ signal mdout1_1_2: std_logic;
+ signal mdout1_0_2: std_logic;
+ signal mdout1_3_3: std_logic;
+ signal mdout1_2_3: std_logic;
+ signal mdout1_1_3: std_logic;
+ signal mdout1_0_3: std_logic;
+ signal mdout1_3_4: std_logic;
+ signal mdout1_2_4: std_logic;
+ signal mdout1_1_4: std_logic;
+ signal mdout1_0_4: std_logic;
+ signal mdout1_3_5: std_logic;
+ signal mdout1_2_5: std_logic;
+ signal mdout1_1_5: std_logic;
+ signal mdout1_0_5: std_logic;
+ signal mdout1_3_6: std_logic;
+ signal mdout1_2_6: std_logic;
+ signal mdout1_1_6: std_logic;
+ signal mdout1_0_6: std_logic;
+ signal mdout1_3_7: std_logic;
+ signal mdout1_2_7: std_logic;
+ signal mdout1_1_7: std_logic;
+ signal mdout1_0_7: std_logic;
+ signal mdout1_3_8: std_logic;
+ signal mdout1_2_8: std_logic;
+ signal mdout1_1_8: std_logic;
+ signal mdout1_0_8: std_logic;
+ signal mdout1_3_9: std_logic;
+ signal mdout1_2_9: std_logic;
+ signal mdout1_1_9: std_logic;
+ signal mdout1_0_9: std_logic;
+ signal mdout1_3_10: std_logic;
+ signal mdout1_2_10: std_logic;
+ signal mdout1_1_10: std_logic;
+ signal mdout1_0_10: std_logic;
+ signal mdout1_3_11: std_logic;
+ signal mdout1_2_11: std_logic;
+ signal mdout1_1_11: std_logic;
+ signal mdout1_0_11: std_logic;
+ signal mdout1_3_12: std_logic;
+ signal mdout1_2_12: std_logic;
+ signal mdout1_1_12: std_logic;
+ signal mdout1_0_12: std_logic;
+ signal mdout1_3_13: std_logic;
+ signal mdout1_2_13: std_logic;
+ signal mdout1_1_13: std_logic;
+ signal mdout1_0_13: std_logic;
+ signal mdout1_3_14: std_logic;
+ signal mdout1_2_14: std_logic;
+ signal mdout1_1_14: std_logic;
+ signal mdout1_0_14: std_logic;
+ signal mdout1_3_15: std_logic;
+ signal mdout1_2_15: std_logic;
+ signal mdout1_1_15: std_logic;
+ signal mdout1_0_15: std_logic;
+ signal mdout1_3_16: std_logic;
+ signal mdout1_2_16: std_logic;
+ signal mdout1_1_16: std_logic;
+ signal mdout1_0_16: std_logic;
+ signal mdout1_3_17: std_logic;
+ signal mdout1_2_17: std_logic;
+ signal mdout1_1_17: std_logic;
+ signal mdout1_0_17: std_logic;
+ signal mdout1_3_18: std_logic;
+ signal mdout1_2_18: std_logic;
+ signal mdout1_1_18: std_logic;
+ signal mdout1_0_18: std_logic;
+ signal mdout1_3_19: std_logic;
+ signal mdout1_2_19: std_logic;
+ signal mdout1_1_19: std_logic;
+ signal mdout1_0_19: std_logic;
+ signal mdout1_3_20: std_logic;
+ signal mdout1_2_20: std_logic;
+ signal mdout1_1_20: std_logic;
+ signal mdout1_0_20: std_logic;
+ signal mdout1_3_21: std_logic;
+ signal mdout1_2_21: std_logic;
+ signal mdout1_1_21: std_logic;
+ signal mdout1_0_21: std_logic;
+ signal mdout1_3_22: std_logic;
+ signal mdout1_2_22: std_logic;
+ signal mdout1_1_22: std_logic;
+ signal mdout1_0_22: std_logic;
+ signal mdout1_3_23: std_logic;
+ signal mdout1_2_23: std_logic;
+ signal mdout1_1_23: std_logic;
+ signal mdout1_0_23: std_logic;
+ signal mdout1_3_24: std_logic;
+ signal mdout1_2_24: std_logic;
+ signal mdout1_1_24: std_logic;
+ signal mdout1_0_24: std_logic;
+ signal mdout1_3_25: std_logic;
+ signal mdout1_2_25: std_logic;
+ signal mdout1_1_25: std_logic;
+ signal mdout1_0_25: std_logic;
+ signal mdout1_3_26: std_logic;
+ signal mdout1_2_26: std_logic;
+ signal mdout1_1_26: std_logic;
+ signal mdout1_0_26: std_logic;
+ signal mdout1_3_27: std_logic;
+ signal mdout1_2_27: std_logic;
+ signal mdout1_1_27: std_logic;
+ signal mdout1_0_27: std_logic;
+ signal mdout1_3_28: std_logic;
+ signal mdout1_2_28: std_logic;
+ signal mdout1_1_28: std_logic;
+ signal mdout1_0_28: std_logic;
+ signal mdout1_3_29: std_logic;
+ signal mdout1_2_29: std_logic;
+ signal mdout1_1_29: std_logic;
+ signal mdout1_0_29: std_logic;
+ signal mdout1_3_30: std_logic;
+ signal mdout1_2_30: std_logic;
+ signal mdout1_1_30: std_logic;
+ signal mdout1_0_30: std_logic;
+ signal mdout1_3_31: std_logic;
+ signal mdout1_2_31: std_logic;
+ signal mdout1_1_31: std_logic;
+ signal mdout1_0_31: std_logic;
+ signal mdout1_3_32: std_logic;
+ signal mdout1_2_32: std_logic;
+ signal mdout1_1_32: std_logic;
+ signal mdout1_0_32: std_logic;
+ signal mdout1_3_33: std_logic;
+ signal mdout1_2_33: std_logic;
+ signal mdout1_1_33: std_logic;
+ signal mdout1_0_33: std_logic;
+ signal mdout1_3_34: std_logic;
+ signal mdout1_2_34: std_logic;
+ signal mdout1_1_34: std_logic;
+ signal mdout1_0_34: std_logic;
+ signal rptr_12_ff: std_logic;
+ signal rptr_11_ff: std_logic;
+ signal mdout1_3_35: std_logic;
+ signal mdout1_2_35: std_logic;
+ signal mdout1_1_35: std_logic;
+ signal mdout1_0_35: std_logic;
+ signal rcnt_sub_0: std_logic;
+ signal r_nw_inv_inv: std_logic;
+ signal rcount_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal rcnt_sub_1: std_logic;
+ signal rcnt_sub_2: std_logic;
+ signal co0_5: std_logic;
+ signal rcount_1: std_logic;
+ signal rcount_2: std_logic;
+ signal rcnt_sub_3: std_logic;
+ signal rcnt_sub_4: std_logic;
+ signal co1_5: std_logic;
+ signal rcount_3: std_logic;
+ signal rcount_4: std_logic;
+ signal rcnt_sub_5: std_logic;
+ signal rcnt_sub_6: std_logic;
+ signal co2_5: std_logic;
+ signal rcount_5: std_logic;
+ signal rcount_6: std_logic;
+ signal rcnt_sub_7: std_logic;
+ signal rcnt_sub_8: std_logic;
+ signal co3_5: std_logic;
+ signal rcount_7: std_logic;
+ signal rcount_8: std_logic;
+ signal rcnt_sub_9: std_logic;
+ signal rcnt_sub_10: std_logic;
+ signal co4_5: std_logic;
+ signal rcount_9: std_logic;
+ signal rcount_10: std_logic;
+ signal rcnt_sub_11: std_logic;
+ signal rcnt_sub_12: std_logic;
+ signal co5_5: std_logic;
+ signal rcount_11: std_logic;
+ signal rcount_12: std_logic;
+ signal rcnt_sub_13: std_logic;
+ signal co6_3: std_logic;
+ signal rcnt_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal rcnt_reg_0: std_logic;
+ signal rcnt_reg_1: std_logic;
+ signal co0_6: std_logic;
+ signal rcnt_reg_2: std_logic;
+ signal rcnt_reg_3: std_logic;
+ signal co1_6: std_logic;
+ signal rcnt_reg_4: std_logic;
+ signal rcnt_reg_5: std_logic;
+ signal co2_6: std_logic;
+ signal rcnt_reg_6: std_logic;
+ signal rcnt_reg_7: std_logic;
+ signal co3_6: std_logic;
+ signal rcnt_reg_8: std_logic;
+ signal rcnt_reg_9: std_logic;
+ signal co4_6: std_logic;
+ signal rcnt_reg_10: std_logic;
+ signal rcnt_reg_11: std_logic;
+ signal co5_6: std_logic;
+ signal rcnt_reg_12: std_logic;
+ signal ae_set_clrsig: std_logic;
+ signal ae_set_setsig: std_logic;
+ signal ae_set_d: std_logic;
+ signal ae_set_d_c: std_logic;
+ signal wcnt_sub_0: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal rptr_0: std_logic;
+ signal cnt_con: std_logic;
+ signal wcount_0: std_logic;
+ signal wcnt_sub_1: std_logic;
+ signal wcnt_sub_2: std_logic;
+ signal co0_7: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal wcount_1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcnt_sub_3: std_logic;
+ signal wcnt_sub_4: std_logic;
+ signal co1_7: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal wcount_3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcnt_sub_5: std_logic;
+ signal wcnt_sub_6: std_logic;
+ signal co2_7: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal wcount_5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcnt_sub_7: std_logic;
+ signal wcnt_sub_8: std_logic;
+ signal co3_7: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal wcount_7: std_logic;
+ signal wcount_8: std_logic;
+ signal wcnt_sub_9: std_logic;
+ signal wcnt_sub_10: std_logic;
+ signal co4_7: std_logic;
+ signal rptr_9: std_logic;
+ signal rptr_10: std_logic;
+ signal wcount_9: std_logic;
+ signal wcount_10: std_logic;
+ signal wcnt_sub_11: std_logic;
+ signal wcnt_sub_12: std_logic;
+ signal co5_7: std_logic;
+ signal rptr_11: std_logic;
+ signal rptr_12: std_logic;
+ signal wcount_11: std_logic;
+ signal wcount_12: std_logic;
+ signal wcnt_sub_13: std_logic;
+ signal co6_4: std_logic;
+ signal wcnt_sub_msb: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_3: std_logic;
+ signal wcnt_reg_0: std_logic;
+ signal wcnt_reg_1: std_logic;
+ signal co0_8: std_logic;
+ signal wcnt_reg_2: std_logic;
+ signal wcnt_reg_3: std_logic;
+ signal co1_8: std_logic;
+ signal wcnt_reg_4: std_logic;
+ signal wcnt_reg_5: std_logic;
+ signal co2_8: std_logic;
+ signal wcnt_reg_6: std_logic;
+ signal wcnt_reg_7: std_logic;
+ signal co3_8: std_logic;
+ signal wcnt_reg_8: std_logic;
+ signal wcnt_reg_9: std_logic;
+ signal co4_8: std_logic;
+ signal wcnt_reg_10: std_logic;
+ signal wcnt_reg_11: std_logic;
+ signal co5_8: std_logic;
+ signal wcnt_reg_12: std_logic;
+ signal wcnt_reg_13: std_logic;
+ signal af_set: std_logic;
+ signal af_set_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component MUX41
+ port (D0: in std_logic; D1: in std_logic; D2: in std_logic;
+ D3: in std_logic; SD1: in std_logic; SD2: in std_logic;
+ Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_15 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_0_15 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_15 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_15 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_15 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_15 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_15 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_0_15 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_15 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_15 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_14 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_14 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_1_14 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_1_14 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_1_14 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_1_14 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_1_14 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_14 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_1_14 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_1_14 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_1_14 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_1_14 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_2_13 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_2_13 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_2_13 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_2_13 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_2_13 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_2_13 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_2_13 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_2_13 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_2_13 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_2_13 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_2_13 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_2_13 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_0_3_12 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_3_12 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_3_12 : label is "0b000";
+ attribute CSDECODE_A of pdp_ram_0_3_12 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_3_12 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_3_12 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_3_12 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_3_12 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_3_12 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_0_3_12 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_3_12 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_0_3_12 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_0_11 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_0_11 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_0_11 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_0_11 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_0_11 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_0_11 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_0_11 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_0_11 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_0_11 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_0_11 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_0_11 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_0_11 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_1_10 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_1_10 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_1_10 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_1_10 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_1_10 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_1_10 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_1_10 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_1_10 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_1_10 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_1_10 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_1_10 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_1_10 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_2_9 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_2_9 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_2_9 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_2_9 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_2_9 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_2_9 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_2_9 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_2_9 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_2_9 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_2_9 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_2_9 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_2_9 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_1_3_8 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_1_3_8 : label is "";
+ attribute CSDECODE_B of pdp_ram_1_3_8 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_1_3_8 : label is "0b001";
+ attribute WRITEMODE_B of pdp_ram_1_3_8 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_1_3_8 : label is "NORMAL";
+ attribute GSR of pdp_ram_1_3_8 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_1_3_8 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_1_3_8 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_1_3_8 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_1_3_8 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_1_3_8 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_0_7 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_0_7 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_0_7 : label is "0b010";
+ attribute CSDECODE_A of pdp_ram_2_0_7 : label is "0b010";
+ attribute WRITEMODE_B of pdp_ram_2_0_7 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_0_7 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_0_7 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_0_7 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_0_7 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_0_7 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_0_7 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_0_7 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_1_6 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_1_6 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_1_6 : label is "0b010";
+ attribute CSDECODE_A of pdp_ram_2_1_6 : label is "0b010";
+ attribute WRITEMODE_B of pdp_ram_2_1_6 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_1_6 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_1_6 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_1_6 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_1_6 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_1_6 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_1_6 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_1_6 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_2_5 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_2_5 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_2_5 : label is "0b010";
+ attribute CSDECODE_A of pdp_ram_2_2_5 : label is "0b010";
+ attribute WRITEMODE_B of pdp_ram_2_2_5 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_2_5 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_2_5 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_2_5 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_2_5 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_2_5 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_2_5 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_2_5 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_2_3_4 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_2_3_4 : label is "";
+ attribute CSDECODE_B of pdp_ram_2_3_4 : label is "0b010";
+ attribute CSDECODE_A of pdp_ram_2_3_4 : label is "0b010";
+ attribute WRITEMODE_B of pdp_ram_2_3_4 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_2_3_4 : label is "NORMAL";
+ attribute GSR of pdp_ram_2_3_4 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_2_3_4 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_2_3_4 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_2_3_4 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_2_3_4 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_2_3_4 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_0_3 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_0_3 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_0_3 : label is "0b011";
+ attribute CSDECODE_A of pdp_ram_3_0_3 : label is "0b011";
+ attribute WRITEMODE_B of pdp_ram_3_0_3 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_0_3 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_0_3 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_0_3 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_0_3 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_0_3 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_0_3 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_0_3 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_1_2 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_1_2 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_1_2 : label is "0b011";
+ attribute CSDECODE_A of pdp_ram_3_1_2 : label is "0b011";
+ attribute WRITEMODE_B of pdp_ram_3_1_2 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_1_2 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_1_2 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_1_2 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_1_2 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_1_2 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_1_2 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_1_2 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_2_1 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_2_1 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_2_1 : label is "0b011";
+ attribute CSDECODE_A of pdp_ram_3_2_1 : label is "0b011";
+ attribute WRITEMODE_B of pdp_ram_3_2_1 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_2_1 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_2_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_2_1 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_2_1 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_2_1 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_2_1 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_2_1 : label is "9";
+ attribute MEM_LPC_FILE of pdp_ram_3_3_0 : label is "fifo_8192depth_36width_dual_thresh.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_3_3_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_3_3_0 : label is "0b011";
+ attribute CSDECODE_A of pdp_ram_3_3_0 : label is "0b011";
+ attribute WRITEMODE_B of pdp_ram_3_3_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_3_3_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_3_3_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_3_3_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_3_3_0 : label is "NOREG";
+ attribute REGMODE_A of pdp_ram_3_3_0 : label is "NOREG";
+ attribute DATA_WIDTH_B of pdp_ram_3_3_0 : label is "9";
+ attribute DATA_WIDTH_A of pdp_ram_3_3_0 : label is "9";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t8: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t7: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t6: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t5: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_6: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_5: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t4: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ XOR2_t3: XOR2
+ port map (A=>wcount_13, B=>rcount_13, Z=>rcnt_sub_msb);
+
+ INV_2: INV
+ port map (A=>r_nw_inv, Z=>r_nw_inv_inv);
+
+ INV_1: INV
+ port map (A=>rcnt_reg_12, Z=>rcnt_reg_12_inv);
+
+ AND2_t2: AND2
+ port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_set_clrsig);
+
+ AND2_t1: AND2
+ port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_set_setsig);
+
+ XOR2_t0: XOR2
+ port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb);
+
+ INV_0: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ pdp_ram_0_0_15: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_0_0, DOB1=>mdout1_0_1,
+ DOB2=>mdout1_0_2, DOB3=>mdout1_0_3, DOB4=>mdout1_0_4,
+ DOB5=>mdout1_0_5, DOB6=>mdout1_0_6, DOB7=>mdout1_0_7,
+ DOB8=>mdout1_0_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ pdp_ram_0_1_14: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_9, DOB1=>mdout1_0_10, DOB2=>mdout1_0_11,
+ DOB3=>mdout1_0_12, DOB4=>mdout1_0_13, DOB5=>mdout1_0_14,
+ DOB6=>mdout1_0_15, DOB7=>mdout1_0_16, DOB8=>mdout1_0_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_0_2_13: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_18, DOB1=>mdout1_0_19, DOB2=>mdout1_0_20,
+ DOB3=>mdout1_0_21, DOB4=>mdout1_0_22, DOB5=>mdout1_0_23,
+ DOB6=>mdout1_0_24, DOB7=>mdout1_0_25, DOB8=>mdout1_0_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_0_3_12: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_0_27, DOB1=>mdout1_0_28, DOB2=>mdout1_0_29,
+ DOB3=>mdout1_0_30, DOB4=>mdout1_0_31, DOB5=>mdout1_0_32,
+ DOB6=>mdout1_0_33, DOB7=>mdout1_0_34, DOB8=>mdout1_0_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_1_0_11: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_1_0, DOB1=>mdout1_1_1,
+ DOB2=>mdout1_1_2, DOB3=>mdout1_1_3, DOB4=>mdout1_1_4,
+ DOB5=>mdout1_1_5, DOB6=>mdout1_1_6, DOB7=>mdout1_1_7,
+ DOB8=>mdout1_1_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ pdp_ram_1_1_10: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_9, DOB1=>mdout1_1_10, DOB2=>mdout1_1_11,
+ DOB3=>mdout1_1_12, DOB4=>mdout1_1_13, DOB5=>mdout1_1_14,
+ DOB6=>mdout1_1_15, DOB7=>mdout1_1_16, DOB8=>mdout1_1_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_1_2_9: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_18, DOB1=>mdout1_1_19, DOB2=>mdout1_1_20,
+ DOB3=>mdout1_1_21, DOB4=>mdout1_1_22, DOB5=>mdout1_1_23,
+ DOB6=>mdout1_1_24, DOB7=>mdout1_1_25, DOB8=>mdout1_1_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_1_3_8: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "001", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_1_27, DOB1=>mdout1_1_28, DOB2=>mdout1_1_29,
+ DOB3=>mdout1_1_30, DOB4=>mdout1_1_31, DOB5=>mdout1_1_32,
+ DOB6=>mdout1_1_33, DOB7=>mdout1_1_34, DOB8=>mdout1_1_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_2_0_7: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_2_0, DOB1=>mdout1_2_1,
+ DOB2=>mdout1_2_2, DOB3=>mdout1_2_3, DOB4=>mdout1_2_4,
+ DOB5=>mdout1_2_5, DOB6=>mdout1_2_6, DOB7=>mdout1_2_7,
+ DOB8=>mdout1_2_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ pdp_ram_2_1_6: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_9, DOB1=>mdout1_2_10, DOB2=>mdout1_2_11,
+ DOB3=>mdout1_2_12, DOB4=>mdout1_2_13, DOB5=>mdout1_2_14,
+ DOB6=>mdout1_2_15, DOB7=>mdout1_2_16, DOB8=>mdout1_2_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_2_2_5: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_18, DOB1=>mdout1_2_19, DOB2=>mdout1_2_20,
+ DOB3=>mdout1_2_21, DOB4=>mdout1_2_22, DOB5=>mdout1_2_23,
+ DOB6=>mdout1_2_24, DOB7=>mdout1_2_25, DOB8=>mdout1_2_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_2_3_4: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "010", CSDECODE_A=> "010", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_2_27, DOB1=>mdout1_2_28, DOB2=>mdout1_2_29,
+ DOB3=>mdout1_2_30, DOB4=>mdout1_2_31, DOB5=>mdout1_2_32,
+ DOB6=>mdout1_2_33, DOB7=>mdout1_2_34, DOB8=>mdout1_2_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_3_0_3: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi,
+ CSA0=>wptr_11, CSA1=>wptr_12, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3,
+ ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7,
+ ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i,
+ CLKB=>Clock, WEB=>scuba_vlo, CSB0=>rptr_11, CSB1=>rptr_12,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>mdout1_3_0, DOB1=>mdout1_3_1,
+ DOB2=>mdout1_3_2, DOB3=>mdout1_3_3, DOB4=>mdout1_3_4,
+ DOB5=>mdout1_3_5, DOB6=>mdout1_3_6, DOB7=>mdout1_3_7,
+ DOB8=>mdout1_3_8, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ pdp_ram_3_1_2: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11),
+ DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14),
+ DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_9, DOB1=>mdout1_3_10, DOB2=>mdout1_3_11,
+ DOB3=>mdout1_3_12, DOB4=>mdout1_3_13, DOB5=>mdout1_3_14,
+ DOB6=>mdout1_3_15, DOB7=>mdout1_3_16, DOB8=>mdout1_3_17,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_3_2_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20),
+ DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23),
+ DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_18, DOB1=>mdout1_3_19, DOB2=>mdout1_3_20,
+ DOB3=>mdout1_3_21, DOB4=>mdout1_3_22, DOB5=>mdout1_3_23,
+ DOB6=>mdout1_3_24, DOB7=>mdout1_3_25, DOB8=>mdout1_3_26,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ pdp_ram_3_3_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "011", CSDECODE_A=> "011", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29),
+ DIA3=>Data(30), DIA4=>Data(31), DIA5=>Data(32),
+ DIA6=>Data(33), DIA7=>Data(34), DIA8=>Data(35),
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
+ ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3,
+ ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7,
+ ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i,
+ CLKA=>Clock, WEA=>scuba_vhi, CSA0=>wptr_11, CSA1=>wptr_12,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1,
+ ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5,
+ ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9,
+ ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, WEB=>scuba_vlo,
+ CSB0=>rptr_11, CSB1=>rptr_12, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open,
+ DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open,
+ DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open,
+ DOA14=>open, DOA15=>open, DOA16=>open, DOA17=>open,
+ DOB0=>mdout1_3_27, DOB1=>mdout1_3_28, DOB2=>mdout1_3_29,
+ DOB3=>mdout1_3_30, DOB4=>mdout1_3_31, DOB5=>mdout1_3_32,
+ DOB6=>mdout1_3_33, DOB7=>mdout1_3_34, DOB8=>mdout1_3_35,
+ DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open,
+ DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open,
+ DOB17=>open);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_10);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_11);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_12);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_13);
+
+ FF_89: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_88: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_87: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_73: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset,
+ Q=>rcount_0);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_10);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_11);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_12);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_13);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_53: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_52: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_51: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_50: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_49: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_48: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_47: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_46: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_45: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_0);
+
+ FF_44: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_1);
+
+ FF_43: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_2);
+
+ FF_42: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_3);
+
+ FF_41: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_4);
+
+ FF_40: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_5);
+
+ FF_39: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_6);
+
+ FF_38: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_7);
+
+ FF_37: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_8);
+
+ FF_36: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_9);
+
+ FF_35: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_10);
+
+ FF_34: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_11);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_12);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rptr_13);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_11_ff);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo,
+ Q=>rptr_12_ff);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_9, CK=>Clock, CD=>Reset, Q=>rcnt_reg_9);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_10, CK=>Clock, CD=>Reset, Q=>rcnt_reg_10);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_11, CK=>Clock, CD=>Reset, Q=>rcnt_reg_11);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_12, CK=>Clock, CD=>Reset, Q=>rcnt_reg_12);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcnt_sub_13, CK=>Clock, CD=>Reset, Q=>rcnt_reg_13);
+
+ FF_15: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3);
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4);
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5);
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6);
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7);
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8);
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9);
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10);
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11);
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12);
+
+ FF_1: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ bdcnt_bctr_5: CB2
+ port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con,
+ CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11);
+
+ bdcnt_bctr_6: CB2
+ port map (CI=>co5, PC0=>fcount_12, PC1=>fcount_13, CON=>cnt_con,
+ CO=>co6, NC0=>ifcount_12, NC1=>ifcount_13);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>co4_1);
+
+ e_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_1, LE=>co5_1);
+
+ e_cmp_6: ALEB2
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co5_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i,
+ CI=>co3_2, GE=>co4_2);
+
+ g_cmp_5: AGEB2
+ port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, B1=>wren_i,
+ CI=>co4_2, GE=>co5_2);
+
+ g_cmp_6: AGEB2
+ port map (A0=>fcount_12, A1=>fcount_13, B0=>wren_i,
+ B1=>wren_i_inv, CI=>co5_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_ctr_5: CU2
+ port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_3,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_ctr_6: CU2
+ port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_1,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_ctr_5: CU2
+ port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_4,
+ NC0=>ircount_10, NC1=>ircount_11);
+
+ r_ctr_6: CU2
+ port map (CI=>co5_4, PC0=>rcount_12, PC1=>rcount_13, CO=>co6_2,
+ NC0=>ircount_12, NC1=>ircount_13);
+
+ mux_35: MUX41
+ port map (D0=>mdout1_0_0, D1=>mdout1_1_0, D2=>mdout1_2_0,
+ D3=>mdout1_3_0, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(0));
+
+ mux_34: MUX41
+ port map (D0=>mdout1_0_1, D1=>mdout1_1_1, D2=>mdout1_2_1,
+ D3=>mdout1_3_1, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(1));
+
+ mux_33: MUX41
+ port map (D0=>mdout1_0_2, D1=>mdout1_1_2, D2=>mdout1_2_2,
+ D3=>mdout1_3_2, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(2));
+
+ mux_32: MUX41
+ port map (D0=>mdout1_0_3, D1=>mdout1_1_3, D2=>mdout1_2_3,
+ D3=>mdout1_3_3, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(3));
+
+ mux_31: MUX41
+ port map (D0=>mdout1_0_4, D1=>mdout1_1_4, D2=>mdout1_2_4,
+ D3=>mdout1_3_4, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(4));
+
+ mux_30: MUX41
+ port map (D0=>mdout1_0_5, D1=>mdout1_1_5, D2=>mdout1_2_5,
+ D3=>mdout1_3_5, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(5));
+
+ mux_29: MUX41
+ port map (D0=>mdout1_0_6, D1=>mdout1_1_6, D2=>mdout1_2_6,
+ D3=>mdout1_3_6, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(6));
+
+ mux_28: MUX41
+ port map (D0=>mdout1_0_7, D1=>mdout1_1_7, D2=>mdout1_2_7,
+ D3=>mdout1_3_7, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(7));
+
+ mux_27: MUX41
+ port map (D0=>mdout1_0_8, D1=>mdout1_1_8, D2=>mdout1_2_8,
+ D3=>mdout1_3_8, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(8));
+
+ mux_26: MUX41
+ port map (D0=>mdout1_0_9, D1=>mdout1_1_9, D2=>mdout1_2_9,
+ D3=>mdout1_3_9, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(9));
+
+ mux_25: MUX41
+ port map (D0=>mdout1_0_10, D1=>mdout1_1_10, D2=>mdout1_2_10,
+ D3=>mdout1_3_10, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(10));
+
+ mux_24: MUX41
+ port map (D0=>mdout1_0_11, D1=>mdout1_1_11, D2=>mdout1_2_11,
+ D3=>mdout1_3_11, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(11));
+
+ mux_23: MUX41
+ port map (D0=>mdout1_0_12, D1=>mdout1_1_12, D2=>mdout1_2_12,
+ D3=>mdout1_3_12, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(12));
+
+ mux_22: MUX41
+ port map (D0=>mdout1_0_13, D1=>mdout1_1_13, D2=>mdout1_2_13,
+ D3=>mdout1_3_13, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(13));
+
+ mux_21: MUX41
+ port map (D0=>mdout1_0_14, D1=>mdout1_1_14, D2=>mdout1_2_14,
+ D3=>mdout1_3_14, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(14));
+
+ mux_20: MUX41
+ port map (D0=>mdout1_0_15, D1=>mdout1_1_15, D2=>mdout1_2_15,
+ D3=>mdout1_3_15, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(15));
+
+ mux_19: MUX41
+ port map (D0=>mdout1_0_16, D1=>mdout1_1_16, D2=>mdout1_2_16,
+ D3=>mdout1_3_16, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(16));
+
+ mux_18: MUX41
+ port map (D0=>mdout1_0_17, D1=>mdout1_1_17, D2=>mdout1_2_17,
+ D3=>mdout1_3_17, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(17));
+
+ mux_17: MUX41
+ port map (D0=>mdout1_0_18, D1=>mdout1_1_18, D2=>mdout1_2_18,
+ D3=>mdout1_3_18, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(18));
+
+ mux_16: MUX41
+ port map (D0=>mdout1_0_19, D1=>mdout1_1_19, D2=>mdout1_2_19,
+ D3=>mdout1_3_19, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(19));
+
+ mux_15: MUX41
+ port map (D0=>mdout1_0_20, D1=>mdout1_1_20, D2=>mdout1_2_20,
+ D3=>mdout1_3_20, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(20));
+
+ mux_14: MUX41
+ port map (D0=>mdout1_0_21, D1=>mdout1_1_21, D2=>mdout1_2_21,
+ D3=>mdout1_3_21, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(21));
+
+ mux_13: MUX41
+ port map (D0=>mdout1_0_22, D1=>mdout1_1_22, D2=>mdout1_2_22,
+ D3=>mdout1_3_22, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(22));
+
+ mux_12: MUX41
+ port map (D0=>mdout1_0_23, D1=>mdout1_1_23, D2=>mdout1_2_23,
+ D3=>mdout1_3_23, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(23));
+
+ mux_11: MUX41
+ port map (D0=>mdout1_0_24, D1=>mdout1_1_24, D2=>mdout1_2_24,
+ D3=>mdout1_3_24, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(24));
+
+ mux_10: MUX41
+ port map (D0=>mdout1_0_25, D1=>mdout1_1_25, D2=>mdout1_2_25,
+ D3=>mdout1_3_25, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(25));
+
+ mux_9: MUX41
+ port map (D0=>mdout1_0_26, D1=>mdout1_1_26, D2=>mdout1_2_26,
+ D3=>mdout1_3_26, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(26));
+
+ mux_8: MUX41
+ port map (D0=>mdout1_0_27, D1=>mdout1_1_27, D2=>mdout1_2_27,
+ D3=>mdout1_3_27, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(27));
+
+ mux_7: MUX41
+ port map (D0=>mdout1_0_28, D1=>mdout1_1_28, D2=>mdout1_2_28,
+ D3=>mdout1_3_28, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(28));
+
+ mux_6: MUX41
+ port map (D0=>mdout1_0_29, D1=>mdout1_1_29, D2=>mdout1_2_29,
+ D3=>mdout1_3_29, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(29));
+
+ mux_5: MUX41
+ port map (D0=>mdout1_0_30, D1=>mdout1_1_30, D2=>mdout1_2_30,
+ D3=>mdout1_3_30, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(30));
+
+ mux_4: MUX41
+ port map (D0=>mdout1_0_31, D1=>mdout1_1_31, D2=>mdout1_2_31,
+ D3=>mdout1_3_31, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(31));
+
+ mux_3: MUX41
+ port map (D0=>mdout1_0_32, D1=>mdout1_1_32, D2=>mdout1_2_32,
+ D3=>mdout1_3_32, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(32));
+
+ mux_2: MUX41
+ port map (D0=>mdout1_0_33, D1=>mdout1_1_33, D2=>mdout1_2_33,
+ D3=>mdout1_3_33, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(33));
+
+ mux_1: MUX41
+ port map (D0=>mdout1_0_34, D1=>mdout1_1_34, D2=>mdout1_2_34,
+ D3=>mdout1_3_34, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(34));
+
+ mux_0: MUX41
+ port map (D0=>mdout1_0_35, D1=>mdout1_1_35, D2=>mdout1_2_35,
+ D3=>mdout1_3_35, SD1=>rptr_11_ff, SD2=>rptr_12_ff, Z=>Q(35));
+
+ rcnt_0: FSUB2B
+ port map (A0=>r_nw_inv, A1=>wcount_0, B0=>r_nw_inv_inv,
+ B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_5, S0=>open,
+ S1=>rcnt_sub_0);
+
+ rcnt_1: FSUB2B
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rcount_1, B1=>rcount_2,
+ BI=>co0_5, BOUT=>co1_5, S0=>rcnt_sub_1, S1=>rcnt_sub_2);
+
+ rcnt_2: FSUB2B
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rcount_3, B1=>rcount_4,
+ BI=>co1_5, BOUT=>co2_5, S0=>rcnt_sub_3, S1=>rcnt_sub_4);
+
+ rcnt_3: FSUB2B
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rcount_5, B1=>rcount_6,
+ BI=>co2_5, BOUT=>co3_5, S0=>rcnt_sub_5, S1=>rcnt_sub_6);
+
+ rcnt_4: FSUB2B
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rcount_7, B1=>rcount_8,
+ BI=>co3_5, BOUT=>co4_5, S0=>rcnt_sub_7, S1=>rcnt_sub_8);
+
+ rcnt_5: FSUB2B
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rcount_9,
+ B1=>rcount_10, BI=>co4_5, BOUT=>co5_5, S0=>rcnt_sub_9,
+ S1=>rcnt_sub_10);
+
+ rcnt_6: FSUB2B
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rcount_11,
+ B1=>rcount_12, BI=>co5_5, BOUT=>co6_3, S0=>rcnt_sub_11,
+ S1=>rcnt_sub_12);
+
+ rcnt_7: FSUB2B
+ port map (A0=>rcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co6_3, BOUT=>open, S0=>rcnt_sub_13,
+ S1=>open);
+
+ ae_set_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open);
+
+ ae_set_cmp_0: AGEB2
+ port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1),
+ B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6);
+
+ ae_set_cmp_1: AGEB2
+ port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3),
+ B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6);
+
+ ae_set_cmp_2: AGEB2
+ port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5),
+ B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6);
+
+ ae_set_cmp_3: AGEB2
+ port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7),
+ B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6);
+
+ ae_set_cmp_4: AGEB2
+ port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9),
+ B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_6, GE=>co4_6);
+
+ ae_set_cmp_5: AGEB2
+ port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11),
+ B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_6, GE=>co5_6);
+
+ ae_set_cmp_6: AGEB2
+ port map (A0=>AmEmptyThresh(12), A1=>ae_set_setsig,
+ B0=>rcnt_reg_12, B1=>ae_set_clrsig, CI=>co5_6,
+ GE=>ae_set_d_c);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d,
+ S1=>open);
+
+ wcnt_0: FSUB2B
+ port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0,
+ BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0);
+
+ wcnt_1: FSUB2B
+ port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2);
+
+ wcnt_2: FSUB2B
+ port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_7, BOUT=>co2_7, S0=>wcnt_sub_3, S1=>wcnt_sub_4);
+
+ wcnt_3: FSUB2B
+ port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6,
+ BI=>co2_7, BOUT=>co3_7, S0=>wcnt_sub_5, S1=>wcnt_sub_6);
+
+ wcnt_4: FSUB2B
+ port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_7, BOUT=>co4_7, S0=>wcnt_sub_7, S1=>wcnt_sub_8);
+
+ wcnt_5: FSUB2B
+ port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10,
+ BI=>co4_7, BOUT=>co5_7, S0=>wcnt_sub_9, S1=>wcnt_sub_10);
+
+ wcnt_6: FSUB2B
+ port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12,
+ BI=>co5_7, BOUT=>co6_4, S0=>wcnt_sub_11, S1=>wcnt_sub_12);
+
+ wcnt_7: FSUB2B
+ port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co6_4, BOUT=>open, S0=>wcnt_sub_13,
+ S1=>open);
+
+ af_set_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open);
+
+ af_set_cmp_0: AGEB2
+ port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0),
+ B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8);
+
+ af_set_cmp_1: AGEB2
+ port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2),
+ B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8);
+
+ af_set_cmp_2: AGEB2
+ port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4),
+ B1=>AmFullThresh(5), CI=>co1_8, GE=>co2_8);
+
+ af_set_cmp_3: AGEB2
+ port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6),
+ B1=>AmFullThresh(7), CI=>co2_8, GE=>co3_8);
+
+ af_set_cmp_4: AGEB2
+ port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8),
+ B1=>AmFullThresh(9), CI=>co3_8, GE=>co4_8);
+
+ af_set_cmp_5: AGEB2
+ port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10),
+ B1=>AmFullThresh(11), CI=>co4_8, GE=>co5_8);
+
+ af_set_cmp_6: AGEB2
+ port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12),
+ B1=>scuba_vlo, CI=>co5_8, GE=>af_set_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a3: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set,
+ S1=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
+ WCNT(11) <= fcount_11;
+ WCNT(12) <= fcount_12;
+ WCNT(13) <= fcount_13;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_8192depth_36width_dual_thresh is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:MUX41 use entity ecp2m.MUX41(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_PROD_Build (44)
+-- Module Version: 4.5
+--/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 52 -depth 512 -no_enable -pe 10 -pf 508 -fill -e
+
+-- Mon May 11 12:43:57 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_fall_through_512depth_52width is
+ port (
+ Data: in std_logic_vector(51 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(51 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo_fall_through_512depth_52width;
+
+architecture Structure of fifo_fall_through_512depth_52width is
+
+ -- internal signal declarations
+ signal invout_2: std_logic;
+ signal invout_1: std_logic;
+ signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal r_nw_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcnt_en_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal co0_2: std_logic;
+ signal co1_2: std_logic;
+ signal co2_2: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal co0_5: std_logic;
+ signal co1_5: std_logic;
+ signal co2_5: std_logic;
+ signal co3_5: std_logic;
+ signal ae_d: std_logic;
+ signal ae_d_c: std_logic;
+ signal cmp_ci_3: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
+ signal cnt_con: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_6: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_6: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_6: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_6: std_logic;
+ signal scuba_vhi: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal af_d: std_logic;
+ signal af_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_fall_through_512depth_52width.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_1 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_1 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_1 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_1 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_1 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_1 : label is "36";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_fall_through_512depth_52width.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_1_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_1_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_1_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_1_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_1_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_1_0 : label is "36";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
+
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
+
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
+
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t1: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_6: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_5: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
+ pdp_ram_0_0_1: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ pdp_ram_0_1_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38),
+ DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42),
+ DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46),
+ DI11=>Data(47), DI12=>Data(48), DI13=>Data(49),
+ DI14=>Data(50), DI15=>Data(51), DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, ADW0=>wcount_0, ADW1=>wcount_1,
+ ADW2=>wcount_2, ADW3=>wcount_3, ADW4=>wcount_4,
+ ADW5=>wcount_5, ADW6=>wcount_6, ADW7=>wcount_7,
+ ADW8=>wcount_8, BE0=>scuba_vhi, BE1=>scuba_vhi,
+ BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock,
+ CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo,
+ ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo,
+ ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rcount_0,
+ ADR6=>rcount_1, ADR7=>rcount_2, ADR8=>rcount_3,
+ ADR9=>rcount_4, ADR10=>rcount_5, ADR11=>rcount_6,
+ ADR12=>rcount_7, ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock,
+ CSR0=>scuba_vlo, CSR1=>scuba_vlo, CSR2=>scuba_vlo,
+ RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36),
+ DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), DO22=>Q(40),
+ DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), DO26=>Q(44),
+ DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), DO30=>Q(48),
+ DO31=>Q(49), DO32=>Q(50), DO33=>Q(51), DO34=>open,
+ DO35=>open);
+
+ FF_33: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_32: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_23: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co3_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ ae_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ ae_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con_inv, CI=>cmp_ci_2, LE=>co0_5);
+
+ ae_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>co0_5, LE=>co1_5);
+
+ ae_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_5, LE=>co2_5);
+
+ ae_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_5, LE=>co3_5);
+
+ ae_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_5, LE=>ae_d_c);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
+ af_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open,
+ S1=>open);
+
+ af_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv,
+ B1=>cnt_con, CI=>cmp_ci_3, GE=>co0_6);
+
+ af_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv,
+ B1=>scuba_vhi, CI=>co0_6, GE=>co1_6);
+
+ af_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co1_6, GE=>co2_6);
+
+ af_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>co2_6, GE=>co3_6);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ af_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi,
+ B1=>scuba_vlo, CI=>co3_6, GE=>af_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a3: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_fall_through_512depth_52width is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
+-- Module Version: 4.1
+--/storage120/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 16 -rdata_width 16 -num_rows 512 -outdataA REGISTERED -outdataB REGISTERED -gsr ENABLED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile ROC1_initialization.mem -memformat orca -e
+
+-- Mon Oct 27 14:40:36 2008
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity initialization_RAM is
+ port (
+ DataInA: in std_logic_vector(15 downto 0);
+ DataInB: in std_logic_vector(15 downto 0);
+ AddressA: in std_logic_vector(8 downto 0);
+ AddressB: in std_logic_vector(8 downto 0);
+ ClockA: in std_logic;
+ ClockB: in std_logic;
+ ClockEnA: in std_logic;
+ ClockEnB: in std_logic;
+ WrA: in std_logic;
+ WrB: in std_logic;
+ ResetA: in std_logic;
+ ResetB: in std_logic;
+ QA: out std_logic_vector(15 downto 0);
+ QB: out std_logic_vector(15 downto 0));
+end initialization_RAM;
+
+architecture Structure of initialization_RAM is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (INITVAL_3F : in String; INITVAL_3E : in String;
+ INITVAL_3D : in String; INITVAL_3C : in String;
+ INITVAL_3B : in String; INITVAL_3A : in String;
+ INITVAL_39 : in String; INITVAL_38 : in String;
+ INITVAL_37 : in String; INITVAL_36 : in String;
+ INITVAL_35 : in String; INITVAL_34 : in String;
+ INITVAL_33 : in String; INITVAL_32 : in String;
+ INITVAL_31 : in String; INITVAL_30 : in String;
+ INITVAL_2F : in String; INITVAL_2E : in String;
+ INITVAL_2D : in String; INITVAL_2C : in String;
+ INITVAL_2B : in String; INITVAL_2A : in String;
+ INITVAL_29 : in String; INITVAL_28 : in String;
+ INITVAL_27 : in String; INITVAL_26 : in String;
+ INITVAL_25 : in String; INITVAL_24 : in String;
+ INITVAL_23 : in String; INITVAL_22 : in String;
+ INITVAL_21 : in String; INITVAL_20 : in String;
+ INITVAL_1F : in String; INITVAL_1E : in String;
+ INITVAL_1D : in String; INITVAL_1C : in String;
+ INITVAL_1B : in String; INITVAL_1A : in String;
+ INITVAL_19 : in String; INITVAL_18 : in String;
+ INITVAL_17 : in String; INITVAL_16 : in String;
+ INITVAL_15 : in String; INITVAL_14 : in String;
+ INITVAL_13 : in String; INITVAL_12 : in String;
+ INITVAL_11 : in String; INITVAL_10 : in String;
+ INITVAL_0F : in String; INITVAL_0E : in String;
+ INITVAL_0D : in String; INITVAL_0C : in String;
+ INITVAL_0B : in String; INITVAL_0A : in String;
+ INITVAL_09 : in String; INITVAL_08 : in String;
+ INITVAL_07 : in String; INITVAL_06 : in String;
+ INITVAL_05 : in String; INITVAL_04 : in String;
+ INITVAL_03 : in String; INITVAL_02 : in String;
+ INITVAL_01 : in String; INITVAL_00 : in String;
+ GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute INITVAL_3F : string;
+ attribute INITVAL_3E : string;
+ attribute INITVAL_3D : string;
+ attribute INITVAL_3C : string;
+ attribute INITVAL_3B : string;
+ attribute INITVAL_3A : string;
+ attribute INITVAL_39 : string;
+ attribute INITVAL_38 : string;
+ attribute INITVAL_37 : string;
+ attribute INITVAL_36 : string;
+ attribute INITVAL_35 : string;
+ attribute INITVAL_34 : string;
+ attribute INITVAL_33 : string;
+ attribute INITVAL_32 : string;
+ attribute INITVAL_31 : string;
+ attribute INITVAL_30 : string;
+ attribute INITVAL_2F : string;
+ attribute INITVAL_2E : string;
+ attribute INITVAL_2D : string;
+ attribute INITVAL_2C : string;
+ attribute INITVAL_2B : string;
+ attribute INITVAL_2A : string;
+ attribute INITVAL_29 : string;
+ attribute INITVAL_28 : string;
+ attribute INITVAL_27 : string;
+ attribute INITVAL_26 : string;
+ attribute INITVAL_25 : string;
+ attribute INITVAL_24 : string;
+ attribute INITVAL_23 : string;
+ attribute INITVAL_22 : string;
+ attribute INITVAL_21 : string;
+ attribute INITVAL_20 : string;
+ attribute INITVAL_1F : string;
+ attribute INITVAL_1E : string;
+ attribute INITVAL_1D : string;
+ attribute INITVAL_1C : string;
+ attribute INITVAL_1B : string;
+ attribute INITVAL_1A : string;
+ attribute INITVAL_19 : string;
+ attribute INITVAL_18 : string;
+ attribute INITVAL_17 : string;
+ attribute INITVAL_16 : string;
+ attribute INITVAL_15 : string;
+ attribute INITVAL_14 : string;
+ attribute INITVAL_13 : string;
+ attribute INITVAL_12 : string;
+ attribute INITVAL_11 : string;
+ attribute INITVAL_10 : string;
+ attribute INITVAL_0F : string;
+ attribute INITVAL_0E : string;
+ attribute INITVAL_0D : string;
+ attribute INITVAL_0C : string;
+ attribute INITVAL_0B : string;
+ attribute INITVAL_0A : string;
+ attribute INITVAL_09 : string;
+ attribute INITVAL_08 : string;
+ attribute INITVAL_07 : string;
+ attribute INITVAL_06 : string;
+ attribute INITVAL_05 : string;
+ attribute INITVAL_04 : string;
+ attribute INITVAL_03 : string;
+ attribute INITVAL_02 : string;
+ attribute INITVAL_01 : string;
+ attribute INITVAL_00 : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of initialization_RAM_0_0_0 : label is "initialization_RAM.lpc";
+ attribute MEM_INIT_FILE of initialization_RAM_0_0_0 : label is "ROC1_initialization.mem";
+ attribute INITVAL_3F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_39 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_38 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_37 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_36 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_35 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_34 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_33 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_32 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_31 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_30 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_29 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_28 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_27 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_26 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_25 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_24 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_23 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_22 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_21 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_20 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_19 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_18 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_17 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_16 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_15 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_14 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_13 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_12 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_11 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_10 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_0A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_09 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+-- attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018";
+ attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11
+
+ -- attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400000000340000000030000000001C0000000018";
+ -- attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00000000140000000010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11
+
+ attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC";--REGISTER_3
+ --<REGISTER_3
+ attribute INITVAL_0A of initialization_RAM_0_0_0 : label is "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128";
+ attribute INITVAL_09 of initialization_RAM_0_0_0 : label is "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028";--REGISTER_2
+ attribute INITVAL_08 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4";--REGISTER_1
+ --<REGISTER_1
+ attribute INITVAL_07 of initialization_RAM_0_0_0 : label is "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120";
+ attribute INITVAL_06 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0 --
+ attribute INITVAL_05 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
+ attribute INITVAL_04 of initialization_RAM_0_0_0 : label is "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 1D 19 15 11
+
+ --attribute INITVAL_05 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114";
+ --attribute INITVAL_04 of initialization_RAM_0_0_0 : label is "0x000610001C000610001800061000140006100010000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 1D 19 15 11
+ attribute INITVAL_03 of initialization_RAM_0_0_0 : label is "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C";--REGISTER_3
+ attribute INITVAL_02 of initialization_RAM_0_0_0 : label is "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028";--REGISTER_2
+ attribute INITVAL_01 of initialization_RAM_0_0_0 : label is "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024";--REGISTER_1
+ attribute INITVAL_00 of initialization_RAM_0_0_0 : label is "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020";--REGISTER_0(101_lastTDC_shortMb)
+ attribute CSDECODE_B of initialization_RAM_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of initialization_RAM_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of initialization_RAM_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of initialization_RAM_0_0_0 : label is "NORMAL";
+ attribute GSR of initialization_RAM_0_0_0 : label is "ENABLED";
+ attribute RESETMODE of initialization_RAM_0_0_0 : label is "SYNC";
+ attribute REGMODE_B of initialization_RAM_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of initialization_RAM_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of initialization_RAM_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of initialization_RAM_0_0_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ initialization_RAM_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+-------------------------------------------------------------------------------
+-- 1 LONG MB
+-------------------------------------------------------------------------------
+ INITVAL_0D=> "0x000000000000000000000000000000000100011400061000340006100030000610001C0006100018",
+ INITVAL_0C=> "0x00061000140006100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11
+ -- INITVAL_0D=> "0x000000000000000000000000000000000100011400000000340000000030000000001C0000000018",
+ -- INITVAL_0C=> "0x00000000140000000010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11
+
+ INITVAL_0B=> "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC",--REGISTER_3
+ --<REGISTER_3
+ INITVAL_0A=> "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128",
+ INITVAL_09=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
+ INITVAL_08=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4",--REGISTER_1
+ --<REGISTER_1
+ INITVAL_07=> "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120",
+ INITVAL_06=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0
+------------------------------------------------------------------------------
+-- 1 SHORT MB
+-------------------------------------------------------------------------------
+ INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
+ INITVAL_04=> "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010",
+-- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114",
+-- INITVAL_04=> "0x000610001C000610001800061000140006100010000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 1D 19 15 11
+ INITVAL_03=> "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C",--REGISTER_3
+ INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2
+ INITVAL_01=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1
+ INITVAL_00=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0(101_lastTDC_shortMb)
+
+ CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2),
+ DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5),
+ DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8),
+ DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11),
+ DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14),
+ DIA15=>DataInA(15), DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo,
+ ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1),
+ ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4),
+ ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7),
+ ADA12=>AddressA(8), ADA13=>scuba_vlo, CEA=>ClockEnA,
+ CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0),
+ DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3),
+ DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6),
+ DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9),
+ DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12),
+ DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15),
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vhi,
+ ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2),
+ ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5),
+ ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>AddressB(8),
+ ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2),
+ DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6),
+ DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10),
+ DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14),
+ DOA15=>QA(15), DOA16=>open, DOA17=>open, DOB0=>QB(0),
+ DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4),
+ DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8),
+ DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12),
+ DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>open,
+ DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of initialization_RAM is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 29/01/2007
+-- Description: it loads the configuration data into tdc (REG 0, REG 1, REG 2,
+-- REG 3, DAQ REG, GDE REG).
+-- This code has not optimized yet.
+--
+-- 20/11/2007 I added the configuration for chains (2 long MB, 2 short MB)
+--
+--test 10/12
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+use ieee.Numeric_STD.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+
+entity load_ROC1_tdc_setup is
+ generic (
+ width : integer := 6); -- number of bit of the counter if 4 and clk 100MHz
+ -- the state remain active 320 ns
+ -- width nr 3 => dst width 160 ns
+ -- width nr 4 => dst width 317 ns
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ A_ADD : out std_logic_vector(8 downto 0);
+ TRIGGER_IN : in std_logic;
+ CALIBRATION_TRIGGER_TDC_SETUP : in std_logic;
+ CALIBRATION_STEP_TDC_SETUP : in std_logic_vector(3 downto 0);
+ A_DST : out std_logic;
+ A_AOD : out std_logic;
+
+ TDC_SETTING_LOADED_OUT : out std_logic;
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ DEBUG_REGISTER : out std_logic_vector(7 downto 0)
+ );
+end load_ROC1_tdc_setup;
+
+architecture behaviour of load_ROC1_tdc_setup is
+
+--constant declaration
+ constant time_limit : std_logic_vector(width - 1 downto 0) := (others => '1');
+
+--ok 25MHz
+--constant time_limit : std_logic_vector(width - 1 downto 0) := "010000";
+
+ type state_type is (idle_state,
+ set_address_state, write_address_state, write_address_strobe,
+ write_address_strobe_next, write_address_no_strobe,
+
+ set_data_state, write_data_state, write_data_strobe,
+ write_data_strobe_next, write_data_no_strobe,
+ write_data_no_strobe_next, stop_state,
+ dummy_wait, maximum_counter_value,
+-------------------------------------------------------------------------------
+-- calibration states
+-------------------------------------------------------------------------------
+ calibration_state_0, calibration_state_1,
+ calibration_state_2, calibration_state_3,
+ calibration_state_4, calibration_state_5,
+ calibration_state_6, dummy_calibration_state, dummy_calibration_state_2,
+ calibration_address_no_strobe_0, calibration_address_with_strobe_0,
+ calibration_address_no_strobe_1, calibration_dummy_wait,
+ calibration_data_no_strobe_0, calibration_data_with_strobe_0,
+ calibration_data_no_strobe_1, calibration_data_no_strobe_2,
+ calibration_maximum_counter_value, wait_mode_load,
+ calibration_finished, wait_calibration_state_6,
+ dummy_calibration_state_3, test_wait,
+ test_wait_1);
+
+ signal current_state, next_state : state_type;
+
+-- type trigger_state_type is (trigger_idle_state,
+-- trigger_calibration_state,
+-- trigger_begrun_state);
+
+-- signal trigger_current_state, trigger_next_state : trigger_state_type;
+ signal send_data : std_logic_vector(15 downto 0);
+ signal up_counter_i, up_counter_register_2 : std_logic;
+ signal time_counter : std_logic_vector(width - 1 downto 0);
+ signal calibration_counter_0 : std_logic_vector (width - 1 downto 0);
+ signal calibration_counter_1 : std_logic_vector (width - 1 downto 0);
+ signal clear_calibration_counter_0, clear_calibration_counter_1 : std_logic;
+
+ signal reg_A_DST, next_A_DST : std_logic;
+ signal reg_A_AOD, next_A_AOD : std_logic;
+ signal reg_TDC_SETTING_LOADED_OUT, next_TDC_SETTING_LOADED_OUT : std_logic;
+ -- signal offset_address : std_logic;
+ signal bus_chain : std_logic_vector(3 downto 0);
+ signal stop_counter_ram, counter_ram, offset_ram, temp_counter_ram : std_logic_vector(9 downto 0);
+ signal calibration_stop_counter_ram_0, calibration_offset_ram : std_logic_vector(9 downto 0);
+ signal calibration_stop_counter_ram_1, calibration_stop_counter_ram: std_logic_vector(9 downto 0);
+ signal next_debug_register, reg_debug_register : std_logic_vector(7 downto 0);
+ signal process_trigger_type : std_logic_vector(3 downto 0);
+ signal counter_register_1, counter_register_1_temp : std_logic_vector(3 downto 0);
+ signal counter_register_2, counter_register_2_temp : std_logic_vector(3 downto 0);
+ signal counter_delay : std_logic_vector(7 downto 0);
+ signal control_register_0, control_register_0_temp, up_control_register_0 : std_logic;
+ signal cpld_register_data : std_logic_vector(8 downto 0);
+ signal external_ram_address : std_logic_vector(9 downto 0);
+ signal external_ram_data : std_logic_vector(15 downto 0);
+ signal external_read_enable, external_write_enable, write_or_read_enable : std_logic;
+ signal clear_time_counter : std_logic;
+
+ component initialization_RAM
+ port (
+ DataInA : in std_logic_vector(15 downto 0);
+ DataInB : in std_logic_vector(15 downto 0);
+ AddressA : in std_logic_vector(8 downto 0);
+ AddressB : in std_logic_vector(8 downto 0);
+ ClockA : in std_logic;
+ ClockB : in std_logic;
+ ClockEnA : in std_logic;
+ ClockEnB : in std_logic;
+ WrA : in std_logic;
+ WrB : in std_logic;
+ ResetA : in std_logic;
+ ResetB : in std_logic;
+ QA : out std_logic_vector(15 downto 0);
+ QB : out std_logic_vector(15 downto 0));
+ end component;
+
+
+begin
+
+
+-- RAMB16_S18_CONFIGURATION_TDC_DATA : RAMB16_S18_S18
+-- generic map (
+-- -- The following generics are only necessary if you wish to
+-- -- change the default behavior.
+-- INIT_A => X"00000", -- Value of output RAM registers at startup
+-- INIT_B => X"00000",
+-- SRVAL_A => X"00000", -- Ouput value upon SSR assertion
+-- SRVAL_B => X"00000",
+-- WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+-- WRITE_MODE_B => "WRITE_FIRST",
+-- -- The following generic INIT_xx declarations are only necessary
+-- -- if you wish to change the initial
+-- -- contents of the RAM to anything other than all zero's.
+
+-- -------------------------------------------------------------------------
+-- -- 2 SHORT MOTHERBOARDs in chain
+-- -------------------------------------------------------------------------
+-- ----A and B
+-- --first MB: START REGISTER 0
+-- INIT_00 => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"0")
+-- --first MB: END REGISTER 0
+
+-- --second MB: START REGISTER 0
+-- INIT_01 => X"00170102001700E2001700C2001700A200170082001700620017004200170022",
+-- --second MB: END REGISTER 0
+
+-- --first MB: START REGISTER 1
+-- INIT_02 => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --first MB: END REGISTER 1
+
+-- --second MB: START REGISTER 1
+-- INIT_03 => X"00990106009900E6009900C6009900A600990086009900660099004600990026",
+-- --second MB: END REGISTER 1
+
+-- --first MB: START REGISTER 2
+-- INIT_04 => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
+-- -- INIT_04 => X"00010109000100E9000100C9000100A900010089000100690001004900010029",
+-- --first MB: END REGISTER 2
+
+-- --second MB: START REGISTER 2
+-- -- INIT_05 => X"00FF010A00FF00EA00FF00CA00FF00AA00FF008A00FF006A00FF004A00FF002A",
+-- INIT_05 => X"0002010A000200EA000200CA000200AA0002008A0002006A0002004A0004002A",
+-- --second MB: END REGISTER 2
+
+-- --first MB: START REGISTER 3 (all channels enable)
+-- INIT_06 => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D",
+-- --first MB: END REGISTER 3
+
+-- --second MB: START REGISTER 3 (I enable only tdc 1)
+-- --INIT_07 => X"0000010E000000EE000000CE000000AE0000008E0000006E0000004E00FF002E",
+
+-- --all channel enable
+-- INIT_07 => X"00FF010E00FF00EE00FF00CE00FF00AE00FF008E00FF006E00FF004E00FF002E",
+-- --second MB: END REGISTER 3
+
+-- --first board: START DAQ REGISTER -- 1D 19 15 11
+-- -- INIT_08 => X"0060001D00600019006000150060001100FF001D00FF001900FF001500FF0011",
+-- INIT_08 => X"0010001D00100019001000150010001100FF001D00FF001900FF001500FF0011",
+-- --first board: END DAQ REGISTER
+
+-- --second board: START DAQ REGISTER -- 1E 1A 16 12
+-- --INIT_09 => X"0060001E0060001A006000160060001200FF001E00FF001A00FF001600FF0012",
+-- INIT_09 => X"0010001E0010001A001000160010001200FF001E00FF001A00FF001600FF0012",
+-- --second board: END DAQ REGISTER
+
+-- --SET RESET REGISTER FOR GLOBAL DISABLE in CPLD
+-- INIT_0A => X"0000000000000000000000000000000000000000000000000010011600100115", --pointer(X"A4")
+-- --END RESET REGISTER
+-- -------------------------------------------------------------------------
+-- -- end ROC file.
+-- -------------------------------------------------------------------------
+
+-- -------------------------------------------------------------------------
+-- -- 1 SHORT MOTHERBOARD
+-- -------------------------------------------------------------------------
+-- --first MB: START REGISTER 0
+-- INIT_0B => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"B1")
+-- --first MB: END REGISTER 0
+
+-- --first MB: START REGISTER 1
+-- INIT_0C => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --first MB: END REGISTER 1
+
+-- --first MB: START REGISTER 2
+-- -- INIT_0D => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
+-- --cal TDC1 INIT_0D => X"00000109000000E9000000C9000000A900000089000000690000004900FF0029",
+-- --cal TDC1 INIT_0D=> X"00050109000400E9000200C9000100A90004008900FF00690000004900000029",
+-- INIT_0D => X"00010109002400E9004200C9008100A900100089000200690004004900800029",
+-- --first MB: END REGISTER 2
+
+-- --first MB: START REGISTER 3
+-- --all channel enable
+-- INIT_0E => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D",
+-- --first MB: END REGISTER 3
+
+-- --first board: START DAQ REGISTER 1D 19 15 11
+-- --INIT_0F => X"0060001D00600019006000150060001100FF001D00FF001900FF001500FF0011",
+-- INIT_0F => X"0010001D0010001900100015001000110010001D001000190010001500100011",
+-- -- INIT_0F => X"0045001D00450019004500150045001100FF001D00FF001900FF001500FF0011",
+-- --first board: END DAQ REGISTER
+
+-- --SET RESET REGISTER FOR GLOBAL DISABLE in CPLD
+-- INIT_10 => X"0000000000000000000000000000000000000000000000000000000000100115", --pointer(X"101")
+-- --END RESET REGISTER
+-- -------------------------------------------------------------------------
+-- -- end ROC file.
+-- -------------------------------------------------------------------------
+
+-- -------------------------------------------------------------------------
+-- -- 1 LONG MOTHERBOARD
+-- -------------------------------------------------------------------------
+-- --START REGISTER 0 AND REGISTER 1
+-- INIT_11 => X"00170101001700E1001700C1001700A100170081001700610017004100170021", --pointer(X"110")
+-- --<
+-- INIT_12 => X"0099008500990065009900450099002500170181001701610017014100170121",
+-- --<
+-- INIT_13 => X"0099018500990165009901450099012500990105009900E5009900C5009900A5",
+
+-- --START REGISTER 2 AND REGISTER 3
+-- INIT_14 => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
+-- --<
+-- INIT_15 => X"00FF008D00FF006D00FF004D00FF002D00FF018900FF016900FF014900FF0129",
+-- --<
+-- INIT_16 => X"00FF018D00FF016D00FF014D00FF012D00FF010D00FF00ED00FF00CD00FF00AD",
+
+-- --DAQ REGISTER: 35 31 1D 19 15 11
+-- --INIT_17 => X"006000150060001100FF003500FF003100FF001D00FF001900FF001500FF0011",
+-- INIT_17 => X"001000150010001100FF003500FF003100FF001D00FF001900FF001500FF0011",
+
+-- INIT_18 => X"0000000000000000000000000010011500600035006000310060001D00600019", --pointer(X"19E")
+-- ------------------------------------------------------------------------
+-- -- end ROC file.
+-- -------------------------------------------------------------------------
+-- -------------------------------------------------------------------------
+
+-- -------------------------------------------------------------------------
+-- -- 2 long MOTHERBOARDs in chain
+-- -------------------------------------------------------------------------
+-- --first AND second MB: START REGISTER 0
+-- INIT_19 => X"00170101001700E1001700C1001700A100170081001700610017004100170021",
+-- --<
+-- INIT_1A => X"0017008200170062001700420017002200170181001701610017014100170121",
+-- --<
+-- INIT_1B => X"0017018200170162001701420017012200170102001700E2001700C2001700A2",
+-- --first AND second MB: END REGISTER 0
+
+-- --first AND second MB: START REGISTER 1
+-- INIT_1C => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --<
+-- INIT_1D => X"0099008600990066009900460099002600990185009901650099014500990125",
+
+-- INIT_1E => X"0099018600990166009901460099012600990106009900E6009900C6009900A6",
+-- --first AND second MB: END REGISTER 1
+
+-- --first AND second MB: START REGISTER 2
+-- INIT_1F => X"00FF010900FF00E900FF00C900FF00A900FF008900FF006900FF004900FF0029",
+-- -- INIT_1F => X"00100109001000E9001000C9001000A900100089001000690010004900100029",
+-- --<
+-- INIT_20 => X"00FF008A00FF006A00FF004A00FF002A00FF018900FF016900FF014900FF0129",
+-- -- INIT_20 => X"0004008A0004006A0004004A0004002A00040189000401690004014900040129",
+
+-- -- INIT_21 => X"00FF018A00FF016A00FF014A00FF012A00FF010A00FF00EA00FF00CA00FF00AA",
+-- --ok INIT_21 => X"000F018A000F016A000F014A000F012A000F010A000F00EA000F00CA000F00AA",
+-- --no ok INIT_21 => X"000F018A000F016A000F014A000F012A00FF010A00FF00EA00FF00CA00FF00AA",
+-- --ok INIT_21 => X"00FF018A00FF016A00FF014A000F012A000F010A000F00EA000F00CA000F00AA",
+-- INIT_21 => X"00FF018A00FF016A00FF014A00FF012A000F010A000F00EA000F00CA000F00AA",
+-- --no ok INIT_21 => X"00FF018A00FF016A00FF014A00FF012A00FF010A000F00EA000F00CA000F00AA",
+-- --no ok INIT_21 => X"00FF018A00FF016A00FF014A00FF012A000F010A00FF00EA000F00CA000F00AA",
+
+-- --first AND second MB: END REGISTER 2
+
+-- --first AND second MB: START REGISTER 3
+-- INIT_22 => X"00FF010D00FF00ED00FF00CD00FF00AD00FF008D00FF006D00FF004D00FF002D",
+-- --<
+-- INIT_23 => X"00FF008E00FF006E00FF004E00FF002E00FF018D00FF016D00FF014D00FF012D",
+
+-- INIT_24 => X"00FF018E00FF016E00FF014E00FF012E00FF010E00FF00EE00FF00CE00FF00AE",
+-- --first AND second MB: END REGISTER 3
+
+-- --first AND second MB: DAQ REGISTER: --36 32 1E 1A 16 12(second) 35 31 1D 19 15 11 (first board)
+-- INIT_25 => X"001000150010001100FF003500FF003100FF001D00FF001900FF001500FF0011",
+-- --<
+-- INIT_26 => X"00FF001E00FF001A00FF001600FF001200100035001000310010001D00100019",
+-- --<
+-- INIT_27 => X"00100036001000320010001E0010001A001000160010001200FF003600FF0032",
+
+-- INIT_28 => X"0000000000000000000000000000000000000000000000000010011600100115",
+-- -------------------------------------------------------------------------
+-- -- end ROC file.
+-- -------------------------------------------------------------------------
+
+
+-- -------------------------------------------------------------------------------
+-- --CALIBRATION PARAMETERS CAL FILE
+-- --!!!REMEMBER TO FIX THE GED BEFORE AND AFTER YOU LOAD THE CAL PARAMETERS!!!!!!
+-- -- i CAN DO IT IN THE CODE!!!
+-- -------------------------------------------------------------------------------
+
+-- -------------------------------------------------------------------------------
+-- -- GDE registers for CAL file
+-- -------------------------------------------------------------------------------
+-- --I do this in the state machine!! this will never change
+-- -------------------------------------------------------------------------
+-- -- 1 SHORT MOTHERBOARD
+-- -------------------------------------------------------------------------
+-- --first MB: START REGISTER 1
+-- INIT_29 => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025",
+-- -- INIT_29 => X"00BA010500BB00E5002200C5000000A5000000850055006500AA004500BD0025",
+-- --first MB: END REGISTER 1
+
+-- --first MB: START REGISTER 1 AFTER CHANGED THE MODE
+-- INIT_2A => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --first MB: END REGISTER 1
+-- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000100115",
+-- -------------------------------------------------------------------------
+-- -- 2 SHORT MOTHERBOARDs in chain
+-- -------------------------------------------------------------------------
+-- --first MB: START REGISTER 1
+-- INIT_2C => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025",
+-- --first MB: END REGISTER 1
+
+-- --second MB: START REGISTER 1
+-- INIT_2D => X"00BD010600BD00E600BD00C600BD00A600BD008600BD006600BD004600BD0026",
+-- --second MB: END REGISTER 1
+
+-- --first MB: START REGISTER 1 AFTER CHANGED THE MODE
+-- INIT_2E => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --first MB: END REGISTER 1
+
+-- --second MB: START REGISTER 1
+-- INIT_2F => X"00990106009900E6009900C6009900A600990086009900660099004600990026",
+-- --second MB: END REGISTER 1
+-- INIT_30 => X"0000000000000000000000000000000000000000000000000010011600100115",
+-- -------------------------------------------------------------------------
+-- -- 1 LONG MOTHERBOARD
+-- -------------------------------------------------------------------------
+-- INIT_31 => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025",
+
+-- INIT_32 => X"0099008500990065009900450099002500BD018500BD016500BD014500BD0125",
+-- -- AFTER CHANGED THE MODE
+-- INIT_33 => X"0099018500990165009901450099012500990105009900E5009900C5009900A5",
+
+-- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000100115",
+-- -------------------------------------------------------------------------
+-- -- 2 LONG MOTHERBOARDS
+-- -------------------------------------------------------------------------
+-- --first AND second MB: START REGISTER 1
+-- INIT_35 => X"00BD010500BD00E500BD00C500BD00A500BD008500BD006500BD004500BD0025",
+-- --<
+-- INIT_36 => X"00BD008600BD006600BD004600BD002600BD018500BD016500BD014500BD0125",
+
+-- INIT_37 => X"00BD018600BD016600BD014600BD012600BD010600BD00E600BD00C600BD00A6",
+-- --first AND second MB: END REGISTER 1
+-- -- AFTER CHANGED THE MODE
+-- --first AND second MB: START REGISTER 1
+-- INIT_38 => X"00990105009900E5009900C5009900A500990085009900650099004500990025",
+-- --<
+-- INIT_39 => X"0099008600990066009900460099002600990185009901650099014500990125",
+
+-- INIT_3A => X"0099018600990166009901460099012600990106009900E6009900C6009900A6",
+-- --first AND second MB: END REGISTER 1
+-- INIT_3B => X"0000000000000000000000000000000000000000000000000010011600100115",
+
+-- -- INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- -- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+
+-- -- The next set of INITP_xx are for the parity bits
+-- -- Address 0 to 255
+-- INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+-- INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+
+-- port map (
+-- DOA => send_data, -- Port A 16-bit Data Output
+-- DOB => RAM_DATA_OUT, --open, -- Port B 16-bit Data Output
+-- DOPA => open, -- Port A 2-bit Parity Output
+-- DOPB => open, -- Port B 2-bit Parity Output
+-- ADDRA => counter_ram, -- counter_out, -- Port A 10-bit Address Input
+-- ADDRB => external_ram_address,--"0000000000", -- Port B 10-bit Address Input
+-- CLKA => CLK, -- Port A Clock
+-- CLKB => CLK, -- Port B Clock
+-- DIA => (others => '0'), -- Port A 16-bit Data Input
+-- DIB => external_ram_data, -- Port B 16-bit Data Input
+-- DIPA => (others => '0'), -- Port A 2-bit parity Input
+-- DIPB => (others => '0'), -- Port-B 2-bit parity Input
+-- ENA => '1', -- Port A RAM Enable Input
+-- ENB => write_or_read_enable, --'0', -- PortB RAM Enable Input
+-- SSRA => RESET, -- Port A Synchronous Set/Reset Input
+-- SSRB => RESET, -- Port B Synchronous Set/Reset Input
+-- WEA => '0', -- Port A Write Enable Input
+-- WEB => external_write_enable --'0' -- Port B Write Enable Input
+-- );
+-- -- End of RAMB16_S9_S9 instantiation
+
+-- external_ram_address <= RAM_ADDRESS_IN;
+-- external_ram_data <= RAM_DATA_IN;
+-- external_read_enable <= RAM_READ_ENABLE_IN;
+-- external_write_enable <= RAM_WRITE_ENABLE_IN;
+-- write_or_read_enable <= external_read_enable or external_write_enable;
+
+ RAM_configuration: initialization_RAM
+ port map (
+ DataInA => (others => '0'),--DataInA_i,
+ DataInB => (others => '0'),--DataInB_i,
+ AddressA => counter_ram(8 downto 0), --AddressA_i, --9 bits
+ AddressB => (others => '0'),--AddressB_i,
+ ClockA => CLK,--ClockA_i,
+ ClockB => '0',--CLK,--ClockB_i,
+ ClockEnA => '1',--ClockEnA_i,
+ ClockEnB => '0',--ClockEnB_i,
+ WrA => '0',--WrA_i,
+ WrB => '0',--WrB_i,
+ ResetA => '0',--ResetA_i,
+ ResetB => '0',--ResetB_i,
+ QA => send_data, -- RAM_DATA_OUT, -- Port A 16-bit Data Output
+ QB => open-- Port B 16-bit Data Output
+ );
+-------------------------------------------------------------------------------
+--purpose: state machine synchronization
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_A_DST <= '0';
+ reg_A_AOD <= '0';
+ reg_TDC_SETTING_LOADED_OUT <= '0';
+ reg_debug_register <= (others => '0');
+ else
+ reg_A_DST <= next_A_DST;
+ reg_A_AOD <= next_A_AOD;
+ reg_TDC_SETTING_LOADED_OUT <= next_TDC_SETTING_LOADED_OUT;
+ current_state <= next_state;
+ reg_debug_register <= next_debug_register;
+ end if;
+ end if;
+ end process;
+
+A_DST <= reg_A_DST;
+A_AOD <= reg_A_AOD;
+TDC_SETTING_LOADED_OUT <= reg_TDC_SETTING_LOADED_OUT;
+--bus_chain <= BUS_CHAIN_IN;
+bus_chain <= x"1";
+
+ DEBUG_REGISTER <= reg_debug_register;
+-------------------------------------------------------------------------------
+--here the state machine starts it extract data and address
+--from ram and put them in the bus
+-------------------------------------------------------------------------------
+ process (current_state, counter_ram,TRIGGER_IN, stop_counter_ram,
+ calibration_stop_counter_ram,
+ time_counter, CALIBRATION_STEP_TDC_SETUP,
+ CALIBRATION_TRIGGER_TDC_SETUP, calibration_counter_0,
+ calibration_counter_1, counter_register_1, counter_delay,
+ bus_chain, control_register_0,
+ cpld_register_data)
+ begin
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_debug_register <= (others => '0');
+ up_counter_i <= '0';
+ up_counter_register_2 <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ A_ADD(8 downto 0) <= (others => '0');
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ up_control_register_0 <= '0';
+ clear_time_counter <= '0';
+
+ case current_state is
+
+ when idle_state =>
+ next_debug_register <= x"01";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ clear_time_counter <= '1';
+ if TRIGGER_IN = '1' then
+ next_state <= set_address_state;
+ else
+ next_state <= idle_state;
+ end if;
+-------------------------------------------------------------------------------
+-- ROC DATA: WRITE ADDRESS PART only for first trigger
+-------------------------------------------------------------------------------
+--here I put data on the bus and NO strobe
+ when set_address_state =>
+ next_debug_register <= x"02";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= write_address_strobe;
+ else
+ next_state <= set_address_state;
+ end if;
+
+ when write_address_strobe =>
+ next_debug_register <= x"03";
+ next_A_DST <= '1';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= write_address_no_strobe;
+ else
+ next_state <= write_address_strobe;
+ end if;
+
+ when write_address_no_strobe =>
+ next_debug_register <= x"04";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= dummy_wait;
+ else
+ next_state <= write_address_no_strobe;
+ end if;
+
+--here I increment the counter to extract data
+ when dummy_wait =>
+ next_debug_register <= x"05";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '1';
+ clear_time_counter <= '1';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ next_state <= set_data_state;
+---------------------------------------------------------------------------
+--WRITE DATA PART
+---------------------------------------------------------------------------
+--I put data on the bus and no strobe
+ when set_data_state =>
+ next_debug_register <= x"06";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';--x"17"; --send_data;. .
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= write_data_strobe;
+ else
+ next_state <= set_data_state;
+ end if;
+
+ when write_data_strobe =>
+ next_debug_register <= x"07";
+ next_A_DST <= '1';--'1';
+ next_A_AOD <= '1';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= write_data_no_strobe;
+ else
+ next_state <= write_data_strobe;
+ end if;
+
+ when write_data_no_strobe =>
+ next_debug_register <= x"08";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';--here I increment to extract address
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= write_data_no_strobe_next;
+ else
+ next_state <= write_data_no_strobe;
+ end if;
+
+ when write_data_no_strobe_next =>
+ next_debug_register <= x"09";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '1';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_time_counter <= '1';
+ next_state <= maximum_counter_value;
+
+ when maximum_counter_value =>
+ next_debug_register <= x"0A";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ if counter_ram >= stop_counter_ram then
+-- if counter_ram >= x"51" then
+ next_TDC_SETTING_LOADED_OUT <= '1';
+ next_state <= stop_state;
+ else
+ next_state <= set_address_state; --goes again to load next address
+ end if;
+
+-- Stay here after ROC1 has been loaded
+ when stop_state =>
+ next_debug_register <= x"0B";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ next_TDC_SETTING_LOADED_OUT <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_time_counter <= '1';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+-- if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
+-- next_state <= calibration_state_0;--bus_chain <= x"1" 1 short MB in the bus
+-- else
+-- next_state <= stop_state;
+-- end if;
+ next_state <= stop_state;
+-------------------------------------------------------------------------------
+-- STOP ROC DATA
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- CALIBRATION PROCESS, Here I use different states, I could use the same I
+-- previously used but It easier in case the timing signal is different for
+-- calibration and for ROC DATA.
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- CPLD register GDE at the beginning and at the end of CAL file.
+-------------------------------------------------------------------------------
+ when calibration_state_0 => --write CPLD REGISTER: address, NO strobe
+ next_debug_register <= x"0C";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15"; --here always the same I do not use
+ --the ram
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_state_1;
+ else
+ next_state <= calibration_state_0;
+ end if;
+
+ when calibration_state_1 => --write CPLD REGISTER: address, with strobe
+ next_debug_register <= x"0D";
+ next_A_DST <= '1';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15";
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_1 >= time_limit then
+ next_state <= calibration_state_2;
+ else
+ next_state <= calibration_state_1;
+ end if;
+
+ when calibration_state_2 => --write CPLD REGISTER : address, NO strobe
+ next_debug_register <= x"0E";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= cpld_register_data;--'1' & x"15";
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_state_3;
+ else
+ next_state <= calibration_state_2;
+ end if;
+
+ when calibration_state_3 => --write CPLD REGISTER : data, NO strobe
+ next_debug_register <= x"0F";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= x"00" & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_1 >= time_limit then
+ next_state <= calibration_state_4;
+ else
+ next_state <= calibration_state_3;
+ end if;
+
+ when calibration_state_4 => --write CPLD REGISTER : data, strobe
+ next_debug_register <= x"10";
+ next_A_DST <= '1';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= x"00" & '0';
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_state_5;
+ else
+ next_state <= calibration_state_4;
+ end if;
+
+ when calibration_state_5 => --write CPLD REGISTER : data, NO strobe
+ next_debug_register <= x"11";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= x"00" & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_1 >= time_limit then
+ -- next_state <= wait_calibration_state_6;
+ next_state <= test_wait;
+ else
+ next_state <= calibration_state_5;
+ end if;
+
+ when test_wait =>
+ next_debug_register <= x"21";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= x"00" & '0';
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+-- if counter_delay >= "01111111" then
+-- next_state <= wait_calibration_state_6;
+-- else
+-- next_state <= test_wait;
+-- end if;
+ if control_register_0 = '0' then
+ next_state <= test_wait_1;
+ elsif control_register_0 = '1' then
+ if counter_delay >= "01111111" then
+ next_state <= wait_calibration_state_6;
+ else
+ next_state <= test_wait;
+ end if;
+ end if;
+
+ when test_wait_1 =>
+ next_debug_register <= x"20";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= x"00" & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ up_control_register_0 <= '1';
+ if (bus_chain = x"2" or bus_chain = x"4") then --2 short or 2 long in chain
+ next_state <= calibration_state_0; --repeat and write again
+ else
+ next_state <= wait_calibration_state_6;
+ end if;
+ ------------------------------------------------------------------------------
+ --
+ ------------------------------------------------------------------------------
+ when wait_calibration_state_6 => --wait till TSTW+GDE (1a01 08) mode line are fixed
+ next_debug_register <= x"12";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if CALIBRATION_STEP_TDC_SETUP = x"1" then
+ next_state <= dummy_calibration_state;
+ else
+ next_state <= wait_calibration_state_6;
+ end if;
+
+ when dummy_calibration_state => --start loading data
+ next_debug_register <= x"13";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '1';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ next_state <= dummy_calibration_state_2;
+
+ when dummy_calibration_state_2 => --start loading data
+ next_debug_register <= x"13";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '1';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ next_state <= calibration_address_no_strobe_0;
+
+-------------------------------------------------------------------------------
+-- CALIBRATION LOAD REGISTER 1
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- WRITE ADDRESS PART
+-------------------------------------------------------------------------------
+--here I put data on the bus and NO strobe
+ when calibration_address_no_strobe_0 =>
+ next_debug_register <= x"14";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_address_with_strobe_0;
+ else
+ next_state <= calibration_address_no_strobe_0;
+ end if;
+
+ when calibration_address_with_strobe_0 =>
+ next_debug_register <= x"15";
+ next_A_DST <= '1';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_1 >= time_limit then
+ next_state <= calibration_address_no_strobe_1;
+ else
+ next_state <= calibration_address_with_strobe_0;
+ end if;
+
+ when calibration_address_no_strobe_1 =>
+ next_debug_register <= x"16";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_dummy_wait;
+ else
+ next_state <= calibration_address_no_strobe_1;
+ end if;
+
+--here I increment the counter to extract data
+ when calibration_dummy_wait =>
+ next_debug_register <= x"17";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '1';
+ A_ADD(8 downto 0) <= send_data(8 downto 0);
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ next_state <= calibration_data_no_strobe_0;
+---------------------------------------------------------------------------
+--CALIBRATION: WRITE DATA PART
+---------------------------------------------------------------------------
+--I put data on the bus and no strobe
+ when calibration_data_no_strobe_0 =>
+ next_debug_register <= x"18";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';--x"17"; --send_data;. .
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_data_with_strobe_0;
+ else
+ next_state <= calibration_data_no_strobe_0;
+ end if;
+
+ when calibration_data_with_strobe_0 =>
+ next_debug_register <= x"19";
+ next_A_DST <= '1';--'1';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '0';
+ if calibration_counter_1 >= time_limit then
+ next_state <= calibration_data_no_strobe_1;
+ else
+ next_state <= calibration_data_with_strobe_0;
+ end if;
+
+ when calibration_data_no_strobe_1 =>
+ next_debug_register <= x"1A";
+ next_A_DST <= '0';
+ next_A_AOD <= '1';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '1';
+ if calibration_counter_0 >= time_limit then
+ next_state <= calibration_data_no_strobe_2;
+ else
+ next_state <= calibration_data_no_strobe_1;
+ end if;
+
+ when calibration_data_no_strobe_2 =>
+ next_debug_register <= x"1B";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '1';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ next_state <= calibration_maximum_counter_value;
+
+ when calibration_maximum_counter_value =>
+ next_debug_register <= x"1C";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '0';
+ clear_calibration_counter_1 <= '0';
+ if counter_ram >= calibration_stop_counter_ram then
+ next_state <= wait_mode_load;
+ else
+ next_state <= calibration_address_no_strobe_0; --goes again to load next address
+ end if;
+
+--counter_register_1 = x"0" means REGISTER 1 has been loaded the first time
+--counter_register_1 = x"1" means REGISTER 1 has been loaded the twice and I
+--finished the calibration process.
+ when wait_mode_load => --08 08 48
+ next_debug_register <= x"1D";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ if (CALIBRATION_STEP_TDC_SETUP = x"3" and counter_register_1 = x"0") then
+ next_state <= dummy_calibration_state_3;
+ elsif CALIBRATION_STEP_TDC_SETUP = x"3" and counter_register_1 = x"1" then
+ next_state <= calibration_finished;
+ else
+ next_state <= wait_mode_load;
+ end if;
+
+ when dummy_calibration_state_3 =>
+ next_debug_register <= x"1F";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ up_counter_register_2 <= '1'; --use second part of CAL1
+ next_state <= calibration_address_no_strobe_0;
+ -- next_state <= dummy_calibration_state_3;
+ -- next_debug_register <= x"1E";
+
+ when calibration_finished => --go to stop state and wait the next
+ --calibration trigger
+ next_debug_register <= x"1E";
+ next_A_DST <= '0';
+ next_A_AOD <= '0';
+ up_counter_i <= '0';
+ A_ADD(8 downto 0) <= send_data(7 downto 0) & '0';
+ clear_calibration_counter_0 <= '1';
+ clear_calibration_counter_1 <= '1';
+ if CALIBRATION_TRIGGER_TDC_SETUP = '1' then
+ next_state <= calibration_state_0;
+ else
+ next_state <= calibration_finished;
+ end if;
+
+ when others =>
+ next_state <= idle_state;
+
+ end case;
+ end process;
+
+-------------------------------------------------------------------------------
+--this counter mantain the tdc setup data lines fixed at a certain value
+--(see debouncer in CPLD on motherboard)
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or clear_time_counter = '1') then
+ time_counter <= (others => '0');
+ elsif (current_state = write_address_strobe or
+ current_state = set_address_state or
+ current_state = write_address_strobe_next or
+ current_state = write_data_strobe or
+ current_state = write_address_no_strobe or
+ current_state = write_data_strobe_next or
+ current_state = dummy_wait or
+ -- current_state = stop_state or
+ current_state = set_data_state or
+ current_state = write_data_no_strobe)
+ then
+ time_counter <= time_counter + 1;
+ else
+ time_counter <= time_counter;
+ end if;
+ end if;
+end process;
+-------------------------------------------------------------------------------
+--Here I decide where I have to stop to take data from RAM, depending which
+--kind of chain is connected to the bus
+--
+--bus_chain <= x"1" 1 short MB in the bus
+--bus_chain <= x"2" 2 short MBs in the same bus
+--bus_chain <= x"3" 1 long MB in the bus
+--bus_chain <= x"4" 2 long MBs in the same bus
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ process_trigger_type <= (others => '0');
+ elsif(current_state = dummy_calibration_state or
+ current_state = dummy_calibration_state_2 or
+ current_state = dummy_calibration_state_3 or
+ current_state = calibration_address_no_strobe_0 or
+ current_state = calibration_address_with_strobe_0 or
+ current_state = calibration_address_no_strobe_1 or
+ current_state = calibration_dummy_wait or
+ current_state = calibration_data_no_strobe_0 or
+ current_state = calibration_data_with_strobe_0 or
+ current_state = calibration_data_no_strobe_1 or
+ current_state = calibration_data_no_strobe_2 or
+ current_state = calibration_maximum_counter_value or
+ current_state = wait_mode_load or
+ current_state = calibration_finished or
+ current_state = calibration_state_0 or
+ current_state = calibration_state_1 or
+ current_state = calibration_state_2 or
+ current_state = calibration_state_3 or
+ current_state = calibration_state_4 or
+ current_state = calibration_state_5 or
+ current_state = test_wait or
+ current_state = test_wait_1 or
+ current_state = wait_calibration_state_6) then
+
+ process_trigger_type <= x"C";
+ else
+ process_trigger_type <= x"B";
+ end if;
+ end if;
+end process;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ calibration_stop_counter_ram_0 <= (others => '0');
+ calibration_stop_counter_ram_1 <= (others => '0');
+ calibration_offset_ram <= (others => '0');
+ stop_counter_ram <= (others => '0');
+ offset_ram <= (others => '0');
+-------------------------------------------------------------------------------
+--CALIBRATION
+-------------------------------------------------------------------------------
+-- elsif process_trigger_type = x"C" then
+-- if bus_chain = x"1" then --1 short MB is configured
+-- calibration_stop_counter_ram_0 <= "1010011111";-- "1010110001";
+-- calibration_offset_ram <= "1010001110";
+-- calibration_stop_counter_ram_1 <= "1010110001";--"1011100000";
+-- elsif bus_chain = x"2" then --2 short MBs are configured in the same bus
+-- calibration_stop_counter_ram_0 <= "1011011111";--0x2DF
+-- calibration_offset_ram <= "1010111110";--0x2BE
+-- calibration_stop_counter_ram_1 <= "1100000011";--0x303
+-- -------------------------------------------------------------------------------
+-- --
+-- -------------------------------------------------------------------------------
+-- elsif bus_chain = x"3" then --1 long MB is configured
+-- calibration_stop_counter_ram_0 <= "1100100111";--0x327
+-- calibration_offset_ram <= "1100001110";--0x30E
+-- calibration_stop_counter_ram_1 <= "1101000001"; --0x341
+
+-- elsif bus_chain = x"4" then --2 long MBs are configured in the same bus
+-- calibration_stop_counter_ram_0 <= "1101111111"; --x37F
+-- calibration_offset_ram <= "1101001110"; --0x34E
+-- calibration_stop_counter_ram_1 <= "1110110011"; --0x3B3
+-- end if;
+-------------------------------------------------------------------------------
+--BEGRUN TRIGGER
+-------------------------------------------------------------------------------
+ elsif process_trigger_type = x"B" then
+ if bus_chain = x"1" then --1 short MB is configured
+ stop_counter_ram <= "00" & x"51"; --"0100000001"; --x"101"
+ offset_ram <= "00" & x"00";
+
+ elsif bus_chain = x"2" then --1 long MB is configured
+ stop_counter_ram <= "00" & x"DA";--"0110001001"; --x"189"
+ offset_ram <= "00" & x"60";--"0100010000"; --x"110"
+ end if;
+ end if;
+ end if;
+--end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- the counter extracts data from the ram.
+-- the data is sended as follows:
+-- address_1 => data_1, address_2 => data_2, . .
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or
+ current_state = stop_state or
+ current_state = calibration_finished)
+ then
+ temp_counter_ram <= (others => '0');
+ elsif up_counter_i = '1' then
+ temp_counter_ram <= temp_counter_ram + 1;
+ else
+ temp_counter_ram <= temp_counter_ram;
+ end if;
+ end if;
+end process;
+--counter_ram <= temp_counter_ram;
+counter_ram <= temp_counter_ram + offset_ram;
+
+
+--counter_ram <= (temp_counter_ram + offset_ram) when process_trigger_type <= x"B"
+-- else (temp_counter_ram + calibration_offset_ram);
+-------------------------------------------------------------------------------
+-- OFFSET COUNTER RAM
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- counter_ram <= (others => '0');
+-- elsif (process_trigger_type = x"B") then
+-- counter_ram <= temp_counter_ram + offset_ram; --!ok per calibration (temp_counter_ram + "0010110000");
+-- else
+-- counter_ram <= temp_counter_ram + offset_ram; --!ok epr cal(temp_counter_ram + "1010001110");
+-- end if;
+-- end if;
+-- end process;
+-------------------------------------------------------------------------------
+--counter to check when I reach half CAL file.
+--counter_register_2 = "0" I'm writing the FIRST part
+--counter_register_2 not "0" I'm writing the SECOND part
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or current_state = calibration_finished) then --reset after CAL is loaded
+ counter_register_2_temp <= (others => '0');
+ elsif (up_counter_register_2 = '1') then
+ counter_register_2_temp <= counter_register_2_temp + 1;
+ else
+ counter_register_2_temp <= counter_register_2_temp;
+ end if;
+ end if;
+end process;
+counter_register_2 <= counter_register_2_temp;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+calibration_stop_counter_ram <= (calibration_stop_counter_ram_0) when counter_register_2 = x"0"
+ else (calibration_stop_counter_ram_1);
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1' or current_state = calibration_finished) then
+-- calibration_stop_counter_ram <= (others => '0');
+-- elsif counter_register_2 = x"0" then
+-- calibration_stop_counter_ram <= "1010011111"; --"1010100000";
+-- else
+-- calibration_stop_counter_ram <= "1010110001";
+-- end if;
+-- end if;
+-- end process;
+-------------------------------------------------------------------------------
+-- CALIBRATION COUNTERs. I use these to keep the state on for a certain time
+-------------------------------------------------------------------------------
+process (CLK)
+begin -- process
+ if rising_edge(CLK) then
+ if RESET = '1' or clear_calibration_counter_0 = '1' then
+ calibration_counter_0 <= (others => '0');
+ elsif (current_state = calibration_state_0 or
+ current_state = calibration_state_2 or
+ current_state = calibration_state_4 or
+ current_state = calibration_address_no_strobe_0 or
+ current_state = calibration_address_no_strobe_1 or
+ current_state = calibration_data_no_strobe_0 or
+ current_state = calibration_data_no_strobe_1 or
+ current_state = wait_calibration_state_6)
+ then
+ calibration_counter_0 <= calibration_counter_0 + 1;
+ end if;
+ end if;
+end process;
+
+process (CLK)
+begin -- process
+ if rising_edge(CLK) then
+ if RESET = '1' or clear_calibration_counter_1 = '1' then
+ calibration_counter_1 <= (others => '0');
+ elsif (current_state = calibration_state_1 or
+ current_state = calibration_state_3 or
+ current_state = calibration_state_5 or
+ current_state = calibration_address_with_strobe_0 or
+ current_state = calibration_data_with_strobe_0)
+ then
+ calibration_counter_1 <= calibration_counter_1 + 1;
+ end if;
+ end if;
+end process;
+
+process (CLK)
+begin -- process
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_delay <= (others => '0');
+ elsif (current_state = test_wait) then
+ counter_delay <= counter_delay + 1;
+ end if;
+ end if;
+end process;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+process (CLK)
+begin -- process
+ if rising_edge(CLK) then
+ if (RESET = '1' or current_state = calibration_finished) then
+ counter_register_1_temp <= (others => '0');
+ elsif (current_state = dummy_calibration_state_3) then
+ counter_register_1_temp <= counter_register_1_temp + 1;
+ else
+ counter_register_1_temp <= counter_register_1_temp;
+ end if;
+ end if;
+end process;
+counter_register_1 <= counter_register_1_temp;
+-------------------------------------------------------------------------------
+-- CONTROL REGISTER
+-------------------------------------------------------------------------------
+process (CLK)
+begin -- process
+ if rising_edge(CLK) then
+ if (RESET = '1' or current_state = stop_state or
+ current_state = calibration_finished) then
+ control_register_0_temp <= '0';
+ elsif up_control_register_0 = '1' then
+ control_register_0_temp <= '1';
+ else
+ control_register_0_temp <= control_register_0_temp;
+ end if;
+ end if;
+end process;
+control_register_0 <= control_register_0_temp;
+
+cpld_register_data <= '1' & x"15" when control_register_0 = '0' else ('1' & x"16");
+
+end behaviour;
+
+
+
+
+
+
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Create Date: 17:39:30 12/18/2006
+-- Design Name:
+-- Module Name: load_ROC1_data_mode
+-- Description: see sheet in the same directory with state machine:it loads
+-- mode into CPLD
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+--Uncomment the following library declaration if instantiating
+--any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity load_mode_line is
+ generic (
+ width : integer := 13);
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ MODE_TRIGGER : in std_logic; --it starts the two sub entity
+ CALIBRATION_TRIGGER_MODE_LINE : in std_logic;
+ CALIBRATION_STEP_MODE_LINE : in std_logic_vector(3 downto 0);
+ RDO : in std_logic; --ready FROM first motherboard.is token back
+
+--mode lines
+ GDE : out std_logic; --add34042007
+ MODD : out std_logic; --TDC working mode
+ RES : out std_logic; --TDC working mode
+ TOK : out std_logic; --TDC working mode
+ WRM : out std_logic; --TDC working mode
+ RDM : out std_logic; --TDC working mode
+
+ MODE_READY_FOR_TDC_SETTING_OUT : out std_logic;
+ TDC_SETTING_LOADED_IN : in std_logic;
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(7 downto 0)
+ );
+
+end load_mode_line;
+
+architecture Behavioral of load_mode_line is
+
+-- subtype mode_definition is std_logic_vector(4 downto 0);
+
+-- constant reset_mode : mode_definition := "00000"; -- hex 00
+-- constant jtag : mode_definition := "11000"; -- hex 70
+-- constant init : mode_definition := "01000"; -- hex 50
+-- constant init_tok : mode_definition := "01001"; -- hex 51: init mode + send token
+-- constant unknown : mode_definition := "00100"; -- hex 48 not declared by Jan???!!!
+-- constant setr : mode_definition := "10110"; -- hex 6c
+-- constant setr_tok : mode_definition := "10111"; -- hex 6d
+-- constant all_null : mode_definition := "00000"; -- hex 00
+
+ type state_type is (idle_state, reset_mode_state,
+ jtag_state, init_state,
+ init_tok_state, wait_token_1_state,
+ wait_token_2_state,
+ unknown_state, setr_state,
+ setr_tok_state,wait_tdc_setting_loaded_in_state,
+ set_mode_after_loaded_ROC1,
+ dummy_state, dummy_state_next,
+ jtag_state_next, init_state_next,
+ init_tok_state_next,
+ wait_token_1_state_next,
+ unknown_state_next,
+ setr_state_next,
+ setr_tok_state_next,
+ jtag_2_state, unknown_2_state,
+ wait_state, test_readout_state,
+--CALIBRATION STATE
+ start_calibration_sequence, write_mb_control_register_1,
+ write_mb_control_register_3, write_mb_control_register_0,
+ write_mb_control_register_2, acquisition_mode_state,
+ wait_calibration_mode_0, wait_calibration_mode_1,
+ wait_calibration_mode_2, wait_calibration_mode_3,
+ stop_calibration_on_acquisition_mode,
+ prepare_readout_state,
+ set_mode_after_loaded_CAL1,
+ dummy_calibration_state);
+
+ signal current_state, next_state : state_type;
+
+ signal enable_i, trigger_i : std_logic;
+ signal output_enable_i : std_logic;
+ signal tdc_setting_done : std_logic :='0';
+ -- signal i : integer; --number of token back
+ signal time_counter : std_logic_vector(width - 1 downto 0); --it's used to mantain data
+ --mode on the bus
+ signal dummy_counter : std_logic_vector(width + 3 downto 0);
+ signal counter_1 : std_logic_vector(width - 1 downto 0);
+ signal counter_2 : std_logic_vector(width - 1 downto 0);
+ signal clear_time_counter : std_logic;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+ signal reg_MODD, next_MODD, reg_RES, next_RES : std_logic;
+ signal reg_TOK, next_TOK, reg_WRM, next_WRM : std_logic;
+ signal reg_RDM, next_RDM : std_logic;
+ signal reg_GDE, next_GDE : std_logic;
+
+ signal reg_mode_ready_for_tdc_setting_out : std_logic;
+ signal next_mode_ready_for_tdc_setting_out : std_logic;
+ signal reg_ROC1_WRITTEN, next_ROC1_WRITTEN : std_logic;
+ signal reg_cal1_written, next_cal1_written : std_logic;
+
+ signal reg_debug_register,next_debug_register : std_logic_vector(7 downto 0);
+ signal clear_counter_1,clear_counter_2 : std_logic;
+
+----------------------------------------------------------------------------
+--
+----------------------------------------------------------------------------
+
+ constant time_limit : std_logic_vector(width - 1 downto 0) := (others => '1');
+
+--ok for 25MHz
+--constant time_limit : std_logic_vector(width - 1 downto 0) := "0011111010000";
+
+begin
+
+-- purpose: sincronization
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_GDE <= '0';
+ reg_MODD <= '0';
+ reg_RES <= '0';
+ reg_TOK <= '0';
+ reg_WRM <= '0';
+ reg_RDM <= '0';
+ reg_mode_ready_for_tdc_setting_out <= '0';
+ reg_debug_register <= (others => '0');
+ reg_cal1_written <= '0';
+ else
+ current_state <= next_state;
+ reg_GDE <= next_GDE;
+ reg_MODD <= next_MODD;
+ reg_RES <= next_RES;
+ reg_TOK <= next_TOK;
+ reg_WRM <= next_WRM;
+ reg_RDM <= next_RDM;
+ reg_mode_ready_for_tdc_setting_out <= next_mode_ready_for_tdc_setting_out;
+ reg_ROC1_WRITTEN <= next_ROC1_WRITTEN;
+ reg_debug_register <= next_debug_register;
+ reg_cal1_written <= next_cal1_written;
+ end if;
+ end if;
+ end process;
+
+ GDE <= reg_GDE;
+ MODD <= reg_MODD;
+ RES <= reg_RES;
+ TOK <= reg_TOK;
+ WRM <= reg_WRM;
+ RDM <= reg_RDM;
+ MODE_READY_FOR_TDC_SETTING_OUT <= reg_mode_ready_for_tdc_setting_out;
+ ROC1_WRITTEN <= reg_ROC1_WRITTEN;
+ DEBUG_REGISTER <= reg_debug_register;
+ CAL1_WRITTEN <= reg_cal1_written;
+-------------------------------------------------------------------------------
+-- purpose: state machine. if I got a trigger I start to write mode
+-- signals into tdc
+-------------------------------------------------------------------------------
+ process (MODE_TRIGGER, RDO, current_state,
+ TDC_SETTING_LOADED_IN, time_counter, dummy_counter,
+ CALIBRATION_TRIGGER_MODE_LINE, counter_2, counter_1,
+ CALIBRATION_STEP_MODE_LINE)
+ begin
+
+ next_debug_register <= (others => '0');
+ next_ROC1_WRITTEN <= '0';
+ next_cal1_written <= '0';
+ next_GDE <= '0';
+ next_MODD <= '0';
+ next_RES <= '0';
+ next_TOK <= '0';
+ next_WRM <= '0';
+ next_RDM <= '0';
+ next_mode_ready_for_tdc_setting_out <= '0';
+ clear_time_counter <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '0';
+
+ case current_state is
+
+ when idle_state =>
+ next_debug_register <= x"00";
+-- hex 00
+ next_GDE <= '0';
+ next_MODD <= '0';
+ next_RES <= '0';
+ next_TOK <= '0';
+ next_WRM <= '0';
+ next_RDM <= '0';
+ clear_time_counter <= '1';
+ if MODE_TRIGGER = '1' then
+ next_state <= reset_mode_state;
+ elsif TDC_SETTING_LOADED_IN = '1' then
+ next_state <= set_mode_after_loaded_ROC1;
+ else
+ next_state <= idle_state;
+ end if;
+
+ when reset_mode_state =>
+ next_debug_register <= x"01";
+ -- hex 00
+ next_GDE <= '0';
+ next_MODD <= '0';
+ next_RES <= '0';
+ next_TOK <= '0';
+ next_WRM <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= jtag_state;
+ else
+ next_state <= reset_mode_state;
+ end if;
+
+ when jtag_state =>
+ next_debug_register <= x"02";
+ -- hex 70
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '1';
+ next_TOK <= '0';
+ next_RES <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ -- if i = 0 then
+ next_state <= init_state;
+ -- elsif i = 1 then
+ -- next_state <= unknown_state;
+-- if time_counter = time_limit then
+-- elsif time_counter = time_limit then
+-- next_state <= init_state;
+ else
+-- next_state <= jtag_state;
+-- end if;
+ next_state <= jtag_state;
+ end if;
+ -- end if;
+
+ when init_state =>
+ next_debug_register <= x"03";
+ -- hex 50
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '1';
+ next_TOK <= '0';
+ next_RES <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= init_tok_state;
+ else
+ next_state <= init_state;
+ end if;
+
+ when init_tok_state =>
+ next_debug_register <= x"04";
+ -- init mode + send token hex 51
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '1';
+ next_TOK <= '0';
+ next_RES <= '0';
+ next_RDM <= '1';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= wait_token_1_state;
+ else
+ next_state <= init_tok_state;
+ end if;
+
+ when wait_token_1_state =>
+ next_debug_register <= x"05";
+ -- init mode + send token hex 51
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '1';
+ next_TOK <= '0';
+ next_RES <= '0';
+ next_RDM <= '1';
+ -- clear_time_counter <= '1';
+ if RDO = '1' then --wait until token is back from motherboard if RDO = '1' --means token back
+ next_state <= unknown_state;
+ else
+ next_state <= wait_token_1_state;
+ end if;
+
+ when wait_token_2_state =>
+ next_debug_register <= x"06";
+ -- hex 6d
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '1';
+ next_RDM <= '1';
+ -- clear_time_counter <= '1';
+ if RDO = '1' then
+ next_state <= jtag_2_state;
+ else
+ next_state <= wait_token_2_state;
+ end if;
+
+ when jtag_2_state =>
+ next_debug_register <= x"07";
+ -- hex 70
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '1';
+ next_TOK <= '0';
+ next_RES <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= unknown_2_state;
+ else
+ next_state <= jtag_2_state;
+ end if;
+
+ when unknown_2_state =>
+ next_debug_register <= x"08";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_mode_ready_for_tdc_setting_out <= '1';
+ -- next_state <= wait_state;
+ next_state <= dummy_state;
+ else
+ next_state <= unknown_2_state;
+ end if;
+
+ when dummy_state =>
+ next_debug_register <= x"09";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_time_counter <= '1';
+ next_state <= wait_state;
+
+-------------------------------------------------------------------------------
+--Here I stop waiting that data is loaded into TDCs
+-------------------------------------------------------------------------------
+ when wait_state =>
+ next_debug_register <= x"0A";
+ next_mode_ready_for_tdc_setting_out <= '0'; --'1';
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ -- clear_time_counter <= '1';
+ if TDC_SETTING_LOADED_IN = '1' then
+ next_state <= set_mode_after_loaded_ROC1;
+ else
+ next_state <= wait_state;
+ end if;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+ when unknown_state =>
+ next_debug_register <= x"0B";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ -- if i = 0 then
+ next_state <= setr_state;
+ -- elsif i = 1 then
+ -- MODE_READY_FOR_TDC_SETTING_OUT <= '1';
+ -- next_state <= unknown_state;
+--elsif i = 1 and time_counter = time_limit then
+-- MODE_READY_FOR_TDC_SETTING_OUT <= '1';
+-- next_state <= wait_tdc_setting_loaded_in_state;
+ else
+ next_state <= unknown_state;
+ end if;
+
+ when setr_state =>
+ next_debug_register <= x"0C";
+ -- hex 6c
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '1';
+ next_RDM <= '0';
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= setr_tok_state;
+-- next_state <= setr_tok_state;
+ else
+ next_state <= setr_state;
+ end if;
+
+ when setr_tok_state =>
+ next_debug_register <= x"0D";
+ -- hex 6d
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '1';
+ next_RDM <= '1';
+ -- i := 1;
+ if time_counter = time_limit then
+ clear_time_counter <= '1';
+ next_state <= wait_token_2_state;
+ else
+ next_state <= setr_tok_state;
+ end if;
+-------------------------------------------------------------------------------
+--this state should be executed only after the ROC1
+--file is loaded. this state loads the mode line: 1A01 64
+--If I get the CALIBRATION TRIGGER I start the procedure for PROCESS
+--the CALIBRATION.
+-------------------------------------------------------------------------------
+ when set_mode_after_loaded_ROC1 =>
+ next_debug_register <= x"0E";
+ next_ROC1_WRITTEN <= '1';
+ -- hex 64
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '0';
+ next_RES <= '1';
+ next_RDM <= '0';
+-- -- hex 6d
+-- next_GDE <= '1';
+-- next_WRM <= '1';
+-- next_MODD <= '0';
+-- next_TOK <= '1';
+-- next_RES <= '1';
+-- next_RDM <= '1';--'0';
+-- next_state <= test_readout_state;
+-- if CALIBRATION_TRIGGER_MODE_LINE = '1' then
+-- next_state <= start_calibration_sequence;
+-- else
+-- next_state <= set_mode_after_loaded_ROC1;
+-- end if;
+ next_state <= set_mode_after_loaded_ROC1;
+
+ when test_readout_state =>
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '1';
+ next_RDM <= '1';
+ next_state <= test_readout_state;
+-------------------------------------------------------------------------------
+-- CALIBRATION STATE MACHINE
+-------------------------------------------------------------------------------
+ when start_calibration_sequence =>
+ next_debug_register <= x"0F";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '0';
+ if counter_1 >= time_limit then
+ next_state <= wait_calibration_mode_0;
+ else
+ next_state <= start_calibration_sequence;
+ end if;
+
+ when wait_calibration_mode_0 => --it holds hex 48
+ next_debug_register <= x"10";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '0';
+ if CALIBRATION_STEP_MODE_LINE = x"1" then
+ next_state <= write_mb_control_register_0; --TSTW
+ else
+ next_state <= wait_calibration_mode_0;
+ end if;
+
+ when write_mb_control_register_0 => --it writes hex 08
+ next_debug_register <= x"11";
+ -- hex 8 = (48-GDE)
+ next_GDE <= '0';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '0';
+ if counter_2 >= time_limit then
+ next_state <= wait_calibration_mode_1;
+ else
+ next_state <= write_mb_control_register_0;
+ end if;
+
+ when wait_calibration_mode_1 => --it holds hex 08
+ next_debug_register <= x"12";
+ -- hex 8 = (48-GDE)
+ next_GDE <= '0';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '1';
+ if CALIBRATION_STEP_MODE_LINE = x"2" then
+ next_state <= write_mb_control_register_1; --TSTW
+ else
+ next_state <= wait_calibration_mode_1;
+ end if;
+
+ when write_mb_control_register_1 => --write hex 08
+ next_debug_register <= x"13";
+ -- hex 8 = (48-GDE)
+ next_GDE <= '0';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '0';
+ if counter_1 >= time_limit then
+ next_state <= write_mb_control_register_2;
+ else
+ next_state <= write_mb_control_register_1;
+ end if;
+
+ when write_mb_control_register_2 => --write hex 08
+ next_debug_register <= x"14";
+ -- hex 8 = (48-GDE)
+ next_GDE <= '0';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '0';
+ if counter_2 >= time_limit then
+ next_state <= write_mb_control_register_3;
+ else
+ next_state <= write_mb_control_register_2;
+ end if;
+
+ when write_mb_control_register_3 => --write hex 48
+ next_debug_register <= x"15";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '1';
+ if counter_1 >= time_limit then
+ next_state <= wait_calibration_mode_3;
+ else
+ next_state <= write_mb_control_register_3;
+ end if;
+
+ when wait_calibration_mode_3 => --it holds hex 48
+ next_debug_register <= x"16";
+ -- hex 48
+ next_GDE <= '1';
+ next_WRM <= '0';
+ next_MODD <= '0';
+ next_TOK <= '1';
+ next_RES <= '0';
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '0';
+ if CALIBRATION_STEP_MODE_LINE = x"3" then
+ next_state <= acquisition_mode_state;
+ else
+ next_state <= wait_calibration_mode_3;
+ end if;
+
+ when acquisition_mode_state =>
+ next_debug_register <= x"17";
+ -- hex 7C
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '1';
+ next_TOK <= '1';
+ next_RES <= '1';
+
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '0';
+ if counter_2 >= time_limit then
+ next_state <= prepare_readout_state;
+ else
+ next_state <= acquisition_mode_state;
+ end if;
+
+ when prepare_readout_state =>
+ next_debug_register <= x"19";
+ -- hex 64 + GDE
+ next_GDE <= '1'; --add for calibration
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '0';
+ next_RES <= '1';
+ next_RDM <= '0';
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '1';
+ if counter_1 >= time_limit then
+ --next_state <= stop_calibration_on_acquisition_mode;
+ next_state <= dummy_calibration_state;
+ else
+ next_state <= prepare_readout_state;
+ end if;
+
+ when dummy_calibration_state =>
+ next_debug_register <= x"21";
+ next_cal1_written <= '1'; --cal done
+-- hex 64 + GDE
+ next_GDE <= '1';
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '0';
+ next_RES <= '1';
+ next_RDM <= '0';
+
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '1';
+ next_state <= stop_calibration_on_acquisition_mode;
+
+ when stop_calibration_on_acquisition_mode =>
+ next_debug_register <= x"18";
+ -- next_cal1_written <= '1';
+ -- hex 64 + GDE
+ next_GDE <= '1'; --add for calibration
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '0';
+ next_RES <= '1';
+ next_RDM <= '0';
+ clear_counter_1 <= '1';
+ clear_counter_2 <= '1';
+ if RDO = '1' then
+ next_state <= set_mode_after_loaded_CAL1;
+ elsif CALIBRATION_TRIGGER_MODE_LINE = '1' then
+ next_state <= start_calibration_sequence;
+ else
+ next_state <= stop_calibration_on_acquisition_mode;
+ end if;
+
+ when set_mode_after_loaded_CAL1 =>
+ next_debug_register <= x"20";
+ -- next_ROC1_WRITTEN <= '1';
+ -- hex 64
+ next_GDE <= '0'; --add for calibration
+ next_WRM <= '1';
+ next_MODD <= '0';
+ next_TOK <= '0';
+ next_RES <= '1';
+ next_RDM <= '0';
+
+ clear_counter_1 <= '0';
+ clear_counter_2 <= '0';
+ if CALIBRATION_TRIGGER_MODE_LINE = '1' then
+ next_state <= start_calibration_sequence;
+ else
+ next_state <= set_mode_after_loaded_CAL1;
+ end if;
+
+
+ when others =>
+ next_state <= idle_state;
+
+ end case;
+ end process;
+-------------------------------------------------------------------------------
+--purpose : this counter mantain the mode line fixed at a certain value
+--(see debouncer in CPLD on motherboard)
+--I use this for mode line when I write the ROC1
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or clear_time_counter = '1') then
+ time_counter <= (others => '0');
+ elsif (current_state = reset_mode_state or
+ current_state = jtag_state or
+ current_state = init_state or
+ current_state = init_tok_state or
+ current_state = unknown_state or
+ current_state = setr_state or
+ current_state = setr_tok_state or
+ current_state = jtag_state_next or
+ current_state = init_state_next or
+ current_state = init_tok_state_next or
+ current_state = unknown_state_next or
+ current_state = setr_state_next or
+ current_state = setr_tok_state_next or
+ current_state = jtag_2_state or
+ current_state = unknown_2_state)
+ then
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+end process;
+-------------------------------------------------------------------------------
+--purpose: these counters mantain the mode line fixed at a certain value
+--(see debouncer in CPLD on motherboard)
+--I use this for mode line when I'm doing the calibration
+-------------------------------------------------------------------------------
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' or clear_counter_1 = '1' then
+ counter_1 <= (others => '0');
+ elsif (current_state = start_calibration_sequence or
+ current_state = write_mb_control_register_1 or
+ current_state = write_mb_control_register_3 or
+ current_state = prepare_readout_state)
+ then
+ counter_1 <= counter_1 + 1;
+ end if;
+ end if;
+end process;
+
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' or clear_counter_2 = '1' then
+ counter_2 <= (others => '0');
+ elsif (current_state = write_mb_control_register_0 or
+ current_state = write_mb_control_register_2 or
+ current_state = acquisition_mode_state)
+ then
+ counter_2 <= counter_2 + 1;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
+
+
+
+
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 01/07/2007
+-- Description: this is the main entity for all buses, it contains:
+--
+-- 1) trigger_handle_tld: entity which loads configuration parameters and sends
+-- token.
+-- 2) tdc_readout_and_trb_interface: it reads out the bus, put data into FIFO
+-- 3) common_stop_generator: every time the TRB asks for data, the common stop
+-- signal is generated and the entity wait for the token back. If the token is
+-- back this entity is able to receive the next data request from TRB.
+--
+-- This code has not optimized yet.
+-- 20/11/2007 I added bus_number signal and BUS_CHAIN_IN port.
+--
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity mdc_addon_daq_bus_0 is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ A_ADS_0 : in std_logic; --Motherboard address
+ A_ADS_1 : in std_logic; --Motherboard address
+ A_ADS_2 : in std_logic; --Motherboard address
+
+-- A_ACK : inout std_logic; --acknowledgment
+ A_ACK : in std_logic;
+ A_CMS : out std_logic; --common stop
+
+-- A_OR : in std_logic; --common or
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_GDE : out std_logic; --global disable
+ A_RDO : in std_logic; --ready FROM first motherboard
+ A_RESERV : in std_logic; --this is 11 bit of dataword
+
+ A_DRA : out std_logic; --A_ACK enable
+ A_DRB_1 : out std_logic; --A_RDO enable
+ A_DRB_2 : out std_logic; --A_RDM enable
+ A_DRE : out std_logic; --address/data line enable
+ A_ENB_1 : out std_logic; --A_AOD enable
+ A_ENB_2 : out std_logic; --A_DST enable
+ A_ENR_1 : out std_logic; --A_GDE enable
+ A_ENR_2 : out std_logic; --A_CMS enable
+-- A_ENR_3 : out std_logic; --A_OR enable
+ A_FET_ENABLE : out std_logic; --it enables 2 FETs
+ A_REN : out std_logic; --A_RESERV enable
+
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+
+ TOKEN_TO_MUX_OUT : out std_logic;
+ TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
+
+-- test pins connected to HPLA
+ LA : out std_logic_vector(31 downto 0);
+ D : out std_logic_vector(6 downto 0);
+-------------------------------------------------------------------------------
+-- CONNECTION TO COMMON STOP GENERATOR
+-------------------------------------------------------------------------------
+ A_RDO_OUT : out std_logic; --ready FROM first motherboard
+
+ ROC1_WRITTEN_OUT : out std_logic;
+ BUS_NUMBER_IN : in std_logic_vector(3 downto 0);
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- TRB INTERFACE
+-------------------------------------------------------------------------------
+ ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0);
+ INIT_TRB_INTERFACE_OUT : out std_logic;
+ DATA_OUT : out std_logic_vector(25 downto 0);--(18 downto 0);
+ READ_FIFO_IN : in std_logic;
+ DEBUG_REGISTER_TRB_INTERFACE : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+-------------------------------------------------------------------------------
+-- SIGNALS DATA, dst,aod multiplexed
+-------------------------------------------------------------------------------
+ A_ADD_CONFIGURATION_OUT : out std_logic_vector(8 downto 0); --address/data line
+ A_DST_CONFIGURATION_OUT : out std_logic; --data strobe
+ A_AOD_CONFIGURATION_OUT : out std_logic; --address or data
+
+ A_ADD_DATA_IN : in std_logic_vector(8 downto 0); --address/data line
+ A_DST_DATA_IN : in std_logic; --data strobe
+ A_AOD_DATA_IN : in std_logic; --address or data
+-------------------------------------------------------------------------------
+-- DEBUG REGISTER
+-------------------------------------------------------------------------------
+ DEBUG_REGISTER_0_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_1_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_2_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_3_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_4_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_5_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_6_BUS_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_7_BUS_0 : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- TRB net connections
+-------------------------------------------------------------------------------
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_IN : in std_logic;
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0';
+
+ --Data Port
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_IN: in std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_OUT : out std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_IN : in std_logic;
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0));
+end mdc_addon_daq_bus_0;
+
+architecture behavioral of mdc_addon_daq_bus_0 is
+
+ signal a_add_configuration_i, a_add_data_i : std_logic_vector(8 downto 0);
+ signal enable_a_add_data_i : std_logic;
+ signal a_aod_configuration_i, a_aod_data_i : std_logic;
+ signal trigger_type_in_i : std_logic_vector(3 downto 0);
+ signal enable_mode_line_i : std_logic_vector(3 downto 0);
+ signal a_dst_configuration_i : std_logic;
+ signal token_back_out_i : std_logic_vector(3 downto 0);
+ signal a_dst_data_i, A_ENR_1_i : std_logic;
+ signal a_cms_out_i : std_logic;
+ signal init_trigger_handle_tld_i : std_logic_vector(3 downto 0);
+ signal a_ads_0_i, a_ads_1_i, a_ads_2_i, a_ack_i : std_logic;
+ signal reset_i : std_logic;
+ signal roc1_written_i, cal1_written_i : std_logic;
+ signal a_res_i, a_tok_i, a_mod_i, a_wrm_i, a_rdm_i, a_rdo_i : std_logic;
+ signal a_gde_i : std_logic;
+ signal token_to_trb_i : std_logic;
+ signal a_reserv_i : std_logic;
+ signal init_tdc_readout_i : std_logic_vector(3 downto 0);
+ signal reinit_roc1_forwarded_i : std_logic;
+ signal reinit_roc1_i : std_logic;
+ signal succesful_reinit_roc1_i, stop_readout_i : std_logic;
+
+ component trigger_handle_tld
+ port (
+ CLK : in std_logic;
+ A_ADD : out std_logic_vector(8 downto 0); -- address/data line
+ A_AOD : out std_logic; --address or data
+ A_DST : out std_logic; --data strobe
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_GDE : out std_logic; --global disable
+ A_RDO : in std_logic; --ready FROM first motherboard
+ A_DRE : out std_logic; --address/data line enable
+ A_ENR_1 : out std_logic; --A_GDE enable
+
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+
+ TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ -- test pins connected to HPLA
+ DEBUG_REGISTER : out std_logic_vector(24 downto 0);
+ ENABLE_MODE_LINE : in std_logic_vector(3 downto 0);
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ TOKEN_BACK_OUT : out std_logic_vector(3 downto 0);
+ REINIT_ROC1_OUT : out std_logic;
+ STOP_READOUT_OUT : out std_logic;
+ RESET : in std_logic);
+ end component;
+
+ component tdc_readout_and_trb_interface
+-- generic (width : integer := 16;
+-- bus_number : std_logic_vector(3 downto 0));
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+-------------------------------------------------------------------------------
+-- tdc_readout
+-------------------------------------------------------------------------------
+ A_ADD : in std_logic_vector(8 downto 0);
+ A_RESERV : in std_logic; --this is 11 bit of dataword
+ A_AOD : in std_logic; --address or data
+ A_ACK : in std_logic;
+ A_DST : in std_logic;
+ -- A_RDO : in std_logic;
+ A_DRE : out std_logic;
+ TOKEN_IN : in std_logic_vector(3 downto 0);
+ INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- tdc_readout_and_trb_interface
+-------------------------------------------------------------------------------
+ BUS_NUMBER_IN : in std_logic_vector(3 downto 0);
+ TOKEN_TO_TRB_OUT : out std_logic;
+ REINIT_ROC1_IN : in std_logic;
+ REINIT_ROC1_OUT : out std_logic;
+ SUCCESFUL_REINIT_ROC1 : in std_logic;
+ STOP_READOUT_IN : in std_logic;
+ -- DATA_BUS_TO_TRB_OUT : out std_logic_vector(25 downto 0);--(18 downto 0);
+ -- DATA_VALID_TO_TRB_OUT : out std_logic;
+ DEBUG_REGISTER_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_1 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_2 : out std_logic_vector(7 downto 0);
+-------------------------------------------------------------------------------
+-- trb interface
+-------------------------------------------------------------------------------
+ -------------------------------------------------------------------------------
+-- CONNECTION TO TRBNET END POINT INTERFACE
+-------------------------------------------------------------------------------
+-- ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0);
+-- INIT_TRB_INTERFACE_OUT : out std_logic;
+-- DATA_OUT : out std_logic_vector(25 downto 0);--(18 downto 0);
+-- READ_FIFO_IN : in std_logic;
+-- DEBUG_REGISTER_TRB_INTERFACE : in std_logic_vector(3 downto 0);
+-- -------------------------------------------------------------------------------
+-- -
+-------------------------------------------------------------------------------
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_IN : in std_logic;
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0';
+
+ --Data Port
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_IN: in std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_OUT : out std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_IN : in std_logic;
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0));
+
+ end component;
+
+ component common_stop_generator
+ generic (width : integer := 5);
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ A_CMS_OUT : out std_logic; -- common stop
+ A_RDO_IN : in std_logic; --ready FROM first motherboard
+ TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger
+ INIT_TDC_READOUT_OUT : out std_logic_vector(3 downto 0);
+ INIT_TRIGGER_HANDLE_TLD_OUT : out std_logic_vector(3 downto 0);
+ ROC1_WRITTEN_IN : in std_logic;
+ CAL1_WRITTEN_IN : in std_logic;
+ ENABLE_MODE_LINE_OUT : out std_logic_vector(3 downto 0);
+ ENABLE_A_ADD_DATA_OUT : out std_logic);
+ end component;
+
+begin --behavioral
+
+ u0 : trigger_handle_tld
+ port map (
+ CLK => CLK,
+ A_ADD => a_add_configuration_i,
+ A_AOD => a_aod_configuration_i, --address or data
+ A_DST => a_dst_configuration_i,
+ A_RDM => a_rdm_i,
+ A_GDE => a_gde_i, -- : out std_logic; --global disable
+ A_RDO => a_rdo_i,
+ A_DRE => open, --enable_a_add_configuration_i,
+ A_ENR_1 => A_ENR_1_i, --A_GDE enable
+ A_MOD => a_mod_i,
+ A_RES => a_res_i,
+ A_TOK => a_tok_i,
+ A_WRM => a_wrm_i,
+ TRIGGER_TYPE_IN => init_trigger_handle_tld_i, --trigger_type_out_i,
+ BUS_CHAIN_IN => BUS_CHAIN_IN,
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN => RAM_ADDRESS_IN,
+ RAM_DATA_IN => RAM_DATA_IN,
+ RAM_DATA_OUT => RAM_DATA_OUT,
+ RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN,
+ RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN,
+
+ DEBUG_REGISTER => open,
+ ENABLE_MODE_LINE => enable_mode_line_i,
+ ROC1_WRITTEN => roc1_written_i,
+ CAL1_WRITTEN => cal1_written_i,
+ TOKEN_BACK_OUT => token_back_out_i,
+ REINIT_ROC1_OUT => reinit_roc1_i,
+ STOP_READOUT_OUT => stop_readout_i,
+ RESET => reset_i);
+
+ A_ADD_CONFIGURATION_OUT <= a_add_configuration_i;
+ A_DST_CONFIGURATION_OUT <= a_dst_configuration_i;
+ A_AOD_CONFIGURATION_OUT <= a_aod_configuration_i;
+
+ a_add_data_i <= A_ADD_DATA_IN;
+ a_dst_data_i <= A_DST_DATA_IN;
+ a_aod_data_i <= A_AOD_DATA_IN;
+
+ u2 : common_stop_generator
+ generic map(width => 5)
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+ A_CMS_OUT => a_cms_out_i,
+ A_RDO_IN => token_to_trb_i,
+ TRIGGER_TYPE_IN => trigger_type_in_i,
+ INIT_TDC_READOUT_OUT => init_tdc_readout_i,
+ INIT_TRIGGER_HANDLE_TLD_OUT => init_trigger_handle_tld_i,
+ ROC1_WRITTEN_IN => roc1_written_i,
+ CAL1_WRITTEN_IN => cal1_written_i,
+ ENABLE_MODE_LINE_OUT => enable_mode_line_i,
+ ENABLE_A_ADD_DATA_OUT => enable_a_add_data_i);
+
+ u3 : tdc_readout_and_trb_interface
+ -- generic map (width => 16, bus_number => bus_number)
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+-- tdc_readout
+ A_ADD => a_add_data_i, --A_ADD, --connected to exteranl bus/mux
+ A_RESERV => a_reserv_i, --A_RESERV, --this is 11 bit of dataword
+ A_AOD => a_aod_data_i, --address or data
+ A_ACK => a_ack_i,
+ A_DST => a_dst_data_i,
+ A_DRE => open, --enable_a_add_data_i,
+ --
+ TOKEN_IN => token_back_out_i,
+ INIT_TDC_READOUT_IN => init_tdc_readout_i,
+
+ BUS_NUMBER_IN => BUS_NUMBER_IN,
+ -- INIT_TRB_INTERFACE_IN => init_trb_interface_i,
+ TOKEN_TO_TRB_OUT => token_to_trb_i,
+ REINIT_ROC1_IN => reinit_roc1_i,
+ REINIT_ROC1_OUT => reinit_roc1_forwarded_i,
+ SUCCESFUL_REINIT_ROC1 => succesful_reinit_roc1_i,
+ STOP_READOUT_IN => stop_readout_i,
+ -- DATA_BUS_TO_TRB_OUT => DATA_BUS_TO_TRB_OUT,
+ -- DATA_VALID_TO_TRB_OUT => DATA_VALID_TO_TRB_OUT,
+ DEBUG_REGISTER_0 => DEBUG_REGISTER_0_BUS_0,
+ DEBUG_REGISTER_1 => DEBUG_REGISTER_1_BUS_0,
+ DEBUG_REGISTER_2 => DEBUG_REGISTER_2_BUS_0,
+-- trb interface
+-- ACKNOWLEDGE_TRB_INTERFACE_IN => ACKNOWLEDGE_TRB_INTERFACE_IN,
+-- INIT_TRB_INTERFACE_OUT => INIT_TRB_INTERFACE_OUT,
+-- DATA_OUT => DATA_OUT,
+-- READ_FIFO_IN => READ_FIFO_IN,
+-- DEBUG_REGISTER_TRB_INTERFACE => DEBUG_REGISTER_TRB_INTERFACE
+ LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
+ LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_IN,
+ LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,
+ LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN,
+ LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
+ LVL1_ERROR_PATTERN_OUT => open,
+ LVL1_TRG_RELEASE_OUT => open,
+ IPU_NUMBER_IN => IPU_NUMBER_IN,
+ IPU_INFORMATION_IN => IPU_INFORMATION_IN,
+ IPU_START_READOUT_IN => IPU_START_READOUT_IN,
+ IPU_DATA_OUT => open,
+ IPU_DATAREADY_OUT => open,
+ IPU_READOUT_FINISHED_OUT => open,
+ IPU_READ_IN => IPU_READ_IN,
+ IPU_LENGTH_OUT => open,
+ IPU_ERROR_PATTERN_OUT => open);
+
+-------------------------------------------------------------------------------
+-- connection to output
+-------------------------------------------------------------------------------
+ TOKEN_TO_MUX_OUT <= token_to_trb_i;
+ a_ads_0_i <= A_ADS_0;
+ a_ads_1_i <= A_ADS_1;
+ a_ads_2_i <= A_ADS_2;
+ a_ack_i <= A_ACK;
+-------------------------------------------------------------------------------
+-- INPUTs
+-------------------------------------------------------------------------------
+ trigger_type_in_i <= TRIGGER_TYPE_IN;
+ reset_i <= RESET;
+-------------------------------------------------------------------------------
+-- OUTPUTs
+-------------------------------------------------------------------------------
+ ROC1_WRITTEN_OUT <= roc1_written_i;
+
+-------------------------------------------------------------------------------
+--the following signal control the FET
+-- 0 A <==> B
+-- 1 Z
+-------------------------------------------------------------------------------
+ A_FET_ENABLE <= '0';
+-------------------------------------------------------------------------------
+-- enable signal to transceivers-only differential signlals
+-- here signal which do not change in the design
+-------------------------------------------------------------------------------
+ A_DRB_1 <= '0'; --A_RDO enable
+ A_ENR_1 <= '1'; --A_GDE enable A_ENR_1_i <= '1';
+ A_REN <= '0'; --A_RESERV(11th bit of data word) enable
+ A_ENR_2 <= '1'; --common stop enable
+ A_DRB_2 <= '1'; --A_RDM enable
+ A_DRA <= '0'; --A_ACK enable
+-------------------------------------------------------------------------------
+
+-- reset_i <= ADO_TTL_IN(0);
+
+ A_GDE <= a_gde_i;
+ A_RES <= a_res_i;
+ A_TOK <= a_tok_i;
+ A_MOD <= a_mod_i;
+ A_WRM <= a_wrm_i;
+ A_RDM <= a_rdm_i;
+ a_rdo_i <= A_RDO; --token back
+ a_reserv_i <= A_RESERV; --this is 11 bit of dataword
+
+ A_CMS <= a_cms_out_i; --common stop
+-- A_RDO_OUT <= token_to_trb_i;
+
+
+end behavioral;
+
#add_file options
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/lattice/ecp2m/pll_in25_out100.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/special/adc_ltc2308_readout.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-# add_file -vhdl -lib work "../mdc_optical/ipcores/lattice_ecp2m_fifo_16x8_dualport.vhd"
-# add_file -vhdl -lib work "../mdc_optical/ipcores/lattice_ecp2m_fifo_8x8_dualport.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../cvs/trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/pll_in25_out100.vhd"
+add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../trbnet/special/adc_ltc2308_readout.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd"
add_file -vhdl -lib work "version.vhd"
add_file -vhdl -lib work "mdc_oepb.vhd"
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity mode_line_multiplexer is
+ port(
+ CLK : in std_logic; --for testing
+
+--mode lines input from "trigger_begrun"
+ A_MOD_TB : in std_logic; -- TDC working mode
+ A_RES_TB : in std_logic; -- TDC working mode
+ A_TOK_TB : in std_logic; -- TDC working mode
+ A_WRM_TB : in std_logic; -- TDC working mode
+ A_RDM_TB : in std_logic; --ready TO first motherboard
+ A_RDO_TB : out std_logic; --ready FROM first motherboard
+ A_GDE_TB : in std_logic; --global disable
+--mode lines input from from "send_token"
+ A_MOD_ST : in std_logic; -- TDC working mode
+ A_RES_ST : in std_logic; -- TDC working mode
+ A_TOK_ST : in std_logic; -- TDC working mode
+ A_WRM_ST : in std_logic; -- TDC working mode
+ A_RDM_ST : in std_logic; --ready TO first motherboard
+ A_RDO_ST : out std_logic; --ready FROM first motherboard
+ A_GDE_ST : in std_logic; --global disable
+--mode lines to from MB
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_RDO : in std_logic; --ready FROM first motherboard
+ A_GDE : out std_logic; --global disable
+-- RESET : in std_logic;
+ ENABLE_MODE_LINE : in std_logic_vector(3 downto 0);
+-- TRIGGER_TYPE : in std_logic_vector(3 downto 0);
+ DEBUG_REGISTER : out std_logic_vector(3 downto 0)
+ );
+
+end mode_line_multiplexer;
+
+architecture behavioral of mode_line_multiplexer is
+
+begin -- behavioral
+
+ process (ENABLE_MODE_LINE, A_RDO,
+ A_MOD_TB, A_RES_TB, A_TOK_TB, A_WRM_TB, A_RDM_TB,
+ A_MOD_ST, A_RES_ST, A_TOK_ST, A_WRM_ST, A_RDM_ST,
+ A_GDE_ST,A_GDE_TB,CLK)
+
+begin
+ if rising_edge(CLK) then
+
+
+ case ENABLE_MODE_LINE is
+
+ when x"D" => --begrun trigger
+ DEBUG_REGISTER <= "0000";
+ A_MOD <= A_MOD_TB;
+ A_RES <= A_RES_TB;
+ A_TOK <= A_TOK_TB;
+ A_WRM <= A_WRM_TB;
+ A_RDM <= A_RDM_TB; --token out
+ A_RDO_TB <= A_RDO; --token back
+ A_GDE <= A_GDE_TB;
+
+ when x"1" => --normal trigger
+ DEBUG_REGISTER <= "0001";
+ A_MOD <= A_MOD_ST;
+ A_RES <= A_RES_ST;
+ A_TOK <= A_TOK_ST;
+ A_WRM <= A_WRM_ST;
+ A_RDM <= A_RDM_ST; --token
+ A_RDO_ST <= A_RDO; --token back
+ A_GDE <= A_GDE_ST;
+
+ when others => --in case wrong trigger the trigger_begrun is connected to out
+ A_MOD <= A_MOD_ST;
+ A_RES <= A_RES_ST;
+ A_TOK <= A_TOK_ST;
+ A_WRM <= A_WRM_ST;
+ A_RDM <= A_RDM_ST; --token
+ A_RDO_ST <= A_RDO; --token back
+ A_GDE <= A_GDE_ST;
+
+
+ end case;
+ end if;
+
+end process;
+
+end behavioral;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity pulse_to_constant is
+
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ PULSE_IN : in std_logic; --token in
+ CONSTANT_OUT : out std_logic;
+ CLEAR_IN : in std_logic); -- next trigger
+
+end pulse_to_constant;
+
+architecture Behavioral of pulse_to_constant is
+
+type state_type is (idle_state, up_state);
+
+signal current_state,next_state : state_type;
+
+signal reg_constant, next_constant : std_logic;
+
+begin -- Behavioral
+
+registering: process (CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_constant <= '0';
+ else
+ current_state <= next_state;
+ reg_constant <= next_constant;
+ end if;
+ end if;
+end process registering;
+CONSTANT_OUT <= reg_constant;
+
+process (current_state, PULSE_IN, CLEAR_IN)
+begin
+
+ next_constant <= '0';
+
+ case current_state is
+
+ when idle_state =>
+ next_constant <= '0';
+ if PULSE_IN = '1' then
+ next_state <= up_state;
+ else
+ next_state <= idle_state;
+ end if;
+
+ when up_state =>
+ next_constant <= '1';
+ if CLEAR_IN = '1' then --when next trigger comes
+ next_state <= idle_state;
+ else
+ next_state <= up_state;
+ end if;
+
+ when others =>
+ next_state <= idle_state;
+ end case;
+end process;
+end Behavioral;
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity send_token_to_mb is
+ generic (
+ width : integer := 5);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TRIGGER_TYPE : in std_logic_vector(3 downto 0);
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_RDO : in std_logic; --ready FROM first motherboard
+ A_GDE : out std_logic; --global disable
+ TOKEN_BACK_OUT : out std_logic_vector(3 downto 0); -- active if token came back
+ REINIT_ROC1 : out std_logic; --active when notoken
+ STOP_READOUT_OUT : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(3 downto 0)
+ );
+end send_token_to_mb;
+
+architecture behavioral of send_token_to_mb is
+
+constant delay_cm_gde : std_logic_vector(width - 1 downto 0) := (others => '1');
+constant time_limit : std_logic_vector(width - 1 downto 0) := (others => '1');
+
+--oep
+--ok for 25MHz
+--constant delay_cm_gde : std_logic_vector(width - 1 downto 0) := "01001";
+--constant time_limit : std_logic_vector(width - 1 downto 0) := "01001";
+
+type state_type is (idle_state, set_mode_after_loaded_ROC1, send_token_state,
+ wait_token_back_state, token_not_back_state,
+ token_is_back_state, token_hanging_state,
+ global_disable_state, wait_state, wait_state_1);
+
+signal current_state, next_state : state_type;
+
+signal reg_A_MOD, reg_A_RES, reg_A_TOK, reg_A_WRM, reg_A_RDM: std_logic;
+signal next_A_MOD, next_A_RES, next_A_TOK, next_A_WRM, next_A_RDM: std_logic;
+signal reg_TOKEN_BACK_OUT, next_TOKEN_BACK_OUT: std_logic_vector(3 downto 0);
+signal reg_DEBUG_REGISTER, next_DEBUG_REGISTER: std_logic_vector(3 downto 0);
+
+signal reg_A_GDE, next_A_GDE : std_logic;
+
+signal time_counter_cm_gde : std_logic_vector(width - 1 downto 0);
+signal time_counter : std_logic_vector(width - 1 downto 0); --it's used to mantain data
+ --mode on the bus
+signal time_counter_wait: std_logic_vector(9 downto 0);
+signal counter_for_token : std_logic_vector(31 downto 0);
+
+begin -- behavioral
+ --
+-------------------------------------------------------------------------------
+-- register output + sincronization of the state machine
+-------------------------------------------------------------------------------
+ REGISTER_ADDR_DATA_MODE : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_A_MOD <= '0';
+ reg_A_RES <= '0';
+ reg_A_TOK <= '0';
+ reg_A_WRM <= '0';
+ reg_A_RDM <= '0';
+ reg_TOKEN_BACK_OUT <= (others => '0');
+ reg_A_GDE <= '0';
+ reg_DEBUG_REGISTER <= (others => '0');
+ current_state <= idle_state;
+ else
+ reg_A_MOD <= next_A_MOD;
+ reg_A_RES <= next_A_RES;
+ reg_A_TOK <= next_A_TOK;
+ reg_A_WRM <= next_A_WRM;
+ reg_A_RDM <= next_A_RDM;
+ reg_TOKEN_BACK_OUT <= next_TOKEN_BACK_OUT;
+ reg_A_GDE <= next_A_GDE;
+ reg_DEBUG_REGISTER <= next_DEBUG_REGISTER;
+ current_state <= next_state;
+ end if;
+ end if;
+ end process REGISTER_ADDR_DATA_MODE;
+
+ A_MOD <= reg_A_MOD;
+ A_RES <= reg_A_RES;
+ A_TOK <= reg_A_TOK;
+ A_WRM <= reg_A_WRM;
+ A_RDM <= reg_A_RDM;
+ TOKEN_BACK_OUT <= reg_TOKEN_BACK_OUT;
+ A_GDE <= reg_A_GDE;
+ DEBUG_REGISTER <= reg_DEBUG_REGISTER;
+-------------------------------------------------------------------------------
+-- state machine: sends the token signal: width 320ns and then a state wait for
+-- token back, if not back after a fixex amount of thime it goes in a state
+-- token not back.
+-------------------------------------------------------------------------------
+process (current_state,TRIGGER_TYPE, A_RDO,
+ time_counter, time_counter_cm_gde,
+ time_counter_wait,counter_for_token)
+ begin
+ --hex 64 + GDE
+ next_A_WRM <= '1';
+ next_A_MOD <= '0';
+ next_A_TOK <= '0';
+ next_A_RES <= '1';
+ next_A_RDM <= '0';
+ next_TOKEN_BACK_OUT <= (others => '0');
+ next_A_GDE <= '0';--'1';-- for cal
+ next_DEBUG_REGISTER <= (others => '0');
+
+ case current_state is
+
+ when idle_state =>
+ next_DEBUG_REGISTER <= "0000";
+ --hex 64 + GDE
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '0';
+ next_A_GDE <= '0';--'1'; --for cal
+ if TRIGGER_TYPE = x"1" then
+ next_state <= wait_state;
+ else
+ next_state <= idle_state;
+ end if;
+
+ when wait_state =>
+ -- hex 64 + GDE
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '0';
+ next_A_GDE <= '1';
+ if time_counter = time_limit then
+ -- next_state <= send_token_state;
+ next_state <= wait_state_1;
+ else
+ next_state <= wait_state;
+ end if;
+
+ when wait_state_1 =>
+ -- hex 64 + GDE
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '0';
+ next_A_GDE <= '1';
+ if time_counter_wait >= "0000011111" then
+--ok 25MHz
+-- if time_counter_wait >= "0000001001" then
+ next_state <= send_token_state;
+ else
+ next_state <= wait_state_1;
+ end if;
+-------------------------------------------------------------------------------
+-- token width
+-------------------------------------------------------------------------------
+ when send_token_state =>
+ next_DEBUG_REGISTER <= "0010";
+ -- hex 65
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '1';
+ next_A_GDE <= '1';
+ if time_counter = time_limit then
+ next_state <= wait_token_back_state;
+ else
+ next_state <= send_token_state;
+ end if;
+
+ when wait_token_back_state =>
+ next_DEBUG_REGISTER <= "0011";
+ -- hex 65
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '1';
+ next_A_GDE <= '1';
+-- if (A_RDO = '1' and counter_for_token < x"000fffff") then
+-- next_state <= token_is_back_state;
+-- elsif (A_RDO = '0' and counter_for_token >= x"000fffff") then
+-- next_state <= token_not_back_state;
+-- else
+-- next_state <= wait_token_back_state;
+-- end if;
+ if A_RDO = '1' then
+ -- next_TOKEN_BACK_OUT <= '1';
+ next_state <= token_is_back_state;
+ -- next_state <= idle_state;
+ else
+ next_state <= wait_token_back_state;
+ end if;
+
+ when token_is_back_state =>
+ next_DEBUG_REGISTER <= "0100";
+ -- hex 64
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '0';
+ next_A_GDE <= '1';
+ next_TOKEN_BACK_OUT <= x"1"; --token received normally
+ next_state <= idle_state;
+
+ when token_not_back_state =>
+ next_DEBUG_REGISTER <= "0101";
+ -- hex 64
+ next_A_MOD <= '0';
+ next_A_RES <= '1';
+ next_A_TOK <= '0';
+ next_A_WRM <= '1';
+ next_A_RDM <= '0';
+ next_A_GDE <= '1';
+ next_TOKEN_BACK_OUT <= x"2"; --token NOT back
+ next_state <= idle_state;
+
+ when others =>
+ next_state <= idle_state;
+
+ end case;
+end process;
+-------------------------------------------------------------------------------
+-- this counter mantain the mode line fixed at a certain value
+--(see debouncer in CPLD on motherboard)
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ time_counter <= (others => '0');
+ elsif (current_state = global_disable_state or
+ current_state = send_token_state or
+ current_state = wait_state)
+ then
+ time_counter <= time_counter + 1;
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or current_state = send_token_state) then
+ time_counter_wait <= (others => '0');
+ elsif (current_state = wait_state_1) then
+ time_counter_wait <= time_counter_wait + 1;
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+-- counter to wait for token. If the counter exceed a certain value a no token
+-- back will be send to tdc_readout
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or current_state = idle_state) then
+ counter_for_token <= (others => '0');
+ elsif (current_state = wait_token_back_state) then
+ counter_for_token <= counter_for_token + 1;
+ else
+ counter_for_token <= counter_for_token;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- delay cms and gde
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- time_counter_cm_gde <= (others => '0');
+-- elsif (current_state = wait_state) then
+-- time_counter_cm_gde <= time_counter_cm_gde + 1;
+-- end if;
+-- end if;
+-- end process;
+-------------------------------------------------------------------------------
+--purpose: this counter control the time
+--limit after which the token is not back
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- token_counter <= (others => '0');
+-- elsif (current_state = wait_token_back_state)
+-- then
+-- token_counter <= token_counter + 1;
+-- end if;
+-- end if;
+-- end process;
+end behavioral ;
+
+
+
+
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+entity tdc_interface is
+ port (
+ CLK : in std_logic;
+ TDC_CLK : in std_logic; -- for input clock should be
+ -- through clock buffer
+ RESET : in std_logic;
+ TDC_DATA_IN : in std_logic_vector (31 downto 0);
+ --data from TDC
+ START_TDC_READOUT : in std_logic;
+ --signal from rpc_trb_v2_fpga - trigger has arrived,one pulse (40MHz long)
+ --or 100MHz long - but make 25 ns from this !!!
+ A_TDC_READY : in std_logic;
+ B_TDC_READY : in std_logic;
+ C_TDC_READY : in std_logic;
+ D_TDC_READY : in std_logic;
+ A_TDC_ERROR : in std_logic;
+ B_TDC_ERROR : in std_logic;
+ C_TDC_ERROR : in std_logic;
+ D_TDC_ERROR : in std_logic;
+ A_TDC_POWERUP : out std_logic; --turn on TDC -should be one ?!
+ B_TDC_POWERUP : out std_logic;
+ C_TDC_POWERUP : out std_logic;
+ D_TDC_POWERUP : out std_logic;
+ SEND_TDC_TOKEN : out std_logic;
+ RECEIVED_TDC_TOKEN : in std_logic;
+ GET_TDC_DATA : out std_logic; --Signal to TDC chip
+ TO_MANY_TDC_DATA : in std_logic;
+--TDC state mechines had to cut data
+--but this should be in FIFO entity and should goes to tdc_interface.vhd (
+--to stop writing to fifo just finish read out)
+--copyt to internal FIFO
+ TDC_READOUT_COMPLETED : out std_logic;
+ LVL1_TAG : in std_logic_vector(7 downto 0);
+ LVL1_CODE : in std_logic_vector(3 downto 0);
+ LVL2_TAG : in std_logic_vector(7 downto 0);
+ HOW_MANY_ADD_DATA : in std_logic_vector(7 downto 0);
+ COUNTER_a : in std_logic_vector(31 downto 0);
+ COUNTER_b : in std_logic_vector(31 downto 0);
+ COUNTER_c : in std_logic_vector(31 downto 0);
+ COUNTER_d : in std_logic_vector(31 downto 0);
+ COUNTER_e : in std_logic_vector(31 downto 0);
+ COUNTER_f : in std_logic_vector(31 downto 0);
+ COUNTER_g : in std_logic_vector(31 downto 0);
+ COUNTER_h : in std_logic_vector(31 downto 0);
+ LVL2_TRIGGER : in std_logic;--_vector(1 downto 0);
+ TDC_DATA_OUT : out std_logic_vector (31 downto 0); --data to ETRAX (LVL2)
+ TDC_DATA_VALID : out std_logic; -- The TDC_DATA_OUT can be written
+ ETRAX_IS_READY_TO_READ : in std_logic;
+ LVL1_BUSY : out std_logic;
+ LVL2_BUSY : out std_logic;
+ TDC_REGISTER_00 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_01 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_02 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_03 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_04 : out std_logic_vector(31 downto 0);
+ TDC_REGISTER_05 : in std_logic_vector(31 downto 0);
+ BUNCH_RESET : out std_logic;
+ EVENT_RESET : out std_logic;
+ READ_ADRESS_END_UP : out std_logic; --here
+ DELAY_TRIGGER : in std_logic_vector(7 downto 0);
+ TDC_START : out std_logic;
+ TRIGGER_WITHOUT_HADES : in std_logic;
+ TRIGGER_WITH_GEN_EN : in std_logic;
+ TRIGGER_WITH_GEN : in std_logic;
+ FIFO_RESET_ERR : out std_logic
+ );
+end tdc_interface;
+architecture tdc_interface of tdc_interface is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ component up_down_counter_16_bit
+ port (
+ QOUT : out std_logic_vector(15 downto 0);
+ UP : in std_logic;
+ DOWN : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic
+ );
+ end component;
+ component BUFG
+ port(
+ O: out std_ulogic;
+ I: in std_ulogic
+ );
+ end component;
+ component simpleupcounter_8bit
+ port (
+ QOUT : out std_logic_vector(7 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ CLR : in std_logic);
+ end component;
+ component lvl1_buffer
+ port (
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_clk : IN std_logic;
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_clk : IN std_logic;
+ wr_en : IN std_logic;
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic;
+ rd_data_count : OUT std_logic_VECTOR(9 downto 0));
+ end component;
+ component lvl1_fifo
+ port (
+ clk : IN std_logic;
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_en : IN std_logic;
+ data_count : OUT std_logic_VECTOR(13 downto 0);
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic);
+ end component;
+ component fifo16kW_through--virtex_13kW_fifo
+ port (
+ din : IN std_logic_VECTOR(31 downto 0);
+ rd_clk : IN std_logic;
+ rd_en : IN std_logic;
+ rst : IN std_logic;
+ wr_clk : IN std_logic;
+ wr_en : IN std_logic;
+ almost_empty : OUT std_logic;
+ almost_full : OUT std_logic;
+ dout : OUT std_logic_VECTOR(31 downto 0);
+ empty : OUT std_logic;
+ full : OUT std_logic;
+ rd_data_count : OUT std_logic_VECTOR(13 downto 0);
+ wr_data_count : OUT std_logic_VECTOR(13 downto 0));
+ end component;
+ signal tdc_ready : std_logic;
+ signal counter_a_i : std_logic_vector(31 downto 0);
+ signal counter_b_i : std_logic_vector(31 downto 0);
+ signal counter_c_i : std_logic_vector(31 downto 0);
+ signal counter_d_i : std_logic_vector(31 downto 0);
+ signal counter_e_i : std_logic_vector(31 downto 0);
+ signal counter_f_i : std_logic_vector(31 downto 0);
+ signal counter_g_i : std_logic_vector(31 downto 0);
+ signal counter_h_i : std_logic_vector(31 downto 0);
+ signal add_data_counter : std_logic_vector(7 downto 0):=(others => '0');
+ signal add_data_pulse : std_logic;
+ signal first_header : std_logic_vector(31 downto 0):=(others => '0');
+ signal second_header : std_logic_vector(31 downto 0):=(others => '0');
+ signal words_in_event : std_logic_vector(15 downto 0):=(others => '0');
+ signal tdc_data_valid_i : std_logic;
+ signal how_many_words_in_event : std_logic_vector(16 downto 0);
+ signal delay_up : std_logic;
+ signal delay_clr : std_logic;
+ signal delay_qout : std_logic_vector(7 downto 0);
+ signal lvl1_trigger_pulse_start : std_logic;
+ signal lvl1_trigger_pulse_delay : std_logic;
+ signal fifo_reset_err_i : std_logic;
+ type DELAY_FSM_TRIGG is
+ (IDLE ,DELAY_1,DELAY_2);
+ signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
+ type LVL1_START_FSM is
+ (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_TOKEN, SAVE_ADD_DATA_1, SAVE_ADD_DATA_2, SAVE_ADD_DATA_3, SAVE_ADD_DATA_4, SEND_LVL2_TRIGG);
+ signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
+ type LVL2_START_FSM is
+ (IDLE, READOUT_WORD1, READOUT_WORD2 ,READOUT_WORD3 ,SAVE_EVENT_SIZE ,SEND_DATA1, LAST_WORD);
+ signal LVL2_START_fsm_currentstate, LVL2_START_fsm_nextstate : LVL2_START_FSM;
+ signal lvl1_busy_i : std_logic;
+ signal lvl1_busy_ff : std_logic;
+ signal lvl1_memory_busy_i : std_logic;
+ signal lvl2_busy_i : std_logic;
+ signal lvl1_trigger_pulse : std_logic;
+ signal lvl1_tdc_trigg_i : std_logic;
+ signal lvl1_tdc_trigg_ff : std_logic;
+
+ signal trigger_register_00_i : std_logic_vector(5 downto 0);
+ signal lvl2_busy_end_pulse : std_logic;
+ signal not_tdc_data_valid_i : std_logic;
+
+ signal not_tdc_clk : std_logic;
+ signal test_counter_0 : std_logic_vector(7 downto 0);
+ signal test_counter_1 : std_logic_vector(7 downto 0);
+ signal test_counter_2 : std_logic_vector(7 downto 0);
+ signal test_counter_3 : std_logic_vector(7 downto 0);
+ signal add_data_i : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_out : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_in : std_logic_vector(31 downto 0);
+ signal lvl1_fifo_counter : std_logic_vector(13 downto 0);
+ signal lvl1_fifo_empty : std_logic;
+ signal lvl1_fifo_full : std_logic;
+ signal lvl1_fifo_wr_en : std_logic;
+ signal lvl1_fifo_rd_en : std_logic;
+ signal lvl1_buffer_out : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_in : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_counter : std_logic_vector(13 downto 0);
+ signal lvl1_buffer_empty : std_logic;
+ signal lvl1_buffer_full : std_logic;
+ signal lvl1_buffer_wr_en : std_logic;
+ signal lvl1_buffer_rd_en : std_logic;
+ signal lvl1_or_lvl2_is_busy : std_logic;
+ signal trigger_with_gen_pulse : std_logic;
+ signal lvl1_tag_minus1 : std_logic_vector(7 downto 0);
+ signal lvl2_debug : std_logic_vector(2 downto 0);
+ signal tdc_start_i : std_logic;
+ signal lvl2_busy_start_pulse : std_logic;
+
+ signal lvl1_tdc_trigg_i_fsm : std_logic;
+ signal lvl1_fifo_wr_en_fsm : std_logic;
+ signal lvl1_fifo_in_fsm : std_logic_vector(31 downto 0);
+ signal lvl1_buffer_rd_en_fsm : std_logic;
+ signal lvl1_busy_i_fsm : std_logic;
+ signal lvl1_fifo_rd_en_fsm : std_logic;
+ signal tdc_data_valid_i_fsm : std_logic;
+ signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0');
+ signal trigger_counter : std_logic_vector(7 downto 0);
+ signal lvl1_code_i : std_logic_vector(3 downto 0);
+ signal tdc_ready_a_i : std_logic;
+ signal tdc_ready_b_i : std_logic;
+ signal tdc_ready_c_i : std_logic;
+ signal tdc_ready_d_i : std_logic;
+ signal lvl1_fifo_rd_en_empty_pulse : std_logic;
+ signal lvl1_fifo_empty_not : std_logic;
+ signal lvl1_fifo_busy_counter : std_logic_vector(31 downto 0);
+ signal tdc_data_clocked : std_logic_vector(31 downto 0);
+begin
+ READ_ADRESS_END_UP <= lvl2_busy_end_pulse; --here
+ TDC_REGISTER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ TDC_REGISTER_00(0) <= A_TDC_ERROR;
+ TDC_REGISTER_00(1) <= B_TDC_ERROR;
+ TDC_REGISTER_00(2) <= C_TDC_ERROR;
+ TDC_REGISTER_00(3) <= D_TDC_ERROR;
+ TDC_REGISTER_00(13 downto 4) <= lvl1_fifo_counter(9 downto 0);
+ TDC_REGISTER_00(14) <= lvl1_busy_i;
+ TDC_REGISTER_00(15) <= lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_memory_busy_i;
+ TDC_REGISTER_00(30) <= lvl1_fifo_wr_en;
+ TDC_REGISTER_00(31) <= lvl2_busy_i;
+ TDC_REGISTER_00(29 downto 16) <= lvl1_fifo_busy_counter(13 downto 0);
+ TDC_REGISTER_01(26 downto 0) <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& how_many_words_in_event(15 downto 0);
+ TDC_REGISTER_01(27) <= lvl1_buffer_wr_en;
+ TDC_REGISTER_01(28) <= tdc_ready;
+ TDC_REGISTER_01(29) <= lvl1_buffer_rd_en;
+ TDC_REGISTER_01(30) <= lvl1_buffer_empty;
+ TDC_REGISTER_01(31) <= '0';
+ TDC_REGISTER_02(31 downto 0) <= lvl1_fifo_out;--LVL2_TAG(3 downto 0) & lvl1_buffer_out(27 downto 0);--lvl1_fifo_out;
+-- TDC_REGISTER_02(31 downto 0) <= LVL2_TAG & lvl1_buffer_out(23 downto 0);--lvl1_fifo_out;
+ -- TDC_REGISTER_03(31 downto 0) <= lvl1_fifo_out;
+ TDC_REGISTER_03(31 downto 0) <= x"0"& LVL1_CODE & LVL1_TAG & x"0" & lvl1_code_i & lvl1_tag_minus1;
+ TDC_REGISTER_04(31 downto 0) <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
+ end if;
+ end process TDC_REGISTER;
+ A_TDC_POWERUP <= '1';
+ B_TDC_POWERUP <= '1';
+ C_TDC_POWERUP <= '1';
+ D_TDC_POWERUP <= '1';
+
+-- SYNCH_TDC_SIGNALS: process (TDC_CLK, RESET)
+-- begin
+-- if rising_edge(TDC_CLK) then
+-- if RESET = '1' then
+-- tdc_ready_a_i <= '0';
+-- tdc_ready_b_i <= '0';
+-- tdc_ready_c_i <= '0';
+-- tdc_ready_d_i <= '0';
+-- tdc_ready <= '0';
+-- else
+-- tdc_ready_a_i <= A_TDC_READY;
+-- tdc_ready_b_i <= B_TDC_READY;
+-- tdc_ready_c_i <= C_TDC_READY;
+-- tdc_ready_d_i <= D_TDC_READY;
+-- tdc_ready <= tdc_ready_a_i or tdc_ready_b_i or tdc_ready_c_i or tdc_ready_d_i;
+-- end if;
+-- end if;
+-- end process SYNCH_TDC_SIGNALS;
+
+ tdc_ready <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
+
+ GET_TDC_DATA <= '1';
+ SEND_BUNCH_RESET: process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' then
+ BUNCH_RESET <= '1';
+ EVENT_RESET <= '1';
+ else
+ EVENT_RESET <= '0';
+ BUNCH_RESET <= RECEIVED_TDC_TOKEN;
+ end if;
+ end if;
+ end process SEND_BUNCH_RESET;
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- LVL1 logic
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+REGISTER_DATA_IN: process (TDC_CLK, RESET)
+begin -- process REGISTER_DATA_IN
+ if rising_edge(TDC_CLK) then -- rising clock edge
+ if RESET = '1' then -- asynchronous reset (active low)
+
+ lvl1_buffer_in <= x"abababab";
+ lvl1_buffer_wr_en <= '0';
+-- tdc_data_clocked <= x"abababab"
+ else
+ lvl1_buffer_in <= TDC_DATA_IN;
+ lvl1_buffer_wr_en <= tdc_ready;
+-- tdc_data_clocked TDC_DATA_IN
+ end if;
+ end if;
+end process REGISTER_DATA_IN;
+ LVL1_BUFF: fifo16kW_through--virtex_13kW_fifo
+ port map (
+ din => lvl1_buffer_in,--TDC_DATA_IN,
+ rd_clk => CLK,
+ rd_en => lvl1_buffer_rd_en,
+ rst => RESET ,
+ wr_clk => TDC_CLK,
+ wr_en => lvl1_buffer_wr_en,
+ almost_empty => open,--almost_empty_i,
+ almost_full => open,--almost_full_i,
+ dout => lvl1_buffer_out,
+ empty => lvl1_buffer_empty,
+ full => lvl1_buffer_full,
+ rd_data_count => lvl1_buffer_counter,
+ wr_data_count => open--wr_data_count_i
+ );
+ LVL2_BUFF: fifo16kW_through--virtex_13kW_fifo
+ port map (
+ din => lvl1_fifo_in,
+ rd_clk => CLK,
+ rd_en => lvl1_fifo_rd_en,
+ rst => RESET,
+ wr_clk => CLK,
+ wr_en => lvl1_fifo_wr_en,
+ almost_empty => open,--almost_empty_i,
+ almost_full => open,--almost_full_i,
+ dout => lvl1_fifo_out,
+ empty => lvl1_fifo_empty,
+ full => lvl1_fifo_full,
+ rd_data_count => lvl1_fifo_counter,
+ wr_data_count => open--wr_data_count_i
+ );
+
+ TDC_DATA_OUT <= lvl1_fifo_out;
+
+
+-- LVL1_BUFF: lvl1_buffer
+-- port map (
+-- din => TDC_DATA_IN,
+-- rd_clk => CLK,
+-- rd_en => lvl1_buffer_rd_en,
+-- rst => RESET,
+-- wr_clk => TDC_CLK,
+-- wr_en => lvl1_buffer_wr_en,
+-- dout => lvl1_buffer_out,
+-- empty => lvl1_buffer_empty,
+-- full => lvl1_buffer_full,
+-- rd_data_count => lvl1_buffer_counter);
+
+
+-- LVL1_FIFO_LVL2: lvl1_fifo
+-- port map (
+-- clk => CLK,
+-- din => lvl1_fifo_in,
+-- rd_en => lvl1_fifo_rd_en,
+-- rst => RESET,
+-- wr_en => lvl1_fifo_wr_en,
+-- data_count => lvl1_fifo_counter,
+-- dout => lvl1_fifo_out,
+-- empty => lvl1_fifo_empty,
+-- full => lvl1_fifo_full);
+
+ START_TRIGGER_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => START_TDC_READOUT,
+ pulse => lvl1_trigger_pulse);
+-- lvl1_trigger_pulse <= START_TDC_READOUT;
+
+ DELAY_COUNTER : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => delay_up,
+ CLR => delay_clr,
+ QOUT => delay_qout
+ );
+ DELAY_FSM_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ delay_fsm_currentstate <= IDLE;
+ else
+ delay_fsm_currentstate <= delay_fsm_nextstate;
+ end if;
+ end if;
+ end process DELAY_FSM_CLOCK;
+ -- purpose: delay trigger whitch is sending to TDC
+ TO_DELAY_TRIGG : process (delay_fsm_currentstate,lvl1_trigger_pulse,delay_qout,DELAY_TRIGGER)
+ begin
+ case (delay_fsm_currentstate) is
+ when IDLE =>
+ trigger_register_00_i(1 downto 0) <= "01";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ if lvl1_trigger_pulse = '1' and DELAY_TRIGGER /= x"00" then
+ delay_fsm_nextstate <= DELAY_1;
+ else
+ delay_fsm_nextstate <= IDLE;
+ end if;
+ when DELAY_1 =>
+ trigger_register_00_i(1 downto 0) <= "10";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '0';
+ delay_up <= '1';
+ if delay_qout = DELAY_TRIGGER(7 downto 0) then
+ delay_fsm_nextstate <= DELAY_2;
+ else
+ delay_fsm_nextstate <= DELAY_1;
+ end if;
+ when DELAY_2 =>
+ trigger_register_00_i(1 downto 0) <= "11";
+ lvl1_trigger_pulse_delay <= '1';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ when others =>
+ trigger_register_00_i(1 downto 0) <= "00";
+ lvl1_trigger_pulse_delay <= '0';
+ delay_clr <= '1';
+ delay_up <= '0';
+ delay_fsm_nextstate <= IDLE;
+ end case;
+ end process TO_DELAY_TRIGG;
+ lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
+ LVL1_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_START_fsm_currentstate <= IDLE;
+ lvl1_tdc_trigg_i <= '0';
+ lvl1_fifo_wr_en <= '0';
+ lvl1_fifo_in <= lvl1_buffer_out;
+ lvl1_buffer_rd_en <= '0';
+ lvl1_busy_i <= '0';
+ lvl1_tdc_trigg_i <= '0';
+ else
+ LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate;
+ lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm;
+ lvl1_fifo_wr_en <= lvl1_fifo_wr_en_fsm;
+ lvl1_fifo_in <= lvl1_fifo_in_fsm ;
+ lvl1_buffer_rd_en <= lvl1_buffer_rd_en_fsm;
+ lvl1_busy_i <= lvl1_busy_i_fsm;
+ lvl1_tdc_trigg_i <= lvl1_tdc_trigg_i_fsm;
+ end if;
+ end if;
+ end process LVL1_START;
+
+ TRIGGER_WITHOUT_HADES_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => TRIGGER_WITH_GEN,
+ pulse => trigger_with_gen_pulse);
+ LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate,RECEIVED_TDC_TOKEN, trigger_with_gen_pulse, lvl1_trigger_pulse_start, add_data_counter, lvl1_data_counter, lvl1_or_lvl2_is_busy, how_many_add_data, lvl1_code, lvl1_buffer_empty, trigger_with_gen_en, add_data_i, second_header, first_header, lvl1_buffer_out)
+ begin
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '0';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+
+ case (LVL1_START_fsm_currentstate) is
+ when IDLE =>
+ trigger_register_00_i(5 downto 2) <= x"1";
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_busy_i_fsm <= '0';
+ if (lvl1_trigger_pulse_start = '1'and LVL1_CODE /= x"d") or (TRIGGER_WITH_GEN_EN ='1' and trigger_with_gen_pulse = '1' and lvl1_busy_i = '0' and lvl2_busy_i = '0') then
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
+ else
+ LVL1_START_fsm_nextstate <= IDLE;
+ end if;
+
+ when SEND_LVL1_TRIGG_1 =>
+ trigger_register_00_i(5 downto 2) <= x"2";
+ lvl1_tdc_trigg_i_fsm <= '1'; --start TDC readout
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_2;
+
+ when SEND_LVL1_TRIGG_2 =>
+ trigger_register_00_i(5 downto 2) <= x"3";
+ lvl1_tdc_trigg_i_fsm <= '1';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_3;
+ when SEND_LVL1_TRIGG_3 =>
+ trigger_register_00_i(5 downto 2) <= x"4";
+ lvl1_tdc_trigg_i_fsm <= '1';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_4;
+ when SEND_LVL1_TRIGG_4 =>
+ trigger_register_00_i(5 downto 2) <= x"5";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= WAIT_FOR_TOKEN;
+ when WAIT_FOR_TOKEN =>
+ trigger_register_00_i(5 downto 2) <= x"6";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ if RECEIVED_TDC_TOKEN = '1' then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_1;
+ else
+ LVL1_START_fsm_nextstate <= WAIT_FOR_TOKEN;
+ end if;
+-- when SET_SIGNALS =>
+-- trigger_register_00_i(5 downto 2) <= x"7";
+-- lvl1_tdc_trigg_i_fsm <= '0';
+-- lvl1_fifo_in_fsm <= first_header;
+-- lvl1_fifo_wr_en_fsm <= '1';
+-- lvl1_buffer_rd_en_fsm <= '0';
+-- lvl1_busy_i_fsm <= '1';
+-- LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_1;
+ when SAVE_ADD_DATA_1 =>
+ trigger_register_00_i(5 downto 2) <= x"7";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= first_header;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_2;
+
+ when SAVE_ADD_DATA_2 =>
+ trigger_register_00_i(5 downto 2) <= x"8";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= second_header;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '1';
+ lvl1_busy_i_fsm <= '1';
+ if HOW_MANY_ADD_DATA = x"00" then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3;
+ end if;
+
+ -----------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------
+ when SAVE_ADD_DATA_3 =>
+ trigger_register_00_i(5 downto 2) <= x"9";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_in_fsm <= add_data_i;
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ if add_data_counter = x"0f" then
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_3;
+ end if;
+ when SAVE_ADD_DATA_4 =>
+ trigger_register_00_i(5 downto 2) <= x"a";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '1';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '1';
+ lvl1_busy_i_fsm <= '1';
+-- if lvl1_buffer_empty = '1' then --here !!! correct this !!!
+ if lvl1_data_counter = x"0000" then
+ LVL1_START_fsm_nextstate <= SEND_LVL2_TRIGG;
+ else
+ LVL1_START_fsm_nextstate <= SAVE_ADD_DATA_4;
+ end if;
+ when SEND_LVL2_TRIGG =>
+ trigger_register_00_i(5 downto 2) <= x"c";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+ when others =>
+ trigger_register_00_i(5 downto 2) <= x"d";
+ lvl1_tdc_trigg_i_fsm <= '0';
+ lvl1_fifo_wr_en_fsm <= '0';
+ lvl1_fifo_in_fsm <= lvl1_buffer_out;
+ lvl1_buffer_rd_en_fsm <= '0';
+ lvl1_busy_i_fsm <= '1';
+ lvl1_tdc_trigg_i_fsm <= '0';
+ LVL1_START_fsm_nextstate <= IDLE;
+ end case;
+ end process LVL1_START_FSM_PROC;
+ SAVE_NUMBER_OF_LVL1_WORDS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_data_counter <= (others => '0');
+ elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_2 then
+ lvl1_data_counter <= words_in_event - 3 - HOW_MANY_ADD_DATA;
+ elsif LVL1_START_fsm_currentstate = SAVE_ADD_DATA_4 and lvl1_data_counter > 0 then
+ lvl1_data_counter <= lvl1_data_counter - 1;
+ else
+ lvl1_data_counter <= lvl1_data_counter;
+ end if;
+ end if;
+ end process SAVE_NUMBER_OF_LVL1_WORDS;
+-- not_tdc_clk <= TDC_CLK;
+ TDC_TRIGGER_PULSER : edge_to_pulse
+ port map (
+ clock => TDC_CLK,
+ en_clk => '1',
+ signal_in => lvl1_tdc_trigg_i,
+ pulse => tdc_start_i);
+ TDC_START <= tdc_start_i;--lvl1_tdc_trigg_ff;--tdc_start_i;
+ SEND_TOKEN: process (TDC_CLK, RESET)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' then
+ SEND_TDC_TOKEN <= '0';
+ else
+ SEND_TDC_TOKEN <= tdc_start_i;
+ end if;
+ end if;
+ end process SEND_TOKEN;
+ SAVE_DATA : process (CLK, RESET,lvl1_tdc_trigg_i)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_a_i <= (others => '0');
+ counter_b_i <= (others => '0');
+ counter_c_i <= (others => '0');
+ counter_d_i <= (others => '0');
+ counter_e_i <= (others => '0');
+ counter_f_i <= (others => '0');
+ counter_g_i <= (others => '0');
+ counter_h_i <= (others => '0');
+ elsif lvl1_tdc_trigg_i = '1' then
+ counter_a_i <= COUNTER_a;
+ counter_b_i <= COUNTER_b;
+ counter_c_i <= COUNTER_c;
+ counter_d_i <= COUNTER_d;
+ counter_e_i <= COUNTER_e;
+ counter_f_i <= COUNTER_f;
+ counter_g_i <= COUNTER_g;
+ counter_h_i <= COUNTER_h;
+ end if;
+ end if;
+ end process SAVE_DATA;
+ CHOOSE_DATA : process (CLK, RESET, add_data_counter)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ add_data_i <= x"00000000";
+ else
+ case add_data_counter(3 downto 0) is
+ when "0000" => add_data_i <= counter_a_i;
+ when "0001" => add_data_i <= counter_b_i;
+ when "0010" => add_data_i <= counter_c_i;
+ when "0011" => add_data_i <= counter_d_i;
+ when "0100" => add_data_i <= counter_e_i;
+ when "0101" => add_data_i <= counter_f_i;
+ when "0110" => add_data_i <= counter_g_i;
+ when "0111" => add_data_i <= counter_h_i;
+ when others => add_data_i <= x"deadface";
+ end case;
+ end if;
+ end if;
+ end process CHOOSE_DATA;
+ add_data_pulse <= '1' when SAVE_ADD_DATA_3 = LVL1_START_fsm_nextstate else '0';
+ not_tdc_clk <= TDC_CLK;
+ ADD_DATA_COUNTER_CONTROL : process (CLK,RESET,lvl1_tdc_trigg_i,add_data_pulse)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_tdc_trigg_i = '1' then
+ add_data_counter <= x"1" & HOW_MANY_ADD_DATA(3 downto 0) - 1;
+ elsif add_data_pulse = '1' then
+ add_data_counter <= add_data_counter - 1;
+ end if;
+ end if;
+ end process ADD_DATA_COUNTER_CONTROL;
+ COUNT_WORDS_IN_EVENT : process (TDC_CLK, RESET, tdc_ready, lvl1_tdc_trigg_i)
+ begin
+ if rising_edge(TDC_CLK) then
+ if RESET = '1' or tdc_start_i = '1' then
+ words_in_event <= x"0002" + HOW_MANY_ADD_DATA;
+ elsif tdc_ready = '1' then
+ words_in_event <= words_in_event + 1;
+ end if;
+ end if;
+ end process COUNT_WORDS_IN_EVENT;
+ TRIGGER_COUNTER_PROC : process (CLK, RESET, LVL1_START_fsm_currentstate)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigger_counter <= x"ff";
+ elsif LVL1_START_fsm_currentstate = SEND_LVL1_TRIGG_1 then
+ trigger_counter <= trigger_counter + 1;
+ else
+ trigger_counter <= trigger_counter;
+ end if;
+ end if;
+ end process TRIGGER_COUNTER_PROC;
+ -- words_in_event <= x"0001" + HOW_MANY_ADD_DATA + 2 + lvl1_buffer_counter;
+ lvl1_tag_minus1 <= trigger_counter when TRIGGER_WITH_GEN_EN = '1' else LVL1_TAG - 1;
+ lvl1_code_i <= x"1" when TRIGGER_WITH_GEN_EN = '1'else LVL1_CODE;
+-- first_header <= x"0" & LVL1_CODE & lvl1_tag_minus1 & words_in_event;
+-- second_header <= x"030000" & HOW_MANY_ADD_DATA;
+ first_header <= x"0" & lvl1_code_i & lvl1_tag_minus1 & words_in_event;
+ second_header <= TDC_REGISTER_05(15 downto 8) & x"0000" & HOW_MANY_ADD_DATA;
+ -----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
+ -- LVL2 logic (only CLK domain)
+ -----------------------------------------------------------------------------
+ -----------------------------------------------------------------------------
+ lvl1_fifo_empty_not <= not lvl1_fifo_empty;
+ FIFO_RD_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_fifo_empty_not,
+ pulse => lvl1_fifo_rd_en_empty_pulse);
+ LVL2_START : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_START_fsm_currentstate <= IDLE;
+ lvl1_fifo_rd_en <= '0';
+ tdc_data_valid_i <= '0';
+ else
+ lvl1_fifo_rd_en <= lvl1_fifo_rd_en_fsm;
+ tdc_data_valid_i <= tdc_data_valid_i_fsm;
+ LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate;
+ end if;
+ end if;
+ end process LVL2_START;
+ START_LVL2_FSM: process (LVL2_TRIGGER,LVL2_START_fsm_currentstate, LVL1_START_fsm_currentstate, how_many_words_in_event, lvl1_fifo_out, etrax_is_ready_to_read, lvl1_fifo_rd_en_empty_pulse)
+ begin
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "000";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= IDLE;
+ case (LVL2_START_fsm_currentstate) is
+ when IDLE =>
+ lvl2_busy_i <= '0';
+ lvl2_debug (2 downto 0) <= "001";
+ lvl1_fifo_rd_en_fsm <= '0';--lvl1_fifo_rd_en_empty_pulse;--'0';
+ tdc_data_valid_i_fsm <= '0';
+-- if LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG then
+ if LVL2_TRIGGER = '1' or (TRIGGER_WITH_GEN_EN ='1' and LVL1_START_fsm_currentstate = SEND_LVL2_TRIGG ) then
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ else
+ LVL2_START_fsm_nextstate <= IDLE;
+ end if;
+ when READOUT_WORD1 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "010";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ if lvl1_fifo_out(31 downto 24) /= x"01" then
+-- if lvl1_fifo_out(31 downto 28) = x"0" then
+ LVL2_START_fsm_nextstate <= READOUT_WORD2;
+ else
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ end if;
+
+ when READOUT_WORD2 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "011";
+ lvl1_fifo_rd_en_fsm <= '1';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= READOUT_WORD3;
+
+ when READOUT_WORD3 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "011";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ if lvl1_fifo_out(31 downto 24) /= x"01" then
+ LVL2_START_fsm_nextstate <= READOUT_WORD2;
+ else
+ LVL2_START_fsm_nextstate <= SAVE_EVENT_SIZE;
+ end if;
+
+ when SAVE_EVENT_SIZE =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "100";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '0';
+ LVL2_START_fsm_nextstate <= SEND_DATA1;
+
+ when SEND_DATA1 =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "101";
+ lvl1_fifo_rd_en_fsm <= ETRAX_IS_READY_TO_READ;
+ tdc_data_valid_i_fsm <= '1';
+-- if how_many_words_in_event(15 downto 0) = x"0000" then
+ if how_many_words_in_event(15 downto 0) = x"0000" then
+ LVL2_START_fsm_nextstate <= IDLE;
+ else
+ LVL2_START_fsm_nextstate <= SEND_DATA1;
+ end if;
+ when LAST_WORD =>
+ lvl2_busy_i <= '1';
+ lvl2_debug (2 downto 0) <= "110";
+ lvl1_fifo_rd_en_fsm <= '0';
+ tdc_data_valid_i_fsm <= '1';
+ if ETRAX_IS_READY_TO_READ = '1' then
+ LVL2_START_fsm_nextstate <= IDLE;
+ else
+ LVL2_START_fsm_nextstate <= LAST_WORD;
+ end if;
+
+ when others =>
+ lvl2_busy_i <= '1';
+ LVL2_START_fsm_nextstate <= IDLE;
+ end case;
+ end process START_LVL2_FSM;
+ COUNT_DOWN_READOUT: process (CLK, RESET,how_many_words_in_event)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ how_many_words_in_event <= (others => '0');
+ elsif LVL2_START_fsm_currentstate = SAVE_EVENT_SIZE then
+ how_many_words_in_event <= '1' & lvl1_fifo_out(15 downto 0);
+ elsif how_many_words_in_event > x"0ffff" and ETRAX_IS_READY_TO_READ = '1' then -- or READ_ADRESS_END_UP='1')then
+ how_many_words_in_event <= how_many_words_in_event - 1;
+ end if;
+ end if;
+ end process COUNT_DOWN_READOUT;
+-- SYNCH_DATA_VALID: process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then --correct this !!!!!!!!!!!!!!!!(falling?)
+-- if RESET = '1' then
+-- TDC_DATA_VALID <= '0';
+-- else
+-- TDC_DATA_VALID <= tdc_data_valid_i;
+-- end if;
+-- end if;
+-- end process SYNCH_DATA_VALID;
+ TDC_DATA_VALID <= tdc_data_valid_i_fsm;
+ not_tdc_data_valid_i <= not tdc_data_valid_i;
+ LVL2_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_tdc_data_valid_i,
+ pulse => lvl2_busy_end_pulse);
+-- LVL2_BUSY_SET: process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' or lvl2_busy_end_pulse = '1'then
+-- lvl2_busy_i <= '0';
+-- elsif LVL2_START_fsm_currentstate /= IDLE then
+-- lvl2_busy_i <= '1';
+-- end if;
+-- end if;
+-- end process LVL2_BUSY_SET;
+ LVL2_BUSY_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_busy_i,
+ pulse => lvl2_busy_start_pulse);
+
+ --set
+ --to
+ --max
+ --value
+ --!!!!!!! and cut data funktion should
+ --be implemented - with busy or max
+ --size or last event ? or both
+ LVL1_OR_LVL2_BUSY: process (CLK, RESET, lvl1_busy_i, lvl2_busy_end_pulse)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_or_lvl2_is_busy <= '0';
+ elsif lvl1_busy_i = '1' then
+ lvl1_or_lvl2_is_busy <= '1';
+ elsif lvl2_busy_end_pulse = '1' then
+ lvl1_or_lvl2_is_busy <= '0';
+ end if;
+ end if;
+ end process LVL1_OR_LVL2_BUSY;
+
+ LVL2_BUSY <= lvl2_busy_i;
+ TDC_READOUT_COMPLETED <= lvl2_busy_end_pulse;
+ -----------------------------------------------------------------------------
+ -- end writing to fifo when TDC_LVL1_BUSY and read all data and send finish signal
+ -----------------------------------------------------------------------------
+ TEST_COUNTER_a : simpleupcounter_8bit
+ port map (
+ CLK => TDC_CLK,
+ UP => tdc_start_i,
+ CLR => RESET,
+ QOUT => test_counter_0
+ );
+ TEST_COUNTER_b : simpleupcounter_8bit
+ port map (
+ CLK => TDC_CLK,
+ UP => RECEIVED_TDC_TOKEN,
+ CLR => RESET,
+ QOUT => test_counter_1
+ );
+ TEST_COUNTER_c : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => lvl2_busy_start_pulse,--lvl2_trigger_pulse,
+ CLR => RESET,
+ QOUT => test_counter_2
+ );
+ TEST_COUNTER_d : simpleupcounter_8bit
+ port map (
+ CLK => CLK,
+ UP => lvl2_busy_end_pulse,
+ CLR => RESET,
+ QOUT => test_counter_3
+ );
+ SET_BUFFER_BUSY: process (CLK, RESET)
+ begin -- process SET_BUFFER_BUSY
+ if rising_edge(CLK) then
+ if RESET = '1' or (test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1') then --or test_counter_3 = test_counter_1 then -- asynchronous reset (active low)
+ lvl1_fifo_busy_counter <= (others => '0');
+ elsif lvl1_fifo_rd_en = '1' and lvl1_fifo_wr_en = '0' and lvl1_fifo_busy_counter > 0 then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter -1;
+ elsif lvl1_fifo_rd_en = '0' and lvl1_fifo_wr_en = '1' then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter +1;
+ elsif lvl1_fifo_rd_en = '1' and lvl1_fifo_wr_en = '1' then
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
+ else
+ lvl1_fifo_busy_counter <= lvl1_fifo_busy_counter;
+ end if;
+ end if;
+ end process SET_BUFFER_BUSY;
+ fifo_reset_err_i <= '1' when test_counter_3 = test_counter_1 and lvl1_memory_busy_i = '1' else '0';
+ -- lvl1_memory_busy_i <= '1' when lvl1_fifo_counter(13) = '1' else '0';
+ lvl1_memory_busy_i <= '1' when lvl1_fifo_busy_counter(13) = '1' and lvl1_fifo_busy_counter(12) = '1'else '0';
+ REGITERING_SIGNALS: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then -- rising clock edge
+ if RESET = '1' then
+ LVL1_BUSY <= '0';
+ else
+ LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i; --here
+ end if;
+ end if;
+ end process REGITERING_SIGNALS;
+end tdc_interface;
+
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 18/04/2007
+-- Description: it reads out data, first I save the first part of the data and
+-- then the second.
+--
+--
+--This code has not optimized yet.
+--
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity tdc_readout is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ A_ADD_IN : in std_logic_vector(8 downto 0); --address/data line
+-- A_ADS_0 : in std_logic; --Motherboard address
+-- A_ADS_1 : in std_logic; --Motherboard address
+-- A_ADS_2 : in std_logic; --Motherboard address
+ A_AOD_IN : in std_logic; --address or data
+-- A_ACK_IN : in std_logic; --acknowledgment
+ A_DST_IN : in std_logic; --data strobe
+ A_RESERV_IN : in std_logic;
+
+ TOKEN_IN : in std_logic_vector(3 downto 0);
+ TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0);
+ FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0);
+
+ DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(18 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ FULL_FIFO_IN : in std_logic;
+ INIT_TDC_READOUT_IN : in std_logic; --from common stop generator
+ DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
+end tdc_readout;
+
+architecture behavioral of tdc_readout is
+
+type state_type is (idle_state,
+ save_H_word_state, save_H_word_state_next,
+ save_L_word_state,save_L_word_state_next,
+ wait_1_state,wait_2_state,wait_3_state, wait_4_state,
+ send_data,send_data_next, send_data_with_valid,
+
+ send_data_with_valid_next, send_data_no_valid,
+ fifo_full_state,
+
+ send_token_state_1, send_token_state_2,
+ send_token_state_3, send_token_state_4);
+
+signal current_state, next_state : state_type;
+signal reg_debug_register, next_debug_register : std_logic_vector(3 downto 0);
+signal reg_data_bus_out, next_data_bus_out : std_logic_vector(35 downto 0);--(18 downto 0);
+signal reg_data_valid_out, next_data_valid_out : std_logic;
+signal saved_data : std_logic_vector(35 downto 0);--(25 downto 0);--(23 downto 0);--(18 downto 0);
+signal reg_token_tdc_readout_i, next_token_tdc_readout_i : std_logic_vector(3 downto 0);
+signal pulse_init_tdc_readout : std_logic;
+
+ component edge_to_pulse
+ port (
+ CLOCK : in std_logic;
+ ENABLE_CLK_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+ end component;
+
+begin -- behavioral
+
+ u1: edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN =>'1',
+ SIGNAL_IN => INIT_TDC_READOUT_IN,
+ PULSE_OUT => pulse_init_tdc_readout);
+
+ REGISTER_OUTPUT : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_data_bus_out <= (others => '0');
+ reg_data_valid_out <= '0';
+ --reg_token_out_to_trb <= '0';
+ reg_token_tdc_readout_i <= (others => '0');
+ reg_debug_register <= (others => '0');
+ else
+ current_state <= next_state;
+ reg_debug_register <= next_debug_register;
+ reg_data_bus_out <= next_data_bus_out;
+ reg_data_valid_out <= next_data_valid_out;
+ -- reg_token_out_to_trb <= next_token_out_to_trb;
+ reg_token_tdc_readout_i <= next_token_tdc_readout_i;
+ end if;
+ end if;
+ end process REGISTER_OUTPUT;
+
+--DATA_BUS_OUT(9) <= '0';
+--saved_data(9) <= '0';
+ DATA_VALID_OUT <= reg_data_valid_out;
+ DATA_BUS_OUT <= saved_data;
+-- A_DRE <= reg_a_dre;
+--TOKEN_OUT_TO_TRB <= reg_token_out_to_trb;
+ TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i;
+ DEBUG_REGISTER_OUT <= reg_debug_register;
+------------------------------------------------------------------------------
+-- purpose: state machine. get TDC data and build a std_logic_vector
+-------------------------------------------------------------------------------
+ process(current_state, TOKEN_IN, INIT_TDC_READOUT_IN,
+ A_DST_IN, A_AOD_IN, FULL_FIFO_IN)
+
+ begin
+
+ next_data_valid_out <= '0';
+ next_data_bus_out <= (others => '0');
+ --next_token_out_to_trb <= '0';
+ next_debug_register <= (others => '0');
+ --next_a_dre <= '0';
+ --up_counter_12bit_i <= '0';
+ next_token_tdc_readout_i <= (others => '0');
+
+ case current_state is
+
+ when idle_state =>
+ next_debug_register <= "0000";
+ if INIT_TDC_READOUT_IN = '1' then
+ next_state <= save_L_word_state;
+ --next_a_dre <= '1';
+ else
+ next_state <= idle_state;
+ end if;
+-------------------------------------------------------------------------------
+-- If (A_DST = '1' and A_AOD_IN = '1') means one dataword is coming, if so it
+-- goes on and saves the lower part and then the higher data part. Every time I
+-- save a full dataword and I wait for token.
+-- It can happen:
+-- 1) no data is coming and the token is back. In this case I send no token
+-- return and nothing goes to fifo.
+-- 2) few data is coming and the token does not come back.
+--
+-- token back: TOKEN_IN = x"1"
+-- token NOT back: TOKEN_IN = x"2"
+-------------------------------------------------------------------------------
+ when save_L_word_state =>
+ next_debug_register <= "0001";
+ --next_a_dre <= '1';
+ if A_DST_IN = '1' and A_AOD_IN = '1' then
+ --next_state <= wait_1_state;
+ next_state <= save_L_word_state_next;
+ elsif TOKEN_IN = x"1" then --token and NO data
+ next_state <= send_token_state_2;
+ elsif TOKEN_IN = x"2" then --NO token and NO data
+ next_state <= send_token_state_3;
+ else
+ next_state <= save_L_word_state;
+ end if;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- when wait_1_state =>
+-- next_state <= wait_2_state;
+
+-- when wait_2_state =>
+-- next_state <= save_L_word_state_next;
+
+ when save_L_word_state_next => --here I save data
+ next_state <= save_H_word_state;
+
+ when save_H_word_state =>
+ next_debug_register <= "0011";
+ if A_DST_IN = '1' and A_AOD_IN = '0' then
+ --next_state <= wait_3_state;
+ next_state <= save_H_word_state_next;
+ else
+ next_state <= save_H_word_state;
+ end if;
+
+-- when wait_3_state =>
+-- next_state <= wait_4_state;
+
+-- when wait_4_state =>
+-- next_state <= save_H_word_state_next;
+
+ when save_H_word_state_next => --here I save data
+ next_data_valid_out <= '1';
+ next_state <= send_data_with_valid;
+
+-------------------------------------------------------------------------------
+-- here I send the data to the FIFO
+-- DATA_VALID_OUT is the write enable signal to fifo
+-- DATA_VALID_OUT <= '1' data is written into FIFO
+-- DATA_VALID_OUT <= '0' data is NOT written into FIFO
+-- I assert DATA_VALID_OUT <= '1', after 1 clk cycle the data on the bus is
+-- written into the FIFO
+-------------------------------------------------------------------------------
+ when send_data_with_valid =>
+ next_debug_register <= "0101";
+ -- next_a_dre <= '1';
+ next_data_valid_out <= '0'; --connected to WRITE_FIFO
+ next_state <= send_data_with_valid_next;
+-- if FULL_FIFO_IN = '1' then --not full
+-- next_state <= send_data_with_valid_next;
+-- else
+-- next_state <= fifo_full_state;
+-- end if;
+
+ when send_data_with_valid_next =>
+ next_debug_register <= "0111";
+ --next_a_dre <= '1';
+ next_data_valid_out <= '0'; --'0'; --only here I write the fifo!
+ next_state <= send_data_no_valid;
+
+ when send_data_no_valid =>
+ next_debug_register <= "1000";
+ --next_a_dre <= '1';
+ next_data_valid_out <= '0'; --connected to WRITE_FIFO
+ if (A_AOD_IN = '1' and TOKEN_IN = x"0") then
+ next_state <= save_L_word_state;
+
+ elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then
+ next_state <= send_token_state_1; --token and data
+
+ elsif (A_AOD_IN = '0' and TOKEN_IN = x"2") then --NO token back and data in fifo
+ next_state <= send_token_state_4; -- NO token and data
+ else
+ next_state <= send_data_no_valid;
+ end if;
+
+-------------------------------------------------------------------------------
+-- token + data => => => => OK
+-------------------------------------------------------------------------------
+ when send_token_state_1 =>
+ next_debug_register <= "1001";
+ -- next_a_dre <= '1';
+ next_token_tdc_readout_i <= x"1";
+ next_state <= idle_state;
+-------------------------------------------------------------------------------
+-- token + NO data => => => => OK
+-------------------------------------------------------------------------------
+ when send_token_state_2 =>
+ next_debug_register <= "1011";
+ -- next_a_dre <= '1';
+ next_token_tdc_readout_i <= x"3";
+ next_state <= idle_state;
+-------------------------------------------------------------------------------
+-- NO token + NO data
+-------------------------------------------------------------------------------
+ when send_token_state_3 =>
+ next_debug_register <= "1100";
+ -- next_a_dre <= '1';
+ next_token_tdc_readout_i <= x"4";
+ next_state <= idle_state;
+-------------------------------------------------------------------------------
+-- NO token + data
+-------------------------------------------------------------------------------
+ when send_token_state_4 =>
+ next_debug_register <= "1100";
+ -- next_a_dre <= '1';
+ next_token_tdc_readout_i <= x"5";
+ next_state <= idle_state;
+
+
+-- when send_data_no_valid =>
+-- next_debug_register <= "1000";
+-- next_a_dre <= '1';
+-- next_data_valid_out <= '0'; --connected to WRITE_FIFO
+-- if A_AOD_IN = '1' and TOKEN_IN = '0' then
+-- next_state <= save_L_word_state;
+-- elsif A_AOD_IN = '0' and TOKEN_IN = '1' then
+-- next_state <= idle_state;
+-- elsif STOP_READOUT_IN = '1' then --means token not back
+-- next_state <= idle_state;
+-- else
+-- next_state <= send_data_no_valid;
+-- end if;
+
+ when fifo_full_state =>
+ next_debug_register <= "1100";
+ -- next_a_dre <= '1';
+ next_data_valid_out <= '0';
+ -- next_token_out_to_trb <= '0';
+--I stay here if there is no space in the fifo
+ if FULL_FIFO_IN = '1' then --cannot write anymore in fifo
+ next_state <= fifo_full_state;
+ else
+ next_state <= idle_state;
+ end if;
+
+ when others =>
+ next_state <= idle_state;
+
+ end case;
+ end process;
+
+------------------------------------------------------------------------------
+-- process: it gets the token from entity "send_token",
+-- it is back I send to TRB
+------------------------------------------------------------------------------
+ save_data: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_data <= (others => '0');
+ -- reg_flag_event_counter <= (others => '0');
+ elsif next_state = save_H_word_state_next then
+ saved_data(35 downto 32) <= FLAG_EVENT_COUNTER_IN;
+ saved_data(31 downto 26) <= "00" & x"0";
+ saved_data(25 downto 23) <= '0' & "00";--mb_number;
+ saved_data(22 downto 19) <= x"0";--reg_bus_number;--x"1";
+ saved_data(18 downto 12) <= A_ADD_IN(8 downto 2);
+ saved_data(11) <= A_RESERV_IN; --11th bit is reserv!
+ saved_data(10 downto 9) <= A_ADD_IN(1 downto 0);
+ saved_data(8 downto 0) <= saved_data(8 downto 0);
+ elsif next_state = save_L_word_state_next then
+ saved_data(18 downto 9) <= saved_data(18 downto 9);
+ saved_data(8 downto 0) <= A_ADD_IN(8 downto 0);
+ else
+ saved_data <= saved_data;
+ end if;
+ end if;
+ end process save_data;
+
+-------------------------------------------------------------------------------
+-- I mark the event using dataword 4-bit saved_data(35 downto 32)
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- reg_flag_event_counter <= (others => '0');
+-- else
+-- reg_flag_event_counter <= FLAG_EVENT_COUNTER_IN;
+-- end if;
+-- end if;
+-- end process;
+-------------------------------------------------------------------------------
+-- I count the ACK signals to see when the transfer for each MB is finished.
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1' or TOKEN_IN = x"1" or
+-- current_state = idle_state or
+-- counter_12bit_i = x"000" or
+-- counter_12bit_i = x"001" or
+-- counter_12bit_i = x"002") then
+-- mb_counter <= (others => '0');
+-- elsif pulse_a_ack = '1' then
+-- mb_counter <= mb_counter + 1;
+-- else
+-- mb_counter <= mb_counter;
+-- end if;
+-- end if;
+-- end process;
+-- clear_counter_12bit_i <= '1' when (current_state = idle_state) else '0';
+
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- mb_number_temp <= (others => '0');
+-- elsif mb_counter = "00" then
+-- mb_number_temp <= "00";
+-- elsif mb_counter = "01" then
+-- mb_number_temp <= "01";
+-- else
+-- mb_number_temp <= mb_number_temp;
+-- end if;
+-- end if;
+-- end process;
+-- mb_number <= mb_number_temp;
+-------------------------------------------------------------------------------
+-- I register the bus number which I put in the dataword
+-----------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (RESET = '1') then
+-- reg_bus_number <= (others => '0');
+-- else
+-- reg_bus_number <= BUS_NUMBER_IN;
+-- end if;
+-- end if;
+-- end process;
+
+
+
+end behavioral;
+
+
+
+
+
+
+
+
+
--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 18/08/2007
+-- Description: it it the top level design of:
+--1) fifo_0
+--2) tdc_readout: it builds the dataword
+--
+--This code has not optimized yet.
+--13/02/2009 I start adapting following TRBNET standards
+
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-------------------------------------------------------------------------------
+--fifo_0 contain maximum 600 dataword. MB sends 1 dataword in 100ns, so I wait
+--the token for maximum 1usec (safety time => at the moment)
+-------------------------------------------------------------------------------
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity tdc_readout_and_trb_interface is
+ -- generic (width : integer := 16;
+ -- bus_number: std_logic_vector(3 downto 0));-- if 5 and clk 100MHz the state remain active 320 ns
+ port ( -- if width 15 => 330 usec:
+ -- I send the token if I do not see it after
+ -- 330 us => BEEF
+ -- if width 16 => 855 usec between token
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+-------------------------------------------------------------------------------
+-- tdc_readout
+-------------------------------------------------------------------------------
+ A_ADD : in std_logic_vector(8 downto 0);
+ A_RESERV : in std_logic; --this is 11 bit of dataword
+ A_AOD : in std_logic; --address or data
+ A_ACK : in std_logic;
+ A_DST : in std_logic;
+ -- A_RDO : in std_logic;
+ A_DRE : out std_logic;
+ TOKEN_IN : in std_logic_vector(3 downto 0);
+ INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0);
+
+-------------------------------------------------------------------------------
+-- tdc_readout_and_trb_interface
+-------------------------------------------------------------------------------
+ BUS_NUMBER_IN : in std_logic_vector(3 downto 0);
+ -- INIT_TRB_INTERFACE_IN : in std_logic;
+ TOKEN_TO_TRB_OUT : out std_logic;
+ REINIT_ROC1_IN : in std_logic;
+ REINIT_ROC1_OUT : out std_logic;
+ SUCCESFUL_REINIT_ROC1 : in std_logic;
+ STOP_READOUT_IN : in std_logic;
+ -- DATA_BUS_TO_TRB_OUT : out std_logic_vector(25 downto 0);--(18 downto 0);
+ -- DATA_VALID_TO_TRB_OUT : out std_logic;
+ DEBUG_REGISTER_0 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_1 : out std_logic_vector(7 downto 0);
+ DEBUG_REGISTER_2 : out std_logic_vector(7 downto 0);
+
+-------------------------------------------------------------------------------
+-- CONNECTION TO TRBNET END POINT INTERFACE
+-------------------------------------------------------------------------------
+-- ACKNOWLEDGE_TRB_INTERFACE_IN : in std_logic_vector(3 downto 0);
+-- INIT_TRB_INTERFACE_OUT : out std_logic;
+-- DATA_OUT : out std_logic_vector(25 downto 0);--(18 downto 0);
+-- READ_FIFO_IN : in std_logic;
+-- DEBUG_REGISTER_TRB_INTERFACE : in std_logic_vector(3 downto 0);
+-- -------------------------------------------------------------------------------
+-- -
+-------------------------------------------------------------------------------
+ -- LVL1 trigger APL
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_RECEIVED_IN : in std_logic;
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0);
+ LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000";
+ LVL1_TRG_RELEASE_OUT : out std_logic := '0';
+
+ --Data Port
+ IPU_NUMBER_IN : in std_logic_vector (15 downto 0);
+ IPU_INFORMATION_IN : in std_logic_vector (7 downto 0);
+ --start strobe
+ IPU_START_READOUT_IN: in std_logic;
+ --detector data, equipped with DHDR
+ IPU_DATA_OUT : out std_logic_vector (31 downto 0);
+ IPU_DATAREADY_OUT : out std_logic;
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_OUT : out std_logic;
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_READ_IN : in std_logic;
+ IPU_LENGTH_OUT : out std_logic_vector (15 downto 0);
+ IPU_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0));
+
+end tdc_readout_and_trb_interface;
+
+architecture behavioral of tdc_readout_and_trb_interface is
+----------------------------------------------------------------------
+-- FSM_HEADER
+----------------------------------------------------------------------
+
+ type state_type is (idle_state, wait_for_token, send_first_header_state,
+ send_second_header_state, send_data_state,
+ send_data_1_state, dummy_wait_1_header_state,busy_header_state);
+
+ signal current_state, next_state : state_type;
+
+----------------------------------------------------------------------
+-- FSM_FIFO_MULTIPLEXER
+----------------------------------------------------------------------
+ type state_type_fsm_multiplexer is (idle_state_fsm_multiplexer,
+ wait_for_complete_event_fsm_multiplexer,
+ send_first_and_second_header_state_fsm_multiplexer,
+
+ send_data_state_fsm_multiplexer,
+ end_of_event_transfer_fsm_multiplexer,
+ dummy_wait_1_fsm_multiplexer,
+ dummy_wait_2_fsm_multiplexer,
+ dummy_wait_3_fsm_multiplexer);
+
+ signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer;
+
+ signal buffer_write_enable_i, reg_buffer_write_enable_i : std_logic;
+ -- signal reg_buffer_read_enable_i, next_buffer_read_enable_i : std_logic;
+ signal buffer_data_in_i, reg_buffer_data_in_i , buffer_data_in_i_32: std_logic_vector(31 downto 0);
+
+ signal buffer_data_out_i : std_logic_vector(31 downto 0);
+
+ signal reg_fifo_data_in_i, next_fifo_data_in_i, fifo_data_in_i : std_logic_vector(31 downto 0);
+ signal reg_fifo_data_out_i, fifo_data_out_i : std_logic_vector(31 downto 0);
+ signal reg_fifo_write_enable_i, next_fifo_write_enable_i : std_logic;
+-- signal reg_fifo_read_enable_i, fifo_read_enable_i : std_logic;
+ signal reg_lvl1_busy_i, next_lvl1_busy_i : std_logic;
+ signal init_tdc_readout_i : std_logic_vector(3 downto 0);
+
+ signal reg_debug_register_i, next_debug_register_i : std_logic_vector(7 downto 0);
+ signal words_in_event : std_logic_vector(15 downto 0):=(others => '0');
+ signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0');
+ signal pulse_a_aod_i : std_logic;
+ signal debug_register_tdc_readout_i : std_logic_vector(3 downto 0);
+ signal reg_trigger_type : std_logic_vector(3 downto 0);
+ signal token_tdc_readout_i : std_logic_vector(3 downto 0);
+ signal first_header : std_logic_vector(51 downto 0):=(others => '0');
+ --signal second_header : std_logic_vector(35 downto 0):=(others => '0');
+ signal reg_token_in : std_logic_vector(3 downto 0);
+ signal data_tdc_readout_i : std_logic_vector(35 downto 0);
+ signal write_fee_data_fifo_i : std_logic;
+ signal reg_LVL1_TRG_TYPE_IN : std_logic_vector(3 downto 0);
+ signal reg_LVL1_TRG_INFORMATION_IN : std_logic_vector(7 downto 0);
+ signal reg_LVL1_TRG_NUMBER_IN : std_logic_vector(15 downto 0);
+ signal flag_event_counter : std_logic_vector(3 downto 0);
+ signal pulse_init_tdc_readout : std_logic;
+
+ signal next_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
+ signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0);
+ signal fee_data_fifo_out_i : std_logic_vector(35 downto 0);
+ signal header_data_fifo_out_i : std_logic_vector(51 downto 0);
+ signal next_data_to_trb_net : std_logic_vector(35 downto 0);
+ signal data_header_fifo_in_i : std_logic_vector(51 downto 0);
+ signal reg_debug_register_fsm_header, next_debug_register_fsm_header : std_logic_vector(7 downto 0);
+ signal write_header_fifo_i, next_write_header_fifo_i : std_logic;
+ signal reg_read_fee_data_fifo_i,next_read_fee_data_fifo_i, next_read_header_fifo_i, reg_read_header_fifo_i : std_logic;
+
+ signal word_count_fee_data_fifo : std_logic_vector(13 downto 0);
+ signal word_count_header_fifo : std_logic_vector(9 downto 0);
+ signal reg_lvl1_trg_received, pulse_ipu_start_readout, reg_ipu_read : std_logic;
+
+ signal reg_lvl1_trg_type : std_logic_vector(3 downto 0);
+ signal reg_lvl1_trg_code : std_logic_vector(7 downto 0);
+ signal reg_lvl1_trg_information, reg_ipu_information : std_logic_vector(7 downto 0);
+ signal reg_ipu_number : std_logic_vector (15 downto 0);
+
+ --signal reg_error_pattern : std_logic_vector (31 downto 0);
+ signal reg_lvl1_error_pattern, next_lvl1_error_pattern : std_logic_vector (31 downto 0);
+ signal reg_lvl1_trg_release, next_lvl1_trg_release : std_logic;
+ signal reg_ipu_data, next_ipu_data : std_logic_vector (31 downto 0);
+ signal reg_ipu_data_ready, next_ipu_data_ready : std_logic;
+ signal reg_ipu_finished, next_ipu_finished : std_logic;
+ --signal reg_ipu_length, next_ipu_length : std_logic_vector (15 downto 0);
+ signal how_many_complete_event_in_fifo_counter : std_logic_vector (31 downto 0);
+ signal pulse_reg_lvl1_trg_received : std_logic;
+ -- signal reg_ipu_read : std_logic;
+-- signal reg_lvl1_trg_type : std_logic_vector(3 downto 0);
+-- signal reg_lvl1_trg_received : std_logic;
+ signal reg_lvl1_trg_number : std_logic_vector(15 downto 0);
+ signal read_header_fifo,read_fee_data_fifo : std_logic;
+ signal counter_word_read_from_trbnet : std_logic_vector(3 downto 0);
+ signal clear_counter_word_read_from_trbnet : std_logic;
+ signal reg_flag_in_header : std_logic_vector(3 downto 0);
+ signal push_read_fee_data_i,push_read_header_data_i : std_logic;
+ signal empty_flag_fee_data_fifo_i, empty_flag_header_data_fifo_i : std_logic;
+ signal pulse_write_header_fifo_i, pulse_write_fee_data_fifo_i : std_logic;
+ signal counter_pulse_write_header_fifo_i, counter_pulse_write_fee_data_fifo_i : std_logic_vector(15 downto 0);
+ signal counter_token_back : std_logic_vector(31 downto 0);
+ signal full_flag_fee_data_fifo_i,almost_empty_flag_fee_data_fifo_i,almost_full_flag_fee_data_fifo_i : std_logic;
+ signal full_flag_header_data_fifo_i,almost_empty_flag_header_data_fifo_i,almost_full_flag_header_data_fifo_i : std_logic;
+-- signal reg_lvl1_trg_code,reg_lvl1_trg_information : std_logic_vector(7 downto 0);
+-- signal reg_ipu_number : std_logic_vector (15 downto 0);
+-- signal reg_ipu_information : std_logic_vector (7 downto 0);
+-- signal reg_ipu_start_readout : std_logic;
+ ------------------------------------------------------------------------------
+-- COUNTERs
+-------------------------------------------------------------------------------
+ component counter_4bit
+ port (
+ QOUT : out std_logic_vector(3 downto 0);
+ UP : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLR : in std_logic);
+ end component;
+
+-------------------------------------------------------------------------------
+-- Make a pulse from pulse
+-------------------------------------------------------------------------------
+ component edge_to_pulse
+ port (
+ CLOCK : in std_logic;
+ ENABLE_CLK_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+ end component;
+
+---------------------------------------------------------------------------
+--tdc_readout
+---------------------------------------------------------------------------
+ component tdc_readout
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+
+ A_ADD_IN : in std_logic_vector(8 downto 0);
+ A_RESERV_IN : in std_logic; --this is 11 bit of dataword
+ A_AOD_IN : in std_logic; --address or data
+ -- A_ACK_IN : in std_logic; --acknowledgment
+ A_DST_IN : in std_logic;
+
+ TOKEN_IN : in std_logic_vector(3 downto 0);
+ TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0);
+ FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0);
+ DATA_BUS_OUT : out std_logic_vector(35 downto 0);--(25 downto 0);--(23 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ FULL_FIFO_IN : in std_logic;
+ INIT_TDC_READOUT_IN : in std_logic;
+ DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0));
+ end component;
+
+-- component fifo_fall_through_2048depth_36width
+-- port (
+-- Data : in std_logic_vector(35 downto 0);
+-- Clock : in std_logic;
+-- WrEn : in std_logic;
+-- RdEn : in std_logic;
+-- Reset : in std_logic;
+-- Q : out std_logic_vector(35 downto 0);
+-- WCNT : out std_logic_vector(11 downto 0);
+-- Empty : out std_logic;
+-- Full : out std_logic;
+-- AlmostEmpty : out std_logic;
+-- AlmostFull : out std_logic);
+-- end component;
+
+ component fifo_8192depth_36width_dual_thresh
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ AmEmptyThresh : in std_logic_vector(12 downto 0);
+ AmFullThresh : in std_logic_vector(12 downto 0);
+ Q : out std_logic_vector(35 downto 0);
+ WCNT : out std_logic_vector(13 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component fifo_fall_through_512depth_52width
+ port (
+ Data : in std_logic_vector(51 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(51 downto 0);
+ WCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+begin -- behavioral
+-- u0: counter_4bit
+-- port map (
+-- QOUT => counter_4bit_i,
+-- UP => up_counter_4bit_i,
+-- CLK => CLK,
+-- RESET => RESET,
+-- CLR => clear_counter_4bit_i);
+
+ A_ADO_PULSE: edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN =>'1',
+ SIGNAL_IN => A_AOD,
+ PULSE_OUT => pulse_a_aod_i);
+
+ INIT_TDC_READOUT_IN_0_PULSE : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => INIT_TDC_READOUT_IN(0),
+ PULSE_OUT => pulse_init_tdc_readout);
+
+ TRIGGER_RECEIVED_PULSE : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => reg_lvl1_trg_received,
+ PULSE_OUT => pulse_reg_lvl1_trg_received);
+
+ IPU_START_READOUT_IN_PULSE : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => IPU_START_READOUT_IN,
+ PULSE_OUT => pulse_ipu_start_readout);
+
+ PUSH_FIRST_HEADER_DATA_OUT : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => write_header_fifo_i,
+ PULSE_OUT => pulse_write_header_fifo_i);
+
+ PUSH_FIRST_FEE_DATA_OUT : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => write_fee_data_fifo_i,
+ PULSE_OUT => pulse_write_fee_data_fifo_i);
+
+-- READ_HEADER_FI0 : edge_to_pulse
+-- port map (
+-- CLOCK => CLK,
+-- ENABLE_CLK_IN => '1',
+-- SIGNAL_IN => read_header_fifo,
+-- PULSE_OUT => pulse_read_header_fifo);
+
+ TDC_READOUT_INTERFACE : tdc_readout
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+
+ A_ADD_IN => A_ADD,
+ A_RESERV_IN => A_RESERV,
+ A_AOD_IN => A_AOD,
+ -- A_ACK_IN => A_ACK,
+ A_DST_IN => A_DST,
+
+ TOKEN_IN => reg_token_in, --here from tld
+ TOKEN_TDC_READOUT_OUT => token_tdc_readout_i,
+ FLAG_EVENT_COUNTER_IN => flag_event_counter,
+
+ DATA_VALID_OUT => write_fee_data_fifo_i,
+ DATA_BUS_OUT => data_tdc_readout_i,
+ INIT_TDC_READOUT_IN => INIT_TDC_READOUT_IN(0),
+ FULL_FIFO_IN => '0',
+ DEBUG_REGISTER_OUT => debug_register_tdc_readout_i);
+-------------------------------------------------------------------------------
+-- OENP point test token back
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- => => . DEVI DECIDERE COME FARE LA CONNESSIONE DEL TOKEN TRA ENETITY <= <=
+-------------------------------------------------------------------------------
+ TOKEN_TO_TRB_OUT <= reg_token_in(0);
+-- TOKEN_TO_TRB_OUT <= '1' when (token_tdc_readout_i = x"1" or
+-- token_tdc_readout_i = x"2" or
+-- token_tdc_readout_i = x"3" or
+-- token_tdc_readout_i = x"4" or
+-- token_tdc_readout_i = x"5") else '0';
+
+--extimated 20 normal evt and 1 cal
+
+-- FEE_DATA_FIFO : fifo_fall_through_2048depth_36width
+-- port map (
+-- Data => data_tdc_readout_i,
+-- Clock => CLK,
+-- WrEn => write_fee_data_fifo_i,
+-- RdEn => read_fee_data_fifo,--reg_read_fee_data_fifo_i,
+-- Reset => RESET,
+-- Q => fee_data_fifo_out_i,
+-- WCNT => word_count_fee_data_fifo,
+-- Empty => empty_flag_fee_data_fifo_i,
+-- Full => full_flag_fee_data_fifo_i,
+-- AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
+-- AlmostFull => almost_full_flag_fee_data_fifo_i);
+
+ FEE_DATA_FIFO: fifo_8192depth_36width_dual_thresh
+ port map (
+ Data => data_tdc_readout_i,
+ Clock => CLK,
+ WrEn => write_fee_data_fifo_i,
+ RdEn => read_fee_data_fifo,
+ Reset => RESET,
+ AmEmptyThresh => "0000000000000",
+ AmFullThresh => "1011101110000",
+ Q => fee_data_fifo_out_i,
+ WCNT => word_count_fee_data_fifo,
+ Empty => empty_flag_fee_data_fifo_i,
+ Full => full_flag_fee_data_fifo_i,
+ AlmostEmpty => almost_empty_flag_fee_data_fifo_i,
+ AlmostFull => almost_full_flag_fee_data_fifo_i);
+
+ read_fee_data_fifo <= (reg_ipu_read and reg_read_fee_data_fifo_i) or push_read_fee_data_i;
+
+ HEADER_FIFO: fifo_fall_through_512depth_52width
+ port map (
+ Data => data_header_fifo_in_i,
+ Clock => CLK,
+ WrEn => write_header_fifo_i,
+ RdEn => read_header_fifo, --reg_read_header_fifo_i,
+ Reset => RESET,
+ Q => header_data_fifo_out_i,
+ WCNT => word_count_header_fifo,
+ Empty => empty_flag_header_data_fifo_i,
+ Full => full_flag_header_data_fifo_i,
+ AlmostEmpty => almost_empty_flag_header_data_fifo_i,
+ AlmostFull => almost_full_flag_header_data_fifo_i);
+-------------------------------------------------------------------------------
+-- reg_ipu_read is setted by TRBNET,
+-- reg_read_header_fifo_i is defined by the state machine
+-------------------------------------------------------------------------------
+read_header_fifo <= (reg_ipu_read and reg_read_header_fifo_i) or push_read_header_data_i;
+
+-------------------------------------------------------------------------------
+-- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO HEADER
+-- OUTPUT
+-------------------------------------------------------------------------------
+ process (CLK, RESET, pulse_write_header_fifo_i,counter_pulse_write_header_fifo_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ push_read_header_data_i <= '0';
+ elsif (pulse_write_header_fifo_i = '1' and counter_pulse_write_header_fifo_i = X"0000") then
+ push_read_header_data_i <= '1';
+ else
+ push_read_header_data_i <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (CLK, pulse_write_header_fifo_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ counter_pulse_write_header_fifo_i <= (others => '0');
+ elsif (pulse_write_header_fifo_i = '1') then
+ counter_pulse_write_header_fifo_i <= counter_pulse_write_header_fifo_i + 1;
+ -- elsif (pulse_read_header_fifo = '1') then
+ else
+ counter_pulse_write_header_fifo_i <= counter_pulse_write_header_fifo_i;
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+-- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO DATA
+-- OUTPUT
+-------------------------------------------------------------------------------
+ process (CLK, RESET, pulse_write_fee_data_fifo_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ push_read_fee_data_i <= '0';
+ elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then
+ push_read_fee_data_i <= '1';
+ else
+ push_read_fee_data_i <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (CLK, pulse_write_fee_data_fifo_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ counter_pulse_write_fee_data_fifo_i <= (others => '0');
+ elsif (pulse_write_fee_data_fifo_i = '1') then
+ counter_pulse_write_fee_data_fifo_i <= counter_pulse_write_fee_data_fifo_i + 1;
+ else
+ counter_pulse_write_fee_data_fifo_i <= counter_pulse_write_fee_data_fifo_i;
+ end if;
+ end if;
+ end process;
+
+
+
+-------------------------------------------------------------------------------
+-- INPUT CONNECTIONS
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- OUTPUT CONNECTIONS
+-------------------------------------------------------------------------------
+ LVL1_ERROR_PATTERN_OUT <= x"00000000";
+ LVL1_TRG_RELEASE_OUT <= reg_lvl1_busy_i;
+
+ IPU_DATA_OUT <= next_data_to_trb_net(31 downto 0);
+ IPU_DATAREADY_OUT <= reg_ipu_data_ready;
+ IPU_READOUT_FINISHED_OUT <= reg_ipu_finished;
+
+ IPU_LENGTH_OUT <= first_header(51 downto 36);
+ IPU_ERROR_PATTERN_OUT <= x"AAAAAAAA";
+--to connect
+--reg_debug_register_fsm_header
+
+------------------------------------------------------------------------------
+-- Count number of dataword per event
+-------------------------------------------------------------------------------
+ a_add_data_counter : process (CLK, pulse_init_tdc_readout, pulse_a_aod_i)
+ begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger
+ words_in_event <= (others => '0');
+ elsif (pulse_a_aod_i = '1') then
+ words_in_event <= words_in_event + 1;
+ else
+ words_in_event <= words_in_event;
+ end if;
+ end if;
+ end process a_add_data_counter;
+
+
+--register input
+ process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_token_in <= (others => '0');
+ reg_ipu_read <= '0';
+ else
+ reg_token_in <= TOKEN_IN;
+ reg_ipu_read <= IPU_READ_IN;
+ end if;
+ end if;
+ end process;
+
+--say if token from first event is back
+--counter number of token back
+ process (CLK, RESET,reg_token_in)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ counter_token_back <= (others => '0');
+ elsif (reg_token_in(0) = '1') then
+ counter_token_back <= counter_token_back + 1;
+ else
+ counter_token_back <= counter_token_back;
+ end if;
+ end if;
+ end process;
+
+
+ process (CLK)
+ begin -- process init_signals
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_debug_register_fsm_header <= (others => '0');
+ write_header_fifo_i <= '0';
+ reg_lvl1_busy_i <= '0';
+ else
+ current_state <= next_state;
+ reg_debug_register_fsm_header <= next_debug_register_fsm_header;
+ write_header_fifo_i <= next_write_header_fifo_i;
+ reg_lvl1_busy_i <= next_lvl1_busy_i;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- FSM_HEADER:
+-- COMBINATORIAL PART: BUILD HEADER AND WRITE THEM IN THE FIFO FOR HEADER,
+-- MANAGES THE BUSY SIGNAL
+-------------------------------------------------------------------------------
+ process(current_state, reg_lvl1_trg_received, reg_token_in,
+ pulse_init_tdc_readout, INIT_TDC_READOUT_IN, almost_empty_flag_fee_data_fifo_i)
+ begin
+
+ next_write_header_fifo_i <= '0';
+ next_debug_register_fsm_header <= (others => '0');
+ next_lvl1_busy_i <= '0';
+ data_header_fifo_in_i <= first_header;
+ case current_state is
+
+ when idle_state =>
+ next_debug_register_fsm_header <= x"00";
+ next_write_header_fifo_i <= '0';
+ data_header_fifo_in_i <= first_header;
+ next_lvl1_busy_i <= '0';
+ if (INIT_TDC_READOUT_IN(0) = '1') then
+ next_state <= wait_for_token;
+ else
+ next_state <= idle_state;
+ end if;
+
+-----------------------------------------------------------------------
+--SEND FIRST HEADER
+--I can send the first header as soon as I receive the
+--trigger info. It is important that this header has the same tag of the
+--corrisponing event which is being collected.
+-----------------------------------------------------------------------
+-- when send_first_header_state =>
+-- next_debug_register_fsm_header <= x"01";
+-- next_write_header_fifo_i <= '0';
+-- data_header_fifo_in_i <= first_header;
+-- next_lvl1_busy_i <= '0';
+-- next_state <= dummy_wait_1_header_state;
+
+-- when dummy_wait_1_header_state =>
+-- next_debug_register_fsm_header <= x"01";
+-- next_write_header_fifo_i <= '0';
+-- data_header_fifo_in_i <= first_header;
+-- next_lvl1_busy_i <= '0';
+-- next_state <= wait_for_token;
+-----------------------------------------------------------------------
+--WAIT FOR TOKEN:
+--I have to wait the event which is being collected is complete.
+--When the event is complete the second header is generated and loaded
+--in the fifo.
+--When I wait in this state the data is written in the data_fifo.
+-----------------------------------------------------------------------
+ when wait_for_token =>
+ next_debug_register_fsm_header <= x"02";
+ next_write_header_fifo_i <= '0';
+ data_header_fifo_in_i <= first_header;
+ next_lvl1_busy_i <= '1';
+ if (reg_token_in(0) = '1' and almost_empty_flag_fee_data_fifo_i = '0') then
+ next_state <= send_second_header_state;
+ elsif (reg_token_in(0) = '1' and almost_empty_flag_fee_data_fifo_i = '1') then
+ next_state <= busy_header_state;
+ else
+ next_state <= wait_for_token;
+ end if;
+
+-------------------------------------------------------------------------------
+-- FOR THE MOMENT WE DECIDED TO SEND ONE HEADER
+-------------------------------------------------------------------------------
+ when send_second_header_state =>
+ next_debug_register_fsm_header <= x"03";
+ next_write_header_fifo_i <= '1'; --write in header fifo
+ data_header_fifo_in_i <= first_header;
+ next_lvl1_busy_i <= '1';
+ next_state <= idle_state;
+
+ --at 6000 dataword in fee data fifo almost_empty_flag_fee_data_fifo_i
+ --is asserted
+ when busy_header_state =>
+ next_debug_register_fsm_header <= x"04";
+ next_write_header_fifo_i <= '0';
+ data_header_fifo_in_i <= first_header;
+ next_lvl1_busy_i <= '1';
+ if (almost_empty_flag_fee_data_fifo_i = '0') then
+ next_state <= send_second_header_state;
+ else
+ next_state <= busy_header_state;
+ end if;
+
+
+ when others =>
+ next_debug_register_fsm_header <= x"00";
+ next_write_header_fifo_i <= '0';
+ data_header_fifo_in_i <= first_header;
+ next_lvl1_busy_i <= '0';
+ next_state <= idle_state;
+ end case;
+ end process;
+
+-----------------------------------------------------------------------------
+-- Syncronization and reset FSM_FIFO_MULTIPLEXER
+-----------------------------------------------------------------------------
+ process (CLK, RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ current_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ next_debug_register_fsm_multiplexer <= (others => '0');
+ --next_data_to_trb_net <= (others => '0');
+ reg_read_fee_data_fifo_i <= '0';
+ reg_read_header_fifo_i <= '0';
+ reg_lvl1_error_pattern <= (others => '0');
+ reg_lvl1_trg_release <= '0';
+ reg_ipu_data <= (others => '0');
+ reg_ipu_data_ready <= '0';
+ reg_ipu_finished <= '0';
+ -- reg_ipu_length <= (others => '0');
+ else
+ current_state_fsm_multiplexer <= next_state_fsm_multiplexer;
+ reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer;
+ -- reg_data_to_trb_net <= next_data_to_trb_net;
+ reg_read_fee_data_fifo_i <= next_read_fee_data_fifo_i;
+ reg_read_header_fifo_i <= next_read_header_fifo_i;
+ reg_lvl1_error_pattern <= next_lvl1_error_pattern;
+ reg_lvl1_trg_release <= next_lvl1_trg_release;
+ reg_ipu_data <= next_ipu_data;
+ reg_ipu_data_ready <= next_ipu_data_ready;
+ reg_ipu_finished <= next_ipu_finished;
+ -- reg_ipu_length <= next_ipu_length;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- FSM_FIFO_MULTIPLEXER:
+-- this fsm multiplex data and header into TRB net entity.
+-------------------------------------------------------------------------------
+ process(current_state_fsm_multiplexer, reg_lvl1_trg_received,
+ how_many_complete_event_in_fifo_counter,
+ counter_word_read_from_trbnet, INIT_TDC_READOUT_IN,
+ word_count_header_fifo, fee_data_fifo_out_i, reg_ipu_read,
+ empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo,
+ pulse_ipu_start_readout,counter_token_back)
+
+ begin
+
+ next_debug_register_fsm_multiplexer <= (others => '0');
+ next_data_to_trb_net <= (others => '0');
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+
+ next_lvl1_error_pattern <= (others => '0');
+ next_lvl1_trg_release <= '0';
+ next_ipu_data <= (others => '0');
+ next_ipu_data_ready <= '0';
+ next_ipu_finished <= '0';
+ -- next_ipu_length <= (others => '0');
+
+ clear_counter_word_read_from_trbnet <= '0';
+
+-- push_read_fee_data_i <= '0';
+-- push_read_header_data_i <= '0';
+
+ case current_state_fsm_multiplexer is
+
+ when idle_state_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"00";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+--start readout if IPU requests comes
+ --if (INIT_TDC_READOUT_IN(0) = '1') then --TRIGGER FROM TRB NET
+ if (pulse_ipu_start_readout = '1') then
+ next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer;
+ else
+ next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ end if;
+-------------------------------------------------------------------------------
+-- WAIT for at least one complete event in the fifo. If I have one complete event
+-- the header fifo must containt at least 1 word (the first dataword is written
+-- at the beginning, after the token comes back). This check is important only
+-- if one event is written and the same event is read
+-------------------------------------------------------------------------------
+ when wait_for_complete_event_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"01";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+--here I wait only when the first token from the first event is back
+ if (conv_integer(counter_token_back) >= 1) then
+ next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
+ else
+ next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer;
+ end if;
+-------------------------------------------------------------------------------
+-- FIRST HEADER and SECOND : Connect header_fifo to trbnet.
+-- The first and second headers can be sended.
+-- I check that the TRBNET read only ONE word than I switch the
+-- to the data fifo
+-------------------------------------------------------------------------------
+ when send_first_and_second_header_state_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"01";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '1';
+ next_ipu_data_ready <= '1'; --trbnet can read
+ next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0); --header_fifo
+ if (read_header_fifo = '1') then --this read correspond to the header
+ --read from trbnet
+ next_ipu_data_ready <= '0';
+ next_state_fsm_multiplexer <= dummy_wait_1_fsm_multiplexer;
+ else
+ next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer;
+ end if;
+
+ when dummy_wait_1_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"01";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0'; --trbnet cannot read
+ next_data_to_trb_net <= fee_data_fifo_out_i;--header_data_fifo_out_i; --header_fifo
+ next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
+
+-- when dummy_wait_3_fsm_multiplexer =>
+-- next_debug_register_fsm_multiplexer <= x"01";
+-- next_read_fee_data_fifo_i <= '0';
+-- next_read_header_fifo_i <= '0';
+-- next_ipu_data_ready <= '0'; --trbnet can read
+-- next_data_to_trb_net <= header_data_fifo_out_i;
+-- next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
+-------------------------------------------------------------------------------
+-- Connect fee_data_fifo to trbnet.
+-- I leave connected till the flag change to next event
+-------------------------------------------------------------------------------
+ when send_data_state_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"02";
+ next_read_fee_data_fifo_i <= '1';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '1'; --trbnet can read
+ next_data_to_trb_net <= fee_data_fifo_out_i; --data_fifo
+ --chenge state if event you read from the fifo is different from the
+ --event you are sending or if the fifo does not contain anymore data.
+ if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header) or
+ (empty_flag_fee_data_fifo_i = '1') ) then
+ next_ipu_data_ready <= '0';
+ next_state_fsm_multiplexer <= dummy_wait_2_fsm_multiplexer;
+ else
+ next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer;
+ end if;
+
+ when dummy_wait_2_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"02";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= fee_data_fifo_out_i; --data_fifo
+ next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer;
+
+ when end_of_event_transfer_fsm_multiplexer =>
+ next_debug_register_fsm_multiplexer <= x"03";
+ next_read_fee_data_fifo_i <= '0';
+ next_read_header_fifo_i <= '0';
+ next_ipu_data_ready <= '0';
+ next_data_to_trb_net <= fee_data_fifo_out_i;
+ next_ipu_finished <= '1'; --transmission terminated
+ clear_counter_word_read_from_trbnet <= '1';
+ next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+
+ when others =>
+ next_debug_register_fsm_multiplexer <= x"00";
+ next_data_to_trb_net <= header_data_fifo_out_i(35 downto 0);
+ next_state_fsm_multiplexer <= idle_state_fsm_multiplexer;
+ end case;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- EVENT FLAG GENERATOR:
+-- For each event I generate a flag (4 bits), which will be used to distinguish
+-- the events. The flag marks the dataword and the header.
+-------------------------------------------------------------------------------
+ process (CLK, RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ flag_event_counter <= (others => '0');
+ elsif (pulse_reg_lvl1_trg_received = '1') then
+ flag_event_counter <= flag_event_counter + 1;
+ else
+ flag_event_counter <= flag_event_counter;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- I see which trigger has been processed and I store it. I use this
+-- information in the first dataword
+-------------------------------------------------------------------------------
+ process (CLK)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_trigger_type <= (others => '0');
+ elsif init_tdc_readout_i = x"1" then --normal trigger
+ reg_trigger_type <= x"1";
+ elsif init_tdc_readout_i = x"9" then --calibration trigger
+ reg_trigger_type <= x"9";
+ else
+ reg_trigger_type <= reg_trigger_type;
+ end if;
+ end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- registering input from TRBnet
+-------------------------------------------------------------------------------
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- reg_LVL1_TRG_TYPE_IN <= (others => '0'); --4bit
+-- reg_LVL1_TRG_INFORMATION_IN <= (others => '0'); --8bit
+-- reg_LVL1_TRG_NUMBER_IN <= (others => '0'); --16bit
+-- else
+-- reg_LVL1_TRG_TYPE_IN <= LVL1_TRG_TYPE_IN;
+-- reg_LVL1_TRG_INFORMATION_IN <= LVL1_TRG_INFORMATION_IN;
+-- reg_LVL1_TRG_NUMBER_IN <= LVL1_TRG_NUMBER_IN;
+-- end if;
+-- end if;
+-- end process;
+
+-------------------------------------------------------------------------------
+-- Make headers 36 bit
+-------------------------------------------------------------------------------
+first_header <= words_in_event & --(16 downto 0)
+ flag_event_counter & --(3 downto 0)
+ "0000" & --(3 downto 0)
+ reg_lvl1_trg_type & --(3 downto 0)
+ reg_lvl1_trg_information & --(7 downto 0)
+ reg_lvl1_trg_number; --(15 downto 0)
+
+--second_header <= flag_event_counter & x"babe" & words_in_event;
+
+--DEBUG_REGISTER_0 <= received_token_number & sended_token_number;
+
+--DEBUG_REGISTER_1 <= reg_debug_register_i;--debug tdc_readout_and_trb_interface
+
+--DEBUG_REGISTER_2 <= "0000" & debug_register_tdc_readout_i;
+
+-------------------------------------------------------------------------------
+-- EVENT COMPLETE in FIFO:
+-- the counter is used to check how many event complete are stored in the fifo.
+-----------------------------------------------------------------------------
+process(CLK, RESET, pulse_init_tdc_readout,
+ pulse_init_tdc_readout, reg_token_in)
+begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ how_many_complete_event_in_fifo_counter <= (others => '0');
+ elsif (( not(pulse_init_tdc_readout) and reg_token_in(0)) = '1') then
+ how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter + 1;
+--decrese by one every event is read out
+-- elsif then
+-- how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter - 1;
+ else
+ how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter;
+ end if;
+ end if;
+end process;
+-------------------------------------------------------------------------------
+-- REGISTER INPUT TRBNET SIGNALS
+-------------------------------------------------------------------------------
+process(CLK, RESET)
+begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ -- LVL1 trigger APL
+ reg_lvl1_trg_type <= (others => '0');
+ reg_lvl1_trg_received <= '0';
+ reg_lvl1_trg_number <= (others => '0');
+ reg_lvl1_trg_code <= (others => '0');
+ reg_lvl1_trg_information <= (others => '0');
+ --Data Port
+ reg_ipu_number <= (others => '0');
+ reg_ipu_information <= (others => '0');
+ --start strobe
+ --reg_ipu_start_readout <= '0';
+ -- reg_ipu_read <= '0';
+ else
+ --reg_ipu_read <= IPU_READ_IN;
+ -- LVL1 trigger APL
+ reg_lvl1_trg_type <= LVL1_TRG_TYPE_IN; --4bit
+ reg_lvl1_trg_received <= LVL1_TRG_RECEIVED_IN;
+ reg_lvl1_trg_number <= LVL1_TRG_NUMBER_IN;--16bit
+ reg_lvl1_trg_code <= LVL1_TRG_CODE_IN;
+ reg_lvl1_trg_information <= LVL1_TRG_INFORMATION_IN;--8bit
+ --Data Port
+ reg_ipu_number <= IPU_NUMBER_IN;
+ reg_ipu_information <= IPU_INFORMATION_IN;
+ --start strobe
+ -- reg_ipu_start_readout <= IPU_START_READOUT_IN;
+ end if;
+ end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- PROCESS to count how many word the TRB net reads from the FIFO_HADER
+-------------------------------------------------------------------------------
+process (CLK, RESET, clear_counter_word_read_from_trbnet, reg_ipu_read, current_state_fsm_multiplexer)
+begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or clear_counter_word_read_from_trbnet = '1') then
+ counter_word_read_from_trbnet <= (others => '0');
+ elsif (reg_ipu_read = '1' and
+ current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then
+ counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1;
+ else
+ counter_word_read_from_trbnet <= counter_word_read_from_trbnet;
+ end if;
+ end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- READ and REGISTER event number
+-----------------------------------------------------------------------------
+process (CLK, RESET, current_state_fsm_multiplexer)
+begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ reg_flag_in_header <= (others => '0');
+-- elsif (header_data_fifo_out_i(31 downto 16) = x"babe") then
+ elsif (current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then
+ reg_flag_in_header <= header_data_fifo_out_i(35 downto 32);
+ else
+ reg_flag_in_header <= reg_flag_in_header;
+ end if;
+ end if;
+end process;
+
+-------------------------------------------------------------------------------
+-- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS.
+-------------------------------------------------------------------------------
+-- simulated! it is ok and tested in a different design
+--
+
+end behavioral;
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity trigger_begrun_state is
+ port(
+ CLK : in std_logic; --for testing
+ A_ADD : out std_logic_vector(8 downto 0); --address/data line
+ A_AOD : out std_logic; --address or data
+ A_DST : out std_logic; --data strobe
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_GDE : out std_logic; --global disable
+ A_RDO : in std_logic; --ready FROM first motherboard
+
+--mode lines
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ BEGRUN_TRIGGER : in std_logic; --test the sub entity it starts "load_ROC1_configuration_data"
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+ CALIBRATION_TRIGGER : in std_logic;
+ RESET : in std_logic;
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(12 downto 0)
+ );
+
+end trigger_begrun_state;
+
+architecture Behavioral of trigger_begrun_state is
+ signal tdc_setting_loaded_out_i : std_logic;
+ signal mode_ready_for_tdc_setting_out_i : std_logic;
+ signal reg_mode_trigger, next_mode_trigger : std_logic;
+
+ signal debug_register_i,debug_register_load_tdc_setup_i : std_logic_vector(7 downto 0);
+
+ signal reg_trigger_in, next_trigger_in, mode_trigger_i : std_logic;
+ signal trigger_in : std_logic;
+ signal next_tdc_setting_loaded_in, reg_tdc_setting_loaded_in : std_logic;
+ signal tdc_setting_loaded_in : std_logic;
+ signal roc1_written_i,cal1_written_i : std_logic;
+ signal reg_cal1_written, next_cal1_written : std_logic;
+ signal reset_i : std_logic;
+ signal debug_register_load_mode_line_i : std_logic_vector(7 downto 0);
+
+ signal next_calibration_trigger_mode_line, reg_calibration_trigger_mode_line : std_logic;
+ signal reg_calibration_step_mode_line : std_logic_vector(3 downto 0);
+ signal next_calibration_trigger_tdc_setup, reg_calibration_trigger_tdc_setup : std_logic;
+ signal next_calibration_step_mode_line : std_logic_vector(3 downto 0);
+ signal reg_calibration_step_tdc_setup, next_calibration_step_tdc_setup : std_logic_vector(3 downto 0);
+
+ type state_type is (idle_state, load_ROC1_data_mode_state,
+ load_ROC1_tdc_data_state,
+ calibration_state_0, calibration_state_1,
+ calibration_state_2, calibration_state_3,
+ calibration_state_4, calibration_state_5,
+ calibration_state_6, calibration_state_7,
+ calibration_ended_state,
+ dummy_calibration_state_0,
+ dummy_calibration_state_1);
+
+ signal current_state, next_state : state_type;
+
+--constant declarations
+-- constant width : integer := 5;
+-------------------------------------------------------------------------------
+-- this entity load into TDCs only MODE settings
+-------------------------------------------------------------------------------
+ component load_mode_line is
+ generic (width : integer := 13);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ MODE_TRIGGER : in std_logic;
+ CALIBRATION_TRIGGER_MODE_LINE : in std_logic;
+ CALIBRATION_STEP_MODE_LINE : in std_logic_vector(3 downto 0);
+ RDO : in std_logic;
+ GDE : out std_logic;
+ MODD : out std_logic;
+ RES : out std_logic;
+ TOK : out std_logic;
+ WRM : out std_logic;
+ RDM : out std_logic;
+ MODE_READY_FOR_TDC_SETTING_OUT : out std_logic;
+ TDC_SETTING_LOADED_IN : in std_logic;
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(7 downto 0));
+ end component;
+-------------------------------------------------------------------------------
+-- this entity load into TDCs setting, threshold
+-------------------------------------------------------------------------------
+ component load_ROC1_tdc_setup
+ generic (width : integer := 6);
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ A_ADD : out std_logic_vector(8 downto 0); --address/data line
+ TRIGGER_IN : in std_logic;
+ CALIBRATION_TRIGGER_TDC_SETUP : in std_logic;
+ CALIBRATION_STEP_TDC_SETUP : in std_logic_vector(3 downto 0);
+ A_DST : out std_logic;
+ A_AOD : out std_logic; --address or data
+ TDC_SETTING_LOADED_OUT : out std_logic;
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ DEBUG_REGISTER : out std_logic_vector(7 downto 0));
+ end component;
+
+--mapping
+
+begin
+ MODE_LINE : load_mode_line
+ generic map (width => 13)
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+ MODE_TRIGGER => mode_trigger_i,
+ CALIBRATION_TRIGGER_MODE_LINE => reg_calibration_trigger_mode_line,
+ CALIBRATION_STEP_MODE_LINE => reg_calibration_step_mode_line,
+ RDO => A_RDO, --token back signal
+ GDE => A_GDE,
+ MODD => A_MOD,
+ RES => A_RES,
+ TOK => A_TOK,
+ WRM => A_WRM,
+ RDM => A_RDM,
+ MODE_READY_FOR_TDC_SETTING_OUT => mode_ready_for_tdc_setting_out_i,
+ TDC_SETTING_LOADED_IN => tdc_setting_loaded_in,
+ ROC1_WRITTEN => roc1_written_i,
+ CAL1_WRITTEN => cal1_written_i,
+ DEBUG_REGISTER => debug_register_load_mode_line_i
+ );
+
+ TDC_SETUP : load_ROC1_tdc_setup
+ generic map (width => 6)
+ port map(
+ CLK => CLK,
+ RESET => reset_i,
+ A_ADD => A_ADD(8 downto 0),
+ TRIGGER_IN => trigger_in,
+ CALIBRATION_TRIGGER_TDC_SETUP => '0',--reg_calibration_trigger_tdc_setup,
+ CALIBRATION_STEP_TDC_SETUP => reg_calibration_step_tdc_setup,
+ A_DST => A_DST,
+ A_AOD => A_AOD,
+
+ TDC_SETTING_LOADED_OUT => tdc_setting_loaded_out_i,
+ BUS_CHAIN_IN => x"1",--BUS_CHAIN_IN,
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN => RAM_ADDRESS_IN,
+ RAM_DATA_IN => RAM_DATA_IN,
+ RAM_DATA_OUT => RAM_DATA_OUT,
+ RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN,
+ RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN,
+ DEBUG_REGISTER => debug_register_load_tdc_setup_i);
+--
+-------------------------------------------------------------------------------
+-- in this state machine I have 3 state: idle load_ROC1_configuration_data and
+-- load_ROC1_tdc_data, the idle control the flow,the second and 3rd state are
+-- in different file
+------------------------------------------------------------------------------
+DEBUG_REGISTER(4) <= roc1_written_i;
+--DEBUG_REGISTER(8 downto 5) <= debug_register_i;
+DEBUG_REGISTER(3 downto 0) <= debug_register_load_mode_line_i(3 downto 0);
+
+ROC1_WRITTEN <= roc1_written_i;
+CAL1_WRITTEN <= reg_cal1_written;
+
+mode_trigger_i <= reg_mode_trigger;
+trigger_in <= next_trigger_in;
+tdc_setting_loaded_in <= reg_tdc_setting_loaded_in;
+reset_i <= RESET;
+-------------------------------------------------------------------------------
+-- purpose: sincronization of the state machine
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin -- process
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_mode_trigger <= '0';
+ reg_trigger_in <= '0';
+ reg_tdc_setting_loaded_in <= '0';
+ reg_calibration_trigger_mode_line <= '0';
+ reg_calibration_trigger_tdc_setup <= '0';
+ reg_calibration_step_tdc_setup <= (others => '0');
+ reg_calibration_step_mode_line <= (others => '0');
+ reg_cal1_written <= '0';
+ else
+ current_state <= next_state;
+ reg_mode_trigger <= next_mode_trigger;
+ reg_trigger_in <= next_trigger_in;
+ reg_tdc_setting_loaded_in <= next_tdc_setting_loaded_in;
+ reg_calibration_trigger_mode_line <= next_calibration_trigger_mode_line;
+ reg_calibration_trigger_tdc_setup <= next_calibration_trigger_tdc_setup;
+ reg_calibration_step_tdc_setup <= next_calibration_step_tdc_setup;
+ reg_calibration_step_mode_line <= next_calibration_step_mode_line;
+ reg_cal1_written <= next_cal1_written;
+ end if;
+ end if;
+ end process;
+
+--purpose: state machine
+ process (BEGRUN_TRIGGER, current_state,
+ mode_ready_for_tdc_setting_out_i,
+ tdc_setting_loaded_out_i, CALIBRATION_TRIGGER,
+ cal1_written_i, debug_register_load_mode_line_i,
+ debug_register_load_tdc_setup_i)
+ begin
+
+ next_mode_trigger <= '0';
+ debug_register_i <= (others => '0');
+ -- A_ADD <= (others => '0');
+ next_trigger_in <= '0';
+ -- tdc_setting_loaded_in_i <= '0';
+ -- A_ADD(0) <= '0';
+ next_tdc_setting_loaded_in <= '0';
+ next_cal1_written <= '0';
+
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+ next_calibration_step_tdc_setup <= (others => '0');
+ next_calibration_step_mode_line <= (others => '0');
+
+ case current_state is
+
+ when idle_state =>
+ -- debug_register_i <= "0000";
+ -- mode_setup_ready_i <= '0';
+ if BEGRUN_TRIGGER = '1' then --begrun trigger
+ next_state <= load_ROC1_data_mode_state;
+ else
+ next_state <= idle_state;
+ end if;
+-------------------------------------------------------------------------------
+-- TRIGGER BEGRUN
+-------------------------------------------------------------------------------
+ when load_ROC1_data_mode_state =>
+ -- debug_register_i <= "0001";
+ next_mode_trigger <= '1'; --activate the state machine and wait
+ --for mode_setup_ready_i = '1' when it
+ --finishes
+ if mode_ready_for_tdc_setting_out_i = '1' then
+ next_state <= load_ROC1_tdc_data_state;
+ elsif CALIBRATION_TRIGGER = '1' then
+ next_calibration_trigger_mode_line <= '1';
+ next_state <= calibration_state_0;
+ else
+ next_state <= load_ROC1_data_mode_state;
+ end if;
+-------------------------------------------------------------------------------
+-- this state also if condition mode_ready_for_tdc_setting_out_i = '1' satisfied
+-------------------------------------------------------------------------------
+ when load_ROC1_tdc_data_state =>
+ -- debug_register_i <= "0010";
+ next_trigger_in <= '1';
+ if tdc_setting_loaded_out_i = '1' then
+ next_state <= load_ROC1_data_mode_state;
+ next_tdc_setting_loaded_in <= '1'; --to MODE LINE ack to write 64
+ else
+ next_state <= load_ROC1_tdc_data_state;
+ end if;
+-------------------------------------------------------------------------------
+-- CALIBRATION TRIGGER
+-------------------------------------------------------------------------------
+ when calibration_state_0 => --hex 48
+ next_calibration_trigger_mode_line <= '1';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_mode_line <= (others => '0');
+ next_calibration_step_tdc_setup <= (others => '0');
+-- if debug_register_load_mode_line_i = x"10" then
+-- next_state <= calibration_state_1;
+-- else
+-- next_state <= calibration_state_0;
+-- end if;
+ next_state <= dummy_calibration_state_0;
+
+ when dummy_calibration_state_0 =>
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_mode_line <= (others => '0');
+ next_calibration_step_tdc_setup <= (others => '0');
+ if debug_register_load_mode_line_i = x"10" then
+ next_state <= calibration_state_1;
+ else
+ next_state <= dummy_calibration_state_0;
+ end if;
+
+ when calibration_state_1 => --GDE registers
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '1';
+
+ next_calibration_step_mode_line <= (others => '0');
+ next_calibration_step_tdc_setup <= (others => '0');
+-- if debug_register_load_tdc_setup_i = x"12" then
+-- next_state <= calibration_state_2;
+-- else
+-- next_state <= calibration_state_1;
+-- end if;
+ next_state <= dummy_calibration_state_1;
+
+ when dummy_calibration_state_1 =>
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_mode_line <= (others => '0');
+ next_calibration_step_tdc_setup <= (others => '0');
+ if debug_register_load_tdc_setup_i = x"12" then
+ next_state <= calibration_state_2;
+ else
+ next_state <= dummy_calibration_state_1;
+ end if;
+
+ when calibration_state_2 => --hex 08
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_tdc_setup <= (others => '0');
+ next_calibration_step_mode_line <= x"1";
+ if debug_register_load_mode_line_i = x"12" then
+ next_state <= calibration_state_3;
+ else
+ next_state <= calibration_state_2;
+ end if;
+
+ when calibration_state_3 => --register 1 "BD"
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_tdc_setup <= x"1";
+ next_calibration_step_mode_line <= x"0";
+ if debug_register_load_tdc_setup_i = x"1D" then
+ next_state <= calibration_state_4;
+ else
+ next_state <= calibration_state_3;
+ end if;
+
+ when calibration_state_4 => --hex 08 and hex 48
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_tdc_setup <= (others => '0');
+ next_calibration_step_mode_line <= x"2";
+ if debug_register_load_mode_line_i = x"16" then
+ next_state <= calibration_state_5;
+ else
+ next_state <= calibration_state_4;
+ end if;
+
+ when calibration_state_5 => --register 1 "99" + GDE
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_tdc_setup <= x"3";
+ next_calibration_step_mode_line <= x"0";
+ if debug_register_load_tdc_setup_i = x"1E" then --calibration terminated
+ next_state <= calibration_state_6;
+ -- next_state <= calibration_ended_state;
+ else
+ next_state <= calibration_state_5;
+ end if;
+
+ when calibration_state_6 => --hex 7C
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+
+ next_calibration_step_tdc_setup <= x"0";
+ next_calibration_step_mode_line <= x"3";
+ if cal1_written_i = '1' then
+ next_state <= calibration_state_7;
+ else
+ next_state <= calibration_state_6;
+ end if;
+
+ when calibration_state_7 =>
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+ next_cal1_written <= '1';
+ next_calibration_step_tdc_setup <= (others => '0');
+ next_calibration_step_mode_line <= (others => '0');
+ next_state <= calibration_ended_state;
+
+ when calibration_ended_state => --hex 64 I'm ready to get token
+ next_calibration_trigger_mode_line <= '0';
+ next_calibration_trigger_tdc_setup <= '0';
+ next_cal1_written <= '0';
+ next_calibration_step_tdc_setup <= (others => '0');
+ next_calibration_step_mode_line <= (others => '0');
+ if CALIBRATION_TRIGGER = '1' then
+ next_calibration_trigger_mode_line <= '1';
+ next_state <= calibration_state_0;
+ else
+ next_state <= calibration_ended_state;
+ end if;
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+ when others =>
+ next_state <= idle_state;
+
+ end case;
+ end process;
+--purpose: when the tdc setting in ROC1 are loaded, this means tdc_setting_loaded_out_i = '1',
+--the signal tdc_setting_loaded_in_i <= '1' is sended to the state machine load_ROC1_data_mode,
+--and it writes the last mode line 64!
+-- process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if (current_state = load_ROC1_tdc_data_state and
+-- tdc_setting_loaded_out_i = '1') then
+-- tdc_setting_loaded_in_i <= '1';
+-- else
+-- tdc_setting_loaded_in_i <= '0';
+-- end if;
+-- end if;
+-- end process;
+end Behavioral;
--- /dev/null
+-------------------------------------------------------------------------------
+-- Attilio Tarantola
+-- Create Date: 18/11/2007
+-- Description: When I receive a trigger this entity distribute it to all bus/buses, wait
+-- for the token back.
+--
+-- 29/02/2008 I add the calibration states. When a calibration trigger is
+-- retrived, it sends the cal trigger to all buses, the CAL parameters are loaded
+-- and data is collected. The input A_RDO_IN is the AND between all buses
+-- This entity generates the token back for TRB.
+-- INIT_ALL_BUSES_OUT <= "1" normal trigger
+-- INIT_ALL_BUSES_OUT <= "B" begrun trigger
+-- INIT_ALL_BUSES_OUT <= "C" calibration trigger
+-- INIT_ALL_BUSES_OUT <= "0" idle
+--
+-- 01/12/2008 I start adapting to the OEPB
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity trigger_distributor is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ INTERNAL_RESET_IN : in std_logic;
+
+ A_RDO_IN : in std_logic;
+ TRIGGER_IN : in std_logic;
+ TRIGGER_TYPE_IN : in std_logic;
+ INIT_ALL_BUSES_OUT : out std_logic_vector(3 downto 0);
+ ROC1_WRITTEN_IN : in std_logic;
+ TOKEN_TO_TRB_OUT : out std_logic;
+ CAL_TRIGGER_REGISTER_IN : in std_logic_vector(15 downto 0);
+
+ DEBUG_REGISTER_OUT : out std_logic_vector(31 downto 0);
+ LED_CNT_1_OUT : out std_logic;
+ LED_CNT_2_OUT : out std_logic;
+ LED_ERROR_OUT : out std_logic;
+ LED_GOOD_OUT : out std_logic);
+end trigger_distributor;
+
+architecture behavioral of trigger_distributor is
+
+
+ constant WAIT_AFTER_ROC1_IS_LOADED : std_logic_vector(12 downto 0) := "0011111010000";
+
+ type state_type is (idle_state, normal_trigger_state,
+ begrun_trigger_state,
+ wait_roc1_written, wait_token_back_state,
+ roc1_written_state, send_token_state,
+--calibration state
+ calibration_state, wait_cal1_written);
+
+ signal current_state, next_state : state_type;
+
+ signal reset_calibration_counter : std_logic;
+ signal reg_init_all_buses, next_init_all_buses : std_logic_vector(3 downto 0);
+ signal reg_token_to_trb, next_token_to_trb : std_logic;
+ signal counter_number_of_trigger : std_logic_vector(11 downto 0);
+ signal up_number_of_trigger : std_logic;
+ signal register_trigger_condition : std_logic_vector(15 downto 0);
+ signal internal_calibration_trigger : std_logic;
+ signal reg_trigger_type_in, reg_trigger_in : std_logic;
+ signal reg_debug_register, next_debug_register : std_logic_vector(3 downto 0);
+ signal debug_normal_trigger_number, debug_calibration_trigger_number : std_logic_vector(7 downto 0);
+ signal debug_token_back_number : std_logic_vector(7 downto 0);
+ signal pulse_a_rdo_in : std_logic;
+ signal pulse_begin_run_trigger : std_logic;
+ signal not_reset : std_logic;
+ signal counter_wait_after_roc1 : std_logic_vector(12 downto 0);
+
+-------------------------------------------------------------------------------
+-- I use this exeption for naming signal(they should be lower case in general). In this case
+-- capital letters with "reg" or "next" at the beginning.
+-------------------------------------------------------------------------------
+ signal reg_LED_CNT_1_OUT, reg_LED_CNT_2_OUT : std_logic;
+ signal reg_LED_ERROR_OUT, reg_LED_GOOD_OUT : std_logic;
+ signal next_LED_CNT_1_OUT, next_LED_CNT_2_OUT : std_logic;
+ signal next_LED_ERROR_OUT, next_LED_GOOD_OUT : std_logic;
+
+
+ component edge_to_pulse
+ port (
+ CLOCK : in std_logic;
+ ENABLE_CLK_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
+ PULSE_OUT : out std_logic);
+ end component;
+
+begin -- behavioral
+
+
+-------------------------------------------------------------------------------
+-- it creates a pulse of 10ns from the input signal.
+-- A_RDO_IN is the token back.
+-------------------------------------------------------------------------------
+ A_RDO_PULSE : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => A_RDO_IN,
+ PULSE_OUT => pulse_a_rdo_in);
+
+-------------------------------------------------------------------------------
+-- it creates a pulse of 10ns from the input signal.
+-- After the the firmware is loaded in the FPGA, the begin run trigger is
+-- generated automatically and the FEE is initialized.
+-------------------------------------------------------------------------------
+ BEGIN_RUN_TRIGGER_FROM_RESET : edge_to_pulse
+ port map (
+ CLOCK => CLK,
+ ENABLE_CLK_IN => '1',
+ SIGNAL_IN => not_reset,
+ PULSE_OUT => pulse_begin_run_trigger);
+
+ not_reset <= not(RESET);
+
+
+-------------------------------------------------------------------------------
+-- Register and reset for the FSM
+-- Signals in the sensitivity list (CLK,RESET) are important for the simulation!!
+-------------------------------------------------------------------------------
+ REGISTER_ADDR_DATA_MODE : process (CLK,RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ current_state <= idle_state;
+ reg_token_to_trb <= '0';
+ reg_init_all_buses <= (others => '0');
+ reg_debug_register <= (others => '0');
+ reg_LED_CNT_1_OUT <= '0';
+ reg_LED_CNT_2_OUT <= '0';
+ reg_LED_ERROR_OUT <= '0';
+ reg_LED_GOOD_OUT <= '0';
+ else
+ current_state <= next_state;
+ reg_token_to_trb <= next_token_to_trb;
+ reg_init_all_buses <= next_init_all_buses;
+ reg_debug_register <= next_debug_register;
+ reg_LED_CNT_1_OUT <= next_LED_CNT_1_OUT;
+ reg_LED_CNT_2_OUT <= next_LED_CNT_2_OUT;
+ reg_LED_ERROR_OUT <= next_LED_ERROR_OUT;
+ reg_LED_GOOD_OUT <= next_LED_GOOD_OUT;
+ end if;
+ end if;
+ end process REGISTER_ADDR_DATA_MODE;
+
+
+-------------------------------------------------------------------------------
+-- Connections to OUTPUT ports
+-------------------------------------------------------------------------------
+ TOKEN_TO_TRB_OUT <= reg_token_to_trb;
+ INIT_ALL_BUSES_OUT <= reg_init_all_buses;
+ DEBUG_REGISTER_OUT <= x"0000000"& reg_debug_register;
+ LED_CNT_1_OUT <= reg_LED_CNT_1_OUT;
+ LED_CNT_2_OUT <= reg_LED_CNT_2_OUT;
+ LED_ERROR_OUT <= reg_LED_ERROR_OUT;
+ LED_GOOD_OUT <= reg_LED_GOOD_OUT;
+
+
+-------------------------------------------------------------------------------
+-- FSM: combinatorial part. It takes input trigger and distributes to other
+-- entities. It sends calibration trigger.
+-- Take care not to use inferred latches, most likely you don't want that!!
+-- Check the .srr report! Also here signals in the sensitivity list are
+-- important for simulation
+-------------------------------------------------------------------------------
+ process (current_state,
+ internal_calibration_trigger,
+ reg_trigger_type_in, reg_trigger_in,
+ ROC1_WRITTEN_IN, A_RDO_IN, pulse_begin_run_trigger,
+ counter_wait_after_roc1)
+ begin
+
+ next_debug_register <= (others => '0');
+ next_init_all_buses <= (others => '0');
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+
+ next_LED_CNT_1_OUT <= '1'; --'1' is off, '0' is on
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '1';
+
+ case current_state is
+
+ when idle_state =>
+ next_debug_register <= x"1";
+ next_LED_CNT_1_OUT <= '1';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= (others => '0');
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ -- if pulse_begin_run_trigger = '1' then
+ if reg_trigger_in = '1' then
+ -- next_state <= begrun_trigger_state;
+-- elsif ( reg_trigger_in = '1') then
+-- next_state <= normal_trigger_state;
+-- if (internal_calibration_trigger = '1') then
+-- next_state <= calibration_state;
+-- else
+ next_state <= normal_trigger_state;
+-- end if;
+ else
+ next_state <= idle_state;
+ end if;
+
+-------------------------------------------------------------------------------
+--NORMAL TRIGGER
+-------------------------------------------------------------------------------
+
+ when normal_trigger_state =>
+ next_debug_register <= x"2";
+ next_LED_CNT_1_OUT <= '0';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= X"1";
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '1';
+ reset_calibration_counter <= '0';
+ next_state <= wait_token_back_state;
+
+ when wait_token_back_state =>
+ next_debug_register <= x"3";
+ next_LED_CNT_1_OUT <= '1';
+ next_LED_CNT_2_OUT <= '0';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= X"0";
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ if A_RDO_IN = '1' then
+ next_state <= send_token_state;
+ else
+ next_state <= wait_token_back_state;
+ end if;
+
+ when send_token_state =>
+ next_debug_register <= x"4";
+ next_LED_CNT_1_OUT <= '0';
+ next_LED_CNT_2_OUT <= '0';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= X"0";
+ next_token_to_trb <= '1';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ --next_state <= normal_trigger_state;
+ next_state <= idle_state;
+
+-------------------------------------------------------------------------------
+-- BEGRUN TRIGGER.
+-- After FPGA is loaded automatically done.
+-------------------------------------------------------------------------------
+ when begrun_trigger_state =>
+ next_debug_register <= x"5";
+ next_LED_CNT_1_OUT <= '1';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '0';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= X"D";
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ next_state <= wait_roc1_written;
+
+ when wait_roc1_written =>
+ next_debug_register <= x"6";
+ next_LED_CNT_1_OUT <= '0';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '0';
+ next_LED_GOOD_OUT <= '1';
+
+ next_init_all_buses <= X"0";
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ if ROC1_WRITTEN_IN = '1' then
+ next_state <= roc1_written_state;
+ else
+ next_state <= wait_roc1_written;
+ end if;
+
+ when roc1_written_state =>
+ next_debug_register <= x"7";
+ next_LED_CNT_1_OUT <= '0';
+ next_LED_CNT_2_OUT <= '0';
+ next_LED_ERROR_OUT <= '0';
+ next_LED_GOOD_OUT <= '1';
+ next_init_all_buses <= (others => '0');
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '0';
+ if counter_wait_after_roc1 = WAIT_AFTER_ROC1_IS_LOADED then
+ -- next_state <= normal_trigger_state;
+ next_state <= idle_state;
+ else
+ next_state <= roc1_written_state;
+ end if;
+
+
+-------------------------------------------------------------------------------
+--CALIBRATION TRIGGER.
+--When the calibration starts the REG2 is
+--loaded from the RAM to the FEE. Calibration data is retrived in the fifo and
+--token comes back as for normal event.
+--In the entity send_token_to_mb.vhd I check the token comes back within 2msec.
+-------------------------------------------------------------------------------
+ when calibration_state =>
+ next_debug_register <= x"8";
+ next_LED_CNT_1_OUT <= '1';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '0';
+ next_init_all_buses <= X"C"; --start calibration
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '1';
+ next_state <= wait_cal1_written;
+
+ when wait_cal1_written =>
+ next_debug_register <= x"9";
+ next_LED_CNT_1_OUT <= '0';
+ next_LED_CNT_2_OUT <= '1';
+ next_LED_ERROR_OUT <= '1';
+ next_LED_GOOD_OUT <= '0';
+ next_init_all_buses <= X"0";
+ next_token_to_trb <= '0';
+ up_number_of_trigger <= '0';
+ reset_calibration_counter <= '1';
+ if A_RDO_IN = '1' then --the token comes back as for normal event
+ next_state <= send_token_state;
+ else
+ next_state <= wait_cal1_written;
+ end if;
+
+ when others =>
+ next_state <= idle_state;
+ end case;
+ end process;
+
+
+-----------------------------------------------------------------------------
+--Counts the number of normal trigger. This number is used to generate the
+--calibration trigger internally.
+--This counter is resetted after the calibration trigger is executed.
+-----------------------------------------------------------------------------
+ process(CLK, RESET, reset_calibration_counter, up_number_of_trigger)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1' or reset_calibration_counter = '1') then
+ counter_number_of_trigger <= (others => '0');
+ elsif (up_number_of_trigger = '1') then
+ counter_number_of_trigger <= counter_number_of_trigger + 1;
+ else
+ counter_number_of_trigger <= counter_number_of_trigger;
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- CAL_TRIGGER_REGISTER_IN says how often the calibration trigger
+-- has to be genereted. This register is written by the TRB at startup.
+-------------------------------------------------------------------------------
+ process (CLK, RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ register_trigger_condition <= (others => '0');
+ else
+ register_trigger_condition <= CAL_TRIGGER_REGISTER_IN;
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- Register input trigger signals. They come from TRB.
+-------------------------------------------------------------------------------
+ process (CLK, RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ reg_trigger_type_in <= '0';
+ reg_trigger_in <= '0';
+ else
+ reg_trigger_type_in <= TRIGGER_TYPE_IN;
+ reg_trigger_in <= TRIGGER_IN;
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- The calibration trigger is generated every
+-- x"register_trigger_condition(15 downto 4)" number of normal trigger
+-------------------------------------------------------------------------------
+ process (CLK, RESET, register_trigger_condition)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ internal_calibration_trigger <= '0';
+
+ elsif ( (register_trigger_condition(3 downto 0) = x"E") and
+ (counter_number_of_trigger(11 downto 0) = register_trigger_condition(15 downto 4)) ) then --enable cal trigger
+ internal_calibration_trigger <= '1';
+
+ elsif (register_trigger_condition(3 downto 0) = x"C") then --only cal trigger
+ internal_calibration_trigger <= '1';
+
+ elsif (register_trigger_condition(3 downto 0) = x"D") then --disable cal trigger
+ internal_calibration_trigger <= '0';
+
+ else
+ internal_calibration_trigger <= '0';
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- DEBUG INFO PROCESS
+-------------------------------------------------------------------------------
+ process (CLK, RESET)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ debug_normal_trigger_number <= (others => '0');
+ elsif (up_number_of_trigger = '1') then
+ debug_normal_trigger_number <= debug_normal_trigger_number + 1;
+ else
+ debug_normal_trigger_number <= debug_normal_trigger_number;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- DEBUG INFO PROCESS
+-------------------------------------------------------------------------------
+ process (CLK, RESET, current_state)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ debug_calibration_trigger_number <= (others => '0');
+ elsif (current_state = calibration_state) then
+ debug_calibration_trigger_number <= debug_calibration_trigger_number + 1;
+ else
+ debug_calibration_trigger_number <= debug_calibration_trigger_number;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- DEBUG INFO PROCESSES: it counts number of token received from FEE
+-------------------------------------------------------------------------------
+ process (CLK, RESET, pulse_a_rdo_in)
+ begin
+ if (rising_edge(CLK)) then
+ if RESET = '1' then
+ debug_token_back_number <= (others => '0');
+ elsif pulse_a_rdo_in = '1' then
+ debug_token_back_number <= debug_token_back_number + 1;
+ else
+ debug_token_back_number <= debug_token_back_number;
+ end if;
+ end if;
+ end process;
+
+
+-------------------------------------------------------------------------------
+-- After the FEE parameters(ROC1) have been loaded an internal signal is
+-- generated (ROC1_WRITTEN_IN = '1').
+-- After this stage the FEE can receive the
+-- data request.
+-- counter_wait_after_roc1 separates the configuration stage from the
+-- acquisition stage.
+-------------------------------------------------------------------------------
+ process (CLK, RESET, current_state)
+ begin
+ if (rising_edge(CLK)) then
+ if (RESET = '1') then
+ counter_wait_after_roc1 <= (others => '0');
+ elsif current_state = roc1_written_state then
+ counter_wait_after_roc1 <= counter_wait_after_roc1 + 1;
+ else
+ counter_wait_after_roc1 <= counter_wait_after_roc1;
+ end if;
+ end if;
+ end process;
+
+end behavioral;
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+-- library UNISIM;
+-- use UNISIM.VComponents.all;
+
+entity trigger_handle_tld is
+ port(
+ CLK : in std_logic; --for testing
+ A_ADD : out std_logic_vector(8 downto 0); --address/data line
+
+-- A_ADS_0 : in std_logic; --Motherboard address
+-- A_ADS_1 : in std_logic; --Motherboard address
+-- A_ADS_2 : in std_logic; --Motherboard address
+ A_AOD : out std_logic; --address or data
+-- A_ACK : inout std_logic; --acknowledgment
+-- A_CMS : out std_logic; --common stop
+
+ A_DST : out std_logic; --data strobe
+-- A_OR : in std_logic; --common or
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_GDE : out std_logic; --global disable
+ A_RDO : in std_logic; --ready FROM first motherboard
+-- A_RESERV : inout std_logic;
+ A_DRE : out std_logic; --address/data line enable
+ A_ENR_1 : out std_logic; --A_GDE enable
+
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+
+ TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); -- I use 4 bit for trigger
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ DEBUG_REGISTER : out std_logic_vector(24 downto 0);
+ ENABLE_MODE_LINE : in std_logic_vector(3 downto 0);
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ TOKEN_BACK_OUT : out std_logic_vector(3 downto 0);
+ REINIT_ROC1_OUT : out std_logic;
+ STOP_READOUT_OUT : out std_logic;
+ RESET : in std_logic
+ );
+
+end trigger_handle_tld;
+
+architecture behavioral of trigger_handle_tld is
+
+--signal declarations
+ type state_type is (idle_trigger_processing,
+ trigger_begrun, send_token,
+ trigger_calibration, wait_calibration);
+
+ signal current_state, next_state : state_type;
+
+ signal roc1_written_i, cal1_written_i : std_logic;
+ signal trigger_type : std_logic_vector(3 downto 0);
+ signal reg_begrun_trigger, next_begrun_trigger, begrun_trigger_i : std_logic;
+ signal debug_register_i : std_logic_vector(3 downto 0);
+ signal A_MOD_TB_i, A_RES_TB_i, A_TOK_TB_i, A_WRM_TB_i, A_RDM_TB_i, A_RDO_TB_i : std_logic;
+ signal A_MOD_ST_i, A_RES_ST_i, A_TOK_ST_i, A_WRM_ST_i, A_RDM_ST_i, A_RDO_ST_i : std_logic;
+ signal A_GDE_ST_i, A_GDE_TB_i : std_logic;
+ signal trigger_type_send_token: std_logic_vector(3 downto 0);
+ signal next_trigger_type_send_token, reg_trigger_type_send_token: std_logic_vector(3 downto 0);
+ signal reset_i, calibration_trigger_i : std_logic;
+ signal reg_calibration_trigger, next_calibration_trigger : std_logic;
+ signal reg_cal1_written, next_cal1_written : std_logic;
+ signal test_signal_i, reg_test_signal_i : std_logic;
+
+--constant declarations
+ constant width : integer := 5;
+ constant width_token : integer := 5;
+
+ component trigger_begrun_state
+ port(
+ CLK : in std_logic; --for testing
+ A_ADD : out std_logic_vector(8 downto 0); --address/data line
+ A_AOD : out std_logic; --address or data
+ A_DST : out std_logic; --data strobe
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_GDE : out std_logic; --global disable
+ A_RDO : in std_logic; --ready FROM first motherboard
+
+--mode lines
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN : in std_logic_vector(9 downto 0);
+ RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit
+ RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit
+ RAM_READ_ENABLE_IN : in std_logic;
+ RAM_WRITE_ENABLE_IN : in std_logic;
+
+ BEGRUN_TRIGGER : in std_logic; --test the sub entity it starts "load_ROC1_configuration_data"
+ BUS_CHAIN_IN : in std_logic_vector(3 downto 0);
+ CALIBRATION_TRIGGER : in std_logic;
+ RESET : in std_logic;
+ ROC1_WRITTEN : out std_logic;
+ CAL1_WRITTEN : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(12 downto 0)
+ );
+ end component;
+-------------------------------------------------------------------------------
+-- mode_line_multiplexer
+-------------------------------------------------------------------------------
+ component mode_line_multiplexer
+ port(
+ CLK : in std_logic; --for testing
+ --mode lines input from trigger_begrun
+ A_MOD_TB : in std_logic; -- TDC working mode
+ A_RES_TB : in std_logic; -- TDC working mode
+ A_TOK_TB : in std_logic; -- TDC working mode
+ A_WRM_TB : in std_logic; -- TDC working mode
+ A_RDM_TB : in std_logic; --ready TO first motherboard
+ A_RDO_TB : out std_logic; --ready FROM first motherboard
+ A_GDE_TB : in std_logic; --global disable
+ --mode lines input from from send_token
+ A_MOD_ST : in std_logic; -- TDC working mode
+ A_RES_ST : in std_logic; -- TDC working mode
+ A_TOK_ST : in std_logic; -- TDC working mode
+ A_WRM_ST : in std_logic; -- TDC working mode
+ A_RDM_ST : in std_logic; --ready TO first motherboard
+ A_RDO_ST : out std_logic; --ready FROM first motherboard
+ A_GDE_ST : in std_logic; --global disable
+ --mode lines to from MB
+ A_MOD : out std_logic; -- TDC working mode
+ A_RES : out std_logic; -- TDC working mode
+ A_TOK : out std_logic; -- TDC working mode
+ A_WRM : out std_logic; -- TDC working mode
+ A_RDM : out std_logic; --ready TO first motherboard
+ A_RDO : in std_logic; --ready FROM first motherboard
+ A_GDE : out std_logic; --global disable
+ -- RESET : in std_logic;
+ ENABLE_MODE_LINE : in std_logic_vector(3 downto 0);
+ -- TRIGGER_TYPE : in std_logic_vector(3 downto 0);
+ DEBUG_REGISTER : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+ component send_token_to_mb
+ generic (--width_token : integer := 5;
+ width : integer);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ TRIGGER_TYPE : in std_logic_vector(3 downto 0);
+ A_MOD : out std_logic;
+ A_RES : out std_logic;
+ A_TOK : out std_logic;
+ A_WRM : out std_logic;
+ A_RDM : out std_logic;
+ A_RDO : in std_logic;
+ A_GDE : out std_logic;
+ TOKEN_BACK_OUT : out std_logic_vector(3 downto 0);
+ REINIT_ROC1 : out std_logic; --active when notoken
+ STOP_READOUT_OUT : out std_logic;
+ DEBUG_REGISTER : out std_logic_vector(3 downto 0));
+ end component;
+
+begin -- behavioral
+
+-------------------------------------------------------------------------------
+-- map trigger_begrun_state
+-------------------------------------------------------------------------------
+ u3 : trigger_begrun_state
+ port map (
+ CLK => CLK,
+ A_ADD => A_ADD,
+ A_AOD => A_AOD,
+ A_DST => A_DST,
+ A_RDM => A_RDM_TB_i,
+ A_GDE => A_GDE_TB_i,
+ A_RDO => A_RDO_TB_i,
+ A_MOD => A_MOD_TB_i,
+ A_RES => A_RES_TB_i,
+ A_TOK => A_TOK_TB_i,
+ A_WRM => A_WRM_TB_i,
+-------------------------------------------------------------------------------
+-- SIGNALS for RAM
+-------------------------------------------------------------------------------
+ RAM_ADDRESS_IN => RAM_ADDRESS_IN,
+ RAM_DATA_IN => RAM_DATA_IN,
+ RAM_DATA_OUT => RAM_DATA_OUT,
+ RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN,
+ RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN,
+
+ BEGRUN_TRIGGER => begrun_trigger_i,
+ BUS_CHAIN_IN => BUS_CHAIN_IN,
+ CALIBRATION_TRIGGER => reg_calibration_trigger,
+ RESET => reset_i,
+ ROC1_WRITTEN => roc1_written_i,
+ CAL1_WRITTEN => cal1_written_i,
+ DEBUG_REGISTER => DEBUG_REGISTER(12 downto 0)
+ );
+-------------------------------------------------------------------------------
+-- map mode_line_multiplexer
+-------------------------------------------------------------------------------
+ u4 : mode_line_multiplexer
+ port map (
+ --CLK : in std_logic; --for testing
+ --mode lines input from trigger_begrun
+ CLK => CLK,
+ A_MOD_TB => A_MOD_TB_i,
+ A_RES_TB => A_RES_TB_i,
+ A_TOK_TB => A_TOK_TB_i,
+ A_WRM_TB => A_WRM_TB_i,
+ A_RDM_TB => A_RDM_TB_i,
+ A_RDO_TB => A_RDO_TB_i,
+ A_GDE_TB => A_GDE_TB_i,
+ --mode lines input from from send_token
+ A_MOD_ST => A_MOD_ST_i,
+ A_RES_ST => A_RES_ST_i,
+ A_TOK_ST => A_TOK_ST_i,
+ A_WRM_ST => A_WRM_ST_i,
+ A_RDM_ST => A_RDM_ST_i,
+ A_RDO_ST => A_RDO_ST_i,
+ A_GDE_ST => reg_test_signal_i,--A_GDE_ST_i,
+ --mode lines to from MB
+ A_MOD => A_MOD,
+ A_RES => A_RES,
+ A_TOK => A_TOK,
+ A_WRM => A_WRM,
+ A_RDM => A_RDM,
+ A_RDO => A_RDO,
+ A_GDE => A_GDE,
+ ENABLE_MODE_LINE => ENABLE_MODE_LINE,
+ DEBUG_REGISTER => open --DEBUG_REGISTER(20 downto 17)
+ );
+reg_test_signal_i <= test_signal_i or A_GDE_ST_i;
+-------------------------------------------------------------------------------
+-- map send_token_to_mb
+-------------------------------------------------------------------------------
+ u5 : send_token_to_mb
+ generic map (--width_token => 5,
+ width => 5)
+ port map (
+ CLK => CLK,
+ RESET => reset_i,
+ TRIGGER_TYPE => trigger_type_send_token,--trigger_type,
+ A_MOD => A_MOD_ST_i,
+ A_RES => A_RES_ST_i,
+ A_TOK => A_TOK_ST_i,
+ A_WRM => A_WRM_ST_i,
+ A_RDM => A_RDM_ST_i,
+ A_RDO => A_RDO_ST_i,
+ A_GDE => A_GDE_ST_i,
+ TOKEN_BACK_OUT => TOKEN_BACK_OUT,
+ REINIT_ROC1 => REINIT_ROC1_OUT, --active when notoken
+ STOP_READOUT_OUT => STOP_READOUT_OUT,
+ DEBUG_REGISTER => DEBUG_REGISTER(16 downto 13)
+ );
+-------------------------------------------------------------------------------
+--the state machine check which kind of trigger arrives. Depending on the
+--trigger,this activates different states: when the beginrun trigger comes the
+--state TRIG_BEG is activated and ROC1 is loaded into MB. If normal trigger
+--comes the SEND_TOKEN state is activated and token is sended to MB to ask data
+--to TDC(the cms should rich the MB 150-200ns before, stop the TDC and then the
+--TDCs wait for token)
+-------------------------------------------------------------------------------
+ trigger_type <= TRIGGER_TYPE_IN;
+ reset_i <= RESET;
+
+ DEBUG_REGISTER(20 downto 17) <= debug_register_i;
+ DEBUG_REGISTER(21) <= roc1_written_i;
+ DEBUG_REGISTER(24 downto 22) <= "000"; --(others => '0');
+
+ ROC1_WRITTEN <= roc1_written_i;
+ begrun_trigger_i <= reg_begrun_trigger;
+ trigger_type_send_token <= reg_trigger_type_send_token;
+ CAL1_WRITTEN <= reg_cal1_written;
+
+-- purpose: sincronization of the state machine
+ process (CLK)
+ begin
+ --process
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ current_state <= idle_trigger_processing;
+ reg_begrun_trigger <= '0';
+ reg_trigger_type_send_token <= (others => '0');
+ reg_calibration_trigger <= '0';
+ reg_cal1_written <= '0';
+ else
+ current_state <= next_state;
+ reg_begrun_trigger <= next_begrun_trigger;
+ reg_trigger_type_send_token <= next_trigger_type_send_token;
+ reg_calibration_trigger <= next_calibration_trigger;
+ reg_cal1_written <= next_cal1_written;
+ end if;
+ end if;
+ end process;
+
+
+--purpose: state machine
+ process (current_state, trigger_type, roc1_written_i,
+ cal1_written_i)
+ begin
+
+--default value
+ next_begrun_trigger <= '0';
+ debug_register_i <= "0000";
+ next_trigger_type_send_token <= (others => '0');
+ next_calibration_trigger <= '0';
+ next_cal1_written <= '0';
+
+ case current_state is
+
+ when idle_trigger_processing =>
+ debug_register_i <= "0000";
+ if trigger_type = x"d" then
+ next_state <= trigger_begrun;
+ elsif trigger_type = x"1" then
+ next_state <= send_token;
+ elsif trigger_type = x"2" then
+ next_state <= trigger_calibration;
+ else
+ next_state <= idle_trigger_processing;
+ end if;
+
+ when trigger_begrun =>
+ debug_register_i <= "0001";
+ next_begrun_trigger <= '1';
+ if roc1_written_i = '1' then
+ next_state <= idle_trigger_processing;
+ else
+ next_state <= trigger_begrun;
+ end if;
+
+--As soon the calibration is terminated I send a token to get the calibration-data
+ when trigger_calibration =>
+ debug_register_i <= "0010";
+ next_calibration_trigger <= '1';
+ next_state <= wait_calibration;
+
+ when wait_calibration =>
+ debug_register_i <= "0011";
+ next_calibration_trigger <= '0';
+ if cal1_written_i = '1' then
+ next_cal1_written <= '1';
+ next_state <= idle_trigger_processing;
+ else
+ next_state <= wait_calibration;
+ end if;
+
+ when send_token =>
+ -- next_state <= send_token;
+ next_trigger_type_send_token <= x"1";
+ next_state <= idle_trigger_processing;
+
+ when others =>
+ next_state <= idle_trigger_processing;
+
+ end case;
+ end process;
+
+-------------------------------------------------------------------------------
+-- the process control enable add _data line
+--
+--A_DRE <= '1' MDC_addon to MB
+--A_DRE <= '0' MB to MDC_addon
+-------------------------------------------------------------------------------
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if (current_state = trigger_begrun or
+ current_state = trigger_calibration or
+ current_state = wait_calibration)
+ then
+-- A_DRA <= '1'; --A_ACK enable
+-- A_DRB_1 <= '1'; --A_RDO enable
+-- A_DRB_2 <= '1'; --A_RDM enable
+ A_DRE <= '1'; --address/data line enable
+-- A_ENB_1 <= '1'; --A_AOD enable
+-- A_ENB_2 <= '1'; --A_DST enable
+-- A_ENR_1 <= '1'; --A_GDE enable
+-- A_ENR_2 <= '1'; --A_CMS enable
+-- A_ENR_3 <= '1'; --A_OR enable
+-- A_FET_ENABLE <= '1'; --it enables 2 FETs
+-- A_REN <= '1'; --A_RESERV enable
+ else
+-- A_DRA <= '0'; --A_ACK enable
+-- A_DRB_1 <= '0'; --A_RDO enable
+-- A_DRB_2 <= '0'; --A_RDM enable
+ A_DRE <= '0'; --address/data line enable
+-- A_ENB_1 <= '0'; --A_AOD enable
+-- A_ENB_2 <= '0'; --A_DST enable
+-- A_ENR_1 <= '0'; --A_GDE enable
+-- A_ENR_2 <= '0'; --A_CMS enable
+-- A_ENR_3 <= '0'; --A_OR enable
+-- A_FET_ENABLE <= '0'; --it enables 2 FETs
+-- A_REN <= '0'; --A_RESERV enable
+ end if;
+ end if;
+ end process;
+-------------------------------------------------------------------------------
+-- test
+-------------------------------------------------------------------------------
+process (CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1' or A_RDO_ST_i = '1') then
+ test_signal_i <= '0';
+ elsif (cal1_written_i = '1') then
+ test_signal_i <= '1';
+ else
+ test_signal_i <= test_signal_i;
+ end if;
+ end if;
+end process;
+
+end behavioral;
+
+
+
jspc29 / mdcoep.git / commitdiff