IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-
-
-#LOCATE COMP "OUT_L_SDO" SITE "D4"; #"DQUL_2" DQUL0_2 #78
-#LOCATE COMP "OUT_L_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
-#LOCATE COMP "IN_L_SDI" SITE "G5"; #"DQUL_6" DQSUL0_T #86
-#LOCATE COMP "OUT_L_CS" SITE "H6"; #"DQUL_10" DQUL0_8 #94
-
-
-#DEFINE PORT GROUP "IN_group" "IN_*" ;
-#IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
-
-#DEFINE PORT GROUP "OUT_group" "OUT_*" ;
-#IOBUF GROUP "OUT_group" IO_TYPE=LVDS25;
-
#################################################################
# Additional Lines to AddOn
#################################################################
#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
+LOCATE COMP "DAC_SDI" SITE "D4"; #"DQUL_2" DQUL0_2 #78
+LOCATE COMP "DAC_SCK" SITE "C3"; #"DQUL_4" DQUL0_4 #82
+LOCATE COMP "DAC_CS_1" SITE "H6"; #"DQUL_10" DQUL0_8 #94
+LOCATE COMP "DAC_CS_2" SITE "AA24"; #"DQUL_10" DQUL0_8 #94
+LOCATE COMP "DAC_CS_3" SITE "U24"; #"DQUL_10" DQUL0_8 #94
+LOCATE COMP "DAC_CS_4" SITE "U23"; #"DQUL_10" DQUL0_8 #94
+#LOCATE COMP "DAC_SDO" SITE "G5"; #"DQUL_6" DQSUL0_T #86
+
+DEFINE PORT GROUP "DAC_group" "DAC_*" ;
+IOBUF GROUP "DAC_group" IO_TYPE=LVDS25;
+
+#IOBUF PORT "DAC_SDO" IO_TYPE=LVDS25 DIFFRESISTOR=100;
#################################################################
# DAC SPI & Flash ROM & Reboot
LOCATE COMP "PROGRAMN" SITE "B11";
IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#LOCATE COMP "DAC_SDI" SITE "G6"; #"DQUL_7" DQSUL0_C #88 #IN_L_SDIb
-#LOCATE COMP "DAC_SCK" SITE "E4"; #"DQUL_3" DQUL0_3 #80 #OUT_L_SDOb
-#LOCATE COMP "DAC_CS_0" SITE "C3"; #"DQUL_4" DQUL0_4 #82 #OUT_L_SCK
-#LOCATE COMP "DAC_CS_1" SITE "D3"; #"DQUL_5" DQUL0_5 #84 #OUT_L_SCKb
-#LOCATE COMP "DAC_CS_2" SITE "H6"; #"DQUL_10" DQUL0_8 #94 #OUT_L_CS
-#LOCATE COMP "DAC_CS_3" SITE "J6"; #"DQUL_11" DQUL0_9 #96 #OUT_L_CSb
-
-#DEFINE PORT GROUP "DAC_group" "DAC*" ;
-#IOBUF GROUP "DAC_group" IO_TYPE=LVCMOS33 PULLMODE=NONE;
-
#################################################################
# Misc
-- File : Channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-08-28
--- Last update: 2013-06-20
+-- Last update: 2013-06-24
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- File : Readout.vhd
-- Author : cugur@gsi.de
-- Created : 2012-10-25
--- Last update: 2013-05-06
+-- Last update: 2013-06-27
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
end if;
wr_number_fsm <= wr_number + to_unsigned(1, 1);
fifo_nr_wr_fsm <= fifo_nr_wr;
- wr_fsm_debug_fsm <= x"2";
+
elsif fifo_nr_wr = CHANNEL_NUMBER-1 then
wr_ch_data_fsm <= '0';
wr_number_fsm <= (others => '0');
wr_finished_fsm <= '1';
- wr_fsm_debug_fsm <= x"3";
WR_NEXT <= IDLE;
else
wr_number_fsm <= (others => '0');
fifo_nr_wr_fsm <= fifo_nr_wr + 1;
- wr_fsm_debug_fsm <= x"4";
end if;
+ wr_fsm_debug_fsm <= x"2";
--
when others =>
WR_NEXT <= IDLE;
STATUS_REGISTERS_BUS_OUT(16)(23 downto 0) <= std_logic_vector(readout_time);
STATUS_REGISTERS_BUS_OUT(17)(23 downto 0) <= std_logic_vector(timeout_number);
STATUS_REGISTERS_BUS_OUT(18)(23 downto 0) <= std_logic_vector(finished_number);
- STATUS_REGISTERS_BUS_OUT(18)(31 downto 24) <= std_logic_vector(wr_number);
+
FILL_BUS1 : for i in 4 to 17 generate
STATUS_REGISTERS_BUS_OUT(i)(31 downto 24) <= (others => '0');
-- File : Reference_channel_200.vhd
-- Author : c.ugur@gsi.de
-- Created : 2012-09-04
--- Last update: 2013-03-18
+-- Last update: 2013-06-24
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
signal data_a_i : std_logic_vector(303 downto 0);
signal data_b_i : std_logic_vector(303 downto 0);
signal result_i : std_logic_vector(303 downto 0) := (others => '1');
- signal ff_array_en_i : std_logic := '0';
+ signal ff_array_en_i : std_logic := '0';
-- hit detection
signal result_2_reg : std_logic;
TimeStampCapture : process (CLK_200)
begin
if rising_edge(CLK_200) then
- if hit_detect_reg = '1' then
- time_stamp_i <= coarse_cntr_reg;
+ if encoder_finished_i = '1' then
+ time_stamp_i <= std_logic_vector(unsigned(coarse_cntr_reg) - to_unsigned(8, 11));
+ --if hit_detect_reg = '1' then
+ --time_stamp_i <= coarse_cntr_reg;
end if;
end if;
end process TimeStampCapture;
signal run_mode_i : std_logic; -- 1: cc reset every trigger
-- 0: free running mode
signal run_mode_200 : std_logic;
+ signal run_mode_edge_200 : std_logic;
signal trigger_win_en_i : std_logic;
signal ch_en_i : std_logic_vector(64 downto 1);
signal data_limit_i : unsigned(7 downto 0);
UP_IN => '1');
end generate GenCoarseCounter;
- Coarse_Counter_Reset : process (CLK_TDC, reset_tdc)
+ Coarse_Counter_Reset : process (CLK_TDC)
begin
if rising_edge(CLK_TDC) then
- if reset_tdc = '1' then
+ if run_mode_200 = '0' then
+ coarse_cntr_reset <= trg_win_end_i;
+ elsif run_mode_edge_200 = '1' then
coarse_cntr_reset <= '1';
- elsif run_mode_200 = '1' then
- coarse_cntr_reset <= '0';
else
- coarse_cntr_reset <= trg_win_end_i;
+ coarse_cntr_reset <= '0';
end if;
end if;
end process Coarse_Counter_Reset;
-
+
+ Run_Mode_Edge_Detect: risingEdgeDetect
+ port map (
+ CLK => CLK_TDC,
+ SIGNAL_IN => run_mode_200,
+ PULSE_OUT => run_mode_edge_200);
+
GenCoarseCounterReset : for i in 1 to 4 generate
coarse_cntr_reset_r(i) <= coarse_cntr_reset when rising_edge(CLK_TDC);
end generate GenCoarseCounterReset;
COUNT_OUT => epoch_cntr,
UP_IN => epoch_cntr_up_i);
epoch_cntr_up_i <= and_all(coarse_cntr(1));
- epoch_cntr_reset_i <= reset_tdc or coarse_cntr_reset;
+ epoch_cntr_reset_i <= coarse_cntr_reset;
-- Bus handler entities
TheHitCounterBus : BusHandler
SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
INP : in std_logic_vector(63 downto 0);
--DAC_SDO : in std_logic;
- --DAC_SDI : out std_logic;
- --DAC_SCK : out std_logic;
- --DAC_CS : out std_logic_vector(3 downto 0);
+ DAC_SDI : out std_logic;
+ DAC_SCK : out std_logic;
+ DAC_CS : out std_logic_vector(4 downto 1);
--Flash ROM & Reboot
FLASH_CLK : out std_logic;
FLASH_CS : out std_logic;
attribute syn_useioff of INP : signal is false;
attribute syn_useioff of SPARE_LINE : signal is true;
--attribute syn_useioff of DAC_SDO : signal is true;
- --attribute syn_useioff of DAC_SDI : signal is true;
- --attribute syn_useioff of DAC_SCK : signal is true;
- --attribute syn_useioff of DAC_CS : signal is true;
+ attribute syn_useioff of DAC_SDI : signal is true;
+ attribute syn_useioff of DAC_SCK : signal is true;
+ attribute syn_useioff of DAC_CS : signal is true;
end entity;
BROADCAST_BITMASK => x"FF",
BROADCAST_SPECIAL_ADDR => x"48",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000860", -- regio_hardware_version_i,
+ REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i,
REGIO_INIT_ADDRESS => x"f305",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 125,
DEBUG_LVL1_HANDLER_OUT => open
);
- timing_trg_received_i <= TRIGGER_RIGHT; --TRIGGER_LEFT;
+ timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; --
common_stat_reg <= (others => '0');
stat_reg <= (others => '0');
-- SPI connections
SPI_CS_OUT(15 downto 4) => open,
SPI_CS_OUT(3 downto 0) => dac_cs_i,
- SPI_SDI_IN => open,
+ SPI_SDI_IN => '0',
SPI_SDO_OUT => dac_sdi_i,
SPI_SCK_OUT => dac_sck_i);
- --DAC_CS <= open; --dac_cs_i;
- --DAC_SDI <= open; --dac_sdi_i;
- --DAC_SCK <= open; --dac_sck_i;
+ DAC_CS <= dac_cs_i;
+ DAC_SDI <= dac_sdi_i;
+ DAC_SCK <= dac_sck_i;
---------------------------------------------------------------------------
-- Reboot FPGA
THE_TDC : TDC
generic map (
- CHANNEL_NUMBER => 65, -- Number of TDC channels
+ CHANNEL_NUMBER => 5, -- Number of TDC channels
CONTROL_REG_NR => 5) -- Number of control regs - higher than 8 check tdc_ctrl_addr
port map (
RESET => reset_i,
CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(64 downto 1), -- Channel start signals
+ HIT_IN => hit_in_i(4 downto 1), -- Channel start signals
HIT_CALIBRATION => clk_20_i, -- Hits for calibrating the TDC
TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
-- For single edge measurements
--hit_in_i <= INP;
+ hit_in_i <= (others => timing_trg_received_i);
- -- For ToT Measurements
- Gen_Hit_In_Signals : for i in 1 to 32 generate
- hit_in_i(i*2-1) <= INP(i-1);
- hit_in_i(i*2) <= not INP(i-1);
- end generate Gen_Hit_In_Signals;
+ ---- For ToT Measurements
+ --Gen_Hit_In_Signals : for i in 1 to 32 generate
+ -- hit_in_i(i*2-1) <= INP(i-1);
+ -- hit_in_i(i*2) <= not INP(i-1);
+ --end generate Gen_Hit_In_Signals;
-- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!!
end architecture;
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