flash disabled after boot, IF

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index b8de49c040d64d5b4471575b76397388e6b410df..70b86278df4264d2ec8430510f3951d1fa7a4b8e 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -127,7 +127,7 @@ architecture arch of generic_flash_ctrl is
   \r
 \r
   type state_type is (IDLE, EnableFLASH1, EnableFLASH2, EnableFLASH3, Start, ReadPage, WaitFlash1, WaitFlash2, ReadRAM, WaitRAM1, WaitRAM2, WaitRAM3, WaitRAM4,\r
-                      WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI);\r
+                      WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI, DisableFLASH1, DisableFLASH2, DisableFLASH3);\r
   signal state : state_type := IDLE;\r
   signal master_running       : std_logic;\r
   signal master_word_counter  : std_logic_vector(3 downto 0);\r
@@ -435,7 +435,7 @@ begin
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
         else -- break\r
           master_DATA_OUT(15 downto 0) <= x"ff" & ram_data_o;\r
-          state <= IDLE;\r
+          state <= DisableFLASH1;\r
         end if;\r
       when WaitRAM2 =>\r
         master_ADDR_OUT <= ram_data_o;\r
@@ -449,7 +449,9 @@ begin
         master_DATA_OUT(15 downto 0) <= ram_data_o & x"00";\r
         state <= WaitRAM4;\r
       when WaitRAM3_32 =>\r
-        master_DATA_OUT(31 downto 0) <= ram_data_o & x"000000";\r
+        if (DATA_BUS_WIDTH > 31) then\r
+          master_DATA_OUT(31 downto 0) <= ram_data_o & x"000000";\r
+        end if;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
         state <= WaitRAM4_32;\r
       when WaitRAM4 =>\r
@@ -457,16 +459,22 @@ begin
         state <= WriteSPI;\r
         master_WRITE_OUT <= '1';\r
       when WaitRAM4_32 =>\r
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 24) & ram_data_o & x"0000";\r
+        if (DATA_BUS_WIDTH > 31) then\r
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 24) & ram_data_o & x"0000";\r
+        end if;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
         state <= WaitRAM5_32;\r
       when WaitRAM5_32 =>\r
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 16) & ram_data_o & x"00";\r
+        if (DATA_BUS_WIDTH > 31) then\r
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 16) & ram_data_o & x"00";\r
+        end if;\r
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 2);\r
                -- padding bytes\r
         state <= WaitRAM6_32;\r
       when WaitRAM6_32 =>\r
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 8) & ram_data_o;\r
+        if (DATA_BUS_WIDTH > 31) then\r
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 8) & ram_data_o;\r
+        end if;\r
         state <= WriteSPI;\r
         master_WRITE_OUT <= '1';\r
       when WriteSPI =>\r
@@ -480,6 +488,19 @@ begin
           state <= ReadRAM;\r
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);\r
         end if;\r
+      when DisableFLASH1 =>\r
+        state <= DisableFLASH2;\r
+        master_flash_command <= "101";\r
+        master_flash_go <= '1';\r
+      when DisableFLASH2 =>\r
+        state <= DisableFLASH3;\r
+        master_flash_go <= '0';\r
+      when DisableFLASH3 =>\r
+        if (flash_busy = '0') then\r
+           state <= IDLE;\r
+           master_flash_command <= "000";\r
+        end if;\r
+                             \r
     end case;\r
   end if;\r
 end process;\r