added last header func. to iobuf / untested, Jan

diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd
index e9c3da3fa9c32aa724181b470cab9a29fce5feca..493eee508e075fe10016ffe18928187719c9f4a4 100644 (file)
--- a/trb_net16_ibuf.vhd
+++ b/trb_net16_ibuf.vhd
@@ -38,6 +38,7 @@ entity trb_net16_ibuf is
     INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
     INT_REPLY_DATAREADY_OUT : out std_logic;
     INT_REPLY_READ_IN       : in  std_logic;
+    INT_REPLY_HEADER_IN     : in  std_logic;    
     INT_ERROR_OUT           : out std_logic_vector (2 downto 0);
     -- Status and control port
     STAT_BUFFER             : out std_logic_vector (31 downto 0)
@@ -92,6 +93,26 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is
       );
   end component;
 
+  component trb_net_ram is
+    generic(
+      depth : integer := 4;
+      width : integer := 16
+      );
+    port(
+      CLK    : in std_logic;
+      wr     : in std_logic;
+      ain    : in std_logic_vector(depth-1 downto 0);
+      din    : in std_logic_vector(width-1 downto 0);
+      aout   : in std_logic_vector(depth-1 downto 0);
+      dout   : out std_logic_vector(width-1 downto 0)
+      );
+  end component;  
+  
+  signal last_header_addr : std_logic_vector(1 downto 0);
+  signal reg_last_header_addr :  std_logic_vector(1 downto 0);
+  signal last_header_data : std_logic_vector(15 downto 0); 
+  signal reg_INT_REPLY_HEADER_IN, next_reg_INT_REPLY_HEADER_IN : std_logic;
+  signal sending_last_header, next_sending_last_header : std_logic;
   signal fifo_data_in          : std_logic_vector(c_DATA_WIDTH-1 downto 0);
   signal fifo_data_out         : std_logic_vector(c_DATA_WIDTH-1 downto 0);
   signal fifo_packet_num_in    : std_logic_vector(c_NUM_WIDTH-1  downto 0);
@@ -117,15 +138,13 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is
   signal tmp_INT_REPLY_DATAREADY_OUT: std_logic;
   signal tmp_INT_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
   signal tmp_INT_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
-  signal current_last_header_F1, current_last_header_F2, current_last_header_F3 : std_logic_vector(15 downto 0);
-  signal next_last_header_F1, next_last_header_F2, next_last_header_F3 : std_logic_vector(15 downto 0);
+
   signal reading_header : std_logic;
   
   type ERROR_STATE is (IDLE, GOT_OVERFLOW_ERROR, GOT_UNDEFINED_ERROR);
   signal current_error_state, next_error_state : ERROR_STATE;
   signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0);
-  signal buf_INT_INIT_DATAREADY_OUT : std_logic;
-  signal buf_INT_REPLY_DATAREADY_OUT : std_logic;
+
 
   signal last_fifo_read : std_logic;
   signal throw_away : std_logic;
@@ -291,17 +310,19 @@ begin
    INT_INIT_DATA_OUT <= tmp_INT_DATA_OUT;
    INT_INIT_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
    INT_INIT_DATAREADY_OUT <= tmp_INT_INIT_DATAREADY_OUT;
-   sbuf_INIT_free <= '1';
+   sbuf_INIT_free <= INT_INIT_READ_IN;
    INT_REPLY_DATA_OUT <= tmp_INT_DATA_OUT;
    INT_REPLY_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT;
    INT_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT;
-   sbuf_REPLY_free <= '1';
+   sbuf_REPLY_free <= INT_REPLY_READ_IN;
   end generate;
 
 
   process(fifo_data_out, fifo_packet_num_out, sbuf_init_free, 
           fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type,
-          fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN)
+          fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, 
+                        sending_last_header, last_header_addr, reg_INT_REPLY_HEADER_IN, 
+                        INT_REPLY_HEADER_IN, last_header_data, reg_last_header_addr)
     begin
       tmp_INT_DATA_OUT <= fifo_data_out;
       tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out;
@@ -310,16 +331,36 @@ begin
       got_eob_init_out <= '0';
       got_eob_reply_out <= '0';
       throw_away <= '0';
+      next_sending_last_header <= sending_last_header;
+      next_reg_INT_REPLY_HEADER_IN <= reg_INT_REPLY_HEADER_IN or INT_REPLY_HEADER_IN;
 
       fifo_read <= not fifo_empty and not (fifo_read_before and not 
                       ((INT_INIT_READ_IN and not current_fifo_packet_type(3)) 
                       or (INT_REPLY_READ_IN and current_fifo_packet_type(3)) or throw_away));
 
+      if reg_INT_REPLY_HEADER_IN = '1' and fifo_packet_num_out = "11" then
+                   next_reg_INT_REPLY_HEADER_IN <= '0';
+        fifo_read <= '0';
+        next_sending_last_header <= '1';
+      end if;
+
+      
       if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then
         tmp_INT_INIT_DATAREADY_OUT <=  sbuf_init_free and not current_fifo_packet_type(3);
         tmp_INT_REPLY_DATAREADY_OUT <=  sbuf_reply_free and current_fifo_packet_type(3);
       end if;
 
+      if sending_last_header = '1' then
+        tmp_INT_REPLY_DATAREADY_OUT <= '1';
+        tmp_INT_DATA_OUT <= last_header_data;
+        tmp_INT_PACKET_NUM_OUT <= reg_last_header_addr;
+        if tmp_INT_REPLY_DATAREADY_OUT = '1' and sbuf_REPLY_free = '1' then
+          if last_header_addr = "11" then
+            next_sending_last_header <= '0';
+          end if;
+        end if;
+      end if;
+      
       if last_fifo_read = '1' then
         if current_fifo_packet_type(2 downto 0) = TYPE_EOB then
           throw_away <= '1';
@@ -344,7 +385,35 @@ begin
         end if;
       end if;
     end process;
-
+    
+   process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          last_header_addr <= "00";
+        elsif sending_last_header = '1' and sbuf_REPLY_free = '1' then
+          last_header_addr <= last_header_addr + 1;
+        end if;
+      end if;
+    end process;
+    
+   process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          reg_INT_REPLY_HEADER_IN <= '0';
+          reg_last_header_addr <= "00";
+--          last_header_addr <= "00";
+                        sending_last_header <= '0';
+        else
+          reg_INT_REPLY_HEADER_IN <= next_reg_INT_REPLY_HEADER_IN;
+          reg_last_header_addr <= last_header_addr;
+--          last_header_addr <= next_last_header_addr;
+                        sending_last_header <= next_sending_last_header;
+        end if;
+      end if;
+    end process;
+    
    process(CLK)
     begin
       if rising_edge(CLK) then
@@ -353,8 +422,8 @@ begin
         else
           if fifo_read = '1' then
             fifo_read_before <= '1';
-          elsif (   (INT_INIT_READ_IN and not current_fifo_packet_type(3)) 
-                 or (INT_REPLY_READ_IN and current_fifo_packet_type(3)) or throw_away) = '1' then
+          elsif (   (sbuf_INIT_free and not current_fifo_packet_type(3)) 
+                 or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then
             fifo_read_before <= '0';
           end if;
         end if;
@@ -378,37 +447,22 @@ begin
   end generate;
 
 --saving last HDR
-  -- reading_header <= '1' when (current_fifo_packet_type = TYPE_HDR and fifo_empty = '0') else '0';
-   -- reg_hdr_f1: process(CLK)
-     -- begin
-      -- if rising_edge(CLK) then
-        -- if RESET = '1' then
-          -- current_last_header_F1 <= (others => '0');
-        -- elsif reading_header = '1' and fifo_packet_num_out = "01" then
-          -- current_last_header_F1 <= fifo_data_out;
-        -- end if;
-      -- end if;
-     -- end process;
-   -- reg_hdr_f2: process(CLK)
-     -- begin
-      -- if rising_edge(CLK) then
-        -- if RESET = '1' then
-          -- current_last_header_F2 <= (others => '0');
-        -- elsif reading_header = '1' and fifo_packet_num_out = "10" then
-          -- current_last_header_F2 <= fifo_data_out;
-        -- end if;
-      -- end if;
-     -- end process;
-   -- reg_hdr_f3: process(CLK)
-     -- begin
-      -- if rising_edge(CLK) then
-        -- if RESET = '1' then
-          -- current_last_header_F3 <= (others => '0');
-        -- elsif reading_header = '1' and fifo_packet_num_out = "11" then
-          -- current_last_header_F3 <= fifo_data_out;
-        -- end if;
-      -- end if;
-     -- end process;
+  last_HDR_RAM : trb_net_ram
+    generic map(
+      depth => 2,
+      width => 16
+      )
+    port map(
+      CLK    => CLK,
+      wr     => reading_header,
+      ain    => fifo_packet_num_out,
+      din    => fifo_data_out,
+      aout   => last_header_addr,
+      dout   => last_header_data
+      );
+
+  reading_header <= '1' when (current_fifo_packet_type = TYPE_HDR and fifo_empty = '0') else '0';
+
 
   
 -- make STAT_BUFFER

diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd
index bd2be1f7ee00df1bfe105c18a710471deb7a28af..8147820c5b336a430e8d9d89d41a97ad496499e0 100644 (file)
--- a/trb_net16_iobuf.vhd
+++ b/trb_net16_iobuf.vhd
@@ -153,6 +153,7 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is
       INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0);
       INT_REPLY_DATAREADY_OUT : out std_logic;
       INT_REPLY_READ_IN       : in  std_logic;
+      INT_REPLY_HEADER_IN     : in  std_logic;
       INT_ERROR_OUT           : out std_logic_vector (2 downto 0);
       -- Status and control port
       STAT_BUFFER             : out std_logic_vector (31 downto 0)
@@ -226,6 +227,7 @@ begin
         INT_REPLY_DATA_OUT => INT_REPLY_DATA_OUT,
         INT_REPLY_PACKET_NUM_OUT => INT_REPLY_PACKET_NUM_OUT,
         INT_REPLY_READ_IN => INT_REPLY_READ_IN,
+        INT_REPLY_HEADER_IN => INT_REPLY_HEADER_IN,
         INT_ERROR_OUT => IBUF_error,
         STAT_BUFFER(31 downto 0) => IBUF_stat_buffer
         );

diff --git a/trb_net_ram.vhd b/trb_net_ram.vhd
new file mode 100644 (file)
index 0000000..5ee0c66
--- /dev/null
+++ b/trb_net_ram.vhd
@@ -0,0 +1,38 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_ram is
+  generic(
+    depth : integer := 3;
+    width : integer := 16
+    );
+  port(
+    CLK    : in std_logic;
+    wr     : in std_logic;
+    ain    : in std_logic_vector(depth-1 downto 0);
+    din    : in std_logic_vector(width-1 downto 0);
+    aout   : in std_logic_vector(depth-1 downto 0);
+    dout   : out std_logic_vector(width-1 downto 0)
+    );
+end entity;
+
+architecture trb_net_ram_arch of trb_net_ram is
+  type ram_t is array(0 to 2**depth-1) of std_logic_vector(width-1 downto 0);
+       SIGNAL ram : ram_t;
+
+begin
+  process(CLK) 
+    begin
+      if rising_edge(CLK) then
+        if wr = '1' then
+          ram(conv_integer((ain))) <= din;
+        end if;
+        dout <= ram(conv_integer((aout)));
+      end if;
+    end process;
+end architecture;