update

diff --git a/base/code/adc_ad9222.vhd b/base/code/adc_ad9222.vhd
index 6b8a52ee39fbad7a1a879043b1b6e503dd431e77..764a28b05f92e607a86cf062c180eccada516d10 100644 (file)
--- a/base/code/adc_ad9222.vhd
+++ b/base/code/adc_ad9222.vhd
@@ -10,7 +10,7 @@ use work.trb3_components.all;
 entity adc_ad9222 is
   generic(
     CHANNELS : integer range 4 to 4 := 4;
-    DEVICES  : integer range 2 to 2 := 2;
+    DEVICES  : integer range 1 to 2 := 1;
     RESOLUTION : integer range 12 to 12 := 12
     );
   port(
@@ -102,14 +102,14 @@ gen_1 : if DEVICES = 1 generate
       sclk => clk_data,
       datain(3 downto 0) => ADC_DATA(3 downto 0),
       datain(4)          => ADC_FCO(0),
-      q => data_in(19 downto 0),
+      q => data_in(19 downto 0)
       );
 end generate;
 
 
 
 
-  gen_chips : for i in 0 to 1 generate
+  gen_chips : for i in 0 to DEVICES-1 generate
     THE_FIFO : fifo_cdt_200
       port map(
         Data     => cdt_data_in(i),
@@ -198,4 +198,4 @@ end generate;
   DEBUG(14)          <= clk_data;
   DEBUG(15)          <= DATA_VALID_OUT(1);
   
-end architecture;
\ No newline at end of file
+end architecture;