]> jspc29.x-matter.uni-frankfurt.de Git - adcm.git/commitdiff
rearrangement of files
authorLudwig Maier <lmaier@crius.e12.ph.tum.de>
Thu, 19 Dec 2013 12:39:18 +0000 (13:39 +0100)
committerLudwig Maier <lmaier@crius.e12.ph.tum.de>
Thu, 19 Dec 2013 12:39:18 +0000 (13:39 +0100)
262 files changed:
0x4c168bfe/adcmv3.lpf [changed mode: 0755->0644]
adcmv3.lpf [new file with mode: 0755]
adcmv3.prj [changed mode: 0755->0644]
adcmv3.vhd [moved from design/adcmv3.vhd with 100% similarity, mode: 0644]
cleanup_workdir.sh [new file with mode: 0755]
compile.pl
compile_munich21.pl [moved from compile_ORIG.pl with 52% similarity]
compile_munich21.sh [new file with mode: 0755]
constraints_adcmv3.lpf [changed mode: 0755->0644]
constraints_adcmv3_BACK.lpf [changed mode: 0755->0644]
cores/adc_apv_map_mem.lpc [moved from design/adc_apv_map_mem.lpc with 100% similarity]
cores/adc_apv_map_mem.vhd [moved from design/adc_apv_map_mem.vhd with 100% similarity]
cores/adc_ch_in.lpc [moved from design/adc_ch_in.lpc with 100% similarity]
cores/adc_ch_in.vhd [moved from design/adc_ch_in.vhd with 100% similarity]
cores/adc_onewire_map_mem.lpc [moved from design/adc_onewire_map_mem.lpc with 100% similarity]
cores/adc_onewire_map_mem.vhd [moved from design/adc_onewire_map_mem.vhd with 100% similarity]
cores/adc_pll.lpc [moved from design/adc_pll.lpc with 100% similarity]
cores/adc_pll.vhd [moved from design/adc_pll.vhd with 100% similarity]
cores/adc_snoop_mem.lpc [moved from design/adc_snoop_mem.lpc with 100% similarity]
cores/adc_snoop_mem.vhd [moved from design/adc_snoop_mem.vhd with 100% similarity]
cores/apv_adc_map_mem.lpc [moved from design/apv_adc_map_mem.lpc with 100% similarity]
cores/apv_adc_map_mem.vhd [moved from design/apv_adc_map_mem.vhd with 100% similarity]
cores/apv_map_mem.lpc [moved from design/apv_map_mem.lpc with 100% similarity]
cores/apv_map_mem.vhd [moved from design/apv_map_mem.vhd with 100% similarity]
cores/crossover.lpc [moved from design/crossover.lpc with 100% similarity]
cores/crossover.vhd [moved from design/crossover.vhd with 100% similarity]
cores/decoder_8bit.lpc [moved from design/decoder_8bit.lpc with 100% similarity]
cores/decoder_8bit.mem [moved from design/decoder_8bit.mem with 100% similarity]
cores/decoder_8bit.vhd [moved from design/decoder_8bit.vhd with 100% similarity]
cores/dll_100m.lpc [moved from design/dll_100m.lpc with 100% similarity]
cores/dll_100m.vhd [moved from design/dll_100m.vhd with 100% similarity]
cores/dpram_8x19.lpc [moved from design/dpram_8x19.lpc with 100% similarity]
cores/dpram_8x19.vhd [moved from design/dpram_8x19.vhd with 100% similarity]
cores/eds_buffer_dpram.lpc [moved from design/eds_buffer_dpram.lpc with 100% similarity]
cores/eds_buffer_dpram.vhd [moved from design/eds_buffer_dpram.vhd with 100% similarity]
cores/fifo_16x11.lpc [moved from design/fifo_16x11.lpc with 100% similarity]
cores/fifo_16x11.vhd [moved from design/fifo_16x11.vhd with 100% similarity]
cores/fifo_1kx18.lpc [moved from design/fifo_1kx18.lpc with 100% similarity]
cores/fifo_1kx18.vhd [moved from design/fifo_1kx18.vhd with 100% similarity]
cores/fifo_2kx27.lpc [moved from design/fifo_2kx27.lpc with 100% similarity]
cores/fifo_2kx27.vhd [moved from design/fifo_2kx27.vhd with 100% similarity]
cores/frame_status_mem.lpc [moved from design/frame_status_mem.lpc with 100% similarity]
cores/frame_status_mem.vhd [moved from design/frame_status_mem.vhd with 100% similarity]
cores/input_bram.lpc [moved from design/input_bram.lpc with 100% similarity]
cores/input_bram.vhd [moved from design/input_bram.vhd with 100% similarity]
cores/mult_3x8.lpc [moved from design/mult_3x8.lpc with 100% similarity]
cores/mult_3x8.vhd [moved from design/mult_3x8.vhd with 100% similarity]
cores/onewire_spare_one.lpc [moved from design/onewire_spare_one.lpc with 100% similarity]
cores/onewire_spare_one.vhd [moved from design/onewire_spare_one.vhd with 100% similarity]
cores/ped_thr_true.lpc [moved from design/ped_thr_true.lpc with 100% similarity]
cores/ped_thr_true.vhd [moved from design/ped_thr_true.vhd with 100% similarity]
cores/pll_40m.lpc [moved from design/pll_40m.lpc with 100% similarity]
cores/pll_40m.vhd [moved from design/pll_40m.vhd with 100% similarity]
cores/slv_onewire_dpram.lpc [moved from design/slv_onewire_dpram.lpc with 100% similarity]
cores/slv_onewire_dpram.vhd [moved from design/slv_onewire_dpram.vhd with 100% similarity]
cores/sync_pll_40m.lpc [moved from design/sync_pll_40m.lpc with 100% similarity]
cores/sync_pll_40m.vhd [moved from design/sync_pll_40m.vhd with 100% similarity]
cores/test_fifo.lpc [moved from design/test_fifo.lpc with 100% similarity]
cores/test_fifo.vhd [moved from design/test_fifo.vhd with 100% similarity]
cores/test_fifo2.lpc [moved from design/test_fifo2.lpc with 100% similarity]
cores/test_fifo2.vhd [moved from design/test_fifo2.vhd with 100% similarity]
cores/testfifo.lpc [moved from design/testfifo.lpc with 100% similarity]
cores/testfifo.vhd [moved from design/testfifo.vhd with 100% similarity]
debug_pin.txt [changed mode: 0755->0644]
featurelist.txt [changed mode: 0755->0644]
howto_adcm_i2c.txt [changed mode: 0755->0644]
lever/.recordref [changed mode: 0755->0644]
lever/adcmv3.ini [changed mode: 0755->0644]
lever/adcmv3.jid [changed mode: 0755->0644]
lever/adcmv3.lci [changed mode: 0755->0644]
lever/adcmv3.lct [changed mode: 0755->0644]
lever/adcmv3.lpf [changed mode: 0755->0644]
lever/adcmv3.mt [changed mode: 0755->0644]
lever/adcmv3.pt [changed mode: 0755->0644]
lever/adcmv3.rev [changed mode: 0755->0644]
lever/adcmv3.rvp [changed mode: 0755->0644]
lever/adcmv3.sty [changed mode: 0755->0644]
lever/adcmv3.syn [changed mode: 0755->0644]
lever/adcmv3.syn.bak [changed mode: 0755->0644]
lever/adcmv3.tcl [changed mode: 0755->0644]
lever/adcmv3_tcl.ini [changed mode: 0755->0644]
lever/chipsim.err [changed mode: 0755->0644]
lever/fifo_18x16_media_interface.vht [changed mode: 0755->0644]
lever/fifo_18x16_media_interface_mb.vht [changed mode: 0755->0644]
lever/pre.clr [changed mode: 0755->0644]
lever/run_options.txt [changed mode: 0755->0644]
lever/sbuf.cmd [changed mode: 0755->0644]
lever/sbuf.edi [changed mode: 0755->0644]
lever/sbuf.fse [changed mode: 0755->0644]
lever/sbuf.srd [changed mode: 0755->0644]
lever/sbuf.srf [changed mode: 0755->0644]
lever/sbuf.szr [changed mode: 0755->0644]
lever/syntmp/hdlorder.tcl [changed mode: 0755->0644]
lever/syntmp/sbuf.plg [changed mode: 0755->0644]
lever/tb_apv_trgctrl.rsp [changed mode: 0755->0644]
lever/tb_apv_trgctrl_activehdl.do [changed mode: 0755->0644]
lever/tb_apv_trgctrl_activehdl2.do [changed mode: 0755->0644]
lever/tb_apv_trgctrl_vhdf.udo [changed mode: 0755->0644]
lever/tb_media_fifo.rsp [changed mode: 0755->0644]
lever/tb_media_fifo_activehdl.do [changed mode: 0755->0644]
lever/tb_media_fifo_activehdl2.do [changed mode: 0755->0644]
lever/tb_media_fifo_mb.rsp [changed mode: 0755->0644]
lever/tb_media_fifo_mb_activehdl.do [changed mode: 0755->0644]
lever/tb_media_fifo_mb_activehdl2.do [changed mode: 0755->0644]
lever/tb_media_fifo_mb_vhdf.udo [changed mode: 0755->0644]
lever/tb_media_fifo_vhdf.udo [changed mode: 0755->0644]
lever/tb_ped_corr_ctrl.rsp [changed mode: 0755->0644]
lever/tb_ped_corr_ctrl_activehdl.do [changed mode: 0755->0644]
lever/tb_ped_corr_ctrl_activehdl2.do [changed mode: 0755->0644]
lever/tb_ped_corr_ctrl_vhdf.udo [changed mode: 0755->0644]
lever/tb_sfp_rx_handler.rsp [changed mode: 0755->0644]
lever/tb_sfp_rx_handler_activehdl.do [changed mode: 0755->0644]
lever/tb_sfp_rx_handler_activehdl2.do [changed mode: 0755->0644]
lever/tb_sfp_rx_handler_vhdf.udo [changed mode: 0755->0644]
lever/tb_spi_master.fado [changed mode: 0755->0644]
lever/tb_spi_master.rsp [changed mode: 0755->0644]
lever/tb_spi_master_activehdl.do [changed mode: 0755->0644]
lever/tb_spi_master_activehdl2.do [changed mode: 0755->0644]
lever/tb_spi_master_vhdf.udo [changed mode: 0755->0644]
lever/tb_test_media.rsp [changed mode: 0755->0644]
lever/tb_test_media_activehdl.do [changed mode: 0755->0644]
lever/tb_test_media_activehdl2.do [changed mode: 0755->0644]
lever/tb_test_media_vhdf.udo [changed mode: 0755->0644]
lever/test_media.vht [changed mode: 0755->0644]
lever/udo.rsp [changed mode: 0755->0644]
lever/work.sbuf.prj [changed mode: 0755->0644]
lever/work/0work.mgf [changed mode: 0755->0644]
lever/work/1work.mgf [changed mode: 0755->0644]
lever/work/3work.mgf [changed mode: 0755->0644]
lever/work/Edfmap.ini [changed mode: 0755->0644]
lever/work/compilation.order [changed mode: 0755->0644]
lever/work/compile.cfg [changed mode: 0755->0644]
lever/work/compile/contents.lib~work [deleted file]
lever/work/compile/sources.sth [changed mode: 0755->0644]
lever/work/compile/work.cmd [changed mode: 0755->0644]
lever/work/compile/work.epr [changed mode: 0755->0644]
lever/work/compile/work.erf [changed mode: 0755->0644]
lever/work/library.cfg [changed mode: 0755->0644]
lever/work/projlib.cfg [changed mode: 0755->0644]
lever/work/work.LIB [changed mode: 0755->0644]
lever/work/work.adf [changed mode: 0755->0644]
lever/work/work.aws [changed mode: 0755->0644]
lever/work/work.wsp [changed mode: 0755->0644]
lever/work/work.wsw [changed mode: 0755->0644]
sim/tb_adc_cross.vhd [changed mode: 0755->0644]
sim/tb_adc_crossover.vhd [changed mode: 0755->0644]
sim/tb_adc_handler.vhd [changed mode: 0755->0644]
sim/tb_adc_handler.vhd.bak [changed mode: 0755->0644]
sim/tb_apv_locker.vhd [changed mode: 0755->0644]
sim/tb_apv_pc_nc_alu.vhd [changed mode: 0755->0644]
sim/tb_apv_trgctrl.vhd [changed mode: 0755->0644]
sim/tb_apv_trgctrl.vhd.bak [changed mode: 0755->0644]
sim/tb_apv_trgctrl_000.vhd [changed mode: 0755->0644]
sim/tb_crossfifo.vhd [changed mode: 0755->0644]
sim/tb_crossover.vhd [changed mode: 0755->0644]
sim/tb_ipu_fifo_stage.vhd [changed mode: 0755->0644]
sim/tb_ipu_fifo_stage.vhd.bak [changed mode: 0755->0644]
sim/tb_ipu_fifo_stage_COPY.vhd [changed mode: 0755->0644]
sim/tb_ipu_fifo_stage_OLD.vhd [changed mode: 0755->0644]
sim/tb_logic_analyzer.vhd [changed mode: 0755->0644]
sim/tb_max_data.vhd [changed mode: 0755->0644]
sim/tb_media_fifo.vhd [changed mode: 0755->0644]
sim/tb_media_fifo.vhd.bak [changed mode: 0755->0644]
sim/tb_media_fifo_mb.vhd [changed mode: 0755->0644]
sim/tb_media_fifo_mb.vhd.bak [changed mode: 0755->0644]
sim/tb_mult_3x8.vhd [changed mode: 0755->0644]
sim/tb_my_sbuf.vhd [changed mode: 0755->0644]
sim/tb_onewire_master.vhd [changed mode: 0755->0644]
sim/tb_ped_corr_ctrl.vhd [changed mode: 0755->0644]
sim/tb_ped_corr_ctrl.vhd.bak [changed mode: 0755->0644]
sim/tb_ped_corr_ctrl_OLD.vhd [changed mode: 0755->0644]
sim/tb_pulse_stretch.vhd [changed mode: 0755->0644]
sim/tb_pulse_sync.vhd [changed mode: 0755->0644]
sim/tb_raw_buf_stage.vhd [changed mode: 0755->0644]
sim/tb_raw_buf_stage_new.vhd [changed mode: 0755->0644]
sim/tb_real_trg_handler.vhd [changed mode: 0755->0644]
sim/tb_reboot_handler.vhd [changed mode: 0755->0644]
sim/tb_reset_handler.vhd [changed mode: 0755->0644]
sim/tb_sfp_rx_handler.vhd [changed mode: 0755->0644]
sim/tb_sfp_rx_handler.vhd.bak [changed mode: 0755->0644]
sim/tb_slv_adc_la.vhd [changed mode: 0755->0644]
sim/tb_slv_adc_snoop.vhd [changed mode: 0755->0644]
sim/tb_slv_onewire_memory.vhd [changed mode: 0755->0644]
sim/tb_slv_ped_thr_mem.vhd [changed mode: 0755->0644]
sim/tb_slv_register_bank.vhd [changed mode: 0755->0644]
sim/tb_spi_master.vhd [changed mode: 0755->0644]
sim/tb_spi_master.vhd.bak [changed mode: 0755->0644]
sim/tb_spi_master_0.vhd [changed mode: 0755->0644]
sim/tb_spi_real_slim.vhd [changed mode: 0755->0644]
sim/tb_test_media.vhd [changed mode: 0755->0644]
sim/tb_test_media.vhd.bak [changed mode: 0755->0644]
sim/tb_trb_net16_ibuf2.vhd [changed mode: 0755->0644]
sim/tb_trb_net_sbuf2.vhd [changed mode: 0755->0644]
sim/tb_trb_net_sbuf3.vhd [changed mode: 0755->0644]
source/adc_apv_mapping.mem [moved from design/adc_apv_mapping.mem with 100% similarity]
source/adc_channel_select.vhd [moved from design/adc_channel_select.vhd with 100% similarity]
source/adc_crossover.vhd [moved from design/adc_crossover.vhd with 100% similarity, mode: 0644]
source/adc_data_handler.vhd [moved from design/adc_data_handler.vhd with 100% similarity, mode: 0644]
source/adc_onewire_mapping.mem [moved from design/adc_onewire_mapping.mem with 100% similarity]
source/adc_twochannels.vhd [moved from design/adc_twochannels.vhd with 100% similarity]
source/adcmv3_components.vhd [moved from design/adcmv3_components.vhd with 100% similarity, mode: 0644]
source/adcmv3_testfifo.vhd [moved from design/adcmv3_testfifo.vhd with 100% similarity]
source/apv_adc_mapping.mem [moved from design/apv_adc_mapping.mem with 100% similarity]
source/apv_digital.vhd [moved from design/apv_digital.vhd with 100% similarity]
source/apv_lock_sm.vhd [moved from design/apv_lock_sm.vhd with 100% similarity]
source/apv_locker.vhd [moved from design/apv_locker.vhd with 100% similarity]
source/apv_mapping.mem [moved from design/apv_mapping.mem with 100% similarity]
source/apv_pc_nc_alu.vhd [moved from design/apv_pc_nc_alu.vhd with 100% similarity, mode: 0644]
source/apv_raw_buffer.vhd [moved from design/apv_raw_buffer.vhd with 100% similarity, mode: 0644]
source/apv_sync_handler.vhd [moved from design/apv_sync_handler.vhd with 100% similarity]
source/apv_trg_handler.vhd [moved from design/apv_trg_handler.vhd with 100% similarity]
source/apv_trgctrl.vhd [moved from design/apv_trgctrl.vhd with 100% similarity, mode: 0644]
source/buf_toc.vhd [moved from design/buf_toc.vhd with 100% similarity]
source/dbg_reg.vhd [moved from design/dbg_reg.vhd with 100% similarity, mode: 0644]
source/eds_buf.vhd [moved from design/eds_buf.vhd with 100% similarity]
source/frmctr_check.vhd [moved from design/frmctr_check.vhd with 100% similarity]
source/i2c_gstart.vhd [moved from design/i2c_gstart.vhd with 100% similarity]
source/i2c_master.vhd [moved from design/i2c_master.vhd with 100% similarity]
source/i2c_sendb.vhd [moved from design/i2c_sendb.vhd with 100% similarity]
source/i2c_slim.vhd [moved from design/i2c_slim.vhd with 100% similarity]
source/ipu_fifo_stage.vhd [moved from design/ipu_fifo_stage.vhd with 100% similarity, mode: 0644]
source/ipu_fifo_stage_BACK.vhd [moved from design/ipu_fifo_stage_BACK.vhd with 100% similarity]
source/logic_analyzer.vhd [moved from design/logic_analyzer.vhd with 100% similarity]
source/max_data.vhd [moved from design/max_data.vhd with 100% similarity]
source/my_sbuf.vhd [moved from design/my_sbuf.vhd with 100% similarity]
source/onewire_master.vhd [moved from design/onewire_master.vhd with 100% similarity]
source/ped_corr_ctrl.vhd [moved from design/ped_corr_ctrl.vhd with 100% similarity, mode: 0644]
source/ped_thr_mem.mem [moved from design/ped_thr_mem.mem with 100% similarity]
source/pulse_stretch.vhd [moved from design/pulse_stretch.vhd with 100% similarity, mode: 0644]
source/pulse_sync.vhd [moved from design/pulse_sync.vhd with 100% similarity, mode: 0644]
source/raw_buf_stage.vhd [moved from design/raw_buf_stage.vhd with 100% similarity, mode: 0644]
source/real_trg_handler.vhd [moved from design/real_trg_handler.vhd with 100% similarity, mode: 0644]
source/real_trg_handler_BACKUP.vhd [moved from design/real_trg_handler_BACKUP.vhd with 100% similarity, mode: 0644]
source/reboot_handler.vhd [moved from design/reboot_handler.vhd with 100% similarity, mode: 0644]
source/ref_row_sel.vhd [moved from design/ref_row_sel.vhd with 100% similarity]
source/replacement.vhd [moved from design/replacement.vhd with 100% similarity]
source/reset_handler.vhd [moved from design/reset_handler.vhd with 100% similarity, mode: 0644]
source/rich_trb.vhd [moved from design/rich_trb.vhd with 98% similarity, mode: 0644]
source/sbuf.vhd [moved from design/sbuf.vhd with 100% similarity, mode: 0644]
source/sfp_rx_handler.vhd [moved from design/sfp_rx_handler.vhd with 100% similarity, mode: 0644]
source/sfp_rx_handler_BACK2.vhd [moved from design/sfp_rx_handler_BACK2.vhd with 100% similarity, mode: 0644]
source/sfp_rx_handler_BACK_0.vhd [moved from design/sfp_rx_handler_BACK_0.vhd with 100% similarity, mode: 0644]
source/slave_bus.vhd [moved from design/slave_bus.vhd with 100% similarity, mode: 0644]
source/slv_adc_la.vhd [moved from design/slv_adc_la.vhd with 100% similarity]
source/slv_adc_snoop.vhd [moved from design/slv_adc_snoop.vhd with 100% similarity]
source/slv_half_register.vhd [moved from design/slv_half_register.vhd with 100% similarity]
source/slv_memory_true.vhd [moved from design/slv_memory_true.vhd with 100% similarity]
source/slv_onewire_memory.vhd [moved from design/slv_onewire_memory.vhd with 100% similarity, mode: 0644]
source/slv_ped_thr_mem.vhd [moved from design/slv_ped_thr_mem.vhd with 100% similarity]
source/slv_register.vhd [moved from design/slv_register.vhd with 100% similarity]
source/slv_register_bank.vhd [moved from design/slv_register_bank.vhd with 100% similarity]
source/slv_status.vhd [moved from design/slv_status.vhd with 100% similarity]
source/slv_status_bank.vhd [moved from design/slv_status_bank.vhd with 100% similarity]
source/spare_onewire_mapping.mem [moved from design/spare_onewire_mapping.mem with 100% similarity]
source/spi_adc_master.vhd [moved from design/spi_adc_master.vhd with 100% similarity]
source/spi_real_slim.vhd [moved from design/spi_real_slim.vhd with 100% similarity]
source/state_sync.vhd [moved from design/state_sync.vhd with 100% similarity, mode: 0644]
source/tb_count_unit.vhd [moved from design/tb_count_unit.vhd with 100% similarity, mode: 0644]
source/tb_count_unit.vhd.bak [moved from design/tb_count_unit.vhd.bak with 100% similarity, mode: 0644]
source/test_media.vhd [moved from design/test_media.vhd with 100% similarity, mode: 0644]
test.txt [changed mode: 0755->0644]
tunnel.sh [changed mode: 0644->0755]

old mode 100755 (executable)
new mode 100644 (file)
diff --git a/adcmv3.lpf b/adcmv3.lpf
new file mode 100755 (executable)
index 0000000..c701a7c
--- /dev/null
@@ -0,0 +1,472 @@
+######################################################################\r
+# ADCMv3 pinouts\r
+######################################################################\r
+\r
+COMMERCIAL;\r
+BLOCK RESETPATHS;\r
+BLOCK ASYNCPATHS;\r
+\r
+######################################################################\r
+# I/O bank 8 - 3.30V\r
+# JTAG and SPI boot interface\r
+######################################################################\r
+#\r
+# These signals are not user definable! Hands off!\r
+\r
+######################################################################\r
+# I/O bank 7 - 2.50V\r
+# APV1 control signals, ADC1 inputs\r
+######################################################################\r
+LOCATE COMP "APV1A_CLK" SITE "J8" ;\r
+IOBUF PORT "APV1A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_CLK" SITE "G5" ;\r
+IOBUF PORT "APV1B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1A_TRG" SITE "L5" ;\r
+IOBUF PORT "APV1A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1B_TRG" SITE "G6" ;\r
+IOBUF PORT "APV1B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV1_SDA" SITE "K7" ;\r
+IOBUF PORT "APV1_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_SCL" SITE "K6" ;\r
+IOBUF PORT "APV1_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV1_RST" SITE "K5" ;\r
+IOBUF PORT "APV1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC1_LCLK" SITE "L3" ;\r
+IOBUF PORT "ADC1_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_ADCLK" SITE "D2" ;\r
+IOBUF PORT "ADC1_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_7" SITE "E2" ;\r
+IOBUF PORT "ADC1_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_6" SITE "G2" ;\r
+IOBUF PORT "ADC1_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_5" SITE "J5" ;\r
+IOBUF PORT "ADC1_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_4" SITE "J3" ;\r
+IOBUF PORT "ADC1_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_3" SITE "K2" ;\r
+IOBUF PORT "ADC1_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_2" SITE "N5" ;\r
+IOBUF PORT "ADC1_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_1" SITE "M4" ;\r
+IOBUF PORT "ADC1_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC1_OUT_0" SITE "P3" ;\r
+IOBUF PORT "ADC1_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC1_CLK" SITE "H2" ;\r
+IOBUF PORT "ADC1_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_RST" SITE "G3" ;\r
+IOBUF PORT "ADC1_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_CS" SITE "E1" ;\r
+IOBUF PORT "ADC1_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_PD" SITE "H1" ;\r
+IOBUF PORT "ADC1_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC1_SDI" SITE "F2" ;\r
+IOBUF PORT "ADC1_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC1_SCK" SITE "F1" ;\r
+IOBUF PORT "ADC1_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_1" SITE "H3" ;\r
+IOBUF PORT "FPGA_LED_ADC_1" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC1_DEBUG" SITE "H4" ;\r
+# IOBUF PORT "ADC1_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_7_IN" SITE "E3" ;\r
+# LOCATE COMP "PIN_CHECK_7_OUT" SITE "E4" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 6 - 2.50V\r
+# APV0 control signals, ADC0 inputs, 12 test outputs to pads\r
+######################################################################\r
+LOCATE COMP "APV0A_CLK" SITE "AC7" ;\r
+IOBUF PORT "APV0A_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_CLK" SITE "W3" ;\r
+IOBUF PORT "APV0B_CLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0A_TRG" SITE "Y9" ;\r
+IOBUF PORT "APV0A_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0B_TRG" SITE "AB4" ;\r
+IOBUF PORT "APV0B_TRG" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_SDA" SITE "Y6" ;\r
+IOBUF PORT "APV0_SDA" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_SCL" SITE "AA6" ;\r
+IOBUF PORT "APV0_SCL" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "APV0_RST" SITE "AA5" ;\r
+IOBUF PORT "APV0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 ;\r
+LOCATE COMP "ADC0_LCLK" SITE "T3" ;\r
+IOBUF PORT "ADC0_LCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_ADCLK" SITE "R3" ;\r
+IOBUF PORT "ADC0_ADCLK" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_7" SITE "T5" ;\r
+IOBUF PORT "ADC0_OUT_7" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_6" SITE "U3" ;\r
+IOBUF PORT "ADC0_OUT_6" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_5" SITE "U5" ;\r
+IOBUF PORT "ADC0_OUT_5" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_4" SITE "Y1" ;\r
+IOBUF PORT "ADC0_OUT_4" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_3" SITE "AA1" ;\r
+IOBUF PORT "ADC0_OUT_3" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_2" SITE "AB2" ;\r
+IOBUF PORT "ADC0_OUT_2" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_1" SITE "AC1" ;\r
+IOBUF PORT "ADC0_OUT_1" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "ADC0_OUT_0" SITE "AD2" ;\r
+IOBUF PORT "ADC0_OUT_0" IO_TYPE=LVDS25 ;\r
+\r
+LOCATE COMP "ADC0_CLK" SITE "W1" ;\r
+IOBUF PORT "ADC0_CLK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4;\r
+LOCATE COMP "ADC0_RST" SITE "AD3" ;\r
+IOBUF PORT "ADC0_RST" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_CS" SITE "AC3" ;\r
+IOBUF PORT "ADC0_CS" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_PD" SITE "V1" ;\r
+IOBUF PORT "ADC0_PD" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8 ;\r
+LOCATE COMP "ADC0_SDI" SITE "AB1" ;\r
+IOBUF PORT "ADC0_SDI" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "ADC0_SCK" SITE "W2" ;\r
+IOBUF PORT "ADC0_SCK" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "FPGA_LED_ADC_0" SITE "V2" ;\r
+IOBUF PORT "FPGA_LED_ADC_0" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LOCATE COMP "ADC0_DEBUG" SITE "AC5" ;\r
+# IOBUF PORT "ADC0_DEBUG" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=4 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 5 - 3.30V\r
+# LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENA_LVDS_7" SITE "AG2" ;\r
+LOCATE COMP "ENA_LVDS_6" SITE "AG3" ;\r
+LOCATE COMP "ENA_LVDS_5" SITE "AG4" ;\r
+LOCATE COMP "ENA_LVDS_4" SITE "AG5" ;\r
+LOCATE COMP "ENA_LVDS_3" SITE "AG11" ;\r
+LOCATE COMP "ENA_LVDS_2" SITE "AG12" ;\r
+LOCATE COMP "ENA_LVDS_1" SITE "AG13" ;\r
+LOCATE COMP "ENA_LVDS_0" SITE "AG15" ;\r
+# LOCATE COMP "FPGA_SECTOR_5" SITE "AF16" ;\r
+# IOBUF PORT "FPGA_SECTOR_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SECTOR_4" SITE "AE16" ;\r
+# IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: sector number\r
+# small assembly bug: switch is 180degree rotated, so number are mirrored\r
+LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15"\r
+IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP  ;\r
+LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13"\r
+IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12"\r
+IOBUF PORT "BP_SECTOR_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_SECTOR_0" SITE "AF15" ; # was "AF11"\r
+IOBUF PORT "BP_MODULE_0 IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+LOCATE COMP "BP_LED" SITE "AE8" ;\r
+IOBUF PORT "BP_LED" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_4" SITE "AF10" ;\r
+# IOBUF PORT "FPGA_SPARE_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_3" SITE "AG8" ;\r
+# IOBUF PORT "FPGA_SPARE_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_2" SITE "AF8" ;\r
+# IOBUF PORT "FPGA_SPARE_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_1" SITE "AG10" ;\r
+# IOBUF PORT "FPGA_SPARE_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_0" SITE "AG9" ;\r
+# IOBUF PORT "FPGA_SPARE_0" IO_TYPE=LVTTL33 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_5_IN" SITE "AF4" ;\r
+# LOCATE COMP "PIN_CHECK_5_OUT" SITE "AF3" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 4 - 3.30V\r
+# 100MHZ clock in, SPI user pins, APV0 OneWire\r
+######################################################################\r
+LOCATE COMP "CLK100M" SITE "AJ14" ;\r
+IOBUF PORT "CLK100M" IO_TYPE=LVDS25 ;\r
+LOCATE COMP "APV0_1W_7" SITE "AJ16" ;\r
+IOBUF PORT "APV0_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_6" SITE "AK16" ;\r
+IOBUF PORT "APV0_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_5" SITE "AJ17" ;\r
+IOBUF PORT "APV0_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_4" SITE "AK17" ;\r
+IOBUF PORT "APV0_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_3" SITE "AG18" ;\r
+IOBUF PORT "APV0_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_2" SITE "AG19" ;\r
+IOBUF PORT "APV0_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_1" SITE "AG20" ;\r
+IOBUF PORT "APV0_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV0_1W_0" SITE "AG21" ;\r
+IOBUF PORT "APV0_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+# LOCATE COMP "EXP_2" SITE "AF21" ;\r
+# IOBUF PORT "EXP_2" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_1" SITE "AE20" ;\r
+# IOBUF PORT "EXP_1" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "EXP_0" SITE "AE21" ;\r
+# IOBUF PORT "EXP_0" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDO" SITE "AE24" ;\r
+IOBUF PORT "U_SPI_SDO" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "U_SPI_SDI" SITE "AE25" ;\r
+IOBUF PORT "U_SPI_SDI" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_CS" SITE "AD24" ;\r
+IOBUF PORT "U_SPI_CS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+LOCATE COMP "U_SPI_SCK" SITE "AF26" ;\r
+IOBUF PORT "U_SPI_SCK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+\r
+LOCATE COMP "FPGA_LED_PLL" SITE "AG22" ;\r
+IOBUF PORT "FPGA_LED_PLL" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_4_IN" SITE "AD23" ;\r
+# LOCATE COMP "PIN_CHECK_4_OUT" SITE "AC23" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 3 - 3.30V\r
+# uC connection, external inputs, debug pins (SMC50)\r
+######################################################################\r
+LOCATE COMP "EXT_IN_3" SITE "AA30" ;\r
+IOBUF PORT "EXT_IN_3" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_2" SITE "AB30" ;\r
+IOBUF PORT "EXT_IN_2" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_1" SITE "AB29" ;\r
+IOBUF PORT "EXT_IN_1" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "EXT_IN_0" SITE "AB28" ;\r
+# alternative, if needed\r
+# LOCATE COMP "EXT_IN_0" SITE "P28" ;\r
+IOBUF PORT "EXT_IN_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "DBG_EXP_41" SITE "T27" ;\r
+# LOCATE COMP "DBG_EXP_39" SITE "T26" ;\r
+# LOCATE COMP "DBG_EXP_37" SITE "U26" ;\r
+# LOCATE COMP "DBG_EXP_35" SITE "V25" ;\r
+# LOCATE COMP "DBG_EXP_33" SITE "W25" ;\r
+# LOCATE COMP "DBG_EXP_31" SITE "W26" ;\r
+# LOCATE COMP "DBG_EXP_29" SITE "Y26" ;\r
+# LOCATE COMP "DBG_EXP_27" SITE "Y27" ;\r
+# LOCATE COMP "DBG_EXP_25" SITE "AB26" ;\r
+# LOCATE COMP "DBG_EXP_23" SITE "AC27" ;\r
+# LOCATE COMP "DBG_EXP_21" SITE "U25" ;\r
+# LOCATE COMP "DBG_EXP_19" SITE "U28" ;\r
+# LOCATE COMP "DBG_EXP_17" SITE "U27" ;\r
+# LOCATE COMP "DBG_EXP_5" SITE "R28" ;\r
+# LOCATE COMP "DBG_EXP_3" SITE "R27" ;\r
+# LOCATE COMP "DBG_EXP_1" SITE "T28" ;\r
+LOCATE COMP "UC_REBOOT" SITE "Y28" ; # was UC_FPGA3\r
+IOBUF PORT "UC_REBOOT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_2" SITE "W27" ;\r
+# IOBUF PORT "UC_FPGA_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_FPGA_1" SITE "W28" ;\r
+# IOBUF PORT "UC_FPGA_1" IO_TYPE=LVTTL33 ;\r
+# UC_FPGA_0 pin is GSR\r
+LOCATE COMP "UC_RESET" SITE "V26" ;\r
+IOBUF PORT "UC_RESET" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_WR" SITE "P29" ;\r
+# IOBUF PORT "UC_WR" IO_TYPE=LVTTL33;\r
+# LOCATE COMP "UC_RD" SITE "P30" ;\r
+# IOBUF PORT "UC_RD" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_ALE" SITE "W29" ;\r
+# IOBUF PORT "UC_ALE" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SCL" SITE "N30" ;\r
+# IOBUF PORT "UC_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_SDA" SITE "N29" ;\r
+# IOBUF PORT "UC_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_7" SITE "W30" ;\r
+# IOBUF PORT "UC_AD_7" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_6" SITE "Y29" ;\r
+# IOBUF PORT "UC_AD_6" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_5" SITE "Y30" ;\r
+# IOBUF PORT "UC_AD_5" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_4" SITE "AA29" ;\r
+# IOBUF PORT "UC_AD_4" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_3" SITE "AB27" ;\r
+# IOBUF PORT "UC_AD_3" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_2" SITE "AC29" ;\r
+# IOBUF PORT "UC_AD_2" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_1" SITE "AC30" ;\r
+# IOBUF PORT "UC_AD_1" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_AD_0" SITE "AC28" ;\r
+# IOBUF PORT "UC_AD_0" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_15" SITE "V30" ;\r
+# IOBUF PORT "UC_A_15" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_14" SITE "V29" ;\r
+# IOBUF PORT "UC_A_14" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_13" SITE "U30" ;\r
+# IOBUF PORT "UC_A_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_12" SITE "U29" ;\r
+# IOBUF PORT "UC_A_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_11" SITE "T30" ;\r
+# IOBUF PORT "UC_A_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_10" SITE "T29" ;\r
+# IOBUF PORT "UC_A_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_9" SITE "R30" ;\r
+# IOBUF PORT "UC_A_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "UC_A_8" SITE "R29" ;\r
+# IOBUF PORT "UC_A_8" IO_TYPE=LVTTL33 ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 2 - 3.30V\r
+# SFP control, LEDs, 1Wire ID, debug pins (SMC50)\r
+######################################################################\r
+# LOCATE COMP "DBG_EXP_43" SITE "R26" ;\r
+# LOCATE COMP "DBG_EXP_42" SITE "P25" ;\r
+# LOCATE COMP "DBG_EXP_40" SITE "P26" ;\r
+# LOCATE COMP "DBG_EXP_38" SITE "N25" ;\r
+# LOCATE COMP "DBG_EXP_36" SITE "M25" ;\r
+# LOCATE COMP "DBG_EXP_34" SITE "M26" ;\r
+# LOCATE COMP "DBG_EXP_32" SITE "L25" ;\r
+# LOCATE COMP "DBG_EXP_30" SITE "L26" ;\r
+# LOCATE COMP "DBG_EXP_28" SITE "K25" ;\r
+# LOCATE COMP "DBG_EXP_26" SITE "J26" ;\r
+# LOCATE COMP "DBG_EXP_24" SITE "H25" ;\r
+# LOCATE COMP "DBG_EXP_22" SITE "H26" ;\r
+# LOCATE COMP "DBG_EXP_20" SITE "H24" ;\r
+# LOCATE COMP "DBG_EXP_18" SITE "G26" ;\r
+# LOCATE COMP "DBG_EXP_16" SITE "G25" ;\r
+# LOCATE COMP "DBG_EXP_15" SITE "L27" ;\r
+# LOCATE COMP "DBG_EXP_14" SITE "L28" ;\r
+# LOCATE COMP "DBG_EXP_13" SITE "M28" ;\r
+# LOCATE COMP "DBG_EXP_12" SITE "K24" ;\r
+# LOCATE COMP "DBG_EXP_11" SITE "M27" ;\r
+# LOCATE COMP "DBG_EXP_10" SITE "M30" ;\r
+# LOCATE COMP "DBG_EXP_9" SITE "N26" ;\r
+# LOCATE COMP "DBG_EXP_8" SITE "M29" ;\r
+# LOCATE COMP "DBG_EXP_7" SITE "P27" ;\r
+# LOCATE COMP "DBG_EXP_6" SITE "L30" ;\r
+# LOCATE COMP "DBG_EXP_4" SITE "L29" ;\r
+# LOCATE COMP "DBG_EXP_2" SITE "K30" ;\r
+# LOCATE COMP "DBG_EXP_0" SITE "K29" ;\r
+LOCATE COMP "FPGA_LED_6" SITE "G28" ;\r
+IOBUF PORT "FPGA_LED_6" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_5" SITE "G27" ;\r
+IOBUF PORT "FPGA_LED_5" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_4" SITE "H28" ;\r
+IOBUF PORT "FPGA_LED_4" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_3" SITE "H27" ;\r
+IOBUF PORT "FPGA_LED_3" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_RXD" SITE "J28" ;\r
+IOBUF PORT "FPGA_LED_RXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_TXD" SITE "J27" ;\r
+IOBUF PORT "FPGA_LED_TXD" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "FPGA_LED_LINK" SITE "K26" ;\r
+IOBUF PORT "FPGA_LED_LINK" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+LOCATE COMP "SD_LOS" SITE "F30" ;\r
+IOBUF PORT "SD_LOS" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_PRESENT" SITE "G30" ; # alias MD[0]\r
+IOBUF PORT "SD_PRESENT" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "SD_TXDIS" SITE "J29" ;\r
+IOBUF PORT "SD_TXDIS" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=4 ;\r
+# LOCATE COMP "SD_TXFAULT" SITE "J30" ;\r
+# IOBUF PORT "SD_TXFAULT" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SDA" SITE "H30" ; # alias MD[2]\r
+# IOBUF PORT "SD_SDA" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_SCL" SITE "H29" ; # alias MD[1]\r
+# IOBUF PORT "SD_SCL" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "SD_RATE" SITE "G29" ;\r
+# IOBUF PORT "SD_RATE" IO_TYPE=LVTTL33 ;\r
+LOCATE COMP "ADCM_ONEWIRE" SITE "F29" ;\r
+IOBUF PORT "ADCM_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 ;\r
+\r
+# short cut pins for FPGA placement control by JTAG\r
+# LOCATE COMP "PIN_CHECK_2_IN" SITE "D29" ;\r
+# LOCATE COMP "PIN_CHECK_2_OUT" SITE "D30" ;\r
+\r
+\r
+######################################################################\r
+# I/O bank 1 - 3.30V\r
+# APV1 OneWire\r
+######################################################################\r
+LOCATE COMP "APV1_1W_7" SITE "B15" ;\r
+IOBUF PORT "APV1_1W_7" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_6" SITE "A16" ;\r
+IOBUF PORT "APV1_1W_6" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_5" SITE "B16" ;\r
+IOBUF PORT "APV1_1W_5" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_4" SITE "A17" ;\r
+IOBUF PORT "APV1_1W_4" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_3" SITE "B17" ;\r
+IOBUF PORT "APV1_1W_3" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_2" SITE "C16" ;\r
+IOBUF PORT "APV1_1W_2" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_1" SITE "C17" ;\r
+IOBUF PORT "APV1_1W_1" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+LOCATE COMP "APV1_1W_0" SITE "D16" ;\r
+IOBUF PORT "APV1_1W_0" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;\r
+\r
+#### HERE WE ARE ######################\r
+\r
+\r
+######################################################################\r
+# I/O bank 0 - 3.30V\r
+# ADC1 control, LVDS driver control, backplane sense pins\r
+######################################################################\r
+LOCATE COMP "ENB_LVDS_7" SITE "F6" ;\r
+LOCATE COMP "ENB_LVDS_6" SITE "D5" ;\r
+LOCATE COMP "ENB_LVDS_5" SITE "D4" ;\r
+LOCATE COMP "ENB_LVDS_4" SITE "E5" ;\r
+LOCATE COMP "ENB_LVDS_3" SITE "D15" ;\r
+LOCATE COMP "ENB_LVDS_2" SITE "E13" ;\r
+LOCATE COMP "ENB_LVDS_1" SITE "D13" ;\r
+LOCATE COMP "ENB_LVDS_0" SITE "D12" ;\r
+# LOCATE COMP "FPGA_BP_13" SITE "C15" ;\r
+# IOBUF PORT "FPGA_BP_13" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_BP_12" SITE "C14" ;\r
+# IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ;\r
+# Backplane sense wires: backplane number\r
+LOCATE COMP "BP_MODULE_3" SITE "A14" ;\r
+IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_2" SITE "F13" ;\r
+IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_1" SITE "E12" ;\r
+IOBUF PORT "BP_MODULE_1" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+LOCATE COMP "BP_MODULE_0" SITE "G11" ;\r
+IOBUF PORT "BP_MODULE_0" IO_TYPE=LVTTL33 PULLMODE=UP ;\r
+\r
+# LOCATE COMP "FPGA_SPARE_12" SITE "D8" ;\r
+# IOBUF PORT "FPGA_SPARE_12" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_11" SITE "E8" ;\r
+# IOBUF PORT "FPGA_SPARE_11" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_10" SITE "D9" ;\r
+# IOBUF PORT "FPGA_SPARE_10" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_9" SITE "D11" ;\r
+# IOBUF PORT "FPGA_SPARE_9" IO_TYPE=LVTTL33 ;\r
+# LOCATE COMP "FPGA_SPARE_8" SITE "F11" ;\r
+# IOBUF PORT "FPGA_SPARE_8" IO_TYPE=LVTTL33 ;\r
+\r
+LOCATE COMP "BP_ONEWIRE" SITE "F7" ;\r
+IOBUF PORT "BP_ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 ;\r
+\r
+\r
+######################################################################\r
+# simplify IO definitions\r
+######################################################################\r
+# Debug header (50pin SMC connector)\r
+# DEFINE PORT GROUP "debug_header_group" "DBG_EXP_{0:43}" ;\r
+# IOBUF GROUP "debug_header_group" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=4 SLEWRATE=FAST ;\r
+\r
+# LED drivers\r
+# DEFINE PORT GROUP "led_output_group" "FPGA_LED*" ;\r
+# IOBUF GROUP "led_output_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16 SLEWRATE=SLOW ;\r
+\r
+# LVDS driver control\r
+DEFINE PORT GROUP "enable_lvds_group" "EN?_LVDS_{0:7}" ;\r
+IOBUF GROUP "enable_lvds_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8 SLEWRATE=SLOW ;\r
+\r
+######################################################################\r
+# FPGA boot et. al.\r
+######################################################################\r
+SYSCONFIG PERSISTENT=OFF ;\r
+SYSCONFIG CONFIG_MODE=SPI ;\r
+SYSCONFIG DONE_OD=OFF ;\r
+SYSCONFIG DONE_EX=OFF ;\r
+SYSCONFIG MCCLK_FREQ=34 ;\r
+SYSCONFIG CONFIG_SECURE=OFF ;\r
+SYSCONFIG WAKE_UP=21 ;\r
+#SYSCONFIG WAKE_ON_LOCK=OFF ;\r
+SYSCONFIG COMPRESS_CONFIG=OFF ;\r
+SYSCONFIG INBUF=OFF ;\r
+SYSCONFIG ENABLE_NDR=OFF ;\r
+USERCODE HEX "DEADAFFE" ;\r
old mode 100755 (executable)
new mode 100644 (file)
index 393b5c1..8f2b6ed
@@ -7,72 +7,76 @@
 add_file -vhdl -lib work "version.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "design/adcmv3_components.vhd"
+add_file -vhdl -lib work "source/adcmv3_components.vhd"
 
 # ADCMv3 design files
-add_file -vhdl -lib work "design/adcmv3.vhd"
-add_file -vhdl -lib work "design/dbg_reg.vhd"
-add_file -vhdl -lib work "design/reset_handler.vhd"
-add_file -vhdl -lib work "design/reboot_handler.vhd"
-add_file -vhdl -lib work "design/pulse_sync.vhd"
-add_file -vhdl -lib work "design/adc_ch_in.vhd"
-add_file -vhdl -lib work "design/state_sync.vhd"
-add_file -vhdl -lib work "design/apv_sync_handler.vhd"
-add_file -vhdl -lib work "design/apv_trg_handler.vhd"
-add_file -vhdl -lib work "design/eds_buffer_dpram.vhd"
-add_file -vhdl -lib work "design/eds_buf.vhd"
-add_file -vhdl -lib work "design/max_data.vhd"
-add_file -vhdl -lib work "design/real_trg_handler.vhd"
-add_file -vhdl -lib work "design/pulse_stretch.vhd"
-add_file -vhdl -lib work "design/apv_trgctrl.vhd"
-add_file -vhdl -lib work "design/adc_channel_select.vhd"
-add_file -vhdl -lib work "design/crossover.vhd"
-add_file -vhdl -lib work "design/adc_crossover.vhd"
-add_file -vhdl -lib work "design/adc_twochannels.vhd"
-add_file -vhdl -lib work "design/adc_data_handler.vhd"
-add_file -vhdl -lib work "design/frame_status_mem.vhd"
-add_file -vhdl -lib work "design/input_bram.vhd"
-add_file -vhdl -lib work "design/apv_raw_buffer.vhd"
-add_file -vhdl -lib work "design/apv_lock_sm.vhd"
-add_file -vhdl -lib work "design/apv_digital.vhd"
-add_file -vhdl -lib work "design/apv_locker.vhd"
-add_file -vhdl -lib work "design/raw_buf_stage.vhd"
-add_file -vhdl -lib work "design/decoder_8bit.vhd"
-add_file -vhdl -lib work "design/apv_pc_nc_alu.vhd"
-add_file -vhdl -lib work "design/buf_toc.vhd"
-add_file -vhdl -lib work "design/ref_row_sel.vhd"
-add_file -vhdl -lib work "design/frmctr_check.vhd"
-add_file -vhdl -lib work "design/ped_corr_ctrl.vhd"
-add_file -vhdl -lib work "design/adc_apv_map_mem.vhd"
-add_file -vhdl -lib work "design/fifo_1kx18.vhd"
-add_file -vhdl -lib work "design/fifo_2kx27.vhd"
-add_file -vhdl -lib work "design/ipu_fifo_stage.vhd"
-add_file -vhdl -lib work "design/slv_register.vhd"
-add_file -vhdl -lib work "design/adc_snoop_mem.vhd"
-add_file -vhdl -lib work "design/slv_adc_snoop.vhd"
-add_file -vhdl -lib work "design/slv_half_register.vhd"
-add_file -vhdl -lib work "design/slv_status.vhd"
-add_file -vhdl -lib work "design/slv_status_bank.vhd"
-add_file -vhdl -lib work "design/apv_adc_map_mem.vhd"
-add_file -vhdl -lib work "design/slv_register_bank.vhd"
-add_file -vhdl -lib work "design/spi_real_slim.vhd"
-add_file -vhdl -lib work "design/spi_adc_master.vhd"
-add_file -vhdl -lib work "design/slv_onewire_dpram.vhd"
-add_file -vhdl -lib work "design/onewire_master.vhd"
-add_file -vhdl -lib work "design/onewire_spare_one.vhd"
-add_file -vhdl -lib work "design/adc_onewire_map_mem.vhd"
-add_file -vhdl -lib work "design/slv_onewire_memory.vhd"
-add_file -vhdl -lib work "design/i2c_gstart.vhd"
-add_file -vhdl -lib work "design/i2c_sendb.vhd"
-add_file -vhdl -lib work "design/i2c_slim.vhd"
-add_file -vhdl -lib work "design/i2c_master.vhd"
-add_file -vhdl -lib work "design/ped_thr_true.vhd"
-add_file -vhdl -lib work "design/slv_ped_thr_mem.vhd"
-add_file -vhdl -lib work "design/slave_bus.vhd"
-add_file -vhdl -lib work "design/rich_trb.vhd"
-add_file -vhdl -lib work "design/sync_pll_40m.vhd"
-add_file -vhdl -lib work "design/dll_100m.vhd"
-add_file -vhdl -lib work "design/pll_40m.vhd"
+# Top level entity
+add_file -vhdl -lib work "adcmv3.vhd"
+
+add_file -vhdl -lib work "source/dbg_reg.vhd"
+add_file -vhdl -lib work "source/reset_handler.vhd"
+add_file -vhdl -lib work "source/reboot_handler.vhd"
+add_file -vhdl -lib work "source/pulse_sync.vhd"
+add_file -vhdl -lib work "source/state_sync.vhd"
+add_file -vhdl -lib work "source/apv_sync_handler.vhd"
+add_file -vhdl -lib work "source/apv_trg_handler.vhd"
+add_file -vhdl -lib work "source/eds_buf.vhd"
+add_file -vhdl -lib work "source/max_data.vhd"
+add_file -vhdl -lib work "source/real_trg_handler.vhd"
+add_file -vhdl -lib work "source/pulse_stretch.vhd"
+add_file -vhdl -lib work "source/apv_trgctrl.vhd"
+add_file -vhdl -lib work "source/adc_channel_select.vhd"
+add_file -vhdl -lib work "source/adc_crossover.vhd"
+add_file -vhdl -lib work "source/adc_twochannels.vhd"
+add_file -vhdl -lib work "source/adc_data_handler.vhd"
+add_file -vhdl -lib work "source/apv_raw_buffer.vhd"
+add_file -vhdl -lib work "source/apv_lock_sm.vhd"
+add_file -vhdl -lib work "source/apv_digital.vhd"
+add_file -vhdl -lib work "source/apv_locker.vhd"
+add_file -vhdl -lib work "source/raw_buf_stage.vhd"
+add_file -vhdl -lib work "source/apv_pc_nc_alu.vhd"
+add_file -vhdl -lib work "source/buf_toc.vhd"
+add_file -vhdl -lib work "source/ref_row_sel.vhd"
+add_file -vhdl -lib work "source/frmctr_check.vhd"
+add_file -vhdl -lib work "source/ped_corr_ctrl.vhd"
+add_file -vhdl -lib work "source/ipu_fifo_stage.vhd"
+add_file -vhdl -lib work "source/slv_register.vhd"
+add_file -vhdl -lib work "source/slv_adc_snoop.vhd"
+add_file -vhdl -lib work "source/slv_half_register.vhd"
+add_file -vhdl -lib work "source/slv_status.vhd"
+add_file -vhdl -lib work "source/slv_status_bank.vhd"
+add_file -vhdl -lib work "source/slv_register_bank.vhd"
+add_file -vhdl -lib work "source/spi_real_slim.vhd"
+add_file -vhdl -lib work "source/spi_adc_master.vhd"
+add_file -vhdl -lib work "source/onewire_master.vhd"
+add_file -vhdl -lib work "source/slv_onewire_memory.vhd"
+add_file -vhdl -lib work "source/i2c_gstart.vhd"
+add_file -vhdl -lib work "source/i2c_sendb.vhd"
+add_file -vhdl -lib work "source/i2c_slim.vhd"
+add_file -vhdl -lib work "source/i2c_master.vhd"
+add_file -vhdl -lib work "source/slv_ped_thr_mem.vhd"
+add_file -vhdl -lib work "source/slave_bus.vhd"
+add_file -vhdl -lib work "source/rich_trb.vhd"
+
+# Core files
+add_file -vhdl -lib work "cores/adc_ch_in.vhd"
+add_file -vhdl -lib work "cores/eds_buffer_dpram.vhd"
+add_file -vhdl -lib work "cores/crossover.vhd"
+add_file -vhdl -lib work "cores/frame_status_mem.vhd"
+add_file -vhdl -lib work "cores/input_bram.vhd"
+add_file -vhdl -lib work "cores/decoder_8bit.vhd"
+add_file -vhdl -lib work "cores/adc_apv_map_mem.vhd"
+add_file -vhdl -lib work "cores/fifo_1kx18.vhd"
+add_file -vhdl -lib work "cores/fifo_2kx27.vhd"
+add_file -vhdl -lib work "cores/adc_snoop_mem.vhd"
+add_file -vhdl -lib work "cores/apv_adc_map_mem.vhd"
+add_file -vhdl -lib work "cores/onewire_spare_one.vhd"
+add_file -vhdl -lib work "cores/adc_onewire_map_mem.vhd"
+add_file -vhdl -lib work "cores/ped_thr_true.vhd"
+add_file -vhdl -lib work "cores/sync_pll_40m.vhd"
+add_file -vhdl -lib work "cores/dll_100m.vhd"
+add_file -vhdl -lib work "cores/pll_40m.vhd"
+add_file -vhdl -lib work "cores/slv_onewire_dpram.vhd"
 
 # TrbNet design files
 add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
@@ -113,14 +117,12 @@ add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
 add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
-
 # add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd"
-# add_file -vhdl -lib work "design/sfp_rx_handler.vhd"
+# add_file -vhdl -lib work "source/sfp_rx_handler.vhd"
 
 # implementation: "workdir"
 impl -add workdir -type fpga
 
-
 # device options
 set_option -technology LATTICE-ECP2M
 set_option -part LFE2M100E
@@ -159,3 +161,4 @@ project -result_file "workdir/adcmv3.edf"
 set_option -vlog_std v2001
 set_option -project_relative_includes 1
 impl -active "workdir"
+
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/adcmv3.vhd
rename to adcmv3.vhd
diff --git a/cleanup_workdir.sh b/cleanup_workdir.sh
new file mode 100755 (executable)
index 0000000..fe88ea6
--- /dev/null
@@ -0,0 +1,18 @@
+#!/bin/sh
+TOPNAME=adcmv3
+
+rm -f workdir/${TOPNAME}.alt
+rm -f workdir/${TOPNAME}.bgn
+rm -f workdir/${TOPNAME}.bit
+rm -f workdir/${TOPNAME}.edf
+rm -f workdir/${TOPNAME}.fse
+rm -f workdir/${TOPNAME}.mrp
+rm -f workdir/${TOPNAME}.ncd
+rm -f workdir/${TOPNAME}.ngd
+rm -f workdir/${TOPNAME}.ngo
+rm -f workdir/${TOPNAME}.ngy
+rm -f workdir/${TOPNAME}.pad
+rm -f workdir/${TOPNAME}.par
+rm -f workdir/${TOPNAME}.sr?
+rm -f workdir/${TOPNAME}.tlg
+rm -f workdir/${TOPNAME}.twr*
index e8ad2135c3e3a87419fb5550ca8ae8e085de6153..c9b4049a0dd318ba4340120e73370e9be9660bed 100755 (executable)
@@ -54,7 +54,9 @@ system("rm workdir/$TOPNAME.tlg");
 system("rm workdir/$TOPNAME.twr*");
 
 # Create full lpf file
-system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf");
 system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
 
 # Generate timestamp for slowcontrol readback
similarity index 52%
rename from compile_ORIG.pl
rename to compile_munich21.pl
index 63d027c3e8cc077c1f4c27917e79b929e2c2e919..67381634bed0221e65fd87e5a643c14a3a783f24 100755 (executable)
@@ -1,29 +1,28 @@
 #!/usr/bin/perl
-###########################################
-# Script file to run the flow
-###########################################
-
-# You need the tunnels before!
-
 use Data::Dumper;
 use warnings;
 use strict;
 
-# Path settings for ispLEVER tools
-my $lattice_path = '/usr/local/opt/synplify/8/isptools';
 
-# Path settings for SynplifyPRO
-# my $synplify_path = '/usr/local/opt/synplify/premier';
-my $synplify_path = '/scratch/rich/synplify/D-2009.12';
+
+
+###################################################################################
+#Settings for this project
+my $TOPNAME                      = "adcmv3";  #Name of top-level entity
+my $lattice_path                 = '/usr/local/opt/lattice_diamond/diamond/2.1';
+my $synplify_path                = '/usr/local/opt/synplify/F-2012.03-SP1/';
+my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
+my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
+###################################################################################
+
+
 
 use FileHandle;
 
 $ENV{'SYNPLIFY'}=$synplify_path;
 $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}="27000\@localhost";
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
 
-# Design top level entity
-my $TOPNAME="adcmv3";
 
 # FPGA chip description
 my $FAMILYNAME="LATTICEECP2M";
@@ -31,11 +30,16 @@ my $DEVICENAME="LFE2M100E";
 my $PACKAGE="FPBGA900";
 my $SPEEDGRADE="6";
 
-# Create full lpf file
-system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#create full lpf file
+system("cp ./$TOPNAME.lpf workdir/$TOPNAME.lpf");
 system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+#system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
+#system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
 
-# Generate timestamp for slowcontrol readback
+#generate timestamp
 my $t=time;
 my $fh = new FileHandle(">version.vhd");
 die "could not open file" if (! defined $fh);
@@ -56,68 +60,71 @@ end package version;
 EOF
 $fh->close;
 
-# Run Synplify on the design
 system("env| grep LM_");
 my $r = "";
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME".".prj";
+
+my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
 $r=execute($c, "do_not_exit" );
 
-# Check for errors
+
 chdir "workdir";
 $fh = new FileHandle("<$TOPNAME".".srr");
 my @a = <$fh>;
 $fh -> close;
 
+
+
 foreach (@a)
 {
     if(/\@E:/)
     {
-       $c="cat  $TOPNAME.srr";
+       print "\n";
+       $c="cat $TOPNAME.srr | grep \"\@E\"";
        system($c);
-        print "ERROR_ERROR_ERROR_ERROR_ERROR\n";
+        print "\n\n";
        exit 129;
     }
 }
 
-# ispLEVER design flow starts here
-# new license file must be given
-$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
 
-# EDIF2NGD
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd  -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
 execute($c);
 
 $c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
 execute($c);
 
-# NGDBUILD
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
 execute($c);
 
-# MAP
 my $tpmap = $TOPNAME . "_map" ;
-$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
 execute($c);
 
 system("rm $TOPNAME.ncd");
 
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
 # IOR IO Timing Report
-#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#execute($c);
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
 
-# TWR Timing Report (setup)
+# TWR Timing Report
 $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
-# TWR Timing Report (hold)
 $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
 execute($c);
 
-# BitGen
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
+# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
 execute($c);
 
 chdir "..";
diff --git a/compile_munich21.sh b/compile_munich21.sh
new file mode 100755 (executable)
index 0000000..5b8795e
--- /dev/null
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env
+
+exec ./compile_munich21.pl
+#exec ./compile.pl
old mode 100755 (executable)
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similarity index 100%
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rename to cores/adc_ch_in.lpc
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rename to cores/adc_ch_in.vhd
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rename to cores/fifo_16x11.vhd
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rename to cores/fifo_1kx18.lpc
similarity index 100%
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rename to cores/fifo_1kx18.vhd
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rename to cores/fifo_2kx27.vhd
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rename to cores/mult_3x8.vhd
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rename to cores/pll_40m.lpc
similarity index 100%
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rename from design/testfifo.lpc
rename to cores/testfifo.lpc
similarity index 100%
rename from design/testfifo.vhd
rename to cores/testfifo.vhd
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diff --git a/lever/work/compile/contents.lib~work b/lever/work/compile/contents.lib~work
deleted file mode 100755 (executable)
index f49dc5d..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-38
-~E 1 "./../../../trbnet/special/spi_slim.vhd" 12 spi_slim
-~A 1 "./../../../trbnet/special/spi_slim.vhd" 44 behavioral
-~E 1 "./../../../trbnet/special/spi_master.vhd" 10 spi_master
-~A 1 "./../../../trbnet/special/spi_master.vhd" 37 behavioral
-~E 1 "./../../sim/tb_spi_master.vhd" 5 testbench
-~A 1 "./../../sim/tb_spi_master.vhd" 8 behavior
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rename to source/adc_data_handler.vhd
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rename from design/pulse_stretch.vhd
rename to source/pulse_stretch.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/pulse_sync.vhd
rename to source/pulse_sync.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/raw_buf_stage.vhd
rename to source/raw_buf_stage.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/real_trg_handler.vhd
rename to source/real_trg_handler.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/real_trg_handler_BACKUP.vhd
rename to source/real_trg_handler_BACKUP.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/reboot_handler.vhd
rename to source/reboot_handler.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/reset_handler.vhd
rename to source/reset_handler.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 98%
rename from design/rich_trb.vhd
rename to source/rich_trb.vhd
index 960127c..a58448e
@@ -24,8 +24,8 @@ port(
        SD_LOS_IN                   : in    std_logic;
        ONEWIRE_INOUT               : inout std_logic;
        -- common regIO status / control registers
-       COMMON_STAT_REG_IN          : in    std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
-       COMMON_CTRL_REG_OUT         : out   std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
+       COMMON_STAT_REG_IN          : in    std_logic_vector(8*32-1 downto 0); -- common status register, bit definitions like in WIKI
+       COMMON_CTRL_REG_OUT         : out   std_logic_vector(3*32-1 downto 0); -- common control register, bit definitions like in WIKI
        -- status register input to regIO / control register output from regIO
        CONTROL_OUT                 : out   std_logic_vector(63 downto 0);
        STATUS_IN                   : in    std_logic_vector(127 downto 0);
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/sbuf.vhd
rename to source/sbuf.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/sfp_rx_handler.vhd
rename to source/sfp_rx_handler.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/sfp_rx_handler_BACK2.vhd
rename to source/sfp_rx_handler_BACK2.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/sfp_rx_handler_BACK_0.vhd
rename to source/sfp_rx_handler_BACK_0.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/slave_bus.vhd
rename to source/slave_bus.vhd
similarity index 100%
rename from design/slv_adc_la.vhd
rename to source/slv_adc_la.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/slv_onewire_memory.vhd
rename to source/slv_onewire_memory.vhd
similarity index 100%
rename from design/slv_status.vhd
rename to source/slv_status.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/state_sync.vhd
rename to source/state_sync.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/tb_count_unit.vhd
rename to source/tb_count_unit.vhd
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/tb_count_unit.vhd.bak
rename to source/tb_count_unit.vhd.bak
old mode 100755 (executable)
new mode 100644 (file)
similarity index 100%
rename from design/test_media.vhd
rename to source/test_media.vhd
old mode 100755 (executable)
new mode 100644 (file)
old mode 100644 (file)
new mode 100755 (executable)