BLOCK PATH TO PORT "TEST_LINE*";
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
-#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
REGION "MEDIA" "R81C44D" 13 25;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;
+
+BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*.FC/FF*";
+BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/TheTriggerHandler/trg_in_r[0]";
+
+MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/sd_los_i" 2x;
-- MBS
---------------------------------------------------------------------------
- THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator
- generic map(
- INCL_REGIO => c_YES
- )
- port map (
- CLK => clk_sys,
- RESET_IN => reset_i,
-
- -- recovered clock, synchronous to DLM @240MHz
- CLK_RCV => med2int(INTERFACE_NUM).clk_full,
-
- --DLM inputs
- DLM_IN => dlm_rx_i,
- DLM_MSG_IN => dlm_rx_word,
-
- --trigger outputs
- TRG_ASYNC_OUT => async_ext_trig,
- TRG_SYNC_OUT => cts_ext_trigger,
-
- --data output for read-out
- TRIGGER_IN => cts_rdo_rx.data_valid,
- TRIGGER_TYPE => cts_rdo_rx.trg_type,
-
- -- Data connection to Streamer
- DATA_OUT => cts_rdo_additional(0).data,
- WRITE_OUT => cts_rdo_additional(0).data_write,
- STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
- FINISHED_OUT => cts_rdo_additional(0).data_finished,
-
- --Registers / Debug
- REGIO_IN => bus_mbs_rx,
- REGIO_OUT => bus_mbs_tx,
-
- -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode)
- CONTROL_REG_IN => cts_ext_control,
- STATUS_REG_OUT => cts_ext_status,
- HEADER_REG_OUT => cts_ext_header,
- DEBUG => cts_ext_debug
- );
-
+ THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator
+ generic map(
+ INCL_REGIO => c_YES
+ )
+ port map (
+ CLK => clk_sys,
+ RESET_IN => reset_i,
+
+ -- recovered clock, synchronous to DLM @240MHz
+ CLK_RCV => med2int(INTERFACE_NUM).clk_full,
+
+ --DLM inputs
+ DLM_IN => dlm_rx_i,
+ DLM_MSG_IN => dlm_rx_word,
+
+ --trigger outputs
+ TRG_ASYNC_OUT => async_ext_trig,
+ TRG_SYNC_OUT => cts_ext_trigger,
+
+ --data output for read-out
+ TRIGGER_IN => cts_rdo_rx.data_valid,
+ TRIGGER_TYPE => cts_rdo_rx.trg_type,
+
+ -- Data connection to Streamer
+ DATA_OUT => cts_rdo_additional(0).data,
+ WRITE_OUT => cts_rdo_additional(0).data_write,
+ STATUSBIT_OUT => cts_rdo_additional(0).statusbits,
+ FINISHED_OUT => cts_rdo_additional(0).data_finished,
+
+ --Registers / Debug
+ REGIO_IN => bus_mbs_rx,
+ REGIO_OUT => bus_mbs_tx,
+
+ -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode)
+ CONTROL_REG_IN => cts_ext_control,
+ STATUS_REG_OUT => cts_ext_status,
+ HEADER_REG_OUT => cts_ext_header,
+ DEBUG => cts_ext_debug
+ );
+
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------