]> jspc29.x-matter.uni-frankfurt.de Git - trb5sc.git/commitdiff
improve timing of cbmrich trb5sc
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 15 Jun 2022 09:17:32 +0000 (11:17 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Wed, 15 Jun 2022 09:17:32 +0000 (11:17 +0200)
cbmrich/config_compile_giessen.pl
cbmrich/nodelist_giessen.txt [new file with mode: 0644]
cbmrich/trb5sc_cbmrich.lpf
cbmrich/trb5sc_cbmrich.prj
cbmrich/trb5sc_cbmrich.vhd

index 903b4917cd3c019302efabe98d32acda83de0799..8a51e043f79d9d894cc2600ad3cd024880b7b053 100644 (file)
@@ -12,7 +12,7 @@ synplify_path                => '/usr/local/diamond/3.11_x64/synpbase',
 synplify_command             => "synpwrap -fg -options",
 #synplify_command             => "ssh  adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"",
 
-nodelist_file                => '../nodes_lxhadeb07.txt',
+nodelist_file                => '../nodelist_giessen.txt',
 par_options                  => '../par.p2t',
 
 #Include only necessary lpf files
diff --git a/cbmrich/nodelist_giessen.txt b/cbmrich/nodelist_giessen.txt
new file mode 100644 (file)
index 0000000..aa23d58
--- /dev/null
@@ -0,0 +1,7 @@
+// nodes file for parallel place&route
+
+
+[fb07pc-u102325]
+SYSTEM = linux
+CORENUM = 12
+WORKDIR = /home/adrian/trbvhdl/trb5sc/cbmrich/workdir
index b6be2d69054b232d23dbdc83cdd2de22fe93b984..60a520076c33797d4fc7479266b71869b2632dc4 100644 (file)
@@ -26,7 +26,7 @@ BLOCK PATH FROM PORT "TEMP_LINE";
 BLOCK PATH TO   PORT "TEST_LINE*";
 
 #MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
-#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
 #MULTICYCLE TO CELL   "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
 #MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
 
@@ -41,3 +41,10 @@ GSR_NET NET "clear_i";
 REGION               "MEDIA" "R81C44D" 13 25;
 LOCATE UGROUP        "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
 
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
+MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x;
+
+BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*.FC/FF*";
+BLOCK PATH FROM CELL "THE_CTS/TIME_REFERENCE_OUT" TO CELL "THE_TDC/TheTriggerHandler/trg_in_r[0]";
+
+MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/sd_los_i" 2x;
index 11a145b02a10aca8434fa7bcbb39235f100fc7b1..728ad6a53af5a9061679f318c2ec4802341f6492 100644 (file)
@@ -267,7 +267,7 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd"
 
 #TDC Calibration
 add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Calibration.vhd"
-add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Cal_Limits_v2.vhd"
+add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/Cal_Limits_v2_1.vhd"
 add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/cnt_val.vhd"
 add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/default_val.vhd"
 add_file -vhdl -lib work "../../dirich/combiner_cts/code_EBR/LUT.vhd"
index 3ecd028e036fe6ab70323512d232d85e2a3509ef..b6df9a81ba862bf4a383bd2c7ac703496dd33228 100644 (file)
@@ -635,46 +635,46 @@ THE_CTS : CTS
 -- MBS
 ---------------------------------------------------------------------------        
         
     THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator
-        generic map(
-          INCL_REGIO      => c_YES
-        )
-        port map (
-           CLK            => clk_sys,
-           RESET_IN       => reset_i,
-           
-           -- recovered clock, synchronous to DLM @240MHz
-           CLK_RCV        => med2int(INTERFACE_NUM).clk_full,
-           
-           --DLM inputs
-           DLM_IN         => dlm_rx_i,
-           DLM_MSG_IN     => dlm_rx_word,
-           
-           --trigger outputs
-           TRG_ASYNC_OUT  => async_ext_trig,
-           TRG_SYNC_OUT   => cts_ext_trigger,
-           
-           --data output for read-out
-           TRIGGER_IN     => cts_rdo_rx.data_valid,
-           TRIGGER_TYPE   => cts_rdo_rx.trg_type,
-           
-           -- Data connection to Streamer
-           DATA_OUT       => cts_rdo_additional(0).data,
-           WRITE_OUT      => cts_rdo_additional(0).data_write,
-           STATUSBIT_OUT  => cts_rdo_additional(0).statusbits,
-           FINISHED_OUT   => cts_rdo_additional(0).data_finished,
-           
-           --Registers / Debug    
-           REGIO_IN       => bus_mbs_rx,
-           REGIO_OUT      => bus_mbs_tx,
-
-           -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode)
-           CONTROL_REG_IN => cts_ext_control,
-           STATUS_REG_OUT => cts_ext_status,
-           HEADER_REG_OUT => cts_ext_header,
-           DEBUG          => cts_ext_debug   
-           );
-        
+ THE_DLM_CTS_GNRTR : entity work.DLM_CTS_generator
+   generic map(
+     INCL_REGIO      => c_YES
+   )
+   port map (
+     CLK            => clk_sys,
+     RESET_IN       => reset_i,
+
+     -- recovered clock, synchronous to DLM @240MHz
+     CLK_RCV        => med2int(INTERFACE_NUM).clk_full,
+
+     --DLM inputs
+     DLM_IN         => dlm_rx_i,
+     DLM_MSG_IN     => dlm_rx_word,
+
+     --trigger outputs
+     TRG_ASYNC_OUT  => async_ext_trig,
+     TRG_SYNC_OUT   => cts_ext_trigger,
+
+     --data output for read-out
+     TRIGGER_IN     => cts_rdo_rx.data_valid,
+     TRIGGER_TYPE   => cts_rdo_rx.trg_type,
+
+     -- Data connection to Streamer
+     DATA_OUT       => cts_rdo_additional(0).data,
+     WRITE_OUT      => cts_rdo_additional(0).data_write,
+     STATUSBIT_OUT  => cts_rdo_additional(0).statusbits,
+     FINISHED_OUT   => cts_rdo_additional(0).data_finished,
+
+     --Registers / Debug
+     REGIO_IN       => bus_mbs_rx,
+     REGIO_OUT      => bus_mbs_tx,
+
+     -- Ctrl and Status registers are only in use, if INCL_REGIO = c_NO ("ETM" mode)
+     CONTROL_REG_IN => cts_ext_control,
+     STATUS_REG_OUT => cts_ext_status,
+     HEADER_REG_OUT => cts_ext_header,
+     DEBUG          => cts_ext_debug
+   );
+
 ---------------------------------------------------------------------------
 -- Bus Handler
 ---------------------------------------------------------------------------