--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 18-11-2014
+-- Module Name: FEE_SODAfrequencydiv5
+-- Description: Converts 200MHz from GTX to 40 MHz SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_SODAfrequencydiv5
+-- Measures the number of pulses in one second
+--
+-- Library
+--
+-- Generics:\r
+--
+-- Inputs:
+-- clock : recovered clock
+-- data : data from GTX
+-- kchar : k-character signal from GTX
+--
+-- Outputs:
+-- clockdiv5 : input clock divided by 5 and synchronous to SODA
+-- error : error in incoming data or phase
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_SODAfrequencydiv5 is\r
+ port ( \r
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic\r
+ );\r
+end FEE_SODAfrequencydiv5;
+
+architecture Behavioral of FEE_SODAfrequencydiv5 is
+constant KCHARSODA : std_logic_vector(7 downto 0) := x"DC";
+
+signal clockdiv5_S : std_logic;
+signal div5count0_S : std_logic;
+signal clock5div2_S : std_logic := '0';
+signal prev_clock5div2_S : std_logic := '0';
+signal clockdiv5_reset_S : std_logic;
+signal SODA_kchar_S : std_logic;
+signal disable_SODAcheck_S : std_logic := '0';\r
+signal disable_clock5check_S : std_logic := '0';\r
+signal SODA40_signal_S : std_logic;
+signal div5count_S : std_logic_vector(2 downto 0) := (others => '0');
+signal SODA_count_S : std_logic_vector(3 downto 0) := (others => '0');
+signal SODAerror_S : std_logic;
+signal clockdiv5error_S : std_logic;
+signal clockbiterror_S : std_logic;
+
+begin
+
+error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_S='1') else '0';
+clockdiv5 <= clockdiv5_S;
+
+rxrecclk_bufrdiv5_i : BUFR
+ generic map ( BUFR_DIVIDE => "5" )
+ port map (
+ CE => '1',
+ CLR => clockdiv5_reset_S,
+ I => clock,
+ O => clockdiv5_S);
+
+process_checkSODA: process(clock)
+variable disable_count_V : std_logic_vector(1 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ div5count0_S <= '0';
+ clockbiterror_S <= '0';
+ if div5count_S/="100" then
+ if (disable_SODAcheck_S='0') and (SODA40_signal_S='1') then -- wrong phase
+ div5count_S <= "000";
+ disable_SODAcheck_S <= '1';
+ disable_count_V := (others => '0');
+ clockbiterror_S <= '1';
+ else
+ div5count_S <= div5count_S+1;
+ end if;
+ else
+ div5count_S <= "000";\r
+ div5count0_S <= '1';
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_SODAcheck_S <= '0';
+ end if;
+ end if;
+ prev_clock5div2_S <= clock5div2_S;
+ end if;
+end process;\r
+\r
+\r
+\r
+process_checkdiv5: process(clock)
+variable disable_count_V : std_logic_vector(3 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ clockdiv5_reset_S <= '0';\r
+ clockdiv5error_S <= '0';
+ if (disable_SODAcheck_S='0') and (disable_clock5check_S='0') then
+ if (clock5div2_S/=prev_clock5div2_S) and div5count0_S='0' then -- div5 clock wrong phase : reset
+ clockdiv5_reset_S <= '1';
+ disable_clock5check_S <= '1';
+ disable_count_V := (others => '0');
+ clockdiv5error_S <= '1';
+ end if;
+ else
+ if disable_count_V(disable_count_V'left)='0' then
+ disable_count_V := disable_count_V+1;
+ else
+ disable_clock5check_S <= '0';
+ end if;
+ end if;\r
+ end if;
+end process;\r
+\r
+process_SODAchar: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ if (kchar='1') and (data=KCHARSODA) then
+ SODA_kchar_S <= '1';
+ else
+ SODA_kchar_S <= '0';
+ end if;
+ end if;
+end process;
+
+process_SODAstart: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+ if (rising_edge(clock)) then
+ SODA40_signal_S <= '0';
+ SODAerror_S <= '0';
+ if (SODA_count_S="0000") and (SODA_kchar_S='1') then
+ SODA40_signal_S <= '1';
+ SODA_count_S <= SODA_count_S+1;
+ elsif SODA_count_S(0)='1' then -- SODA data
+ if SODA_kchar_S='1' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(2 downto 1)/="00") then -- SODA k-char
+ if SODA_kchar_S='0' then -- error
+ SODA_count_S <= "0000";
+ SODAerror_S <= '1';
+ else
+ SODA_count_S <= SODA_count_S+1;
+ end if;
+ elsif (SODA_count_S(3)='1') then -- end SODA packet
+ SODA_count_S <= "0000";
+ if SODA_kchar_S='1' then -- error
+ SODAerror_S <= '1';
+ end if;
+ end if;
+ end if;
+end process;
+
+process_clock5div2: process(clockdiv5_S)
+begin
+ if (rising_edge(clockdiv5_S)) then
+ clock5div2_S <= not clock5div2_S;
+ end if;
+end process;
+\r
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 15-02-2012
+-- Module Name: FEE_adc32_module
+-- Description: Module with Front End Electronics
+-- Modifications:
+-- 15-09-2014 New datafromat for fibers, removed ZPU\r
+-- 16-09-2014 name changed from FEE_V2_adc32_module to FEE_adc32_module
+-- 22-09-2014 single clock
+-- 23-09-2014 system monitor module moved to top-level
+-- 01-10-2014 request_init added: request initialize FEE
+-- 02-10-2014 onesecondpulse, errorbyte
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_adc32_module\r
+-- Module for Front End Electronics: fiber connection, adc waveform reading & multiplexers & feature extraction.\r
+-- ADC data is analysed or put in waveforms if regarded as pileup. \r
+--
+-- The data is sent to the GTP/GTX transceiver in packets\r
+-- Slow control processes slow-control packets on the fiber to/from the multiplexer board.\r
+-- The clock from the GTP/GTX receiver is used to synchronise the SODA-clock. This should be used for the ADC's if that is possible with the hardware.\r
+-- Special SODA package can start/stop data transmitting and reset the timepstamp.\r
+-- The from the fiber also SODA packets.\r
+--\r
+-- The addresses that are used:\r
+-- board_register A: write/read\r
+-- bit0: reset all
+-- bit2: clear errors
+-- bit3: enable waveforms
+-- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
+-- bit 18 = reset/initializes FPGA System monitor
+-- board_register B: read\r
+-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
+-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
+-- bit 15..6 = ADC value from FPGA System monitor
+-- bit23..16 : error occurred bits: in case of error a bit is set. Clearing is done with ADDRESS_FEE_CONTROL
+-- bit16 : error : NotInTable
+-- bit17 : error : receive data error (slowcontrol)
+-- bit18 : error : slowcontrol buffer overrun
+-- bit19 : error : not used
+-- bit20 : error : transmit data error, multiplexer error
+-- bit21 : error : receive data buffer overrun
+-- bit22 : error : adc data buffer overrun
+-- bit23 : error : data taken disabled
+-- board_register C: automatically sent
+-- data not important; this slowcontrol command indicates buffer full
+-- board_register D: read
+-- bit 31..0 = Number of pulses in 1 second on selected input
+--\r
+-- Each ADC has its own set of registers. See module FEE_pulse_and_pileup_waveforms for addresses.\r
+--
+--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+-- NROFADCS : number of the adc's, probably 16
+-- ADCBITS : number of ADC-bits
+-- BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
+-- ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
+-- CF_DELAYBITS : number of bits for the constant fraction delay
+-- CF_FRACTIONBIT : number of bits for the calculated fraction of the precise timestamp
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--
+-- Inputs:
+-- clock : clock for everything
+-- reset : reset all\r
+-- enable_data : enable data, controlled by SODA\r
+-- ADCdata : parallel sampling adc data
+-- rxNotInTable : error in received fiber data, used for status\r
+-- superburst_start : Signal to indicate start of new superburst, received (back) from pin\r
+-- superburst_received : superburstnumber
+-- startupready : startup procedure is finished: ready to send data
+-- request_init : send a request to the DC to initialize all registers
+-- packet_in_data : 32 bits data input from fiber module\r
+-- packet_in_present : data available from fiber module\r
+-- packet_out_fifofull : connected fifo for packet data is full
+-- errorbyte_in : errors occurred for slow control reply\r
+-- smaart_in : serial input from external TMP104 sensor
+-- sysmon_data : data from the FPGA system monitor module\r
+-- \r
+-- Outputs:
+-- packet_in_read : read signal to fiber module to read next data\r
+-- packet_out_data : packet data to fiber module
+-- packet_out_first : first 32-bit data word of a packet
+-- packet_out_last : last 32-bit data word of a packet
+-- packet_out_write : write signal for packet data
+-- errorbyte_out : errors occurred: adjust with other FE instances for comparison\r
+-- smaart_out : serial output to external TMP104 sensor
+-- sysmon_reset : reset signal to the FPGA system monitor module\r
+-- sysmon_address : selection address for the FPGA system monitor module\r
+-- sysmon_read : read signal to the FPGA system monitor module\r
+--
+-- Components:
+-- FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
+-- FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
+-- FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream\r
+-- FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX\r
+-- FEE_measure_frequency : measure frequency of hits\r
+-- TMP104module : module to access external temperature sensor TMP104
+--
+----------------------------------------------------------------------------------
+
+entity FEE_adc32_module is
+ generic (
+ NROFADCS : natural := 32;
+ ADCBITS : natural := 14;
+ BASELINE_BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ ADCCLOCKFREQUENCY : natural := 80000000;
+ CF_DELAYBITS : natural := 4;
+ CF_FRACTIONBIT : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;\r
+ enable_data : in std_logic;
+ ADCdata : in array_adc_type;\r
+ superburst_start : in std_logic;
+ superburst_received : in std_logic_vector(30 downto 0);
+ onesecondpulse : in std_logic;
+ rxNotInTable : in std_logic;
+ startupready : in std_logic;
+ request_init : in std_logic;
+ packet_in_data : in std_logic_vector (31 downto 0);
+ packet_in_present : in std_logic;
+ packet_in_read : out std_logic;\r
+ packet_out_data : out std_logic_vector(31 downto 0);
+ packet_out_first : out std_logic;
+ packet_out_last : out std_logic;
+ packet_out_write : out std_logic;
+ packet_out_fifofull : in std_logic;\r
+ errorbyte_out : out std_logic_vector(7 downto 0);\r
+ errorbyte_in : in std_logic_vector(7 downto 0);\r
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;\r
+ sysmon_data : in std_logic_vector(15 downto 0);\r
+ sysmon_reset : out std_logic;\r
+ sysmon_address : out std_logic_vector(6 downto 0);\r
+ sysmon_read : out std_logic;\r
+ testindex : in integer range 0 to NROFADCS/2-1;\r
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);\r
+ testword2 : out std_logic_vector(35 downto 0)\r
+ );
+end FEE_adc32_module;
+
+architecture Behavioral of FEE_adc32_module is
+
+
+component FEE_board_slowcontrol is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ overflow_in : in std_logic;
+ request_init : in std_logic;
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ slowcontrol_read : in std_logic;
+ slowcontrol_notpresent : out std_logic;
+ slowcontrol_data : out std_logic_vector (31 downto 0);
+ slowcontrol_address : out std_logic_vector (7 downto 0);
+ slowcontrol_reply : out std_logic;
+ board_status_A : in std_logic_vector(31 downto 0);
+ board_status_B : in std_logic_vector(31 downto 0);
+ board_status_C : in std_logic_vector(31 downto 0);
+ board_status_D : in std_logic_vector(31 downto 0);
+ board_control_A : out std_logic_vector(31 downto 0);
+ board_control_B : out std_logic_vector(31 downto 0);
+ board_control_C : out std_logic_vector(31 downto 0);
+ board_control_D : out std_logic_vector(31 downto 0);
+ overflow_out : out std_logic
+ );
+end component;
+
+component FEE_slowcontrol_packet_receiver is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ packet_data_in : in std_logic_vector (31 downto 0);
+ packet_data_present : in std_logic;
+ packet_data_read : out std_logic;
+ byte_data : out std_logic_vector(7 downto 0);
+ byte_write : out std_logic;
+ byte_request : out std_logic;
+ data_error : out std_logic;
+ overflow : out std_logic);
+end component;
+
+component FEE_pulse_and_pileup_waveforms is\r
+ generic (
+ NROFADCS : natural := NROFADCS;
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BASELINE_BWBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ timestampcounter : in std_logic_vector(15 downto 0); \r
+ ADCdata : in array_adc_type;
+ enable_data : in std_logic;
+ slowcontrol_byte_data : in std_logic_vector (7 downto 0);
+ slowcontrol_byte_write : in std_logic;
+ slowcontrol_byte_request: in std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_read : in std_logic;
+ pulsedata_available : out std_logic;
+ pulsedata_inpipe : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_read : in std_logic;
+ pileupdata_available : out std_logic;\r
+ pileupdata_inpipe : out std_logic;
+ pulsedetect : out std_logic_vector(0 to NROFADCS-1);
+ overflow : out std_logic;\r
+ testindex : in integer range 0 to NROFADCS/2-1;\r
+ testword0 : out std_logic_vector(35 downto 0);\r
+ testword1 : out std_logic_vector(35 downto 0);\r
+ testword2 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;\r
+\r
+component FEE_combine_data is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ -- signals to/from data fifo :
+ pulse_data : in std_logic_vector(35 downto 0);
+ pulse_notpresent : in std_logic; -- empty signal from fifo
+ pulse_inpipe : in std_logic;
+ pulse_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data : in std_logic_vector(31 downto 0);
+ slowcontrol_address : in std_logic_vector(7 downto 0);
+ slowcontrol_reply : in std_logic;
+ slowcontrol_notpresent : in std_logic; -- empty signal from fifo
+ slowcontrol_read : out std_logic; -- read from normal fifo
+ -- signals to/from waveform fifo
+ wave_data : in std_logic_vector(35 downto 0);
+ wave_notpresent : in std_logic; -- empty signal from fifo
+ wave_inpipe : in std_logic;
+ wave_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from fiber module
+ packet_data_out : out std_logic_vector(31 downto 0);
+ packet_firstword : out std_logic;
+ packet_lastword : out std_logic;
+ packet_datawrite : out std_logic;
+ packet_fifofull : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)\r
+ );
+end component;\r
+
+component FEE_measure_frequency is\r
+ generic (\r
+ CLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY\r
+ );\r
+ port ( \r
+ clock : in std_logic;
+ pulse : in std_logic;\r
+ onesecondpulse : in std_logic;
+ frequency : out std_logic_vector(31 downto 0)\r
+ );\r
+end component;\r
+\r
+\r
+component TMP104module is
+ generic (
+ TMP104CLOCKDIVIDER : natural := 2500;
+ TMP104INTERVAL : natural := 50
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;\r
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;
+ temperature : out std_logic_vector (7 downto 0)
+ );
+end component;\r
+
+constant init_frequency_in_kHz : integer := 30;
+constant init_freqnr : integer := init_frequency_in_kHz * 83322;
+
+signal error_occurred_S : std_logic_vector (7 downto 0) := (others => '0');
+signal enable_data_S : std_logic := '0';\r
+signal startupready_S : std_logic := '0';\r
+
+signal rxAsyncDataRead_S : std_logic := '0';
+signal rxAsyncData_S : std_logic_vector (31 downto 0) := (others => '0');
+\r
+signal packet_in_read_S : std_logic;
+\r
+signal superburstnumber_s : std_logic_vector(30 downto 0);\r
+
+signal SODA_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0');
+signal SODA_cmd_valid_S : std_logic := '0';\r
+
+signal slowcontrol_error1_S : std_logic := '0';
+
+signal clear_errors_S : std_logic := '0';
+
+signal pulsedata_out_S : std_logic_vector(35 downto 0);
+signal pulsedata_read_S : std_logic;
+signal pulsedata_available_S : std_logic;\r
+signal pulsedata_inpipe_S : std_logic;\r
+signal pileupdata_out_S : std_logic_vector(35 downto 0);
+signal pileupdata_read_S : std_logic;
+signal pileupdata_available_S : std_logic;
+signal pulse_notpresent_S : std_logic;
+signal pileupdata_inpipe_s : std_logic;
+signal overflow_S : std_logic;
+
+signal slowcontrol_data_S : std_logic_vector(31 downto 0);
+signal slowcontrol_address_S : std_logic_vector(7 downto 0);
+signal slowcontrol_reply_S : std_logic;
+signal slowcontrol_notpresent_S : std_logic;
+signal slowcontrol_read_S : std_logic;
+signal receive_overflow_S : std_logic;
+\r
+signal slowcontrol_byte_data_S : std_logic_vector(7 downto 0);
+signal slowcontrol_byte_write_S : std_logic;
+signal slowcontrol_byte_request_S : std_logic;
+signal slowcontrol_overflow_S : std_logic;
+
+signal board_status_A_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_B_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_C_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_status_D_S : std_logic_vector(31 downto 0) := (others => '0');
+signal board_control_A_S : std_logic_vector(31 downto 0);
+signal board_control_B_S : std_logic_vector(31 downto 0);
+signal board_control_C_S : std_logic_vector(31 downto 0);
+signal board_control_D_S : std_logic_vector(31 downto 0);
+\r
+
+signal timestampcounter_s : std_logic_vector(15 downto 0) := (others => '0');
+signal start_of_superburst_S : std_logic := '0';\r
+\r
+signal MUX_error_S : std_logic := '0';\r
+\r
+signal enable_waveform_S : std_logic := '0';\r
+signal wave_notpresent_S : std_logic := '0';\r
+signal wave_read_S : std_logic := '0';\r
+\r
+signal pulsedetect_S : std_logic_vector(0 to NROFADCS-1);\r
+signal pulsedetectmux_S : std_logic := '0';\r
+signal pulsefrequency_S : std_logic_vector (31 downto 0);\r
+\r
+signal sysmon_address_S : std_logic_vector(6 downto 0);
+signal sysmon_address_saved_S : std_logic_vector(6 downto 0);
+signal temperature_S : std_logic_vector (7 downto 0) := (others => '0');\r
+signal testword0_S : std_logic_vector(35 downto 0);
+signal testword1_S : std_logic_vector(35 downto 0);\r
+
+constant DEBUG : std_logic := '0';
+begin
+\r
+ \r
+timestampcounter: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if superburst_start='1' then\r
+ timestampcounter_S <= (others => '0');\r
+ superburstnumber_S <= superburst_received;\r
+ else\r
+ timestampcounter_S <= timestampcounter_S+1;\r
+ end if;\r
+ end if;
+end process;\r
+ \r
+ \r
+gendebug2: if DEBUG='0' generate\r
+
+
+FEE_slowcontrol_packet_receiver1: FEE_slowcontrol_packet_receiver port map(
+ clock => clock,
+ reset => reset,
+ enable => startupready,
+ packet_data_in => packet_in_data,
+ packet_data_present => packet_in_present,
+ packet_data_read => packet_in_read_S,
+ byte_data => slowcontrol_byte_data_S,
+ byte_write => slowcontrol_byte_write_S,
+ byte_request => slowcontrol_byte_request_S,
+ data_error => slowcontrol_error1_S,
+ overflow => receive_overflow_S);
+packet_in_read <= packet_in_read_S;\r
+
+FEE_board_slowcontrol1: FEE_board_slowcontrol port map(
+ clock => clock,
+ reset => reset,
+ enable => startupready,
+ overflow_in => receive_overflow_S,
+ request_init => request_init,
+ byte_data => slowcontrol_byte_data_S,
+ byte_write => slowcontrol_byte_write_S,
+ byte_request => slowcontrol_byte_request_S,
+ slowcontrol_read => slowcontrol_read_S,
+ slowcontrol_notpresent => slowcontrol_notpresent_S,
+ slowcontrol_data => slowcontrol_data_S,
+ slowcontrol_address => slowcontrol_address_S,
+ slowcontrol_reply => slowcontrol_reply_S,
+ board_status_A => board_status_A_S,
+ board_status_B => board_status_B_S,
+ board_status_C => board_status_C_S,
+ board_status_D => board_status_D_S,
+ board_control_A => board_control_A_S,
+ board_control_B => board_control_B_S,
+ board_control_C => board_control_C_S,
+ board_control_D => board_control_D_S,
+ overflow_out => slowcontrol_overflow_S);
+
+\r
+
+slowcontrolhandling: process(clock)
+variable clear_timeout_V : integer range 0 to 15 := 15;
+begin
+ if (rising_edge(clock)) then
+ if (clear_errors_S='1') or (reset='1') then
+ error_occurred_S <= (others => '0');
+ else
+ if rxNotInTable='1' then
+ error_occurred_S(0) <= '1';
+ end if;
+ if slowcontrol_error1_S='1' then
+ error_occurred_S(1) <= '1';
+ end if;
+ if (slowcontrol_overflow_S='1') then
+ error_occurred_S(2) <= '1';
+ end if;\r
+-- if cf_error_S='1' then
+-- error_occurred_S(3) <= '1';
+-- end if;\r
+ if MUX_error_S='1' then
+ error_occurred_S(4) <= '1';
+ end if;\r
+-- if (rxAsyncDataOverflow_S='1') then
+-- error_occurred_S(5) <= '1';
+-- end if;
+ if overflow_S='1' then
+ error_occurred_S(6) <= '1';
+ end if;
+ error_occurred_S(7) <= not enable_data;
+ end if;
+ end if;
+end process;
+\r
+\r
+
+
+clear_errors_S <= board_control_A_S(2);\r
+enable_waveform_S <= board_control_A_S(3);\r
+pulsedetectmux_S <= pulsedetect_S(conv_integer(unsigned(board_control_A_S(20 downto 16))));\r
+sysmon_reset <= '1' when (reset='1') or (board_control_A_S(21)='1') else '0';
+sysmon_address_S(1 downto 0) <= board_control_A_S(23 downto 22);
+sysmon_address_S(6 downto 2) <= (others => '0');\r
+\r
+checksysmonchange: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if sysmon_address_S(1 downto 0)/=sysmon_address_saved_S(1 downto 0) then
+ sysmon_read <= '1';
+ else
+ sysmon_read <= '0';
+ end if;
+ sysmon_address_saved_S(1 downto 0) <= sysmon_address_S(1 downto 0);
+ end if;
+end process;\r
+sysmon_address <= sysmon_address_S;
+\r
+
+board_status_A_S <= board_control_A_S;
+
+board_status_B_S(0) <= '0';
+board_status_B_S(1) <= enable_data;
+board_status_B_S(3 downto 2) <= (others => '0');
+board_status_B_S(5 downto 4) <= sysmon_address_saved_S(1 downto 0);
+board_status_B_S(15 downto 6) <= sysmon_data(15 downto 6);
+board_status_B_S(23 downto 16) <= errorbyte_in;
+board_status_B_S(31 downto 24) <= temperature_S;
+errorbyte_out <= error_occurred_S;\r
+\r
+
+board_status_D_S(31 downto 0) <= pulsefrequency_S;\r
+\r
+\r
+FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms port map(
+ clock => clock,
+ reset => reset,
+ superburstnumber => superburstnumber_S,
+ timestampcounter => timestampcounter_S,
+ ADCdata => ADCdata,
+ enable_data => enable_data,
+ slowcontrol_byte_data => slowcontrol_byte_data_S,
+ slowcontrol_byte_write => slowcontrol_byte_write_S,
+ slowcontrol_byte_request => slowcontrol_byte_request_S,
+ pulsedata_out => pulsedata_out_S,
+ pulsedata_read => pulsedata_read_S,
+ pulsedata_available => pulsedata_available_S,
+ pulsedata_inpipe => pulsedata_inpipe_S,
+ pileupdata_out => pileupdata_out_S,
+ pileupdata_read => pileupdata_read_S,
+ pileupdata_available => pileupdata_available_S,
+ pileupdata_inpipe => pileupdata_inpipe_S,
+ pulsedetect => pulsedetect_S,
+ overflow => overflow_S,
+ testindex => testindex,\r
+ testword0 => testword0,
+ testword1 => testword1,
+ testword2 => testword2
+ );
+ \r
+pulse_notpresent_S <= not pulsedata_available_S;
+FEE_combine_data1: FEE_combine_data port map(
+ clock => clock,
+ reset => reset,
+ -- signals to/from data fifo :
+ pulse_data => pulsedata_out_S,
+ pulse_notpresent => pulse_notpresent_S,
+ pulse_inpipe => pulsedata_inpipe_S,
+ pulse_read => pulsedata_read_S,\r
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data => slowcontrol_data_S,
+ slowcontrol_address => slowcontrol_address_S,
+ slowcontrol_reply => slowcontrol_reply_S,
+ slowcontrol_notpresent => slowcontrol_notpresent_S,
+ slowcontrol_read => slowcontrol_read_S,
+ -- signals to/from waveform fifo
+ wave_data => pileupdata_out_S,
+ wave_notpresent => wave_notpresent_S,
+ wave_inpipe => pileupdata_inpipe_S,
+ wave_read => wave_read_S,
+ -- signals to/from fiber module
+ packet_data_out => packet_out_data,
+ packet_firstword => packet_out_first,
+ packet_lastword => packet_out_last,
+ packet_datawrite => packet_out_write,
+ packet_fifofull => packet_out_fifofull,
+ error => MUX_error_S,
+ testword0 => open);
+\r
+wave_notpresent_S <= '1' when (pileupdata_available_S='0') or (enable_waveform_S='0') else '0';\r
+pileupdata_read_S <= '1' when (enable_waveform_S='0') and (pileupdata_available_S='1') else wave_read_S;\r
+
+--gtpClk_I : IBUFDS port map(
+-- O => gtpClk_S,
+-- I => gtpClkP0,
+-- IB => gtpClkN0);\r
+
+--GTX_refclock: IBUFDS_GTXE1 port map(
+-- O => gtpClk_S,
+-- ODIV2 => open,
+-- CEB => '0',
+-- I => MGTREFCLK_P,
+-- IB => MGTREFCLK_N);\r
+end generate; --debug\r
+
+gendebug3: if DEBUG='0' generate\r
+FEE_measure_frequency1: FEE_measure_frequency port map(\r
+ clock => clock,
+ pulse => pulsedetectmux_S,\r
+ onesecondpulse => onesecondpulse,
+ frequency => pulsefrequency_S);\r
+end generate; -- debug\r
+
+--TMP104module1: TMP104module port map(
+-- clock => clock,
+-- reset => reset,\r
+-- smaart_in => smaart_in,
+-- smaart_out => smaart_out,
+-- temperature => temperature_S);\r
+--testword0(34 downto 0) <= testword0_S(34 downto 0);\r
+--testword0(35) <= enable_waveform_S;\r
+
+--testword1(15 downto 0) <= packet_in_data(31 downto 16); \r
+--testword1(16) <= packet_in_present; \r
+--testword1(17) <= packet_in_read_S; \r
+--testword1(18) <= slowcontrol_byte_write_S; \r
+--testword1(19) <= slowcontrol_byte_request_S; \r
+--testword1(27 downto 20) <= slowcontrol_byte_data_S; \r
+--testword1(28) <= slowcontrol_error1_S; \r
+--testword1(29) <= receive_overflow_S; \r
+--testword1(34 downto 30) <= testword1_S(4 downto 0); \r
+--testword1(35) <= '1' when testword1_S(23 downto 0)=x"000000" else '0';\r
+\r
+ \r
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 27-01-2012
+-- Module Name: FEE_baselinefollower_eventdetector
+-- Description: Baseline reconstruction, pulse detection
+-- Modifications:
+-- 16-09-2014 name changed from baselinefollower_eventdetector to FEE_baselinefollower_eventdetector
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+----------------------------------------------------------------------------------
+-- FEE_baselinefollower_eventdetector
+-- Baseline reconstruction, pulse detection
+--
+-- generics
+-- ADCBITS : number of ADC bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset\r
+-- enable : enable detection of pulses
+-- ADCdata : ADC sampling data
+-- threshold : threshold above baseline for start of pulse
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+--
+-- outputs
+-- baseline : resulting corrected baseline\r
+-- ADC_delayed : ADC data delayed with 1 clock
+-- ADC_minus_baseline : ADC values delayed minus baseline
+-- baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
+-- pulse_active : the ADC-signal exceeds the trigger-level\r
+-- pulse_rising : the pulse has not yet reached its maximum\r
+-- max_data : maximum value of waveform\r
+--
+-- components
+-- IIRfilter_1order : IIR filter for the baseline
+-- FEE_eventdetector : detection of pulse
+--
+----------------------------------------------------------------------------------
+
+
+
+entity FEE_baselinefollower_eventdetector is
+ generic (
+ ADCBITS : natural := 16;
+ BWBITS : natural := 10
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold : in std_logic_vector((ADCBITS-1) downto 0);
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ baseline : out std_logic_vector((ADCBITS-1) downto 0);
+ ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
+ ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
+ baseline_inhibit : out std_logic;
+ pulse_active : out std_logic;\r
+ pulse_rising : out std_logic;\r
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)\r
+ );
+end FEE_baselinefollower_eventdetector;
+
+architecture Behavioral of FEE_baselinefollower_eventdetector is
+
+component iirfilter_1order_selectBW is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector ((ADCBITS-1) downto 0);
+ BWidx : in std_logic_vector (2 downto 0);
+ inhibit : in std_logic;
+ data_out : out std_logic_vector ((ADCBITS-1) downto 0));
+end component;
+
+component FEE_eventdetector is\r
+ generic (\r
+ ADCBITS : natural := ADCBITS\r
+ );\r
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector (ADCBITS downto 0); \r
+ threshold : in std_logic_vector ((ADCBITS-1) downto 0);\r
+ maxabovebaseline : in std_logic_vector (3 downto 0);\r
+ baseline_freeze : out std_logic;\r
+ pulse_active : out std_logic;\r
+ pulse_rising : out std_logic;\r
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)\r
+ );\r
+end component;
+
+signal ADC_delayed_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
+signal baseline_S : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
+signal ADC_minusbaseline_S : std_logic_vector(ADCBITS downto 0) := (others => '0');\r
+signal baseline_inhibit_S : std_logic := '0';\r
+signal pulse_active_S : std_logic := '0';\r
+signal enable_S : std_logic := '0';\r
+\r
+
+
+begin
+
+
+
+baselinefilter: iirfilter_1order_selectBW port map(
+ clock => clock,
+ reset => reset,
+ data_in => ADC_delayed_S,
+ BWidx => IIRfilterBW(2 downto 0),
+ inhibit => baseline_inhibit_S,
+ data_out => baseline_S);
+
+ADC_minusbaseline_S <= conv_std_logic_vector(conv_integer(signed('0' & ADCdata)) - conv_integer(signed('0' & baseline_S)),(ADCBITS+1));
+
+FEE_eventdetector1: FEE_eventdetector port map(\r
+ clock => clock,
+ reset => reset,
+ data_in => ADC_minusbaseline_S,
+ threshold => threshold,\r
+ maxabovebaseline => maxabovebaseline,\r
+ baseline_freeze => baseline_inhibit_S,\r
+ pulse_active => pulse_active_S,\r
+ pulse_rising => pulse_rising,\r
+ max_data => max_data);\r
+pulse_active <= pulse_active_S when enable_S='1' else '0';\r
+\r
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ ADC_delayed_S <= ADCdata;\r
+ if pulse_active_S='0' then\r
+ enable_S <= enable;\r
+ end if;
+ end if;
+end process;\r
+
+baseline <= baseline_S;
+baseline_inhibit <= baseline_inhibit_S;\r
+ADC_delayed <= ADC_delayed_S;
+ADC_minus_baseline <= ADC_minusbaseline_S;\r
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------\r
+-- Company: KVI/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 15-09-2014\r
+-- Module Name: FEE_board_slowcontrol \r
+-- Description: Handles FEE board slowcontrol\r
+-- 22-09-2014 single clock
+-- 01-10-2014 request_init added: request initialize FEE\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+USE ieee.std_logic_unsigned.all ;\r
+USE ieee.std_logic_arith.all ;\r
+USE work.panda_package.all;\r
+\r
+----------------------------------------------------------------------------------\r
+-- FEE_board_slowcontrol\r
+-- Handles slow control for the FEE board control and status registers.\r
+--\r
+-- The slow control commands are receives byte-wise: first 8-bits address, then 4 bytes data, MSB first.\r
+-- There are four control registers.\r
+--\r
+-- The status registers are requested with a request signal and the same 8-bits address, but no data bytes.\r
+-- There are also four status registers.\r
+-- These registers are buffered in a fifo.\r
+-- \r
+-- The slow control output to be send to the Data Concentrator consist of a 8-bits address, a 32 bits data word and a reply bit.\r
+--\r
+-- Library\r
+-- work.panda_package : for type declarations and constants\r
+--\r
+-- Generics:\r
+-- \r
+-- Inputs:\r
+-- clock : clock input\r
+-- reset : reset\r
+-- enable : enable module\r
+-- overflow_in : overflow from the fiber packet receiver; this will issue an error slow command to be send to the DC\r
+-- request_init : send a request to the DC to initialize all registers\r
+-- byte_data : 8-bits slowcontrol data:\r
+-- Byte0 : 8-bits address, lowest 2 bits selects register A,B,C or D\r
+-- Byte1,2,3,4 : 32-bits data, MSB first\r
+-- byte_write : write signal for byte-data\r
+-- byte_request : request signal for reading data\r
+-- slowcontrol_read : read signal for the slowcontrol output fifo \r
+-- board_status_A : status register A\r
+-- board_status_B : status register B\r
+-- board_status_C : status register C\r
+-- board_status_D : status register D\r
+-- \r
+-- Outputs:\r
+-- slowcontrol_notpresent : empty signal \r
+-- slowcontrol_data : slowcontrol 32-bits data\r
+-- slowcontrol_address : slowcontrol 8-bits address\r
+-- slowcontrol_reply : slowcontrol reply bit\r
+-- board_control_A : control register A\r
+-- board_control_B : control register B\r
+-- board_control_C : control register C\r
+-- board_control_D : control register D\r
+-- overflow_out : buffer overflow form slowcontrol fifo or fiber packet buffer\r
+--\r
+-- Components:\r
+-- sync_fifo_512x41 : fifo for the slowcontrol commands\r
+-- \r
+----------------------------------------------------------------------------------\r
+\r
+entity FEE_board_slowcontrol is\r
+ Port ( \r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ overflow_in : in std_logic;\r
+ request_init : in std_logic;\r
+ byte_data : in std_logic_vector(7 downto 0);\r
+ byte_write : in std_logic;\r
+ byte_request : in std_logic;\r
+ slowcontrol_read : in std_logic; \r
+ slowcontrol_notpresent : out std_logic; \r
+ slowcontrol_data : out std_logic_vector (31 downto 0);\r
+ slowcontrol_address : out std_logic_vector (7 downto 0);\r
+ slowcontrol_reply : out std_logic;\r
+ board_status_A : in std_logic_vector(31 downto 0);\r
+ board_status_B : in std_logic_vector(31 downto 0);\r
+ board_status_C : in std_logic_vector(31 downto 0);\r
+ board_status_D : in std_logic_vector(31 downto 0);\r
+ board_control_A : out std_logic_vector(31 downto 0);\r
+ board_control_B : out std_logic_vector(31 downto 0);\r
+ board_control_C : out std_logic_vector(31 downto 0);\r
+ board_control_D : out std_logic_vector(31 downto 0);\r
+ overflow_out : out std_logic\r
+ );\r
+end FEE_board_slowcontrol;\r
+\r
+architecture Behavioral of FEE_board_slowcontrol is\r
+\r
+component sync_fifo_512x41\r
+ port (\r
+ rst : in std_logic;\r
+ clk : in std_logic;\r
+ din : in std_logic_vector(40 downto 0);\r
+ wr_en : in std_logic;\r
+ rd_en : in std_logic;\r
+ dout : out std_logic_vector(40 downto 0);\r
+ full : out std_logic;\r
+ empty : out std_logic);\r
+end component;\r
+\r
+signal enable_S : std_logic;\r
+\r
+signal slowpacketvalid_S : std_logic := '0';\r
+signal slowcontrol_data_S : std_logic_vector (31 downto 0);\r
+signal slowcontrol_address_S : std_logic_vector (7 downto 0);\r
+signal slowcontrol_reply_S : std_logic := '0';\r
+signal slowcontrol_write_S : std_logic;\r
+signal slowcontrol_fifofull_S : std_logic;\r
+\r
+signal board_control_A_S : std_logic_vector (31 downto 0) := x"00000000";\r
+signal board_control_B_S : std_logic_vector (31 downto 0) := x"00000000";\r
+signal board_control_C_S : std_logic_vector (31 downto 0) := x"00000000";\r
+signal board_control_D_S : std_logic_vector (31 downto 0) := x"00000000";\r
+\r
+\r
+signal slowcontrol_read_S : std_logic := '0';\r
+signal slowcontrol_read_after1clk_S : std_logic := '0';\r
+signal slowcontrol_fifoempty_S : std_logic := '0';\r
+\r
+signal register_buf_S : std_logic_vector (31 downto 0);\r
+signal byte_idx_S : integer range 0 to 4 := 0;\r
+signal overflow1_S : std_logic := '0';\r
+signal overflow2_S : std_logic := '0';\r
+signal overflow_in_S : std_logic := '0';\r
+signal selected_S : std_logic := '0';\r
+signal selected_reg_s : std_logic_vector (1 downto 0);\r
+signal request_init1_S : std_logic := '0';\r
+signal request_init_S : std_logic := '0';\r
+ \r
+signal fifo_in_S : std_logic_vector (40 downto 0);\r
+signal fifo_out_S : std_logic_vector (40 downto 0);\r
+\r
+begin\r
+\r
+board_control_A <= board_control_A_S;\r
+board_control_B <= board_control_B_S;\r
+board_control_C <= board_control_C_S;\r
+board_control_D <= board_control_D_S;\r
+overflow_out <= '1' when (overflow1_S='1') or (overflow2_S='1') else '0';\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ enable_S <= enable;\r
+ end if;\r
+end process;\r
+\r
+read_bytewise_process: process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ slowcontrol_write_S <= '0';\r
+ if (reset='1') or (enable_S='0') then\r
+ byte_idx_S <= 0;\r
+ selected_S <= '0';\r
+ overflow1_S <= '0';\r
+ overflow2_S <= '0';\r
+ request_init1_S <= '0';\r
+ else\r
+ if (overflow_in='1') and (overflow_in_S='0') then\r
+ overflow1_S <= '1';\r
+ end if;\r
+ if (request_init='1') and (request_init_S='0') then\r
+ request_init1_S <= '1';\r
+ end if;\r
+ if byte_idx_S=0 then\r
+ if (byte_write='1') then\r
+ if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
+ selected_S <= '1';\r
+ selected_reg_S <= byte_data(1 downto 0);\r
+ else\r
+ selected_S <= '0';\r
+ end if;\r
+ byte_idx_S <= 1;\r
+ elsif byte_request='1' then\r
+ if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then\r
+ case byte_data(1 downto 0) is\r
+ when "00" => slowcontrol_data_S <= board_status_A;\r
+ when "01" => slowcontrol_data_S <= board_status_B;\r
+ when "10" => slowcontrol_data_S <= board_status_C;\r
+ when "11" => slowcontrol_data_S <= board_status_D;\r
+ when others => \r
+ end case;\r
+ slowcontrol_address_S <= byte_data;\r
+ slowcontrol_reply_S <= '1';\r
+ slowcontrol_write_S <= '1';\r
+ if slowcontrol_fifofull_S='1' then\r
+ overflow2_S <= '1';\r
+ end if;\r
+ end if; \r
+ selected_S <= '0';\r
+ byte_idx_S <= 0;\r
+ elsif request_init1_S='1' then\r
+ selected_S <= '0';\r
+ if (slowcontrol_fifofull_S='0') then -- send request init FEE command\r
+ request_init1_S <= '0';\r
+ slowcontrol_data_S <= (others => '0');\r
+ slowcontrol_address_S <= ADDRESS_FEE_REQUESTALLREGISTERS;\r
+ slowcontrol_reply_S <= '1';\r
+ slowcontrol_write_S <= '1';\r
+ end if;\r
+ else \r
+ selected_S <= '0';\r
+ if (overflow1_S='1') or (overflow2_S='1') then\r
+ if (slowcontrol_fifofull_S='0') then -- send error slowcontrol command\r
+ overflow1_S <= '0';\r
+ overflow2_S <= '0';\r
+ slowcontrol_data_S <= (others => '0');\r
+ slowcontrol_address_S <= ADDRESS_FEE_SLOWCONTROLERROR;\r
+ slowcontrol_reply_S <= '1'; -- ??\r
+ slowcontrol_write_S <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ elsif byte_request='1' then -- unexpected : synchronize\r
+ byte_idx_S <= 0;\r
+ else\r
+ if selected_S='1' then\r
+ case byte_idx_S is \r
+ when 1 => \r
+ register_buf_S(31 downto 24) <= byte_data;\r
+ when 2 => \r
+ register_buf_S(23 downto 16) <= byte_data;\r
+ when 3 => \r
+ register_buf_S(15 downto 8) <= byte_data;\r
+ when 4 => \r
+ case selected_reg_S is \r
+ when "00" => board_control_A_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "01" => board_control_B_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "10" => board_control_C_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "11" => board_control_D_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when others =>\r
+ end case;\r
+ when others =>\r
+ end case;\r
+ end if;\r
+ if byte_idx_S<4 then\r
+ byte_idx_S <= byte_idx_S+1;\r
+ else\r
+ byte_idx_S <= 0;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ overflow_in_S <= overflow_in;\r
+ request_init_S <= request_init;\r
+ end if;\r
+end process;\r
+\r
+fifo_in_S <= slowcontrol_reply_S & slowcontrol_address_S & slowcontrol_data_S;\r
+fifo1: sync_fifo_512x41 port map(\r
+ rst => reset,\r
+ clk => clock,\r
+ din => fifo_in_S,\r
+ wr_en => slowcontrol_write_S,\r
+ rd_en => slowcontrol_read,\r
+ dout => fifo_out_S,\r
+ full => slowcontrol_fifofull_S,\r
+ empty => slowcontrol_notpresent);\r
+\r
+slowcontrol_data <= fifo_out_S(31 downto 0);\r
+slowcontrol_address <= fifo_out_S(39 downto 32);\r
+slowcontrol_reply <= fifo_out_S(40);\r
+\r
+\r
+\r
+end Behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 28-02-2012
+-- Module Name: FEE_combine_data
+-- Description: Write Front End Data, waveforms and Slow-control commands to fiber to Multiplexer
+-- Modifications:
+-- 09-09-2014 New data formats without hamming code
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 Inpipe signals, better sorting between waveforms and single pulse packets
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_combine_data
+-- Module in the Front End Electronics that builds packets from Pulse data, waveforms and
+-- Slow-control data to send to the fiber module.
+--
+-- The pulse data consists of three successive 36-bits words with bits 35..34 the index:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--
+-- The Slow-control commands consists of address and data plus a bit to indicate reply.
+-- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent
+--
+-- The waveform data consists of 36-bits data with variable length :
+-- bits(35..32)="0000" : bits(31..16)=superburstnumber, bits(31..0)=timestamp inside superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--
+--
+-- The resulting data packets : 4 32-bit words, with CRC8 in last word
+-- 0xDA ADCnumber(7..0) superburstnumber(15..0)
+-- 0000 energy(15..0)
+-- CF_before(15..0) CF_after(15..0)
+-- timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+-- 0xAF ADCnumber(7..0) superburstnumber(15..0)
+-- timestamp(15..0) 0x00 statusbyte(7..0)
+-- 0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+-- 0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+-- .........
+-- 1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+-- or
+-- 0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock input
+-- reset : synchronous reset
+-- pulse_data : data with results from Feature Extraction
+-- pulse_notpresent : pulse data not available (empty signal from connected fifo)
+-- pulse_inpipe : more single pulse data on its way
+-- slowcontrol_data : slow-control command :
+-- first address-word with bit31=reply, bit30..28=101 and bit23..0=address then data-word
+-- slowcontrol_notpresent : slow-control not available (empty signal from fifo)
+-- wave_data : data with pileup waveforms from pileup multiplexer
+-- wave_notpresent : pileup waveform not available (empty signal from fifo)\r
+-- wave_inpipe : more wave data on its way
+-- packet_fifofull : connected fifo for packet data is full
+--
+-- Outputs:
+-- pulse_read : read signal for pulse data
+-- slowcontrol_read : read signal for slow-control data
+-- wave_read : read signal for pileup waveform data
+-- packet_data_out : packet data to fiber module\r
+-- packet_firstword : first 32-bit data word of a packet
+-- packet_lastword : last 32-bit data word of a packet
+-- packet_datawrite : write signal for packet data
+-- error : error on incomming data (no sequential index)
+--
+-- Components:
+-- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words
+-- the check is not used in this module
+--
+----------------------------------------------------------------------------------
+
+entity FEE_combine_data is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ -- signals to/from data fifo :
+ pulse_data : in std_logic_vector(35 downto 0);
+ pulse_notpresent : in std_logic; -- empty signal from fifo
+ pulse_inpipe : in std_logic;
+ pulse_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from slowcontrol fifo
+ slowcontrol_data : in std_logic_vector(31 downto 0);
+ slowcontrol_address : in std_logic_vector(7 downto 0);
+ slowcontrol_reply : in std_logic;
+ slowcontrol_notpresent : in std_logic; -- empty signal from fifo
+ slowcontrol_read : out std_logic; -- read from normal fifo
+ -- signals to/from waveform fifo
+ wave_data : in std_logic_vector(35 downto 0);
+ wave_notpresent : in std_logic; -- empty signal from fifo
+ wave_inpipe : in std_logic;
+ wave_read : out std_logic; -- read from FWFT fifo
+ -- signals to/from fiber module
+ packet_data_out : out std_logic_vector(31 downto 0);
+ packet_firstword : out std_logic;
+ packet_lastword : out std_logic;
+ packet_datawrite : out std_logic;
+ packet_fifofull : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0));
+end FEE_combine_data;
+
+architecture Behavioral of FEE_combine_data is
+
+component crc8_add_check32 is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;
+ crc_error : out std_logic
+ );
+end component;
+
+constant INPIPE_DELAY : integer := 255;
+
+type tx_state_type is (init,idle,data0,data1,data2,wave0,wave1,wave2,slow0);
+signal tx_state_S : tx_state_type := init;
+
+signal error_S : std_logic := '0';
+signal pulse_read0_S : std_logic := '0';
+signal pulse_read_S : std_logic := '0';
+
+signal crc8_data_in_S : std_logic_vector (31 downto 0);
+signal crc8_reset_S : std_logic := '0';
+signal crc8_clear_S : std_logic := '0';
+signal crc8_data_in_valid_S : std_logic := '0';
+signal crc8_data_in_last_S : std_logic := '0';
+signal crc8_writeword_S : std_logic := '0';
+signal crc8_data_out_valid_S : std_logic := '0';
+signal prev_crc8_data_out_valid_S : std_logic := '0';
+signal crc8_data_out_last_S : std_logic := '0';
+signal prev_crc8_data_out_last_S : std_logic := '0';
+
+signal crc8_lastword_S : std_logic_vector (31 downto 0);
+signal crc8_lastwrite_S : std_logic := '0';
+signal slowcontrol_read_S : std_logic := '0';
+\r
+signal packet_datawrite_S : std_logic;
+signal packet_lastword_S : std_logic;
+signal packet_firstword_S : std_logic := '1';
+
+
+--signal delay_inpipe_pulse_S : std_logic := '0';
+--signal delay_inpipe_wave_S : std_logic := '0';
+
+signal wave_read0_S : std_logic := '0';
+signal wave_read_S : std_logic := '0';
+signal superburst_S : std_logic_vector (15 downto 0);
+signal timestamp_S : std_logic_vector (15 downto 0);
+signal statusbyte_S : std_logic_vector (7 downto 0);
+--signal channel_S : std_logic_vector (7 downto 0);
+signal energy_S : std_logic_vector (15 downto 0);
+signal CF_before_S : std_logic_vector (15 downto 0);
+signal CF_after_S : std_logic_vector (15 downto 0);
+
+
+signal waveisolder_S : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+crc8_data_in_valid_S <= '1' when (crc8_writeword_S='1') and (packet_fifofull='0') else '0';
+crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
+crc8check: crc8_add_check32 port map(
+ clock => clock,
+ reset => crc8_reset_S,
+ data_in => crc8_data_in_S,
+ data_in_valid => crc8_data_in_valid_S,
+ data_in_last => crc8_data_in_last_S,
+ data_out => packet_data_out,
+ data_out_valid => crc8_data_out_valid_S,
+ data_out_last => crc8_data_out_last_S,
+ crc_error => open); -- only generate, no check
+ \r
+packet_datawrite <= packet_datawrite_S;
+packet_datawrite_S <= '1' when ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) or
+ ((prev_crc8_data_out_valid_S='1') and (packet_fifofull='0')) else '0';\r
+packet_lastword <= packet_lastword_S;
+packet_lastword_S <= '1' when (crc8_data_out_last_S='1') or (prev_crc8_data_out_last_S='1') else '0';\r
+packet_firstword <= '1' when (packet_firstword_S='1') and (packet_datawrite_S='1') else '0';
+\r
+process(clock) -- process to determine firstword
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ packet_firstword_S <= '1';
+ else
+ if (packet_datawrite_S='1') and (packet_lastword_S='1') then
+ packet_firstword_S <= '1';\r
+ elsif packet_datawrite_S='1' then\r
+ packet_firstword_S <= '0';\r
+ end if;\r
+ end if;
+ end if;
+end process;
+\r
+
+process(clock) -- process to freeze output of crc8 in case of packet_fifofull
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ prev_crc8_data_out_valid_S <= '0';
+ prev_crc8_data_out_last_S <= '0';
+ else
+ if ((crc8_data_out_valid_S='1') and (packet_fifofull='1')) then
+ prev_crc8_data_out_valid_S <= '1';
+ prev_crc8_data_out_last_S <= crc8_data_out_last_S;
+ elsif ((crc8_data_out_valid_S='1') and (packet_fifofull='0')) then
+ prev_crc8_data_out_valid_S <= '0';
+ prev_crc8_data_out_last_S <= '0';
+ elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='0')) then
+ prev_crc8_data_out_last_S <= '0';
+ prev_crc8_data_out_valid_S <= '0';
+ elsif ((crc8_data_out_valid_S='0') and (packet_fifofull='1')) then
+ prev_crc8_data_out_valid_S <= prev_crc8_data_out_valid_S;
+ prev_crc8_data_out_last_S <= prev_crc8_data_out_last_S;
+ end if;
+ end if;
+ end if;
+end process;
+
+wave_read <= wave_read_S;
+pulse_read <= pulse_read_S;
+slowcontrol_read <= slowcontrol_read_S;
+
+--process(clock)
+--variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
+--begin
+-- if rising_edge(clock) then
+-- if reset='1' then
+-- inpipe_counter_V := 0;
+-- delay_inpipe_pulse_S <= '0';
+-- else
+-- if (pulse_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
+-- (wave_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
+-- then
+-- inpipe_counter_V := INPIPE_DELAY;
+-- delay_inpipe_pulse_S <= '1';
+-- else
+-- if inpipe_counter_V/=0 then
+-- inpipe_counter_V := inpipe_counter_V-1;
+-- delay_inpipe_pulse_S <= '1';
+-- else
+-- delay_inpipe_pulse_S <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end if;
+--end process;
+--
+--process(clock)
+--variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
+--begin
+-- if rising_edge(clock) then
+-- if reset='1' then
+-- inpipe_counter_V := 0;
+-- delay_inpipe_wave_S <= '0';
+-- else
+-- if (wave_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
+-- (pulse_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
+-- then
+-- inpipe_counter_V := INPIPE_DELAY;
+-- delay_inpipe_wave_S <= '1';
+-- else
+-- if inpipe_counter_V/=0 then
+-- inpipe_counter_V := inpipe_counter_V-1;
+-- delay_inpipe_wave_S <= '1';
+-- else
+-- delay_inpipe_wave_S <= '0';
+-- end if;
+-- end if;
+-- end if;
+-- end if;
+--end process;
+
+waveisolder_S <= '1' when ((wave_data(31 downto 16)<pulse_data(31 downto 16)) and (not ((wave_data(31 downto 30)="00") and (pulse_data(31 downto 30)="11")))) or
+ ((wave_data(31 downto 16)=pulse_data(31 downto 16)) and (wave_data(15 downto 0)<pulse_data(15 downto 0)))
+ else '0';
+\r
+wave_read_S <= '1' when (wave_data(35 downto 32)/="0000") and (tx_state_S=idle) and (wave_notpresent='0') else wave_read0_S;\r
+
+wave_read0_S <= '1' when (wave_notpresent='0') and (packet_fifofull='0') and
+ (((pulse_notpresent='0') or (pulse_inpipe='0')) or (tx_state_S/=idle)) and
+ ((tx_state_S=wave0) or (tx_state_S=wave2) or
+ ((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((pulse_notpresent='1') or (waveisolder_S='1'))))
+ else '0';
+
+pulse_read_S <= '1' when (pulse_data(35 downto 34)/="00") and (tx_state_S=idle) and (pulse_notpresent='0') else pulse_read0_S;\r
+
+pulse_read0_S <= '1' when (pulse_notpresent='0') and (packet_fifofull='0') and
+ ((wave_notpresent='0') or (wave_inpipe='0') or (tx_state_S/=idle)) and
+ ((tx_state_S=data0) or (tx_state_S=data1) or
+ ((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((wave_notpresent='1') or (waveisolder_S='0'))))
+ else '0';
+
+slowcontrol_read_S <= '1' when (slowcontrol_notpresent='0') and (packet_fifofull='0') and (tx_state_S=idle) else '0';
+
+
+datahandling: process(clock)
+variable timeoutcounter_V : integer range 0 to 15 := 0;
+begin
+ if rising_edge(clock) then
+ crc8_clear_S <= '0';
+ crc8_writeword_S <= '0';
+ if reset='1' then
+ crc8_data_in_last_S <= '0';
+ crc8_clear_S <= '1';
+ tx_state_S <= init;\r
+ crc8_data_in_last_S <= '0';
+ error_S <= '0';
+ else
+ if ((crc8_writeword_S='1') and (crc8_data_in_valid_S='0')) then -- unsuccessful write, keep on trying
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= crc8_data_in_last_S;
+ else
+ case tx_state_S is
+ when init =>
+ crc8_data_in_last_S <= '0';
+ timeoutcounter_V := 0;
+ crc8_clear_S <= '1'; -- clear crc
+ error_S <= '0';
+ crc8_lastwrite_S <= '0';
+ tx_state_S <= idle;
+ when idle =>
+ timeoutcounter_V := 0;
+ crc8_clear_S <= '0';
+ if crc8_lastwrite_S='1' then
+ crc8_lastwrite_S <= '0';
+ crc8_data_in_S <= crc8_lastword_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '1';
+ else
+ crc8_data_in_last_S <= '0';
+ end if;
+
+ if pulse_read_S='1' then
+ if pulse_data(35 downto 34)="00" then
+ error_S <= '0';
+-- channel_S(0) <= pulse_data(33);
+ if pulse_data(32)='1' then
+ statusbyte_S <= STATBYTE_FEEPULSESKIPPED;
+ else
+ statusbyte_S <= x"00";
+ end if;
+ superburst_S <= pulse_data(31 downto 16);
+ timestamp_S <= pulse_data(15 downto 0);
+ tx_state_S <= data0;
+ else
+ error_S <= '1';
+ end if;
+ elsif slowcontrol_read_S='1' then
+ error_S <= '0';
+ tx_state_S <= slow0;
+ elsif wave_read_S='1' then
+ if wave_data(35 downto 32)="0000" then
+ superburst_S <= wave_data(31 downto 16);
+ timestamp_S <= wave_data(15 downto 0);
+ error_S <= '0';
+ tx_state_S <= wave0;
+ else
+ error_S <= '1';
+ end if;
+ else
+ end if;
+ when data0 =>
+ if pulse_read_S='1' then
+ timeoutcounter_V := 0;
+ if pulse_data(35 downto 34)="01" then
+-- channel_S(7 downto 0) <= pulse_data(23 downto 16);
+ energy_S <= pulse_data(15 downto 0);
+ crc8_data_in_S <= x"DA" & pulse_data(23 downto 16) & superburst_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when data1 =>
+ if pulse_read_S='1' then
+ timeoutcounter_V := 0;
+ if pulse_data(35 downto 34)="10" then
+ CF_before_S <= pulse_data(31 downto 16);
+ CF_after_S <= pulse_data(15 downto 0);
+ crc8_data_in_S <= x"0000" & energy_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= data2;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when data2 =>
+ crc8_data_in_S <= CF_before_S & CF_after_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= timestamp_S & statusbyte_S & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+
+ when wave0 =>
+ if wave_read_S='1' then
+ timeoutcounter_V := 0;
+ if wave_data(35 downto 32)="0001" then
+ statusbyte_S <= wave_data(31 downto 24);
+-- channel_S <= wave_data(7 downto 0);
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave1;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+ when wave1 =>
+ crc8_data_in_S <= timestamp_S & x"00" & statusbyte_S;
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave2;
+ when wave2 =>
+ if wave_read_S='1' then
+ timeoutcounter_V := 0;
+ if wave_data(35 downto 32)="0010" then -- 2 samples
+ crc8_data_in_S <= '0' & wave_data(30 downto 16) & '0' & wave_data(14 downto 0);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ tx_state_S <= wave2;
+ elsif wave_data(35 downto 32)="0100" then -- last sample
+ crc8_data_in_S <= '1' & wave_data(30 downto 16) & "1000" & x"000";
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '1';
+ crc8_lastwrite_S <= '0';
+ tx_state_S <= idle;
+ elsif wave_data(35 downto 32)="0101" then -- last 2 samples, one lastword with crc needed
+ crc8_data_in_S <= '0' & wave_data(30 downto 16) & '0' & wave_data(14 downto 0);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= x"0000" & x"80" & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ else
+ if timeoutcounter_V/=15 then
+ timeoutcounter_V := timeoutcounter_V+1;
+ else
+ error_S <= '1';
+ tx_state_S <= init;
+ end if;
+ end if;
+
+ when slow0 =>
+ crc8_data_in_S <= x"5c" & slowcontrol_address & slowcontrol_reply & "0000000" & slowcontrol_data(31 downto 24);
+ crc8_writeword_S <= '1';
+ crc8_data_in_last_S <= '0';
+ crc8_lastword_S <= slowcontrol_data(23 downto 0) & x"00";
+ crc8_lastwrite_S <= '1';
+ tx_state_S <= idle;
+
+ when others =>
+ error_S <= '1';
+ tx_state_S <= init;
+ end case;
+ end if;
+ end if;
+ end if;
+end process datahandling;
+
+\r
+\r
+\r
+testword0(3 downto 0) <= pulse_data(35 downto 32);
+testword0(4) <= pulse_notpresent;
+testword0(5) <= pulse_inpipe;
+testword0(6) <= pulse_read_S;
+testword0(7) <= pulse_read0_S;
+\r
+testword0(11 downto 8) <= wave_data(35 downto 32);
+testword0(12) <= wave_notpresent;
+testword0(13) <= wave_inpipe;
+testword0(14) <= wave_read_S;
+testword0(15) <= wave_read0_S;
+\r
+testword0(19 downto 16) <= \r
+ x"0" when tx_state_S=init else\r
+ x"1" when tx_state_S=idle else\r
+ x"2" when tx_state_S=data0 else\r
+ x"3" when tx_state_S=data1 else\r
+ x"4" when tx_state_S=data2 else\r
+ x"5" when tx_state_S=wave0 else\r
+ x"6" when tx_state_S=wave1 else\r
+ x"7" when tx_state_S=wave2 else\r
+ x"8" when tx_state_S=slow0 else\r
+ x"f";\r
+
+testword0(20) <= waveisolder_S;\r
+testword0(21) <= crc8_reset_S;\r
+testword0(22) <= crc8_clear_S;\r
+testword0(23) <= crc8_data_in_valid_S;\r
+testword0(24) <= crc8_data_in_last_S;\r
+testword0(25) <= crc8_writeword_S;\r
+testword0(26) <= crc8_data_out_valid_S;\r
+testword0(27) <= crc8_data_out_last_S;\r
+testword0(28) <= '0';\r
+testword0(29) <= crc8_lastwrite_S;\r
+testword0(30) <= slowcontrol_notpresent;\r
+testword0(31) <= slowcontrol_read_S;\r
+testword0(32) <= packet_datawrite_S;\r
+testword0(33) <= packet_lastword_S;\r
+testword0(34) <= packet_firstword_S;\r
+\r
+ \r
+testword0(35) <= error_S;\r
+\r
+\r
+end Behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 30-01-2012
+-- Module Name: FEE_dual_pulse_waveform
+-- Description: Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs
+-- Modifications:
+-- 08-09-2014 Added: Constant Fraction values before and after zero-crossing
+-- 16-09-2014 name changed from dual_pulse_waveform to FEE_dual_pulse_waveform
+-- 22-09-2014 single clock
+-- 24-09-2014 enable_highgain and enable_lowgain inputs added
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_dual_pulse_waveform
+-- Module to detect pulses and outputs them as waveforms with single pulse or pile-up
+-- Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.
+-- If a pulse or pileup is detected at the low-gain input, the high-gain input is ignored.
+-- Pulses are detected: check if the ADC signal is above the adjustable tresshold.
+-- The samples are stored in buffer memory as waveform.
+-- The actual superburst-number and a timestamp within the superburst is added.
+-- Waveforms longer than an adjustable duration are treated as pileup waveforms,
+-- waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:
+-- The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
+-- The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
+-- From the single pulse waveforms the Constant Fraction values before and after the zero-crossing are put in the
+-- resulting packet, as well as two successive samples containing the maximum of the pulse.
+--
+--
+-- generics
+-- ADCBITS : number of ADC-bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+--
+-- inputs
+-- clock : clock
+-- reset : synchrounous reset
+-- enable : enable pulse detection
+-- superburstnumber : actual superburstnumber
+-- timestampcounter : timestampcounter within superburst
+-- ADCdata_highgain : ADC signal from the high-gain input
+-- ADCdata_lowgain : ADC signal from the low-gain input
+-- threshold_highgain : threshold above baseline for start of pulse (high gain)
+-- threshold_lowgain : threshold above baseline for start of pulse (low gain)
+-- enable_highgain : enable high gain input
+-- enable_lowgain : enable low gain input
+-- IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+-- minpulselength : number of samples below which the pulse is ignored
+-- pileuplength : number of samples above which the pulse is treated as pileup
+-- maxwavelength : maximum number of samples that can be saved in one waveform
+-- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
+-- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
+-- fullsize_wave_highgain : take waveforms with maximum size for highgain input
+-- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
+-- pulsedata_allowed : writing of pulse 36-bits data result allowed
+-- pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+-- pileupdata_allowed : writing of pileup 36-bits data result allowed
+-- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--
+-- outputs
+-- ADC_minus_baseline_highgain : baseline compensated signal from high gain input, signed
+-- ADC_minus_baseline_lowgain : baseline compensated signal from low gain input, signed
+-- pulsedata_write : write 36-bits pulse data result
+-- pulsedata_out : 36-bits pulse data result:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- pileupdata_write : write 36-bits pileup data result
+-- pileupdata_out : 36-bits pileup data result:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identification)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input
+-- overflow : pulse or pileup waveform is lost
+--
+-- Components:
+-- FEE_baselinefollower_eventdetector : baseline follower with detection of pulse
+-- FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred
+-- FEE_extract_pulse : perform maximum check and constant fraction
+-- FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added
+-- FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream
+-- FEE_wavemux2to1 : select next waveform, based on timestamp
+-- FEE_pulse2to1_pulse : combine hits from high and low gain ADC inputs to one data packet stream
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_dual_pulse_waveform is
+ generic (
+ ADCBITS : natural := 14;
+ BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ enable_highgain : in std_logic;
+ enable_lowgain : in std_logic;
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
+ ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
+ pulsedata_allowed : in std_logic;
+ pulsedata_almostfull : in std_logic;
+ pulsedata_write : out std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ pileupdata_write : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pulsedetect : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);
+ testword2 : out std_logic_vector(35 downto 0)
+ );
+end FEE_dual_pulse_waveform;
+
+architecture Behavioral of FEE_dual_pulse_waveform is
+
+component FEE_baselinefollower_eventdetector is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ enable : in std_logic;
+ ADCdata : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold : in std_logic_vector((ADCBITS-1) downto 0);
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ baseline : out std_logic_vector((ADCBITS-1) downto 0);
+ ADC_delayed : out std_logic_vector(ADCBITS-1 downto 0);
+ ADC_minus_baseline : out std_logic_vector(ADCBITS downto 0);
+ baseline_inhibit : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end component;
+
+component FEE_pileup_check is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestampcounter : in std_logic_vector(15 downto 0);
+ ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_highgain : in std_logic;
+ max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_highgain : in std_logic;
+ pulse_rising_highgain : in std_logic;
+ clipping_highgain : in std_logic;
+ ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed
+ enable_lowgain : in std_logic;
+ max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_lowgain : in std_logic;
+ pulse_rising_lowgain : in std_logic;
+ minpulselength : in std_logic_vector(7 downto 0);
+ pileuplength : in std_logic_vector(7 downto 0);
+ maxwavelength : in std_logic_vector(7 downto 0);
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+ fullsize_wave_highgain : in std_logic;
+ fullsize_wave_lowgain : in std_logic;
+ pulse_valid_highgain : out std_logic;
+ singlepulse_highgain : out std_logic;
+ pileuppulse_highgain : out std_logic;
+ clearpulse_highgain : out std_logic;
+ integral_highgain : out std_logic_vector(15 downto 0);\r
+ pulse_valid_lowgain : out std_logic;\r
+ singlepulse_lowgain : out std_logic;\r
+ pileuppulse_lowgain : out std_logic;\r
+ clearpulse_lowgain : out std_logic;\r
+ integral_lowgain : out std_logic_vector(15 downto 0);\r
+ superburst : out std_logic_vector(15 downto 0);\r
+ timestamp : out std_logic_vector(15 downto 0);\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+\r
+component FEE_extract_pulse is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ integral : in std_logic_vector(15 downto 0);\r
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);\r
+ pulse_write : out std_logic;\r
+ pulse_superburst : out std_logic_vector(15 downto 0);\r
+ pulse_timestamp : out std_logic_vector(15 downto 0);\r
+ pulse_skipped : out std_logic;\r
+ pulse_energy : out std_logic_vector(15 downto 0);\r
+ pulse_CF1 : out std_logic_vector(15 downto 0);\r
+ pulse_CF2 : out std_logic_vector(15 downto 0)\r
+ );\r
+end component;
+\r
+
+component FEE_pulsewaveform_buffer is
+ generic (
+ ADCBITS : natural := ADCBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ superburst : in std_logic_vector(15 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_waveform_to_36bits is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ overflow_in : in std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_write : out std_logic;
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ error : out std_logic;
+ overflow_out : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+
+component FEE_wavemux2to1 is
+ generic(
+ TIMEOUTBITS : natural := 16
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+\r
+component FEE_pulse2to1_pulse is\r
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ channel : in std_logic_vector(7 downto 0);
+ pulse1_write : in std_logic;\r
+ pulse1_superburst : in std_logic_vector(15 downto 0);\r
+ pulse1_timestamp : in std_logic_vector(15 downto 0);\r
+ pulse1_skipped : in std_logic;\r
+ pulse1_energy : in std_logic_vector(15 downto 0);\r
+ pulse1_CF1 : in std_logic_vector(15 downto 0);\r
+ pulse1_CF2 : in std_logic_vector(15 downto 0);\r
+ pulse2_write : in std_logic;\r
+ pulse2_superburst : in std_logic_vector(15 downto 0);\r
+ pulse2_timestamp : in std_logic_vector(15 downto 0);\r
+ pulse2_skipped : in std_logic;\r
+ pulse2_energy : in std_logic_vector(15 downto 0);\r
+ pulse2_CF1 : in std_logic_vector(15 downto 0);\r
+ pulse2_CF2 : in std_logic_vector(15 downto 0);\r
+ pulse_skipped : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_almostfull : in std_logic;
+ data_out_allowed : in std_logic
+ );
+end component;
+\r
+
+
+signal pulsedetect_S : std_logic := '0';
+
+signal pulse_active_highgain_S : std_logic := '0';
+signal pulse_rising_highgain0_S : std_logic := '0';
+signal pulse_rising_highgain_S : std_logic := '0';
+signal pulse_active_lowgain_S : std_logic := '0';
+signal pulse_rising_lowgain0_S : std_logic := '0';
+signal pulse_rising_lowgain_S : std_logic := '0';
+signal ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);
+
+signal pulse_valid_highgain0_S : std_logic := '0';
+signal pulse_valid_highgain_S : std_logic := '0';
+signal singlepulse_highgain_S : std_logic := '0';
+signal pileuppulse_highgain_S : std_logic := '0';
+signal clearpulse_highgain_S : std_logic := '0';
+signal integral_highgain_S : std_logic_vector(15 downto 0);
+signal max_data_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal clipping_highgain_S : std_logic := '0';
+
+signal baseline_highgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal baseline_inhibit_highgain_S : std_logic := '0';
+signal baseline_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal baseline_inhibit_lowgain_S : std_logic := '0';
+
+signal pulse_valid_lowgain0_S : std_logic := '0';
+signal pulse_valid_lowgain_S : std_logic := '0';
+signal singlepulse_lowgain_S : std_logic := '0';
+signal pileuppulse_lowgain_S : std_logic := '0';
+signal clearpulse_lowgain_S : std_logic := '0';\r
+signal integral_lowgain_S : std_logic_vector(15 downto 0);
+signal max_data_lowgain_S : std_logic_vector(ADCBITS-1 downto 0);
+signal superburst_S : std_logic_vector(15 downto 0);
+signal timestamp_S : std_logic_vector(15 downto 0);
+
+signal adcnumber_highgain_S : std_logic_vector(7 downto 0);
+signal data_out_highgain_S : std_logic_vector(35 downto 0);
+signal data_out_available_highgain_S : std_logic := '0';
+signal data_out_read_highgain_S : std_logic := '0';
+signal overflow_highgain_S : std_logic := '0';
+signal overflow_hg_S : std_logic := '0';
+signal pileupdata1_out_S : std_logic_vector(35 downto 0);
+signal pileupdata1_write_S : std_logic := '0';
+signal pileupdata1_allowed_S : std_logic := '0';
+\r
+signal pulse_write_highgain_S : std_logic;
+signal pulse_superburst_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_timestamp_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_skipped_highgain_S : std_logic;
+signal pulse_energy_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF1_highgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF2_highgain_S : std_logic_vector(15 downto 0);
+\r
+signal pulse_write_lowgain_S : std_logic;
+signal pulse_superburst_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_timestamp_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_skipped_lowgain_S : std_logic;
+signal pulse_energy_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF1_lowgain_S : std_logic_vector(15 downto 0);
+signal pulse_CF2_lowgain_S : std_logic_vector(15 downto 0);
+\r
+ \r
+
+signal adcnumber_lowgain_S : std_logic_vector(7 downto 0);
+signal data_out_lowgain_S : std_logic_vector(35 downto 0);
+signal data_out_available_lowgain_S : std_logic := '0';
+signal data_out_read_lowgain_S : std_logic := '0';
+signal overflow_lowgain_S : std_logic := '0';
+signal overflow_lg_S : std_logic := '0';
+signal pileupdata2_out_S : std_logic_vector(35 downto 0);
+signal pileupdata2_write_S : std_logic := '0';
+signal pileupdata2_allowed_S : std_logic := '0';
+
+signal pulsedata_out_S : std_logic_vector(35 downto 0);
+signal pulsedata_write_S : std_logic := '0';
+signal pileupdata_out_S : std_logic_vector(35 downto 0);
+signal pileupdata_write_S : std_logic := '0';
+
+signal error_pulse_S : std_logic := '0';
+signal error_pileup_S : std_logic := '0';
+signal error_to36_1_S : std_logic := '0';
+signal error_to36_2_S : std_logic := '0';
+
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword2_S : std_logic_vector(35 downto 0) := (others => '0');
+
+begin
+
+pulsedetect <= pulsedetect_S;
+pulsedetect_S <= '1' when (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1')
+ or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else '0';
+
+FEE_baselinefollower_eventdetector_highgain: FEE_baselinefollower_eventdetector port map(
+ clock => clock,
+ reset => reset,
+ enable => enable,
+ ADCdata => ADCdata_highgain,
+ threshold => threshold_highgain,
+ IIRfilterBW => IIRfilterBW,
+ maxabovebaseline => maxabovebaseline,
+ baseline => baseline_highgain_S,
+ ADC_delayed => open,
+ ADC_minus_baseline => ADC_minus_baseline_highgain0_S,
+ baseline_inhibit => baseline_inhibit_highgain_S,
+ pulse_active => pulse_active_highgain_S,
+ pulse_rising => pulse_rising_highgain0_S,
+ max_data => max_data_highgain_S);
+ADC_minus_baseline_highgain <= ADC_minus_baseline_highgain_S;
+
+FEE_baselinefollower_eventdetector_lowgain: FEE_baselinefollower_eventdetector port map(
+ clock => clock,
+ reset => reset,
+ enable => enable,
+ ADCdata => ADCdata_lowgain,
+ threshold => threshold_lowgain,
+ IIRfilterBW => IIRfilterBW,
+ maxabovebaseline => maxabovebaseline,
+ baseline => baseline_lowgain_S,
+ ADC_delayed => open,
+ ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,
+ baseline_inhibit => baseline_inhibit_lowgain_S,
+ pulse_active => pulse_active_lowgain_S,
+ pulse_rising => pulse_rising_lowgain0_S,
+ max_data => max_data_lowgain_S);
+ADC_minus_baseline_lowgain <= ADC_minus_baseline_lowgain_S;
+
+FEE_pileup_check1: FEE_pileup_check port map(
+ clock => clock,
+ reset => reset,
+ superburstnumber => superburstnumber,
+ timestampcounter => timestampcounter,
+ ADC_highgain => ADC_minus_baseline_highgain0_S,
+ enable_highgain => enable_highgain,
+ max_data_highgain => max_data_highgain_S,
+ pulse_active_highgain => pulse_active_highgain_S,
+ pulse_rising_highgain => pulse_rising_highgain0_S,
+ clipping_highgain => clipping_highgain_S,
+ ADC_lowgain => ADC_minus_baseline_lowgain0_S,
+ enable_lowgain => enable_lowgain,
+ max_data_lowgain => max_data_lowgain_S,
+ pulse_active_lowgain => pulse_active_lowgain_S,
+ pulse_rising_lowgain => pulse_rising_lowgain0_S,
+ minpulselength => minpulselength,
+ pileuplength => pileuplength,
+ maxwavelength => maxwavelength,
+ IdivMAX_discard => IdivMAX_discard,
+ IdivMAX_pileup => IdivMAX_pileup,
+ fullsize_wave_highgain => fullsize_wave_highgain,
+ fullsize_wave_lowgain => fullsize_wave_lowgain,
+ pulse_valid_highgain => pulse_valid_highgain0_S,
+ singlepulse_highgain => singlepulse_highgain_S,
+ pileuppulse_highgain => pileuppulse_highgain_S,
+ clearpulse_highgain => clearpulse_highgain_S,
+ integral_highgain => integral_highgain_S,\r
+ pulse_valid_lowgain => pulse_valid_lowgain0_S,
+ singlepulse_lowgain => singlepulse_lowgain_S,
+ pileuppulse_lowgain => pileuppulse_lowgain_S,
+ clearpulse_lowgain => clearpulse_lowgain_S,
+ integral_lowgain => integral_lowgain_S,\r
+ superburst => superburst_S,\r
+ timestamp => timestamp_S,
+ testword0 => open);
+\r
+
+process(clock)
+begin
+ if (rising_edge(clock)) then \r
+ if enable_highgain='1' then
+ pulse_valid_highgain_S <= pulse_valid_highgain0_S;
+ pulse_rising_highgain_S <= pulse_rising_highgain0_S;\r
+ else\r
+ pulse_valid_highgain_S <= '0';
+ pulse_rising_highgain_S <= '0';\r
+ end if;
+ ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;\r
+ if enable_lowgain='1' then
+ pulse_valid_lowgain_S <= pulse_valid_lowgain0_S;
+ pulse_rising_lowgain_S <= pulse_rising_lowgain0_S;\r
+ else\r
+ pulse_valid_lowgain_S <= '0';
+ pulse_rising_lowgain_S <= '0';\r
+ end if;
+ ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;
+ if pulse_active_highgain_S='1' then
+ if ADCdata_highgain((ADCBITS-1) downto (ADCBITS-4)) = "1111" then
+ clipping_highgain_S <= '1';
+ end if;
+ else
+ clipping_highgain_S <= '0';
+ end if;
+ end if;
+end process;\r
+\r
+FEE_extract_pulse1: FEE_extract_pulse port map(
+ clock => clock,
+ reset => reset,
+ cf_delay => cf_delay,
+ pulse_valid => pulse_valid_highgain_S,
+ pulse_rising => pulse_rising_highgain_S,
+ pulse_detected => singlepulse_highgain_S,
+ pileup_detected => pileuppulse_highgain_S,
+ clear_waveform => clearpulse_highgain_S,
+ data_in => ADC_minus_baseline_highgain_S,\r
+ integral => integral_highgain_S,\r
+ superburstnumber => superburstnumber,
+ timestamp => timestampcounter,\r
+ pulse_write => pulse_write_highgain_S,
+ pulse_superburst => pulse_superburst_highgain_S,
+ pulse_timestamp => pulse_timestamp_highgain_S,\r
+ pulse_skipped => pulse_skipped_highgain_S,
+ pulse_energy => pulse_energy_highgain_S,
+ pulse_CF1 => pulse_CF1_highgain_S,
+ pulse_CF2 => pulse_CF2_highgain_S);\r
+\r
+FEE_extract_pulse2: FEE_extract_pulse port map(
+ clock => clock,
+ reset => reset,
+ cf_delay => cf_delay,
+ pulse_valid => pulse_valid_lowgain_S,
+ pulse_rising => pulse_rising_lowgain_S,
+ pulse_detected => singlepulse_lowgain_S,
+ pileup_detected => pileuppulse_lowgain_S,
+ clear_waveform => clearpulse_lowgain_S,
+ data_in => ADC_minus_baseline_lowgain_S,\r
+ integral => integral_lowgain_S,\r
+ superburstnumber => superburstnumber,
+ timestamp => timestampcounter,\r
+ pulse_write => pulse_write_lowgain_S,
+ pulse_superburst => pulse_superburst_lowgain_S,
+ pulse_timestamp => pulse_timestamp_lowgain_S,
+ pulse_skipped => pulse_skipped_lowgain_S,
+ pulse_energy => pulse_energy_lowgain_S,
+ pulse_CF1 => pulse_CF1_lowgain_S,
+ pulse_CF2 => pulse_CF2_lowgain_S); \r
+\r
+FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(
+ clock => clock,
+ reset => reset,
+ pulse_valid => pulse_valid_highgain_S,
+ pulse_rising => pulse_rising_highgain_S,
+ pulse_detected => singlepulse_highgain_S,
+ pileup_detected => pileuppulse_highgain_S,
+ clear_waveform => clearpulse_highgain_S,
+ data_in => ADC_minus_baseline_highgain_S,
+ superburst => superburst_S,
+ timestamp => timestamp_S,
+ data_out => data_out_highgain_S,
+ data_out_read => data_out_read_highgain_S,
+ data_out_available => data_out_available_highgain_S,
+ overflow => overflow_highgain_S,
+ testword0 => testword1);
+
+FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(
+ clock => clock,
+ reset => reset,
+ pulse_valid => pulse_valid_lowgain_S,
+ pulse_rising => pulse_rising_lowgain_S,
+ pulse_detected => singlepulse_lowgain_S,
+ pileup_detected => pileuppulse_lowgain_S,
+ clear_waveform => clearpulse_lowgain_S,
+ data_in => ADC_minus_baseline_lowgain_S,
+ superburst => superburst_S,
+ timestamp => timestamp_S,
+ data_out => data_out_lowgain_S,
+ data_out_read => data_out_read_lowgain_S,
+ data_out_available => data_out_available_lowgain_S,
+ overflow => overflow_lowgain_S,
+ testword0 => open); \r
+
+FEE_pulse2to1_pulse1: FEE_pulse2to1_pulse port map(
+ clock => clock,
+ reset => reset,
+ channel => adcnumber,
+ pulse1_write => pulse_write_highgain_S,
+ pulse1_superburst => pulse_superburst_highgain_S,
+ pulse1_timestamp => pulse_timestamp_highgain_S,\r
+ pulse1_skipped => pulse_skipped_highgain_S,
+ pulse1_energy => pulse_energy_highgain_S,
+ pulse1_CF1 => pulse_CF1_highgain_S,
+ pulse1_CF2 => pulse_CF2_highgain_S,\r
+ pulse2_write => pulse_write_lowgain_S,
+ pulse2_superburst => pulse_superburst_lowgain_S,
+ pulse2_timestamp => pulse_timestamp_lowgain_S,
+ pulse2_skipped => pulse_skipped_lowgain_S,
+ pulse2_energy => pulse_energy_lowgain_S,
+ pulse2_CF1 => pulse_CF1_lowgain_S,
+ pulse2_CF2 => pulse_CF2_lowgain_S, \r
+ pulse_skipped => open, \r
+ data_out => pulsedata_out_S,
+ data_out_write => pulsedata_write_S,
+ data_out_almostfull => pulsedata_almostfull,
+ data_out_allowed => pulsedata_allowed);
+pulsedata_out <= pulsedata_out_S;
+pulsedata_write <= pulsedata_write_S;\r
+\r
+\r
+
+adcnumber_highgain_S <= adcnumber AND x"fe";
+FEE_waveform_to_36bits1: FEE_waveform_to_36bits port map(
+ clock => clock,
+ reset => reset,
+ adcnumber => adcnumber_highgain_S,
+ data_in => data_out_highgain_S,
+ data_in_available => data_out_available_highgain_S,
+ data_in_read => data_out_read_highgain_S,
+ overflow_in => overflow_highgain_S,
+ pileupdata_out => pileupdata1_out_S,
+ pileupdata_write => pileupdata1_write_S,
+ pileupdata_allowed => pileupdata1_allowed_S,
+ pileupdata_almostfull => pileupdata_almostfull,
+ overflow_out => overflow_hg_S,
+ error => error_to36_1_S,
+ testword0 => open);
+
+adcnumber_lowgain_S <= adcnumber OR x"01";
+FEE_waveform_to_36bits2: FEE_waveform_to_36bits port map(
+ clock => clock,
+ reset => reset,
+ adcnumber => adcnumber_lowgain_S,
+ data_in => data_out_lowgain_S,
+ data_in_available => data_out_available_lowgain_S,
+ data_in_read => data_out_read_lowgain_S,
+ overflow_in => overflow_lowgain_S,
+ pileupdata_out => pileupdata2_out_S,
+ pileupdata_write => pileupdata2_write_S,
+ pileupdata_allowed => pileupdata2_allowed_S,
+ pileupdata_almostfull => pileupdata_almostfull,
+ overflow_out => overflow_lg_S,
+ error => error_to36_2_S,
+ testword0 => open);
+overflow <= '1' when (overflow_highgain_S='1') or (overflow_lowgain_S='1') or (overflow_hg_S='1') or (overflow_lg_S='1') else '0';
+
+FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(
+ clock => clock,
+ reset => reset,
+ data1_in => pileupdata1_out_S,
+ data1_in_write => pileupdata1_write_S,
+ data1_in_available => data_out_available_highgain_S, -- '0',
+ data1_in_allowed => pileupdata1_allowed_S,
+ data2_in => pileupdata2_out_S,
+ data2_in_write => pileupdata2_write_S,
+ data2_in_available => data_out_available_lowgain_S, -- '0',
+ data2_in_allowed => pileupdata2_allowed_S,
+ data_out => pileupdata_out_S,
+ data_out_write => pileupdata_write_S,
+ data_out_available => open,
+ data_out_allowed => pileupdata_allowed,
+ error => error_pileup_S,
+ testword0 => testword2);
+pileupdata_out <= pileupdata_out_S;
+pileupdata_write <= pileupdata_write_S;
+\r
+-----------------------------------------------------------------\r
+-- tests:\r
+
+process(clock)\r
+variable prev_data_V : std_logic_vector(3 downto 0);
+begin
+ if rising_edge(clock) then\r
+ testword0_S(35) <= '0';\r
+ if pileupdata_write_S='1' then\r
+ case pileupdata_out_S(35 downto 32) is\r
+ when "0000" =>\r
+ if (prev_data_V/="0100") and (prev_data_V/="0101") then\r
+ testword0_S(35) <= '1';\r
+ end if;\r
+ when "0001" =>\r
+ if (prev_data_V/="0000") then\r
+ testword0_S(35) <= '1';\r
+ end if;\r
+ when "0010" =>\r
+ if (prev_data_V/="0001") and (prev_data_V/="0010") then\r
+ testword0_S(35) <= '1';\r
+ end if;\r
+ when "0100" =>\r
+ if (prev_data_V/="0010") then\r
+ testword0_S(35) <= '1';\r
+ end if;\r
+ when "0101" =>\r
+ if (prev_data_V/="0010") then\r
+ testword0_S(35) <= '1';\r
+ end if;\r
+ when others =>\r
+ testword0_S(35) <= '1';\r
+ end case;\r
+ prev_data_V := pileupdata_out_S(35 downto 32);\r
+ end if;
+ end if;
+end process;\r
+\r
+\r
+testword0 <= testword0_S;\r
+\r
+\r
+\r
+testword0_S(3 downto 0) <= data_out_highgain_S(35 downto 32);
+testword0_S(4) <= data_out_read_highgain_S;
+testword0_S(5) <= data_out_available_highgain_S;
+--testword0_S(6) <= overflow_highgain_S;
+testword0_S(9 downto 6) <= data_out_lowgain_S(35 downto 32);
+testword0_S(10) <= data_out_read_lowgain_S;
+testword0_S(11) <= data_out_available_lowgain_S;
+--testword0_S(13) <= overflow_lowgain_S;
+\r
+testword0_S(15 downto 12) <= pileupdata1_out_S(35 downto 32);
+testword0_S(16) <= pileupdata1_write_S;
+testword0_S(17) <= pileupdata1_allowed_S;
+testword0_S(18) <= pileupdata_almostfull;
+--testword0_S(21) <= overflow_hg_S;
+testword0_S(19) <= error_to36_1_S;
+
+testword0_S(23 downto 20) <= pileupdata2_out_S(35 downto 32);
+testword0_S(24) <= pileupdata2_write_S;
+testword0_S(25) <= pileupdata2_allowed_S;
+testword0_S(26) <= pileupdata_almostfull;
+--testword0_S(30) <= overflow_lg_S;
+testword0_S(27) <= error_to36_2_S;
+testword0_S(28) <= error_pileup_S;
+\r
+testword0_S(32 downto 29) <= pileupdata_out_S(35 downto 32);\r
+testword0_S(33) <= pileupdata_write_S;\r
+testword0_S(34) <= pileupdata_allowed;\r
+\r
+\r
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 27-01-2012
+-- Module Name: FEE_eventdetector
+-- Description: Detect pulses by comparing ADC-signal with threshold
+-- Modifications: \r
+-- 16-09-2014: name changed from eventdetector to FEE_eventdetector
+-- 10-10-2014: threshold for end of pulse is half the normal threshold
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+\r
+------------------------------------------------------------------------------------------------------
+-- FEE_eventdetector
+-- Detect pulses by comparing ADC-signal with threshold
+-- Generates inhibit for baseline IIR filter
+--
+--
+-- generics
+-- ADCBITS : number of ADC bits
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : signed ADC sampling data : minus baseline
+-- threshold : threshold above baseline
+-- maxabovebaseline : 2^ maximum number of samples a pulse can last to prevent deadlock threshold/baseline
+--
+-- outputs
+-- baseline_freeze : detected signal pulse is busy : inhibit baseline IIR filter
+-- pulse_active : the ADC-signal exceeds the trigger-level
+-- pulse_rising : the pulse has not yet reached its maximum
+-- max_data : maximum value of waveform
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+entity FEE_eventdetector is
+ generic (
+ ADCBITS : natural := 14
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector (ADCBITS downto 0);
+ threshold : in std_logic_vector ((ADCBITS-1) downto 0);
+ maxabovebaseline : in std_logic_vector (3 downto 0);
+ baseline_freeze : out std_logic;
+ pulse_active : out std_logic;
+ pulse_rising : out std_logic;
+ max_data : out std_logic_vector(ADCBITS-1 downto 0)
+ );
+end FEE_eventdetector;
+
+architecture Behavioral of FEE_eventdetector is
+
+signal abovetriggerlevel_S : std_logic;
+signal freeze_extend_S : std_logic;
+signal pulsetoolong_S : std_logic;
+signal data_below_max_S : std_logic;
+signal counter_S : std_logic_vector(2**4-1 downto 0);
+signal max_data_S : std_logic_vector(ADCBITS downto 0);
+signal half_threshold_S : std_logic;
+
+begin
+
+max_data <= max_data_S(ADCBITS-1 downto 0); -- unsigned, should be always positive
+pulse_active <= abovetriggerlevel_S;
+
+baseline_freeze <= '1' when ((abovetriggerlevel_S='1') or (freeze_extend_S='1')) and (pulsetoolong_S='0') else '0';
+abovetriggerlevel_S <= '1'
+ when ((conv_integer(signed(data_in))>conv_integer(signed('0' & threshold))) and (half_threshold_S='0')) or
+ ((conv_integer(signed(data_in))>conv_integer(signed("00" & threshold(ADCBITS-1 downto 1)))) and (half_threshold_S='1'))
+ else '0';\r
+
+process(clock)\r
+variable counter_V : std_logic_vector(3 downto 0);\r
+--variable below_zero_V : std_logic;
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ freeze_extend_S <= '0';\r
+ else\r
+ if abovetriggerlevel_S='1' then\r
+ freeze_extend_S <= '1';\r
+ counter_V := (others => '0');\r
+ -- below_zero_V := '0';\r
+ elsif counter_V(counter_V'left)='0' then\r
+ -- if (conv_integer(signed(data_in))>0) and (below_zero_V='0') then\r
+ -- counter_V := (others => '0');\r
+ -- else\r
+ -- below_zero_V := '1';\r
+ counter_V := counter_V+1;\r
+ -- end if;\r
+ freeze_extend_S <= '1';\r
+ else\r
+ freeze_extend_S <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+
+pulsetoolong_S <= counter_S(conv_integer(unsigned(maxabovebaseline)));
+data_below_max_S <= '1' when conv_integer(signed(data_in))<=conv_integer(signed(max_data_S)) else '0';
+pulse_rising <= '1'
+ when (data_below_max_S='0')
+ and (abovetriggerlevel_S='1')
+ and (pulsetoolong_S='0')
+ else '0';
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ counter_S <= (others => '0');
+ max_data_S <= data_in;
+ half_threshold_S <= '0';
+ else
+ if abovetriggerlevel_S='0' then
+ counter_S <= (others => '0');
+ max_data_S <= data_in;\r
+ half_threshold_S <= '0';
+ elsif pulsetoolong_S='0' then\r
+ if (half_threshold_S='0') and (counter_S(2)='1') then\r
+ half_threshold_S <= '1';\r
+ end if;
+ counter_S <= counter_S+1;
+ if data_below_max_S='0' then
+ max_data_S <= data_in;
+ end if;
+ else
+ end if;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 02-09-2014
+-- Module Name: FEE_extract_pulse
+-- Description: Extract pulse components from ADC data: time, maximum(2*), Constant Fraction signals
+-- Modifications:
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 27-10-2014 Constant Fraction with negative or equal instead of negative
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_extract_pulse
+-- Extract pulse components from ADC data: time, maximum(2*), Constant Fraction signals
+--
+-- The integral of the pulse is passed on as the energy of the pulse.
+---
+-- The Constant Fraction signal for precise time measurement is done with the formula:
+-- CF_signal = -ADCvalue + 4*ADCvalue'delayed
+-- This results in a signal that has a zero-crossing near the rising edge of the pulse.
+-- The CF_signal before and after the zero-crossing are passed on to calculate the precise timestamp.
+--
+--
+-- generics
+-- ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- cf_delay : delay (number of ADC samples) for the constant fraction
+-- pulse_valid : input data is valid pulse data
+-- pulse_rising : the pulse has not yet reached its maximum
+-- pulse_detected : previous samples are regarded as valid pulse data
+-- pileup_detected : previous samples are regarded as pileup waveform data
+-- clear_waveform : previous samples do not give valid data, clear this data
+-- data_in : input data: adc values minus baseline: signed data
+-- integral : scaled integral of the waveform\r
+-- superburstnumber : actual superburstnumber from SODA
+-- timestamp : actual 16-bits time inside the superburst
+--
+-- outputs
+-- pulse_write : write signal for the output signals
+-- pulse_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse_energy : energy of the pulse, calculated from integeral
+-- pulse_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse_CF2 : CF_signal value of the value after the zero-crossing
+--
+--
+-- components
+-- shift_register : shift register for the constant fraction delay
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_extract_pulse is
+ generic (
+ ADCBITS : natural := 14;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ integral : in std_logic_vector(15 downto 0);\r
+ superburstnumber : in std_logic_vector(30 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);\r
+ pulse_write : out std_logic;\r
+ pulse_superburst : out std_logic_vector(15 downto 0);\r
+ pulse_timestamp : out std_logic_vector(15 downto 0);\r
+ pulse_skipped : out std_logic;\r
+ pulse_energy : out std_logic_vector(15 downto 0);\r
+ pulse_CF1 : out std_logic_vector(15 downto 0);\r
+ pulse_CF2 : out std_logic_vector(15 downto 0)\r
+ );
+end FEE_extract_pulse;
+
+architecture Behavioral of FEE_extract_pulse is\r
+
+component shift_register is
+ generic (
+ width : natural := ADCBITS+1; -- signed signal
+ depthbits : natural := CF_DELAYBITS
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ hold : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end component;
+\r
+
+constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');\r
+\r
+signal pulse_write_S : std_logic;\r
+signal pulse_superburst_S : std_logic_vector(15 downto 0);\r
+signal pulse_timestamp_S : std_logic_vector(15 downto 0);\r
+signal pulse_max_S : std_logic_vector(ADCBITS downto 0); \r
+signal pulse_CF1_S : std_logic_vector(15 downto 0);\r
+signal pulse_CF2_S : std_logic_vector(15 downto 0);\r
+
+signal prev_setmax_S : std_logic; -- maximum set in previous clock cycle\r
+signal prev_pulse_valid_S : std_logic; -- valid signal in previous clock cycle\r
+signal after_max_counter_S : std_logic_vector(CF_DELAYBITS downto 0) := (others => '0');\r
+\r
+signal pulse_skipped_S : std_logic := '0'; \r
+signal CF_available_S : std_logic := '0'; \r
+\r
+signal data_delayed_S : std_logic_vector(ADCBITS downto 0) := (others => '0');
+signal data_delayedx4_S : std_logic_vector(ADCBITS+2 downto 0) := (others => '0');
+signal cf_signal_S : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
+signal prev_cf_signal_S : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
+signal cf_negorzero_S : std_logic;\r
+signal prev_cf_negorzero_S : std_logic;\r
+signal enable_CF_S : std_logic;\r
+\r
+begin\r
+\r
+pulse_write <= pulse_write_S;\r
+pulse_superburst <= pulse_superburst_S;\r
+pulse_timestamp <= pulse_timestamp_S;\r
+pulse_skipped <= pulse_skipped_S;\r
+pulse_energy <= integral;\r
+pulse_CF1 <= pulse_CF1_S;\r
+pulse_CF2 <= pulse_CF2_S;\r
+\r
+pulse_write_S <= pulse_detected when CF_available_S='1' else '0';\r
+\r
+check_skipped: process(clock)\r
+variable holdcounter_V : integer range 0 to 3 := 3; -- keep value at the output for 4 clock cycles
+begin\r
+ if rising_edge(clock) then\r
+ if (pulse_detected='1') and (CF_available_S='0') then\r
+ pulse_skipped_S <= '1';\r
+ elsif pulse_detected='1' then\r
+ holdcounter_V := 0;\r
+ elsif holdcounter_V<3 then\r
+ holdcounter_V := holdcounter_V+1;\r
+ if holdcounter_V=2 then\r
+ pulse_skipped_S <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+\r
+get_maxima: process(clock)
+begin\r
+ if rising_edge(clock) then\r
+ prev_setmax_S <= '0';\r
+ if (pulse_valid='0') then\r
+ pulse_max_S <= data_in; \r
+ else\r
+ if conv_integer(signed(data_in))>=conv_integer(signed(pulse_max_S)) then\r
+ pulse_max_S <= data_in;\r
+ prev_setmax_S <= '1';\r
+ end if;\r
+ end if;\r
+ prev_pulse_valid_S <= pulse_valid;
+ end if;\r
+end process; \r
+\r
+after_max: process(clock)
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ enable_CF_S <= '0';\r
+ else \r
+ if (pulse_valid='0') then\r
+ enable_CF_S <= '0';\r
+ else\r
+ if prev_pulse_valid_S='0' then\r
+ enable_CF_S <= '1';\r
+ else\r
+ if prev_setmax_S='1' then\r
+ after_max_counter_S <= (others => '0');\r
+ else\r
+ if after_max_counter_S(CF_DELAYBITS-1 downto 0) = cf_delay then\r
+ enable_CF_S <= '0';\r
+ end if;\r
+ if after_max_counter_S(CF_DELAYBITS)='0' then\r
+ after_max_counter_S <= after_max_counter_S+1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;
+
+shiftregister1: shift_register
+ generic map(
+ width => ADCBITS+1, -- signed signal
+ depthbits => CF_DELAYBITS
+ )
+ port map(
+ clock => clock,
+ reset => reset,
+ hold => '0',
+ data_in => data_in,
+ depth => cf_delay,
+ data_out => data_delayed_S);\r
+\r
+\r
+data_delayedx4_S <= data_delayed_S & "00";
+cf_signal_S <= conv_std_logic_vector(conv_integer(signed(data_delayedx4_S))-conv_integer(signed(data_in)),ADCBITS+4);
+\r
+cf_negorzero_S <= '1' when (conv_integer(signed(cf_signal_S))<=0) else '0';\r
+\r
+count_samples: process(clock)\r
+variable pulse_CF1_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
+variable pulse_CF2_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
+begin
+ if (rising_edge(clock)) then\r
+ if reset='1' then\r
+ CF_available_S <= '0';\r
+ else
+ if (pulse_valid='0') and (pulse_detected='0') then\r
+ CF_available_S <= '0';\r
+ else\r
+ if prev_cf_negorzero_S='1' then\r
+ if cf_negorzero_S='0' then\r
+ if enable_CF_S='1' then\r
+ pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));\r
+ if pulse_CF1_V>65535 then\r
+ pulse_CF1_S <= x"ffff";\r
+ else\r
+ pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);\r
+ end if;\r
+ pulse_CF2_V := conv_integer(signed(cf_signal_S));\r
+ if pulse_CF2_V>65535 then\r
+ pulse_CF2_S <= x"ffff";\r
+ else\r
+ pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);\r
+ end if;\r
+ pulse_superburst_S <= superburstnumber(15 downto 0);\r
+ pulse_timestamp_S <= timestamp;\r
+ CF_available_S <= '1';\r
+ end if;\r
+ else\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ prev_cf_negorzero_S <= cf_negorzero_S;\r
+ prev_cf_signal_S <= cf_signal_S;\r
+ end if;\r
+end process;\r
+\r
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 19-11-2014
+-- Module Name: FEE_fifo32to8_SODA
+-- Description: FIFO with 32 bits to 8 bits conversion and SODA\r
+----------------------------------------------------------------------------------\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library work;
+use work.panda_package.all;
+\r
+----------------------------------------------------------------------------------
+-- FEE_fifo32to8_SODA
+-- FIFO with 32 bits to 8 bits conversion and additional K-character\r
+-- Data is written in asynchronous 32-bits fifo\r
+-- After reading the data is splitted in bytes.\r
+-- If no data is available an Idle is put on the output (BC and the K-character signal).\r
+-- SODA signals (DLM) are passed on directly (highest priority).\r
+--\r
+-- Library\r
+-- work.gtpBufLayer : for GTP/GTX/serdes constants\r
+--\r
+-- Generics:\r
+--
+-- Inputs:
+-- write_clock : clock for the 32-bits input data\r
+-- read_clock : clock for the 16-bits output data\r
+-- reset : reset\r
+-- data_in : 32-bits input data\r
+-- data_write : write signal for 32-bits input data\r
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+--
+-- Outputs:\r
+-- data_out : 16-bits output data\r
+-- char_is_k : corresponding byte in 16-bits output data is K-character\r
+-- \r
+-- Components:\r
+-- async_fifo_512x32 : 32-bits asynchronous fifo\r
+--
+----------------------------------------------------------------------------------\r
+\r
+\r
+entity FEE_fifo32to8_SODA is\r
+ port (
+ write_clock : in std_logic;\r
+ read_clock : in std_logic;
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(31 downto 0);\r
+ data_write : in std_logic;
+ full : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);\r
+ char_is_k : out std_logic
+ );\r
+end FEE_fifo32to8_SODA;\r
+\r
+architecture Behavioral of FEE_fifo32to8_SODA is\r
+
+component async_fifo_512x32
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(31 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(31 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;\r
+
+signal fifo_read_S : std_logic;
+signal fifo_dataout_S : std_logic_vector(31 downto 0);
+signal fifo_databuf_S : std_logic_vector(31 downto 0);
+signal data_out_S : std_logic_vector(7 downto 0);
+signal char_is_k_S : std_logic;
+signal fifo_empty_S : std_logic;
+signal prev_fifo_empty_S : std_logic;
+
+signal fifo_buffilled_S : std_logic := '0';
+signal fifo_read_after1clk_S : std_logic := '0';
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal bytecounter_S : integer range 0 to 3 := 0;
+signal write_data_S : std_logic;
+signal lastbytefilled_S : std_logic;
+signal lastbyte_S : std_logic_vector(7 downto 0);
+
+
+begin
+
+process (read_clock)
+begin
+ if rising_edge(read_clock) then
+ data_out <= data_out_S;
+ char_is_k <= char_is_k_S;
+ end if;
+end process;
+
+
+fifo: async_fifo_512x32 port map(
+ rst => reset,
+ wr_clk => write_clock,
+ rd_clk => read_clock,
+ din => data_in,
+ wr_en => data_write,
+ rd_en => fifo_read_S,
+ dout => fifo_dataout_S,
+ full => full,
+ empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') and (fifo_read_after1clk_S='0') and (lastbytefilled_S='0')
+ and (((bytecounter_S=0) and (fifo_buffilled_S='0')) or ((bytecounter_S=3) and (fifo_buffilled_S='0')))
+ else '0';
+
+data_out_S <=
+ KCHARSODA when TX_DLM='1' else
+ TX_DLM_WORD_S when (TX_DLM_S='1') else
+ KCHAR285 when (write_data_S='0') else
+ lastbyte_S when (lastbytefilled_S='1') else
+ fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
+ fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
+
+char_is_k_S <=
+ '1' when TX_DLM='1' else
+ '0' when (TX_DLM_S='1') else
+ '1' when (write_data_S='0') else
+ '0' when fifo_read_after1clk_S='1' else
+ '0';
+
+write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and
+ ((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
+
+tx_process : process (read_clock)
+begin
+ if rising_edge(read_clock) then
+ if reset='1' then
+ fifo_read_after1clk_S <= '0';
+ TX_DLM_S <= '0';
+ lastbytefilled_S <= '0';
+ bytecounter_S <= 0;
+ else
+ TX_DLM_S <= TX_DLM;
+ if TX_DLM='1' then
+ TX_DLM_WORD_S <= TX_DLM_WORD;
+ end if;
+ fifo_read_after1clk_S <= fifo_read_S;
+ prev_fifo_empty_S <= fifo_empty_S;
+ if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
+ lastbytefilled_S <= '0';
+ end if;
+ if (fifo_read_after1clk_S='1') then
+ if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then
+ lastbytefilled_S <= '1';
+ lastbyte_S <= fifo_databuf_S(7 downto 0);
+ end if;
+ fifo_databuf_S <= fifo_dataout_S;
+ fifo_buffilled_S <= '1';
+ end if;
+ if (TX_DLM='1') or (TX_DLM_S='1') then
+ elsif lastbytefilled_S='1' then
+ bytecounter_S <= 0;
+ else
+ case bytecounter_S is
+ when 0 =>
+ if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
+ fifo_buffilled_S <= '1';
+ bytecounter_S <= 1;
+ end if;
+ when 1 =>
+ fifo_buffilled_S <= '1';
+ bytecounter_S <= 2;
+ when 2 =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 3;
+ when 3 =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 0;
+ when others =>
+ fifo_buffilled_S <= '0';
+ bytecounter_S <= 0;
+ end case;
+ end if;
+ end if;
+ end if;
+end process;
+
+\r
+end Behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 19-11-2014
+-- Module Name: FEE_fifo8to32_SODA
+-- Description: FIFO with 8 bits to 32 bits conversion and SODA\r
+-- Modifications:
+----------------------------------------------------------------------------------\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.NUMERIC_STD.ALL;\r
+library work;
+use work.panda_package.all;
+\r
+----------------------------------------------------------------------------------
+-- FEE_fifo8to32_SODA
+-- FIFO with 8 bits to 32 bits conversion and SODA\r
+-- Byte data is converted to 32-bits, alignment is done with check on first word after idles
+-- The resulting 32-bits word is written in an asynchronous 32-bits fifo.\r
+-- SODA signals (DLM) are passed on directly (highest priority).
+--\r
+-- Library\r
+-- work.gtpBufLayer : for GTP/GTX/serdes constants\r
+--\r
+-- Generics:\r
+--
+-- Inputs:
+-- write_clock : clock for the 32-bits input data\r
+-- read_clock : clock for the 16-bits output data\r
+-- reset : reset\r
+-- data_in : 8-bits input data\r
+-- char_is_k : corresponding byte in 16-bits data input is K-character\r
+-- data_read : read signal for 32-bits output data\r
+--
+-- Outputs:\r
+-- RX_DLM : SODA character received
+-- RX_DLM_WORD : SODA character
+-- data_out : 32-bits output data (asynchrounous)\r
+-- data_available : 32-bits output data available (fifo not empty)\r
+-- overflow : fifo overflow : data has been thrown away\r
+-- error : error in input data\r
+-- \r
+-- Components:\r
+-- async_fifo_512x32 : 32-bits asynchronous fifo\r
+--
+----------------------------------------------------------------------------------\r
+\r
+\r
+entity FEE_fifo8to32_SODA is\r
+ port (
+ write_clock : in std_logic;\r
+ read_clock : in std_logic;
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;\r
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(31 downto 0);\r
+ data_read : in std_logic;
+ data_available : out std_logic;
+ overflow : out std_logic;
+ error : out std_logic
+ );\r
+end FEE_fifo8to32_SODA;\r
+\r
+architecture Behavioral of FEE_fifo8to32_SODA is\r
+
+component async_fifo_512x32
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(31 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(31 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;\r
+
+signal fifo_write_S : std_logic;
+signal fifo_datain_S : std_logic_vector(31 downto 0);
+signal fifo_full_S : std_logic;
+signal fifo_empty_S : std_logic;
+signal error_S : std_logic := '0';
+signal RX_DLM0_S : std_logic := '0';
+signal RX_DLM_S : std_logic := '0';
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0) := (others => '0');
+signal bytecounter_S : integer range 0 to 3 := 0;
+\r
+begin
+
+error <= error_S;\r
+RX_DLM_WORD <= RX_DLM_WORD_S;\r
+RX_DLM <= RX_DLM_S;
+\r
+fifo: async_fifo_512x32 port map(
+ rst => reset,
+ wr_clk => write_clock,
+ rd_clk => read_clock,
+ din => fifo_datain_S,
+ wr_en => fifo_write_S,
+ rd_en => data_read,
+ dout => data_out,
+ full => fifo_full_S,
+ empty => fifo_empty_S);
+data_available <= '1' when fifo_empty_S='0' else '0';
+
+overflow <= '1' when (fifo_write_S='1') and (fifo_full_S='1') else '0';
+
+rx_process : process(write_clock)
+variable idlecounter_V : integer range 0 to 4;
+begin
+ if rising_edge(write_clock) then
+ RX_DLM_S <= '0';
+ error_S <= '0';
+ fifo_write_S <= '0';
+ if reset='1' then
+ RX_DLM0_S <= '0';
+ bytecounter_S <= 0;
+ idlecounter_V := 0;
+ else
+ if (char_is_k='1') and (data_in=KCHARSODA) then
+ RX_DLM0_S <= '1';
+ error_S <= RX_DLM0_S; -- not 2 DLM after each other
+ elsif RX_DLM0_S='1' then
+ RX_DLM0_S <= '0';
+ RX_DLM_S <= '1';
+ RX_DLM_WORD_S <= data_in;
+ elsif (char_is_k='1') then -- idle: ignore a few
+ if idlecounter_V<4 then
+ idlecounter_V := idlecounter_V+1;
+ else
+ bytecounter_S <= 0;
+ end if;
+ error_S <= RX_DLM0_S; -- not an idle after DLM
+ else -- data
+ idlecounter_V := 0;
+ fifo_datain_S(31 downto 24) <= fifo_datain_S(23 downto 16);
+ fifo_datain_S(23 downto 16) <= fifo_datain_S(15 downto 8);
+ fifo_datain_S(15 downto 8) <= fifo_datain_S(7 downto 0);
+ fifo_datain_S(7 downto 0) <= data_in;
+ if bytecounter_S=3 then
+ bytecounter_S <= 0;
+ fifo_write_S <= '1';
+ else
+ bytecounter_S <= bytecounter_S+1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+\r
+end Behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 26-08-2013
+-- Module Name: FEE_gtxModule
+-- Description: GTP/GTX/serdes tranceiver for PANDA Front End Electronics with clock synchronization\r
+-- Modifications:
+-- 19-11-2014 Name changed from gtpBufLayerFee to FEE_gtxModule\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.NUMERIC_STD.ALL;\r
+\r
+Library UNISIM;\r
+use UNISIM.vcomponents.all;\r
+library work;
+use work.panda_package.all;
+\r
+----------------------------------------------------------------------------------
+-- FEE_gtxModule
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization:\r
+--\r
+-- Receiver generates synchronous clock on incomming serial data (SODA) and detects synchronous \r
+-- data packages (SODA-commands) with fixed delay. \r
+-- Receives also asynchronous data from fibre and outputs it as 32 bits.\r
+-- SODA packages use the DLM i/o. Data is send along with K27.7 character (0xFB)\r
+-- Idle's consists of K28.1 & K28.5 characters (0x3c,0xBC)\r
+-- All other valid (non K) characters is treated as data and combined to 32-bits\r
+--\r
+-- Transmitter sends data (asynchronous to SODA). The data is organised as 32-bits words.\r
+-- If no data is available then idle's are sent (0x3CBC)\r
+--\r
+-- Only one channel of the dual GTP or GTX is used.\r
+--\r
+-- Library\r
+-- work.gtpBufLayer : for GTP/GTX constants\r
+--\r
+-- Generics:\r
+--
+-- Inputs:
+-- gtpClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency (finally probably 155.52 MHz)\r
+-- asyncclk : clock for asynchronous resetting of GTP/GTX\r
+-- reset : reset GTP/GTX\r
+-- disable_GTX_reset : disable reset of GTX (during clock switching)
+-- TX_DLM : transmit SODA character
+-- TX_DLM_WORD : SODA character to be transmitted
+-- rxAsyncClk : Clock for the asynchronous (32-bits) data (used for slow-control in FEE)\r
+-- txAsyncData : asynchronous 32-bits data to be transmitted\r
+-- txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted\r
+-- txAsyncLastData : Last asynchronous 32-bits word of the data packet to be transmitted, used for separating packets on the fiber\r
+-- txAsyncClk : clock for the asynchronous 32-bits data to be transmitted\r
+-- rxAsyncDataRead : read signal for the asynchronous data fifo\r
+-- gtpRxP0,gtpRxN0 : differential GTP/GTX inputs \r
+--
+-- Outputs:\r
+-- RX_DLM : SODA character received
+-- RX_DLM_WORD : SODA character \r
+-- txAsyncFifoFull : fifo for 32-bits transmit data is full\r
+-- txLocked : Transmitter PLL locked\r
+-- rxAsyncData : asynchronous 32 bits data from the receiver fifo\r
+-- rxNotInTable : invalid character or other receiver error
+-- rxAsyncDataOverflow : overflow bit of the receiver asynchronous data fifo\r
+-- rxAsyncDataPresent : Indicates if asynchronous data is available in the receiver fifo\r
+-- rxSodaClk : Reconstructed clock, synchronous with original SODA clock but different frequency (200MHz)\r
+-- rxSodaClk40 : Reconstructed SODA clock : 40MHz\r
+-- rxLocked : Receiver locked\r
+-- gtpTxP0,gtpTxN0 : differential transmit outputs of the GTP/GTX (not used at the moment)\r
+-- \r
+-- Components:\r
+-- FEE_gtxWrapper_Virtex6 : module with the GTP/GTX interface\r
+-- FEE_SODAfrequencydiv5 : make divide by 5 clock from recovered clock\r
+-- FEE_fifo32to8_SODA : fifo for data to be transmitted, converts data from 32-bits to 16-bits\r
+-- FEE_fifo8to32_SODA : fifo for received asynchronous data, converts data from 16-bits to 32-bits\r
+-- sync_to_different_phase : synchronize to clock with same frequency but different phase\r
+--
+----------------------------------------------------------------------------------\r
+\r
+entity FEE_gtxModule is\r
+ Port (\r
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;\r
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;\r
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);\r
+ \r
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;\r
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncDataRead : in std_logic;
+ rxNotInTable : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;\r
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end FEE_gtxModule;\r
+\r
+\r
+architecture Behavioral of FEE_gtxModule is\r
+\r
+component FEE_gtxWrapper_Virtex6 is\r
+ port (\r
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;\r
+ gtpReset : in std_logic;\r
+ disable_GTX_reset : in std_logic;\r
+ \r
+ txData : in std_logic_vector (7 downto 0);\r
+ txCharIsK : in std_logic;\r
+ txP : out std_logic;\r
+ txN : out std_logic;\r
+ txUsrClk : out std_logic;\r
+ txLocked : out std_logic;\r
+ \r
+ rxData : out std_logic_vector (7 downto 0);\r
+ rxCharIsK : out std_logic;\r
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;\r
+ rxN : in std_logic;\r
+ rxUsrClk : out std_logic;\r
+ rxLocked : out std_logic;\r
+ \r
+ resetDone : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end component;\r
+\r
+component FEE_SODAfrequencydiv5 is
+ port (
+ clock : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ kchar : in std_logic;
+ clockdiv5 : out std_logic;
+ error : out std_logic
+ );
+end component;
+\r
+component FEE_fifo32to8_SODA is
+ port (
+ write_clock : in std_logic;\r
+ read_clock : in std_logic;
+ reset : in std_logic;\r
+ data_in : in std_logic_vector(31 downto 0);\r
+ data_write : in std_logic;
+ full : out std_logic;
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);\r
+ char_is_k : out std_logic
+ );
+end component;\r
+\r
+component FEE_fifo8to32_SODA is
+ port (
+ write_clock : in std_logic;
+ read_clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(7 downto 0);
+ char_is_k : in std_logic;
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ data_read : in std_logic;
+ data_available : out std_logic;
+ overflow : out std_logic;
+ error : out std_logic
+ );
+end component;\r
+\r
+component sync_to_different_phase is\r
+ generic (\r
+ WIDTH : natural := 18\r
+ );\r
+ port ( \r
+ clock1 : in std_logic;
+ clock2 : in std_logic;
+ data_in : in std_logic_vector(WIDTH-1 downto 0);\r
+ data_out : out std_logic_vector(WIDTH-1 downto 0)\r
+ );\r
+end component;\r
+\r
+component async_fifo_16x9
+ port (
+ rst : in std_logic;
+ wr_clk : in std_logic;
+ rd_clk : in std_logic;
+ din : in std_logic_vector(8 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(8 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;\r
+\r
+component asyncfifo is
+ generic (
+ DATA_WIDTH : natural := 9;
+ ADDR_WIDTH : natural := 2
+ );
+ port (
+ reset : in std_logic;
+ read_clock : in std_logic;
+ read_request : in std_logic;
+ data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+ write_clock : in std_logic;
+ write_request : in std_logic;
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+ empty : out std_logic;
+ full : out std_logic;\r
+ valid : out std_logic
+ );
+end component;\r
+\r
+signal rxSodaClk40_S : std_logic := '0';\r
+signal rxNotInTable_S : std_logic := '0';\r
+signal rxLocked_S : std_logic := '0';\r
+signal txLocked_S : std_logic := '0';\r
+signal txreset_S : std_logic := '0';\r
+signal txCharIsK_S : std_logic := '0';\r
+signal txUsrClk_S : std_logic;\r
+signal txData_S : std_logic_vector(7 downto 0);\r
+signal rxCharIsK_S : std_logic;\r
+\r
+signal rxUsrClk_S : std_logic;\r
+signal rxData_S : std_logic_vector(7 downto 0);\r
+signal rxerror_s : std_logic;\r
+\r
+signal TX_DLM_S : std_logic;\r
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);\r
+\r
+signal fifo_dout_S : std_logic_vector(8 downto 0) := (others => '0');\r
+signal fifosync_write_S : std_logic :='0';\r
+signal fifosync_read_S : std_logic :='0';\r
+signal fifosync_empty_S : std_logic :='0';\r
+signal fifosync_full_S : std_logic :='0';\r
+signal fifosync_valid_S : std_logic :='0';\r
+attribute keep : string;\r
+attribute keep of txUsrClk_S : signal is "TRUE";\r
+\r
+\r
+\r
+signal testword0_S : std_logic_vector (35 downto 0):= (others => '0');\r
+ \r
+begin\r
+\r
+txUsrClk <= txUsrClk_S;\r
+rxSodaClk <= rxUsrClk_S;\r
+rxSodaClk40 <= rxSodaClk40_S;\r
+\r
+FEE_gtxWrapper_Virtex6_1 : FEE_gtxWrapper_Virtex6 \r
+ port map ( \r
+ gtpClk => gtpClk,\r
+ asyncclk => asyncclk,\r
+ gtpReset => reset,\r
+ disable_GTX_reset => disable_GTX_reset,
+ txData => txData_S,\r
+ txCharIsK => txCharIsK_S,\r
+ txP => gtpTxP0,\r
+ txN => gtpTxN0,\r
+ txUsrClk => txUsrClk_S,\r
+ txLocked => txLocked_S,\r
+ rxData => rxData_S,\r
+ rxCharIsK => rxCharIsK_S,\r
+ rxNotInTable => rxNotInTable_S,\r
+ rxP => gtpRxP0,\r
+ rxN => gtpRxN0,\r
+ rxUsrClk => rxUsrClk_S,\r
+ rxLocked => rxLocked_S,\r
+ resetDone => open,\r
+ testword0 => testword0\r
+ );\r
+\r
+FEE_SODAfrequencydiv51: FEE_SODAfrequencydiv5 port map(
+ clock => rxUsrClk_S,
+ data => rxData_S,
+ kchar => rxCharIsK_S,
+ clockdiv5 => rxSodaClk40_S,
+ error => open
+ );
+\r
+-- synchronise SODA signals to txUsrClk_S. same frequency, differe4nt phase -----------------\r
+txreset_S <= '1' when (txLocked_S='0') or (reset='1') else '0';\r
+fifosync: async_fifo_16x9 port map(
+ rst => txreset_S,
+ wr_clk => rxUsrClk_S,
+ rd_clk => txUsrClk_S,
+ din(7 downto 0) => TX_DLM_WORD,
+ din(8) => TX_DLM,
+ wr_en => fifosync_write_S,
+ rd_en => fifosync_read_S,
+ dout => fifo_dout_S,
+ full => fifosync_full_S,
+ empty => fifosync_empty_S);\r
+--fifosync: asyncfifo
+-- generic map(
+-- DATA_WIDTH => 9,
+-- ADDR_WIDTH => 2
+-- )
+-- port map(
+-- reset => txreset_S,
+-- read_clock => txUsrClk_S,
+-- read_request => fifosync_read_S,
+-- data_in(7 downto 0) => TX_DLM_WORD,
+-- data_in(8) => TX_DLM,
+-- write_clock => rxUsrClk_S,
+-- write_request => fifosync_write_S,
+-- data_out => fifo_dout_S,
+-- empty => fifosync_empty_S,
+-- full => fifosync_full_S,\r
+-- valid => fifosync_valid_S);
+fifosync_read_S <= '1' when fifosync_empty_S='0' else '0';\r
+fifosync_write_S <= '1' when fifosync_full_S='0' else '0';\r
+
+TX_DLM_WORD_S <= fifo_dout_S(7 downto 0);\r
+TX_DLM_S <= fifo_dout_S(8);-- when fifosync_valid_S='1' else '0';\r
+\r
+FEE_fifo32to8_SODA1: FEE_fifo32to8_SODA port map(
+ write_clock => txAsyncClk,
+ read_clock => txUsrClk_S,
+ reset => reset,
+ data_in => txAsyncData,
+ data_write => txAsyncDataWrite,
+ full => txAsyncFifoFull,
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ data_out => txData_S,
+ char_is_k => txCharIsK_S \r
+ );\r
+\r
+\r
+\r
+\r
+FEE_fifo8to32_SODA1: FEE_fifo8to32_SODA port map(
+ write_clock => rxUsrClk_S,
+ read_clock => rxAsyncClk,
+ reset => reset,
+ data_in => rxData_S,
+ char_is_k => rxCharIsK_S,
+ RX_DLM => RX_DLM,
+ RX_DLM_WORD => RX_DLM_WORD,
+ data_out => rxAsyncData,
+ data_read => rxAsyncDataRead,
+ data_available => rxAsyncDataPresent,
+ overflow => rxAsyncDataOverflow,
+ error => rxerror_S);
+\r
+txLocked <= txLocked_S; -- 1 => OK\r
+rxLocked <= rxLocked_S; -- 1 => OK\r
+rxNotInTable <= rxNotInTable_S or rxerror_S; -- '1' => error\r
+\r
+--sync_to_different_phase1: sync_to_different_phase port map(\r
+-- clock1 => rxUsrClk_S,
+-- clock2 => txUsrClk_S,
+-- data_in(15 downto 0) => txData_rxclk_S,\r
+-- data_in(17 downto 16) => txCharisK_rxclk_S,\r
+-- data_out(15 downto 0) => txData_S,\r
+-- data_out(17 downto 16) => txCharIsK_S);\r
+\r
+\r
+--testword0 <= testword0_S;\r
+\r
+
+--testword0(15 downto 0) <= rxData_S;
+--testword0(17 downto 16) <= rxCharIsK_S;
+--testword0(33 downto 18) <= txData_rxclk_S;
+--testword0(34) <= '1' when txCharisK_rxclk_S="11" else '0';\r
+\r
+\r
+ \r
+end Behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Michel Hevinga / Peter Schakel
+-- Create Date: 2010
+-- Module Name: FEE_gtxWrapper_Virtex6
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Virtex6 with clock synchronization\r
+-- Modifications:
+-- 19-11-2014 Name changed from gtxWrapperVirtex6Fee to FEE_gtxWrapper_Virtex6\r
+----------------------------------------------------------------------------------\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+library work;
+use work.panda_package.all;
+library UNISIM;\r
+use UNISIM.VComponents.all;\r
+\r
+----------------------------------------------------------------------------------
+-- FEE_gtxWrapper_Virtex6
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.\r
+--\r
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA). \r
+-- Data is 16-bits, synchronous to recovered clock.\r
+-- Transmitter sends 16-bits data.\r
+--\r
+-- Only one channel of the dual GTP or GTX is used.\r
+--\r
+-- Library\r
+-- work.gtpBufLayer : for GTP/GTX constants\r
+--\r
+-- Generics:
+--
+-- Inputs:
+-- gtpClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency \r
+-- asyncclk : clock for synchronous resetting\r
+-- gtpReset : reset GTP/GTX\r
+-- disable_GTX_reset : disable ressetting temporarely\r
+-- txData : 16-bits input data to transmit\r
+-- txCharIsK : data to transmit are K-characters\r
+-- rxP,rxN : differential transmit inputs from the GTP/GTX\r
+--
+-- Outputs:\r
+-- txP,txN : differential transmit outputs of the GTP/GTX\r
+-- txUsrClk : clock for transmit data\r
+-- txLocked : transmitter locked\r
+-- rxData : 16-bits received data\r
+-- rxCharIsK : received 16-bits data (2 bytes) are K-characters\r
+-- rxNotInTable : receiver data not valid
+-- rxUsrClk : Recovered synchronous clock\r
+-- rxLocked : receiver locked to incomming data\r
+-- resetDone : resetting ready\r
+-- \r
+-- Components:\r
+-- GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments\r
+-- FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase\r
+-- Clock_62M5_doubler : Clock doubler with PLL\r
+--
+----------------------------------------------------------------------------------\r
+\r
+entity FEE_gtxWrapper_Virtex6 is\r
+ port (\r
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;\r
+ gtpReset : in std_logic;\r
+ disable_GTX_reset : in std_logic;\r
+ \r
+ txData : in std_logic_vector (7 downto 0);\r
+ txCharIsK : in std_logic;\r
+ txP : out std_logic;\r
+ txN : out std_logic;\r
+ txUsrClk : out std_logic;\r
+ txLocked : out std_logic;\r
+ \r
+ rxData : out std_logic_vector (7 downto 0);\r
+ rxCharIsK : out std_logic;\r
+ rxNotInTable : out std_logic;
+ rxP : in std_logic;\r
+ rxN : in std_logic;\r
+ rxUsrClk : out std_logic;\r
+ rxLocked : out std_logic;\r
+ \r
+ resetDone : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end FEE_gtxWrapper_Virtex6;\r
+\r
+architecture Behavioral of FEE_gtxWrapper_Virtex6 is\r
+\r
+component gtxVirtex6FEE80 is\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+ \r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+ \r
+ GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+\r
+ \r
+);\r
+\r
+\r
+end component;\r
+\r
+\r
+component FEE_rxBitLock is
+ Port ( clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0));
+end component;
+\r
+component gtxVirtex6FEE80_tx_sync
+generic
+(
+ -- Simulation attributes
+ SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset
+);
+port
+(
+ TXENPMAPHASEALIGN : out std_logic;
+ TXPMASETPHASE : out std_logic;
+ TXDLYALIGNDISABLE : out std_logic;
+ TXDLYALIGNRESET : out std_logic;
+ SYNC_DONE : out std_logic;
+ USER_CLK : in std_logic;
+ RESET : in std_logic
+);
+end component;
+\r
+component MGT_USRCLK_SOURCE_MMCM
+generic
+(
+ MULT : real := 2.0;
+ DIVIDE : integer := 2;
+ CLK_PERIOD : real := 6.4;
+ OUT0_DIVIDE : real := 2.0;
+ OUT1_DIVIDE : integer := 2;
+ OUT2_DIVIDE : integer := 2;
+ OUT3_DIVIDE : integer := 2
+);
+port
+(
+ CLKFBOUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ CLK1_OUT : out std_logic;
+ CLK2_OUT : out std_logic;
+ CLK3_OUT : out std_logic;
+ CLK_IN : in std_logic;
+ MMCM_LOCKED_OUT : out std_logic;
+ MMCM_RESET_IN : in std_logic
+);
+end component;\r
+\r
+signal rxCharIsK_S : std_logic;\r
+signal rxData_S : std_logic_vector(7 downto 0);\r
+signal rxReset_S : std_logic :='0';\r
+signal rxRecClk_S : std_logic :='0';\r
+signal rxRecClk_buf_S : std_logic :='0';\r
+signal rxRecClk_double_S : std_logic :='0';\r
+\r
+signal rxLocked_S : std_logic;\r
+signal txLocked_S : std_logic;\r
+signal txReset_S : std_logic;\r
+signal txResetdone_S : std_logic;\r
+\r
+signal rxLossOfSync_S : std_logic_vector(1 downto 0);\r
+signal rxLossOfSync1_S : std_logic;\r
+signal rxNotInTable_S : std_logic;\r
+signal rxDispError_S : std_logic; \r
+
+signal rxResetBitLock_S : std_logic :='0';
+signal pllLkDet_S : std_logic :='0';\r
+signal resetDone_S : std_logic :='0';\r
+signal txOutClk_S : std_logic :='0';\r
+\r
+--signal txUsrClk0_S : std_logic :='0';\r
+signal txUsrClk_buf_S : std_logic :='0';\r
+\r
+signal fsmStatus_S : std_logic_vector(1 downto 0);\r
+signal gtx0_double_reset_clk_i : std_logic;
+\r
+signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
+\r
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal disable_GTX_reset_S : std_logic :='0';\r
+
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ signal gtx0_txdlyaligndisable_i : std_logic;
+ signal gtx0_txdlyalignmonenb_i : std_logic;
+ signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_txdlyalignreset_i : std_logic;
+ signal gtx0_txenpmaphasealign_i : std_logic;
+ signal gtx0_txpmasetphase_i : std_logic;
+ signal gtx0_txresetdone_r : std_logic;
+ signal gtx0_txresetdone_r2 : std_logic;\r
+ signal gtx0_reset_txsync_c : std_logic;
+ signal gtx0_tx_sync_done_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+\r
+\r
+signal testword0_S : std_logic_vector(35 downto 0); \r
+\r
+begin\r
+ rxUsrClk <= rxRecClk_buf_S;\r
+ rxData <= rxData_S; \r
+ txUsrClk <= txUsrClk_buf_S;\r
+ resetDone <= resetDone_S;\r
+ rxLocked <= rxLocked_S;\r
+ txLocked <= txLocked_S; \r
+ rxCharIsK <= rxCharIsK_S; \r
+ \r
+--rxRecClk0_BUFG: BUFG port map (
+-- I => rxRecClk_S,
+-- O => rxRecClk_buf_S);\r
+
+rxrecclk_bufr1_i : BUFR
+ generic map ( BUFR_DIVIDE => "BYPASS" )
+ port map (
+ CE => '1',
+ CLR => '0',
+ I => rxRecClk_S,
+ O => rxRecClk_buf_S);
+
+-----------------------Dedicated GTX Reference Clock Inputs ---------------
+-- The dedicated reference clock inputs you selected in the GUI are implemented using
+-- IBUFDS_GTXE1 instances.
+--
+-- In the UCF file for this example design, you will see that each of
+-- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these
+-- locations, we tell the tools to use the dedicated input buffers to the GTX reference
+-- clock network, rather than general purpose IOs. To select other pins, consult the
+-- Implementation chapter of UG___, or rerun the wizard.
+--
+-- This network is the highest performace (lowest jitter) option for providing clocks
+-- to the GTX transceivers.
+q3_clk0_refclk_bufg_i : BUFG port map (
+ I => gtpClk,
+ O => gtx0_double_reset_clk_i);
+
+\r
+\r
+gtx_i : gtxVirtex6FEE80 port map(\r
+ GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT => rxCharIsK_S,
+ GTX0_RXDISPERR_OUT => rxDispError_S,
+ GTX0_RXNOTINTABLE_OUT => rxNotInTable_S,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN => '0', -- disable byte boundery alignment
+ GTX0_RXENPCOMMAALIGN_IN => '0', -- disable byte boundery alignment
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT => rxData_S,
+ GTX0_RXRECCLK_OUT => rxRecClk_S,
+ GTX0_RXRESET_IN => rxReset_S,
+ GTX0_RXUSRCLK2_IN => rxRecClk_buf_S,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN => rxReset_S,
+--? GTX0_RXELECIDLE_OUT => open,
+ GTX0_RXN_IN => rxN,
+ GTX0_RXP_IN => rxP,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN => '0', --- ??????????????????
+ GTX0_RXDLYALIGNMONENB_IN => '0', --- ??????????????????
+ GTX0_RXDLYALIGNMONITOR_OUT => open, --- ??????????????????
+ GTX0_RXDLYALIGNOVERRIDE_IN => '1', --- ??????????????????
+ GTX0_RXDLYALIGNRESET_IN => '0', --- ??????????????????
+ GTX0_RXENPMAPHASEALIGN_IN => '0',
+ GTX0_RXPMASETPHASE_IN => '0',
+ GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT => rxLossOfSync_S,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN => gtpReset,
+ GTX0_MGTREFCLKRX_IN => gtpClk,
+ GTX0_PLLRXRESET_IN => '0', -- gtpReset, --- ??????????????????????
+ GTX0_RXPLLLKDET_OUT => pllLkDet_S,
+ GTX0_RXRESETDONE_OUT => resetDone_S,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT => open, --?
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN => txCharIsK,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN => txData,
+ GTX0_TXOUTCLK_OUT => txOutClk_S,
+ GTX0_TXRESET_IN => txReset_S,
+ GTX0_TXUSRCLK2_IN => txUsrClk_buf_S,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT => txN,
+ GTX0_TXP_OUT => txP,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
+ GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
+ GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
+ GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
+ GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
+ GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN => gtpReset, --- ??????????????????????
+ GTX0_TXRESETDONE_OUT => txResetdone_S
+ );
+
+\r
+rxLossOfSync1_S <= '0' when (rxNotInTable_S='0') or (disable_GTX_reset_S='1') else '1';\r
+FEE_rxBitLock1 : FEE_rxBitLock port map (\r
+ clk => rxRecClk_buf_S,
+ reset => gtpReset,
+ resetDone => resetDone_S,
+ lossOfSync => rxLossOfSync1_S,
+ rxPllLocked => PllLkDet_S,
+ rxReset => rxResetBitLock_S,
+ fsmStatus => fsmStatus_S
+ );
+\r
+---- rxReset_S <= gtpReset;\r
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset='1')) and (disable_GTX_reset_S='0') else '0';
+rxLocked_S <= '1' when (fsmStatus_S = "10") else '0';
+rxNotInTable <= rxNotInTable_S;
+-- peter: gepulste reset (op refclk) voor zowel GTP als PLL
+-- lengte van de reset-pulse varieert om te voorkomen dat de reset synchroon is met de GTP
+----rxPLLwrapper_reset_S <= '1' when (notPllLkDet_S='1') or (rxResetBitLock_pulse_S='1') else '0';
+rxPLLwrapper_reset_S <= '1' when (rxResetBitLock_pulse_S='1') else '0';
+\r
+\r
+--ADCclkbuf : BUFG port map (
+-- O => txUsrClk_buf_S,
+-- I => txOutClk_S);\r
+txLocked_S <= '1' when (txResetdone_S='1') and (gtx0_tx_sync_done_i='1') else '0'; \r
+ \r
+rxRecClk_double_S <= '0';\r
+ \r
+process(rxRecClk_buf_S)
+begin
+ if rising_edge(rxRecClk_buf_S) then\r
+ disable_GTX_reset_S <= disable_GTX_reset;\r
+ end if;\r
+end process;
+
+
+process(asyncclk)
+variable resetcounter_V : integer range 0 to 63 := 0;
+variable lastresetcounter_V : integer range 0 to 63 := 10;
+begin
+ if rising_edge(asyncclk) then
+ if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+ rxResetBitLock_pulse_S <= '1';
+ resetcounter_V := 0;
+ if lastresetcounter_V<63 then
+ lastresetcounter_V := lastresetcounter_V+1;
+ else
+ lastresetcounter_V := 10;
+ end if;
+ elsif resetcounter_V<lastresetcounter_V then
+ rxResetBitLock_pulse_S <= '1';
+ resetcounter_V := resetcounter_V+1;
+ else
+ rxResetBitLock_pulse_S <= '0';
+ end if;
+ sync_rxResetBitLock_S <= rxResetBitLock_S;
+ prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+ end if;
+end process;\r
+\r
+\r
+ ------------------------------ TXSYNC module ------------------------------
+ -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It
+ -- waits for the user clocks to be stable, then drives the phase align signals on each
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
+
+ -- Include the TX_SYNC module in your own design to perform phase synchronization if
+ -- your protocol bypasses the TX Buffers
+ gtx0_reset_txsync_c <= not gtx0_txresetdone_r2;
+ -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0
+ -- during implementation
+ gtx0_txsync_i : gtxVirtex6FEE80_tx_sync
+ generic map
+ (
+ SIM_TXPMASETPHASE_SPEEDUP => 0
+ )
+ port map
+ (
+ TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,
+ TXPMASETPHASE => gtx0_txpmasetphase_i,
+ TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,
+ TXDLYALIGNRESET => gtx0_txdlyalignreset_i,
+ SYNC_DONE => gtx0_tx_sync_done_i,
+ USER_CLK => txUsrClk_buf_S,
+ RESET => gtx0_reset_txsync_c
+ );
+ -- The clock resources in this section were added based on userclk source selections on
+ -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:
+ -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to
+ -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits
+ -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency
+ -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when
+ -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all
+ -- the channels using the clock are receiving data from TX channels that share a reference clock
+ -- source with each other.
+
+ txoutclk_mmcm0_reset_i <= not pllLkDet_S;
+ txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
+ generic map
+ (
+ MULT => 15.0,
+ DIVIDE => 1,
+ CLK_PERIOD => 12.5,
+ OUT0_DIVIDE => 6.0,
+ OUT1_DIVIDE => 1,
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLKFBOUT => open,
+ CLK0_OUT => txUsrClk_buf_S,
+ CLK1_OUT => open,
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => txOutClk_S,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+ process( txUsrClk_buf_S,txResetdone_S)
+ begin
+ if(txResetdone_S = '0') then
+ gtx0_txresetdone_r <= '0';
+ gtx0_txresetdone_r2 <= '0';
+ elsif(txUsrClk_buf_S'event and txUsrClk_buf_S = '1') then
+ gtx0_txresetdone_r <= txResetdone_S;
+ gtx0_txresetdone_r2 <= gtx0_txresetdone_r;
+ end if;
+ end process;
+ txReset_S <= not txoutclk_mmcm0_locked_i;
+\r
+\r
+testword0(7 downto 0) <= rxData_S;
+testword0(8) <= rxCharIsK_S;
+testword0(10 downto 9) <= fsmStatus_S;
+testword0(12 downto 11) <= rxLossOfSync_S;\r
+testword0(13) <= rxNotInTable_S;
+
+testword0(14) <= rxReset_S;
+testword0(15) <= resetDone_S;
+testword0(16) <= rxPLLwrapper_reset_S;\r
+
+testword0(17) <= disable_GTX_reset_S;
+testword0(18) <= rxResetBitLock_S;
+testword0(19) <= rxResetBitLock_pulse_S;
+--testword0(20) <= rxLocked_S;
+--\r
+--testword0(21) <= gtpReset;
+--testword0(22) <= PllLkDet_S;
+--testword0(23) <= rxDispError_S;
+--testword0(24) <= rxLossOfSync1_S;
+--testword0(27 downto 25) <= gtx0_rxstatus_i;
+--testword0(28) <= sync_rxResetBitLock_S;
+testword0(29) <= prev_rxResetBitLock_S;
+testword0(30) <= txLocked_S;
+testword0(31) <= txResetdone_S;
+\r
+testword0(27 downto 20) <= txData;
+testword0(28) <= txCharIsK;
+\r
+\r
+end Behavioral;\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 16-09-2014
+-- Module Name: FEE_measure_frequency
+-- Description: Measures the frequency of pulses
+-- Modifications:
+-- 02-10-2014 onesecondpulse outside module
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_measure_frequency
+-- Measures the number of pulses in one second
+--
+-- Library
+-- work.panda_package : for type declarations and constants
+--
+-- Generics:\r
+-- CLOCKFREQUENCY : frequency of the clock
+--
+-- Inputs:
+-- clock : clock
+-- pulse : pulse to count
+--
+-- Outputs:
+-- frequency : number of pulses measured in one second
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_measure_frequency is\r
+ generic (\r
+ CLOCKFREQUENCY : natural := 80000000\r
+ );\r
+ port ( \r
+ clock : in std_logic;
+ pulse : in std_logic;\r
+ onesecondpulse : in std_logic;
+ frequency : out std_logic_vector(31 downto 0)\r
+ );\r
+end FEE_measure_frequency;
+
+architecture Behavioral of FEE_measure_frequency is
+
+signal counter_S : std_logic_vector(31 downto 0) := (others => '0');
+
+begin
+\r
+process(clock)\r
+begin
+ if (rising_edge(clock)) then \r
+ if onesecondpulse='1' then\r
+ frequency <= counter_S;\r
+ if pulse='1' then\r
+ counter_S <= x"00000001";\r
+ else\r
+ counter_S <= x"00000000";\r
+ end if;\r
+ else\r
+ if pulse='1' then\r
+ counter_S <= counter_S+1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_mux2to1
+-- Description: compare timestamp of 36bits data pass on first
+-- Modifications:
+-- 16-10-2014: 3*36bits words; bits 35 and 34 as indenticication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_mux2to1
+-- Compare timestamp of 36bits data and pass on first
+-- If data from only one is available then this is passed on directly
+-- The 36-bits data contains packets with 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data1_in : data from first 36-bits input, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data1_in_write : write signal for data1_in
+-- data1_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data2_in : data from second 36-bits input, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data2_in_write : write signal for data2_in
+-- data2_in_available : more data available: wait with timestamp check until the timestamp is read
+-- data_out_allowed : writing of resulting data allowed
+--
+-- outputs
+-- data1_in_allowed : signal to allow data input 1
+-- data2_in_allowed : signal to allow data input 2
+-- data_out : 36-bits data with valid pulse waveform, 3 words:
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_write : write signal for 36-bits output data
+-- data_out_available : data available: in this module or at the input
+-- error : error in data bits 35..32
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_mux2to1 is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data1_in : in std_logic_vector(35 downto 0);
+ data1_in_write : in std_logic;
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;
+ data2_in : in std_logic_vector(35 downto 0);
+ data2_in_write : in std_logic;
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_mux2to1;
+
+
+architecture Behavioral of FEE_mux2to1 is
+
+constant TIMEOUTBITS : integer := 6;
+signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+
+signal error_S : std_logic := '0';
+signal read_pulse1_S : std_logic := '0';
+signal read_pulse2_S : std_logic := '0';
+signal data1_in_allowed_S : std_logic := '0';
+signal data2_in_allowed_S : std_logic := '0';
+signal data1_in_write_S : std_logic := '0';
+signal data2_in_write_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_available_S : std_logic := '0';
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data1_timestamp_valid_S : std_logic := '0';
+signal data2_timestamp_valid_S : std_logic := '0';
+
+begin
+
+error <= error_S;
+
+data_out_available <= data_out_available_S;
+data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1')
+ or (data_out_trywrite_S='1')
+ or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
+ else '0';
+
+data_out <= data_out_S;
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data1_in_allowed <= data1_in_allowed_S;
+data1_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse1_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
+ else '0';
+
+data2_in_allowed <= data2_in_allowed_S;
+data2_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse2_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+ else '0';
+
+--data2_in_allowed_S <= '1' when (data_out_allowed='1')
+-- and ((read_pulse2_S='1')
+-- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
+-- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+-- else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
+
+readprocess: process(clock)
+variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data1_timestamp_valid_V : std_logic;
+variable data2_timestamp_valid_V : std_logic;
+variable data1_lowchannel_V : std_logic;
+variable data2_lowchannel_V : std_logic;
+variable data1_pulseskipped_V : std_logic;
+variable data2_pulseskipped_V : std_logic;
+
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_trywrite_S <= '0';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data1_timestamp_valid_S <= '0';
+ data2_timestamp_valid_S <= '0';
+ timeout_counter_S <= (others => '0');
+ else
+ if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+ data_out_trywrite_S <= '1'; -- try again
+ timeout_counter_S <= (others => '0');
+ else
+ if read_pulse1_S='1' then
+ data1_timestamp_valid_V := '0';
+ if data1_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data1_in(35 downto 34)="01") then -- next data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';
+ elsif (data1_in(35 downto 34)="10") then -- last data
+ error_S <= '0';
+ data_out_S <= data1_in;
+ read_pulse1_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ elsif read_pulse2_S='1' then
+ data2_timestamp_valid_V := '0';
+ if data2_in_write_S='1' then
+ timeout_counter_S <= (others => '0');
+ if (data2_in(35 downto 34)="01") then -- next data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';
+ elsif (data2_in(35 downto 34)="10") then -- last data
+ error_S <= '0';
+ data_out_S <= data2_in;
+ read_pulse2_S <= '0';
+ data_out_trywrite_S <= '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';
+ end if;
+ else
+ data_out_trywrite_S <= '0';
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ else
+ if data_out_allowed='1' then
+ timeout_counter_S <= timeout_counter_S+1;
+ end if;
+ error_S <= '0';
+ end if;
+ end if;
+ else
+ timeout_counter_S <= (others => '0');
+ if data1_in_write_S='1' then
+ if (data1_in(35 downto 34)="00") then
+ data1_timestamp_V := data1_in(31 downto 0);
+ data1_lowchannel_V := data1_in(33);
+ data1_pulseskipped_V := data1_in(32);
+ data1_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data2_in_write_S='1' then
+ if (data2_in(35 downto 34)="00") then
+ data2_timestamp_V := data2_in(31 downto 0);
+ data2_lowchannel_V := data1_in(33);
+ data2_pulseskipped_V := data1_in(32);
+ data2_timestamp_valid_V := '1';
+ else -- error
+ error_S <= '1';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;
+ end if;
+ if data1_timestamp_valid_V='1' then
+ if data2_timestamp_valid_V='1' then
+ if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
+ or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then
+ read_pulse1_S <= '1';
+ data1_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
+ else -- select 2
+ read_pulse2_S <= '1';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
+ end if;
+ elsif data2_in_available='1' then -- data expected: wait
+ data_out_trywrite_S <= '0';
+ else -- write 1
+ read_pulse1_S <= '1';
+ data1_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
+ end if;
+ elsif data2_timestamp_valid_V='1' then
+ if data1_in_available='1' then -- data expected: wait
+ data_out_trywrite_S <= '0';
+ else -- write 2
+ read_pulse2_S <= '1';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '1';
+ data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
+ end if;
+ else -- no valid timestamps
+ data_out_trywrite_S <= '0';
+ end if;
+ end if;
+ data1_timestamp_valid_S <= data1_timestamp_valid_V;
+ data2_timestamp_valid_S <= data2_timestamp_valid_V;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+
+-- testword0 <= (others => '0');
+
+testword0(0) <= data1_in_write;
+testword0(1) <= data1_in_available;
+testword0(2) <= data1_in_allowed_S;
+testword0(3) <= read_pulse1_S;
+testword0(4) <= data1_in_write_S;
+testword0(5) <= data1_timestamp_valid_S;
+testword0(9 downto 6) <= data1_in(35 downto 32);
+
+testword0(10) <= data2_in_write;
+testword0(11) <= data2_in_available;
+testword0(12) <= data2_in_allowed_S;
+testword0(13) <= read_pulse2_S;
+testword0(14) <= data2_in_write_S;
+testword0(15) <= data2_timestamp_valid_S;
+testword0(19 downto 16) <= data2_in(35 downto 32);
+
+
+testword0(20) <= data_out_trywrite_S;
+testword0(21) <= data_out_write_S;
+testword0(22) <= data_out_available_S;
+testword0(23) <= data_out_allowed;
+testword0(27 downto 24) <= data_out_S(35 downto 32);
+testword0(28) <= error_S;
+
+
+
+testword0(35 downto 29) <= (others => '0');
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_mux_readfifo
+-- Description: Read 36-bits data from fifo and write to next module
+-- Modifications:
+-- 16-10-2014 new name for output : data_out_inpipe
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- MUX_mux_readfifo
+-- Read 36-bits data from fifo and write to next module.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : ADC sampling clock \r
+-- reset : synchrounous reset\r
+-- data_in : 36-bits input data from fifo
+-- data_in_available : input fifo not empty\r
+-- data_out_allowed : allowed to write output data data
+--
+-- Outputs:
+-- data_in_read : read signal to input fifo
+-- data_out : 36-bits output data
+-- data_out_write : write signal for output data
+-- data_out_inpipe : data available, in this module or in input fifo
+--
+-- Components:\r
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_mux_readfifo is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);\r
+end FEE_mux_readfifo;
+
+
+architecture Behavioral of FEE_mux_readfifo is\r
+\r
+signal data_in_S : std_logic_vector(35 downto 0) := (others => '0');\r
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');\r
+signal data_out_write_S : std_logic := '0';\r
+signal data_in_saved_S : std_logic := '0';
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+\r
+\r
+begin
+\r
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or \r
+ (data_in_saved_S='1') else '0';\r
+\r
+data_in_read <= data_in_read_S;\r
+data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';\r
+\r
+data_out_write <= data_out_write_S;\r
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';\r
+\r
+data_out <= data_out_S;\r
+\r
+process(clock)\r
+begin
+ if (rising_edge(clock)) then \r
+ if reset='1' then\r
+ data_in_read_after1clk_S <= '0';\r
+ data_out_trywrite_S <= '0';\r
+ data_in_saved_S <= '0';\r
+ else\r
+ if (data_out_write_S='0') and (data_out_trywrite_S='1') then -- unsuccesfull try again\r
+ data_out_trywrite_S <= '1';\r
+ if data_in_read_after1clk_S='1' then\r
+ data_in_S <= data_in;\r
+ data_in_saved_S <= '1';\r
+ end if;\r
+ elsif data_in_saved_S='1' then -- write saved data\r
+ data_out_S <= data_in_S;\r
+ data_out_trywrite_S <= '1';\r
+ if data_in_read_after1clk_S='1' then -- save next data\r
+ data_in_S <= data_in;\r
+ data_in_saved_S <= '1';\r
+ else\r
+ data_in_saved_S <= '0';\r
+ end if;\r
+ elsif data_in_read_after1clk_S='1' then -- next read\r
+ data_out_S <= data_in;\r
+ data_out_trywrite_S <= '1';\r
+ else\r
+ data_out_trywrite_S <= '0';\r
+ end if;\r
+ data_in_read_after1clk_S <= data_in_read_S;\r
+ end if;\r
+ end if;\r
+end process;
+
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 16-03-2012
+-- Module Name: FEE_pileup_check
+-- Description: Checks and compares two pulselength's
+-- Modifications:
+-- 02-09-2014 timestamp output indicates now the time of pulse or pileup valid signal
+-- 16-09-2014 name changed from pileup_check to FEE_pileup_check
+-- 24-09-2014 enable_highgain and enable_lowgain inputs added
+-- 10-10-2014 Integral output added, as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_pileup_check\r
+-- Determines if pulses should be regarded as pileup, as single pulse, or rejected.\r
+-- If the pulse-time is below an adjustable number of samples then the pulse is rejected.\r
+-- If the pulse-time is longer than an adjustable number of samples then the pulse is regarded as pileup.\r
+-- The other pulses are tested for Integral/Maximum ratio:\r
+-- Pulse is valid until the signal dropps below Triggerlevel_endofpulse\r
+-- The pulse is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.\r
+-- The pulse is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.\r
+-- At the end of the pulse 1-clockcycle signals are generated for : valid pulse, pileup or cleanup\r
+--\r
+--\r
+--\r
+-- generics\r
+-- ADCBITS : number of ADC-bits
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check\r
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- \r
+-- inputs\r
+-- clock : ADC sampling clock \r
+-- reset : synchrounous reset\r
+-- superburstnumber : actual superburstnumber\r
+-- timestampcounter : timestampcounter within superburst\r
+-- ADC_highgain : signed ADC value, corrected for baseline\r
+-- enable_highgain : enable high gain input
+-- max_data_highgain : maximum of the waveform, calculated by the eventdetector (unsigned)
+-- pulse_active_highgain : high gain pulse active (signal above threshold)\r
+-- pulse_rising_highgain : high gain pulse has not yet reached maximum\r
+-- ADC_lowgain : signed ADC value, corrected for baseline\r
+-- enable_lowgain : enable low gain input
+-- max_data_lowgain : maximum of the waveform, calculated by the eventdetector (unsigned)
+-- pulse_active_lowgain : low gain pulse active (signal above threshold)\r
+-- pulse_rising_lowgain : low gain pulse has not yet reached maximum\r
+-- minpulselength : number of samples below which the pulse is ignored\r
+-- pileuplength : number of samples above which the pulse is treated as pileup\r
+-- maxwavelength : maximum number of samples that can be saved in one waveform\r
+-- IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded\r
+-- IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup\r
+-- fullsize_wave_highgain : take waveforms with maximum size for highgain input\r
+-- fullsize_wave_lowgain : take waveforms with maximum size for lowgain input\r
+-- \r
+-- outputs\r
+-- pulse_valid_highgain : high gain pulse data valid, and pulse not too long\r
+-- singlepulse_highgain : high gain pulse detected\r
+-- pileuppulse_highgain : high gain pileup signal detected\r
+-- clearpulse_highgain : high gain pulse too short: clear saved samples\r
+-- integral_highgain : high gain scaled integral output as value for the energy
+-- pulse_valid_lowgain : low gain pulse data valid, and pulse not too long\r
+-- singlepulse_lowgain : low gain pulse detected\r
+-- pileuppulse_lowgain : low gain pileup signal detected\r
+-- clearpulse_lowgain : low gain pulse too short: clear saved samples\r
+-- integral_lowgain : low gain scaled integral output as value for the energy
+-- superburst : superburst of the detected pulse or pileup signal (start of valid)\r
+-- timestamp : timestamp within the superburst of the detected pulse or pileup signal (start of valid)\r
+--\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_pileup_check is\r
+ generic (
+ ADCBITS : natural := 14;
+ IDIVMAXBITS : natural := 5;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;\r
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ timestampcounter : in std_logic_vector(15 downto 0); \r
+ ADC_highgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
+ enable_highgain : in std_logic;
+ max_data_highgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_highgain : in std_logic;\r
+ pulse_rising_highgain : in std_logic;\r
+ clipping_highgain : in std_logic;\r
+ ADC_lowgain : in std_logic_vector(ADCBITS downto 0); -- signed\r
+ enable_lowgain : in std_logic;
+ max_data_lowgain : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+ pulse_active_lowgain : in std_logic;\r
+ pulse_rising_lowgain : in std_logic;\r
+ minpulselength : in std_logic_vector(7 downto 0);\r
+ pileuplength : in std_logic_vector(7 downto 0);\r
+ maxwavelength : in std_logic_vector(7 downto 0);\r
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ fullsize_wave_highgain : in std_logic;\r
+ fullsize_wave_lowgain : in std_logic;\r
+ pulse_valid_highgain : out std_logic;\r
+ singlepulse_highgain : out std_logic;\r
+ pileuppulse_highgain : out std_logic;\r
+ clearpulse_highgain : out std_logic;\r
+ integral_highgain : out std_logic_vector(15 downto 0);\r
+ pulse_valid_lowgain : out std_logic;\r
+ singlepulse_lowgain : out std_logic;\r
+ pileuppulse_lowgain : out std_logic;\r
+ clearpulse_lowgain : out std_logic;\r
+ integral_lowgain : out std_logic_vector(15 downto 0);\r
+ superburst : out std_logic_vector(15 downto 0);\r
+ timestamp : out std_logic_vector(15 downto 0);\r
+ testword0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end FEE_pileup_check;\r
+\r
+architecture Behavioral of FEE_pileup_check is\r
+\r
+constant ZEROS : std_logic_vector(31 downto 0) := (others => '0');\r
+signal pulse_highgain_tooshort_S : std_logic := '0';\r
+signal pulse_highgain_toolong_S : std_logic := '0';\r
+signal pulse_highgain_pileup_S : std_logic := '0';\r
+signal prev_pulse_highgain_toolong_S : std_logic := '0';\r
+signal prev_pulseactive_highgain_S : std_logic := '0';\r
+signal singlepulse_highgain_S : std_logic := '0';\r
+signal pileuppulse_highgain_S : std_logic := '0';\r
+signal clearpulse_highgain_S : std_logic := '0';\r
+signal pulse_active_highgain_prev1_S : std_logic := '0';\r
+signal pulse_active_highgain_prev2_S : std_logic := '0';\r
+signal counter_highgain_S : std_logic_vector(7 downto 0);\r
+\r
+signal singlepulse_lowgain_occured_S : std_logic := '0';\r
+signal pileuppulse_lowgain_occured_S : std_logic := '0';\r
+signal pulse_lowgain_tooshort_S : std_logic := '0';\r
+signal pulse_lowgain_toolong_S : std_logic := '0';\r
+signal pulse_lowgain_pileup_S : std_logic := '0';\r
+signal prev_pulse_lowgain_toolong_S : std_logic := '0';\r
+signal prev_pulseactive_lowgain_S : std_logic := '0';\r
+signal singlepulse_lowgain_S : std_logic := '0';\r
+signal pileuppulse_lowgain_S : std_logic := '0';\r
+signal clearpulse_lowgain_S : std_logic := '0';\r
+signal pulse_active_lowgain_prev1_S : std_logic := '0';\r
+signal pulse_active_lowgain_prev2_S : std_logic := '0';\r
+\r
+signal clipping_highgain_S : std_logic := '0';\r
+signal counter_lowgain_S : std_logic_vector(7 downto 0) := (others => '0');\r
+\r
+signal superburst_highgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+signal timestamp_highgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+signal superburst_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+signal timestamp_lowgain_S : std_logic_vector(15 downto 0) := (others => '0');\r
+\r
+\r
+signal integral_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal maxXconstant1_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal maxXconstant2_highgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal integral_highgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);\r
+signal pulse_highgain_toonarrow_s : std_logic := '0';\r
+signal pulse_highgain_toowide_S : std_logic := '0';\r
+\r
+\r
+signal integral_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal maxXconstant1_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal maxXconstant2_lowgain_S : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;\r
+signal integral_lowgain_stdl_S : std_logic_vector(ADCBITS+9 downto 0);\r
+signal pulse_lowgain_toonarrow_s : std_logic := '0';\r
+signal pulse_lowgain_toowide_S : std_logic := '0';\r
+\r
+signal fullsize_wave_highgain_S : std_logic := '0';\r
+signal fullsize_wave_lowgain_S : std_logic := '0';\r
+\r
+signal pulse_active_highgain_S : std_logic := '0';\r
+signal prev_pulseactive_highgainS_S : std_logic := '0';\r
+signal pulse_busy_highgain_S : std_logic := '0';\r
+signal pulse_active_lowgain_S : std_logic := '0';\r
+signal prev_pulse_active_lowgains_s : std_logic := '0';\r
+signal pulse_busy_lowgain_S : std_logic := '0';\r
+\r
+--integer range 0 to 2**(ADCBITS+IDIVMAXBITS-1)-1;\r
+begin\r
+\r
+integral_highgain_stdl_S <= conv_std_logic_vector(integral_highgain_S,ADCBITS+10);\r
+integral_highgain <= \r
+ x"0000" when (integral_highgain_stdl_S(ADCBITS+9)='1') else -- negative\r
+ x"ffff" when (integral_highgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip\r
+ else integral_highgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);\r
+\r
+integral_lowgain_stdl_S <= conv_std_logic_vector(integral_lowgain_S,ADCBITS+10);\r
+integral_lowgain <= \r
+ x"0000" when (integral_lowgain_stdl_S(ADCBITS+9)='1') else -- negative\r
+ x"ffff" when (integral_lowgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip\r
+ else integral_lowgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);\r
+\r
+\r
+process(clock)\r
+begin\r
+ if (rising_edge(clock)) then \r
+ if (enable_highgain='1') then\r
+ fullsize_wave_highgain_S <= fullsize_wave_highgain;\r
+ else\r
+ fullsize_wave_highgain_S <= '0';\r
+ end if;\r
+ if (enable_lowgain='1') then\r
+ fullsize_wave_lowgain_S <= fullsize_wave_lowgain;\r
+ else\r
+ fullsize_wave_lowgain_S <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+clipping_highgain_S <= clipping_highgain;\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if (reset='1') then\r
+ integral_highgain_S <= conv_integer(signed(ADC_highgain));\r
+ else\r
+ if ((pulse_active_highgain='0') and (pulse_active_highgain_prev1_S='0')) or\r
+ ((pulse_active_highgain='1') and (pulse_active_highgain_prev1_S='0') and (pulse_active_highgain_prev2_S='1'))then\r
+ integral_highgain_S <= conv_integer(signed(ADC_highgain));\r
+ else\r
+ integral_highgain_S <= integral_highgain_S+conv_integer(signed(ADC_highgain));\r
+ end if;\r
+ end if;\r
+ pulse_active_highgain_prev2_S <= pulse_active_highgain_prev1_S;
+ pulse_active_highgain_prev1_S <= pulse_active_highgain;\r
+ end if;\r
+end process;\r
+ \r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ maxXconstant1_highgain_S <= conv_integer(unsigned(max_data_highgain)) * conv_integer(unsigned(IdivMAX_discard));\r
+ maxXconstant2_highgain_S <= conv_integer(unsigned(max_data_highgain)) * conv_integer(unsigned(IdivMAX_pileup));\r
+ end if;\r
+end process;\r
+pulse_highgain_toonarrow_S <= '1' when maxXconstant1_highgain_S>integral_highgain_S else '0';\r
+pulse_highgain_toowide_S <= '1' when maxXconstant2_highgain_S<integral_highgain_S else '0';\r
+\r
+process(clock)
+begin
+ if rising_edge(clock) then
+ if (reset='1') then\r
+ integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+ else
+ if ((pulse_active_lowgain='0') and (pulse_active_lowgain_prev1_S='0')) or \r
+ ((pulse_active_lowgain='1') and (pulse_active_lowgain_prev1_S='0') and (pulse_active_lowgain_prev2_S='1')) then -- if 2nd pulse within 1 clock
+ integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+ else
+ integral_lowgain_S <= integral_lowgain_S+conv_integer(signed(ADC_lowgain));
+ end if;
+ end if;\r
+ pulse_active_lowgain_prev2_S <= pulse_active_lowgain_prev1_S;
+ pulse_active_lowgain_prev1_S <= pulse_active_lowgain;
+ end if;
+end process;
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ maxXconstant1_lowgain_S <= conv_integer(unsigned(max_data_lowgain)) * conv_integer(unsigned(IdivMAX_discard));
+ maxXconstant2_lowgain_S <= conv_integer(unsigned(max_data_lowgain)) * conv_integer(unsigned(IdivMAX_pileup));
+ end if;
+end process;
+pulse_lowgain_toonarrow_S <= '1' when maxXconstant1_lowgain_S>integral_lowgain_S else '0';
+pulse_lowgain_toowide_S <= '1' when maxXconstant2_lowgain_S<integral_lowgain_S else '0';
+\r
+pulse_highgain_tooshort_S <= '1' when (counter_highgain_S<minpulselength) else '0';\r
+clearpulse_highgain_S <= enable_highgain \r
+ when ((pulse_active_highgain='0') and (prev_pulseactive_highgain_S='1'))\r
+ and ((pulse_highgain_tooshort_S='1') or (pulse_highgain_toonarrow_S='1'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ else '0';\r
+clearpulse_highgain <= clearpulse_highgain_S;\r
+singlepulse_highgain_S <= enable_highgain \r
+ when ((pulse_active_highgain='0') and (prev_pulseactive_highgain_S='1'))\r
+ and ((pulse_highgain_toolong_S='0') and ((pulse_highgain_tooshort_S='0') and (pulse_highgain_toonarrow_S='0')))\r
+ and (pulse_highgain_pileup_S='0')\r
+ and (pulse_highgain_toowide_S='0')\r
+ and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1')\r
+ and (pileuppulse_lowgain_occured_S='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ else '0';\r
+singlepulse_highgain <= singlepulse_highgain_S;\r
+\r
+\r
+pileuppulse_highgain_S <= enable_highgain \r
+ when\r
+ (((pulse_active_highgain='0') and (prev_pulseactive_highgain_S='1')) \r
+ and ((pulse_highgain_toolong_S='0') and ((pulse_highgain_tooshort_S='0') and (pulse_highgain_toonarrow_S='0')))\r
+ and ((pulse_highgain_pileup_S='1') or (pulse_highgain_toowide_S='1'))\r
+ and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
+ and (pileuppulse_lowgain_occured_S='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))\r
+ and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1') \r
+ and (pileuppulse_lowgain_occured_S='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))\r
+ and ((fullsize_wave_highgain_S='1') and (fullsize_wave_lowgain_S='0')))\r
+ else '0';\r
+pileuppulse_highgain <= pileuppulse_highgain_S;\r
+\r
+pulse_valid_highgain <= enable_highgain \r
+ when (pulse_active_highgain_S='1') and (pulse_highgain_toolong_S='0')\r
+ else '0';\r
+\r
+pulse_active_highgain_S <= enable_highgain \r
+ when ((pulse_active_highgain='1') and ((fullsize_wave_highgain_S='0') or (pulse_busy_highgain_S='0')))\r
+ or ((fullsize_wave_highgain_S='1') and (pulse_highgain_toolong_S='0') and (pulse_busy_highgain_S='1'))\r
+ else '0';\r
+\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ counter_highgain_S <= (others => '0');\r
+ pulse_highgain_toolong_S <= '0';\r
+ pulse_highgain_pileup_S <= '0';\r
+ pulse_busy_highgain_S <= '0';\r
+ else \r
+ if (pulse_active_highgain_S='1') or (pulse_active_highgain='1') then\r
+ pulse_busy_highgain_S <= enable_highgain;\r
+ if counter_highgain_S<maxwavelength then\r
+ counter_highgain_S <= counter_highgain_S+1;\r
+ pulse_highgain_toolong_S <= '0';\r
+ if counter_highgain_S=pileuplength then\r
+ pulse_highgain_pileup_S <= '1';\r
+ end if;\r
+ else\r
+ pulse_highgain_toolong_S <= enable_highgain;\r
+ end if;\r
+ if (pulse_active_highgain_S='1') and (prev_pulseactive_highgainS_S='0') then\r
+ superburst_highgain_S <= superburstnumber(15 downto 0);\r
+ timestamp_highgain_S <= timestampcounter;\r
+ end if;\r
+ else\r
+ pulse_busy_highgain_S <= '0';\r
+ pulse_highgain_toolong_S <= '0';\r
+ counter_highgain_S <= (others => '0');\r
+ pulse_highgain_pileup_S <= '0';\r
+ end if;\r
+ end if;\r
+ prev_pulse_highgain_toolong_S <= pulse_highgain_toolong_S;\r
+ prev_pulseactive_highgain_S <= pulse_active_highgain;\r
+ prev_pulseactive_highgainS_S <= pulse_active_highgain_S;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ singlepulse_lowgain_occured_S <= '0';\r
+ pileuppulse_lowgain_occured_S <= '0';\r
+ else \r
+ if (pulse_active_highgain='0') then\r
+ singlepulse_lowgain_occured_S <= '0'; -- clear indicator for low-gain pulse happened\r
+ elsif singlepulse_lowgain_S='1' then\r
+ singlepulse_lowgain_occured_S <= enable_lowgain;\r
+ end if;\r
+ if (pulse_active_highgain='0') then\r
+ pileuppulse_lowgain_occured_S <= '0'; -- clear indicator for low-gain pileup-pulse happened\r
+ elsif pileuppulse_lowgain_S='1' then\r
+ pileuppulse_lowgain_occured_S <= enable_lowgain;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+pulse_lowgain_tooshort_S <= '1' when (counter_lowgain_S<minpulselength) else '0';
+clearpulse_lowgain_S <= enable_lowgain
+ when ((pulse_active_lowgain='0') and (prev_pulseactive_lowgain_S='1')) \r
+ and ((pulse_lowgain_tooshort_S='1') or (pulse_lowgain_toonarrow_S='1'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ else '0';\r
+clearpulse_lowgain <= clearpulse_lowgain_S;
+singlepulse_lowgain_S <= enable_lowgain
+ when ((pulse_active_lowgain='0') and (prev_pulseactive_lowgain_S='1')) \r
+ and (pulse_lowgain_pileup_S='0') \r
+ and (pulse_lowgain_toowide_S='0')
+ and ((pulse_lowgain_toolong_S='0') and (pulse_lowgain_tooshort_S='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))\r
+ and ((clipping_highgain_S='1') or (enable_highgain='0'))
+ else '0';
+singlepulse_lowgain <= singlepulse_lowgain_S;\r
+\r
+pileuppulse_lowgain_S <= enable_lowgain\r
+ when \r
+ (((pulse_active_lowgain='0') and (prev_pulseactive_lowgain_S='1')) \r
+ and ((pulse_lowgain_pileup_S='1') or (pulse_lowgain_toowide_S='1'))
+ and ((pulse_lowgain_toolong_S='0') and (pulse_lowgain_tooshort_S='0'))\r
+ and ((clipping_highgain_S='1') or (enable_highgain='0'))
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))\r
+ and ((clipping_highgain_S='1') or (enable_highgain='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))\r
+ or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))\r
+ and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='1')))\r
+ else '0';\r
+pileuppulse_lowgain <= pileuppulse_lowgain_S;\r
+pulse_valid_lowgain <= '1' \r
+ when (pulse_active_lowgain_S='1') and (pulse_lowgain_toolong_S='0')\r
+ else '0';\r
+\r
+pulse_active_lowgain_S <= enable_lowgain \r
+ when ((pulse_active_lowgain='1') and ((fullsize_wave_lowgain_S='0') or (pulse_busy_lowgain_S='0')))\r
+ or ((fullsize_wave_lowgain_S='1') and (pulse_lowgain_toolong_S='0') and (pulse_busy_lowgain_S='1'))\r
+ else '0';\r
+\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ counter_lowgain_S <= (others => '0');\r
+ pulse_lowgain_toolong_S <= '0';\r
+ pulse_lowgain_pileup_S <= '0';\r
+ pulse_busy_lowgain_S <= '0';\r
+ else\r
+ if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') then\r
+ pulse_busy_lowgain_S <= enable_lowgain;\r
+ if counter_lowgain_S<maxwavelength then\r
+ counter_lowgain_S <= counter_lowgain_S+1;\r
+ pulse_lowgain_toolong_S <= '0';\r
+ if counter_lowgain_S=pileuplength then\r
+ pulse_lowgain_pileup_S <= enable_lowgain;\r
+ end if;\r
+ else\r
+ pulse_lowgain_toolong_S <= enable_lowgain;\r
+ end if;\r
+ if (pulse_active_lowgain_S='1') or (prev_pulse_active_lowgainS_S='0') then\r
+ superburst_lowgain_S <= superburstnumber(15 downto 0);\r
+ timestamp_lowgain_S <= timestampcounter;\r
+ end if;\r
+ else\r
+ pulse_busy_lowgain_S <= '0';\r
+ pulse_lowgain_toolong_S <= '0';\r
+ counter_lowgain_S <= (others => '0');\r
+ pulse_lowgain_pileup_S <= '0';\r
+ end if;\r
+ end if;\r
+ prev_pulse_lowgain_toolong_S <= pulse_lowgain_toolong_S;\r
+ prev_pulseactive_lowgain_S <= pulse_active_lowgain;\r
+ prev_pulse_active_lowgainS_S <= pulse_active_lowgain_S;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ superburst <= (others => '0');\r
+ timestamp <= (others => '0');\r
+ else \r
+ if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then\r
+ superburst <= superburst_lowgain_S;\r
+ timestamp <= timestamp_lowgain_S;\r
+ elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then\r
+ superburst <= superburst_highgain_S;\r
+ timestamp <= timestamp_highgain_S;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+--testword0(0) <= pulse_active_highgain;\r
+--testword0(1) <= pulse_rising_highgain;\r
+--\r
+--testword0(2) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;\r
+--testword0(3) <= pulse_highgain_toolong_S;\r
+--testword0(4) <= prev_pulse_highgain_toolong_S;\r
+--testword0(5) <= prev_pulseactive_highgain_S;\r
+--testword0(6) <= singlepulse_highgain_S;\r
+--testword0(7) <= pileuppulse_highgain_S;\r
+--testword0(8) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;\r
+--testword0(9) <= pulse_highgain_toowide_S;\r
+--\r
+--testword0(15 downto 10) <= counter_highgain_S(5 downto 0);\r
+--testword0(16) <= pulse_active_lowgain;\r
+--testword0(17) <= pulse_rising_lowgain;\r
+--testword0(18) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;\r
+--testword0(19) <= pulse_lowgain_toolong_S;\r
+--testword0(20) <= prev_pulse_lowgain_toolong_S;\r
+--testword0(21) <= prev_pulseactive_lowgain_S;\r
+--testword0(22) <= singlepulse_lowgain_S;\r
+--testword0(23) <= pileuppulse_lowgain_S;\r
+--testword0(24) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;\r
+--testword0(25) <= pulse_lowgain_toowide_S;\r
+--\r
+--testword0(31 downto 26) <= counter_lowgain_S(5 downto 0);\r
+--\r
+--testword0(32) <= singlepulse_lowgain_occured_S;\r
+--testword0(33) <= pileuppulse_lowgain_occured_S;\r
+--testword0(34) <= clearpulse_highgain_S;\r
+--testword0(35) <= clearpulse_lowgain_S;\r
+\r
+\r
+testword0(22) <= pulse_active_highgain;\r
+testword0(23) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;\r
+testword0(24) <= singlepulse_highgain_S;\r
+testword0(25) <= pileuppulse_highgain_S;\r
+testword0(26) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;\r
+testword0(27) <= pulse_active_lowgain;\r
+testword0(28) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;\r
+testword0(29) <= singlepulse_lowgain_S;\r
+testword0(30) <= pileuppulse_lowgain_S;\r
+testword0(31) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;\r
+testword0(32) <= singlepulse_lowgain_occured_S;\r
+testword0(33) <= pileuppulse_lowgain_occured_S;\r
+testword0(34) <= clearpulse_highgain_S;\r
+testword0(35) <= clearpulse_lowgain_S;\r
+\r
+end Behavioral;\r
+\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-09-2014
+-- Module Name: FEE_pulse2to1_pulse
+-- Description: Get hit-members from high and low gain input and put in a 36-bits wide stream
+-- Modifications:
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_pulse2to1_pulse\r
+-- Get hit-members from high and low gain input and put in a 36-bits wide stream.
+-- The members are:
+-- superburstnumber, timestamp,
+-- CF_signal before and after zero-crossing,
+-- two samples at the maximum of the pulse,
+-- status that indicates if a previous pulse was skipped
+--\r
+-- The output data consist of packets with three 36-bits each containing the members of one hit:\r
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--\r
+--\r
+-- generics\r
+-- \r
+-- inputs\r
+-- clock : ADC sampling clock \r
+-- reset : synchrounous reset\r
+-- channel : adc index
+-- pulse1_write : write signal for the input signal from first input
+-- pulse1_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse1_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse1_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse1_energy : energy of the pulse : scaled integral
+-- pulse1_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse1_CF2 : CF_signal value of the value after the zero-crossing (absolute value)
+-- pulse2_write : write signal for the input signal from second input
+-- pulse2_superburst : superburstnumber at the time of the constant fraction signal before the zero crossing
+-- pulse2_timestamp : 16-bits timestamp (inside the superburst) of the constant fraction signal before the zero crossing
+-- pulse2_skipped : signal to indicate that the previous constant fraction was not successful and that the pulse was discarded
+-- pulse2_energy : energy of the pulse : scaled integral
+-- pulse2_CF1 : CF_signal value of the value before the zero-crossing (absolute value)
+-- pulse2_CF2 : CF_signal value of the value after the zero-crossing (absolute value)
+-- data_out_almostfull : target fifo is almost full : discard data-packet and report skipped pulse at next hit-result packet
+-- data_out_allowed : writing of resulting data allowed
+-- \r
+-- outputs\r
+-- pulse_skipped : indicates that a hit is skipped (buffer overrun or faulty constant fraction)\r
+-- data2_in_allowed : signal to allow data input 2\r
+-- data_out : 36-bits data with valid pulse waveform:\r
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_write : write signal for 36-bits output data\r
+--\r
+-- components\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_pulse2to1_pulse is\r
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;
+ channel : in std_logic_vector(7 downto 0);
+ pulse1_write : in std_logic;\r
+ pulse1_superburst : in std_logic_vector(15 downto 0);\r
+ pulse1_timestamp : in std_logic_vector(15 downto 0);\r
+ pulse1_skipped : in std_logic;\r
+ pulse1_energy : in std_logic_vector(15 downto 0);\r
+ pulse1_CF1 : in std_logic_vector(15 downto 0);\r
+ pulse1_CF2 : in std_logic_vector(15 downto 0);\r
+ pulse2_write : in std_logic;\r
+ pulse2_superburst : in std_logic_vector(15 downto 0);\r
+ pulse2_timestamp : in std_logic_vector(15 downto 0);\r
+ pulse2_skipped : in std_logic;\r
+ pulse2_energy : in std_logic_vector(15 downto 0);\r
+ pulse2_CF1 : in std_logic_vector(15 downto 0);\r
+ pulse2_CF2 : in std_logic_vector(15 downto 0);\r
+ pulse_skipped : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_almostfull : in std_logic;
+ data_out_allowed : in std_logic\r
+ );\r
+end FEE_pulse2to1_pulse;\r
+\r
+\r
+architecture Behavioral of FEE_pulse2to1_pulse is\r
+constant zeros : std_logic_vector(35 downto 0) := (others => '0');
+signal select2_S : std_logic;
+signal select2b_S : std_logic := '0';
+signal writeindex_S : integer range 0 to 2 := 0;
+signal pulse1_skipped_S : std_logic := '0';
+signal pulse2_skipped_S : std_logic := '0';
+signal pulse1_skipbit_S : std_logic;
+signal pulse2_skipbit_S : std_logic;
+
+begin\r
+\r
+pulse_skipped <= '1' when (pulse1_skipped_S='1') or (pulse2_skipped_S='1') else '0';\r
+\r
+select2_S <= \r
+ '0' when ((writeindex_S=0) and (pulse1_write='1')) else\r
+ '1' when ((writeindex_S=0) and (pulse2_write='1')) else\r
+ select2b_S;\r
+data_out <= \r
+ "00" & '0' & pulse1_skipbit_S & pulse1_superburst & pulse1_timestamp when (select2_S='0') and (writeindex_S=0) else\r
+ "00" & '1' & pulse2_skipbit_S & pulse2_superburst & pulse2_timestamp when (select2_S='1') and (writeindex_S=0) else\r
+ "01" & "00" & x"00" & channel(7 downto 1) & '0' & pulse1_energy when (select2_S='0') and (writeindex_S=1) else\r
+ "01" & "00" & x"00" & channel(7 downto 1) & '1' & pulse2_energy when (select2_S='1') and (writeindex_S=1) else\r
+ "10" & "00" & pulse1_CF1 & pulse1_CF2 when (select2_S='0') and (writeindex_S=2) else\r
+ "10" & "00" & pulse2_CF1 & pulse2_CF2; -- when (select2_S='1') and (writeindex_S=2) else\r
+pulse1_skipbit_S <= '1' when (pulse1_skipped_S='1') or (pulse1_skipped='1') else '0'; \r
+pulse2_skipbit_S <= '1' when (pulse2_skipped_S='1') or (pulse2_skipped='1') else '0'; \r
+\r
+data_out_write <= '1' when\r
+ ((writeindex_S=0) and (data_out_almostfull='0') and (data_out_allowed='1') and ((pulse1_write='1') or (pulse2_write='1'))) or\r
+ ((writeindex_S=1) or (writeindex_S=2))\r
+ else '0';\r
+ \r
+process(clock)\r
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ select2b_S <= '0';\r
+ writeindex_S <= 0;\r
+ else\r
+ if (writeindex_S=0) then\r
+ if (data_out_almostfull='0') and (data_out_allowed='1') then\r
+ if pulse1_write='1' then\r
+ select2b_S <= '0';\r
+ writeindex_S <= 1;\r
+ elsif pulse2_write='1' then\r
+ select2b_S <= '1';\r
+ writeindex_S <= 1;\r
+ end if;\r
+ end if;\r
+ elsif writeindex_S=1 then\r
+ writeindex_S <= 2;\r
+ else\r
+ writeindex_S <= 0;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;
+\r
+\r
+process(clock)\r
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ pulse1_skipped_S <= '0';\r
+ else\r
+ if (pulse1_write='1') and \r
+ ((data_out_almostfull='1') or (data_out_allowed='0') or (writeindex_S/=0)) then\r
+ pulse1_skipped_S <= '1';\r
+ elsif writeindex_S=2 then\r
+ pulse1_skipped_S <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+process(clock)\r
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ pulse2_skipped_S <= '0';\r
+ else\r
+ if (pulse2_write='1') and \r
+ ((data_out_almostfull='1') or (data_out_allowed='0') or (writeindex_S/=0)) then\r
+ pulse2_skipped_S <= '1';\r
+ elsif writeindex_S=2 then\r
+ pulse2_skipped_S <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_pulse_and_pileup_waveforms
+-- Description: Multiple adc inputs with output stream for pulse-waveforms and pileup-waveforms, dual gain version
+-- Modifications:
+-- 08-09-2014 Part of Constant Fraction calculation moved to input module (before mux)
+-- 22-09-2014 single clock
+-- 23-09-2014 sort pileup waveforms
+-- 10-10-2014 Integral as measurement for the energy instead of maximum
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+library work;\r
+USE work.panda_package.all;\r
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_pulse_and_pileup_waveforms\r
+-- Multiple adc inputs with output stream for pulse-waveforms and pileup-waveforms.\r
+-- on each input pulses are detected and the waveform is put in a buffer.\r
+-- A timestamp is added, based on maximum signal in waveform.\r
+-- From each high-gain and low-gain input pair only one waveform at the same time is choosen and passed on.\r
+-- The waveform are distinguish for single pulse and pileup waveforms.\r
+-- The single pulse waveforms are sorted, based on timestamp, and multiplexed to one stream.\r
+-- The pileup waveforms multiplexed to one stream (unsorted).\r
+-- The parameters are organised in registers A,B,C,D :\r
+-- board_register A: write\r
+-- register_A(7..0) = threshold High
+-- register_A(15..8) = threshold Low
+-- register_A(16) = disable High
+-- register_A(17) = disable Low
+-- register_A(23..18) = I/Max discard
+-- register_A(29..24) = I/Max pileup
+-- board_register B: write
+-- register_B(7..0) = minimum pulselength
+-- register_B(15..8) = pileup length
+-- register_B(23..16) = maximum wavelength
+-- register_B(24) = fullsize High
+-- register_B(25) = fullsize Low
+-- register_B(29..26) = CF delay\r
+--\r
+--\r
+-- generics\r
+-- NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
+-- ADCBITS : number of ADC-bits
+-- BWBITS : number of bits for the baseline IIR filter bandwidth
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size\r
+-- IDIVMAXBITS : number of bits for maximum to integral ratio check
+-- INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+-- CF_DELAYBITS : number of bits for the Constant Fraction delay
+-- \r
+-- inputs\r
+-- clock : clock\r
+-- reset : synchrounous reset\r
+-- superburstnumber : actual superburstnumber\r
+-- timestampcounter : timestampcounter within superburst\r
+-- ADCdata : array with ADC data for each input\r
+-- enable_data : enable adc data\r
+-- slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
+-- slowcontrol_byte_write : write signal for the slowcontrol commands
+-- slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
+-- pulsedata_read : read signal for data with resulting single pulse waveforms\r
+-- pileupdata_read : read signal for data with resulting pileup waveforms\r
+-- \r
+-- outputs\r
+-- pulsedata_out : 36 bits output data with resulting single pulse waveforms:\r
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- pulsedata_available : output single pulse data is available\r
+-- pulsedata_inpipe : more single pulse data on its way
+-- pileupdata_out : 36-bits output data with resulting pileup waveforms:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..16) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- pileupdata_available : output pileup data is available
+-- pileupdata_inpipe : more pileup data on its way
+-- pulsedetect : pulse detected for each of the ADC channels
+-- overflow : overflow in data from one of the channels: data is lost\r
+--\r
+-- components\r
+-- FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair\r
+-- FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp\r
+-- FEE_sorting_wavemux : sorted multiplexer for waveform data\r
+-- FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
+--\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_pulse_and_pileup_waveforms is\r
+ generic (
+ NROFADCS : natural := 16;
+ ADCBITS : natural := 14;
+ BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3;
+ CF_DELAYBITS : natural := 8
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ timestampcounter : in std_logic_vector(15 downto 0); \r
+ ADCdata : in array_adc_type;
+ enable_data : in std_logic;
+ slowcontrol_byte_data : in std_logic_vector (7 downto 0);
+ slowcontrol_byte_write : in std_logic;
+ slowcontrol_byte_request: in std_logic;
+ pulsedata_out : out std_logic_vector(35 downto 0);
+ pulsedata_read : in std_logic;
+ pulsedata_available : out std_logic;
+ pulsedata_inpipe : out std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_read : in std_logic;
+ pileupdata_available : out std_logic;\r
+ pileupdata_inpipe : out std_logic;
+ pulsedetect : out std_logic_vector(0 to NROFADCS-1);
+ overflow : out std_logic;\r
+ testindex : in integer range 0 to NROFADCS/2-1;\r
+ testword0 : out std_logic_vector(35 downto 0);\r
+ testword1 : out std_logic_vector(35 downto 0);\r
+ testword2 : out std_logic_vector(35 downto 0)\r
+ );\r
+end FEE_pulse_and_pileup_waveforms;\r
+\r
+architecture Behavioral of FEE_pulse_and_pileup_waveforms is\r
+\r
+component FEE_dual_pulse_waveform is\r
+ generic (
+ ADCBITS : natural := ADCBITS;
+ BWBITS : natural := BWBITS;
+ WAVEFORMBUFFERSIZE : natural := WAVEFORMBUFFERSIZE;
+ IDIVMAXBITS : natural := IDIVMAXBITS;
+ INTEGRALRATIOBITS : natural := INTEGRALRATIOBITS;
+ CF_DELAYBITS : natural := CF_DELAYBITS
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ adcnumber : in std_logic_vector(7 downto 0); \r
+ cf_delay : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+ superburstnumber : in std_logic_vector(30 downto 0); \r
+ timestampcounter : in std_logic_vector(15 downto 0); \r
+ ADCdata_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ ADCdata_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_highgain : in std_logic_vector((ADCBITS-1) downto 0);
+ threshold_lowgain : in std_logic_vector((ADCBITS-1) downto 0);
+ enable_highgain : in std_logic;
+ enable_lowgain : in std_logic;
+ IIRfilterBW : in std_logic_vector(2 downto 0);
+ maxabovebaseline : in std_logic_vector(3 downto 0);
+ minpulselength : in std_logic_vector(7 downto 0);\r
+ pileuplength : in std_logic_vector(7 downto 0);\r
+ maxwavelength : in std_logic_vector(7 downto 0);\r
+ IdivMAX_discard : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ IdivMAX_pileup : in std_logic_vector(IDIVMAXBITS-1 downto 0);\r
+ fullsize_wave_highgain : in std_logic;\r
+ fullsize_wave_lowgain : in std_logic;\r
+ ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
+ ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);\r
+ pulsedata_allowed : in std_logic;\r
+ pulsedata_almostfull : in std_logic;
+ pulsedata_write : out std_logic;\r
+ pulsedata_out : out std_logic_vector(35 downto 0);\r
+ pileupdata_allowed : in std_logic;\r
+ pileupdata_almostfull : in std_logic;
+ pileupdata_write : out std_logic;\r
+ pileupdata_out : out std_logic_vector(35 downto 0);\r
+ pulsedetect : out std_logic;
+ overflow : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0);\r
+ testword1 : out std_logic_vector(35 downto 0);\r
+ testword2 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;\r
+\r
+component FEE_sorting_mux is
+ generic(
+ NROFMUXINPUTS : natural := NROFADCS/2
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );
+end component;\r
+\r
+
+component FEE_sorting_wavemux is\r
+ generic(\r
+ NROFMUXINPUTS : natural := NROFADCS/2\r
+ );\r
+ Port ( \r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ data_in : in array_halfadc36bits_type;\r
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);\r
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_read : in std_logic;\r
+ data_out_available : out std_logic;\r
+ data_out_inpipe : out std_logic;
+ error : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );\r
+end component;\r
+\r
+component FEE_slowcontrol_receive_from_cpu is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(7 downto 0);
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ register_A : out std_logic_vector (31 downto 0);
+ register_B : out std_logic_vector (31 downto 0)
+ );
+end component;
+\r
+constant zeros : std_logic_vector(0 to NROFADCS/2-1) := (others => '0');\r
+signal ADCdata_S : array_adc_type;
+signal enable_high_S : std_logic_vector(0 to NROFADCS/2-1);
+signal enable_low_S : std_logic_vector(0 to NROFADCS/2-1);
+signal adcnumber_S : array_halfadc8bits_type;\r
+signal pulsedata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pulsedata_write_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pulsedata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pulsedata_out_S : array_halfadc36bits_type;\r
+signal pulsedata_inpipe_S : std_logic;\r
+signal pileupdata_allowed_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pileupdata_write_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pileupdata_almostfull_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pileupdata_out_S : array_halfadc36bits_type;\r
+signal overflow_S : std_logic_vector(0 to NROFADCS/2-1);\r
+signal pulsedata_available_S : std_logic;\r
+signal pileupdata_available_S : std_logic;\r
+signal pileupdata_inpipe_S : std_logic;\r
+\r
+signal pulsedetect_S : std_logic_vector(0 to NROFADCS-1);
+signal pileupdata_output_S : std_logic_vector(35 downto 0);\r
+\r
+signal register_A_S : array_halfadc32bits_type := (others => (others => '0'));
+signal register_B_S : array_halfadc32bits_type := (others => (others => '0'));
+\r
+signal dataerrors_S : std_logic_vector(0 to NROFADCS/2-1);\r
+\r
+signal testword0_S : array_halfadc36bits_type;\r
+signal testword1_S : array_halfadc36bits_type;\r
+signal testword2_S : array_halfadc36bits_type;\r
+\r
+\r
+begin\r
+\r
+\r
+ waves : for index in 0 to NROFADCS/2-1 generate\r
+ \r
+ FEE_slowcontrol_receive_from_cpu_all: FEE_slowcontrol_receive_from_cpu port map(
+ clock => clock,
+ reset => reset,
+ address => conv_std_logic_vector(index*2,8),
+ byte_data => slowcontrol_byte_data,
+ byte_write => slowcontrol_byte_write,
+ byte_request => slowcontrol_byte_request,
+ register_A => register_A_S(index),
+ register_B => register_B_S(index));
+\r
+ adcnumber_S(index) <= conv_std_logic_vector(index*2,8);\r
+ process(clock)
+ begin
+ if (rising_edge(clock)) then \r
+ enable_high_S(index) <= not register_A_S(index)(16);
+ enable_low_S(index) <= not register_A_S(index)(17);
+ end if;
+ end process; \r
+ ADCdata_S(index*2) <= ADCdata(index*2);-- when enable_high_S(index)='1' else (others => '0');\r
+ ADCdata_S(index*2+1) <= ADCdata(index*2+1);-- when enable_low_S(index)='1' else (others => '0');\r
+ \r
+ FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform port map(\r
+ clock => clock,
+ reset => reset,
+ enable => enable_data,\r
+ adcnumber => adcnumber_S(index),\r
+ cf_delay => register_B_S(index)(29 downto 26),
+ superburstnumber => superburstnumber,\r
+ timestampcounter => timestampcounter,\r
+ ADCdata_highgain => ADCdata_S(index*2),
+ ADCdata_lowgain => ADCdata_S(index*2+1),\r
+ threshold_highgain(7 downto 0) => register_A_S(index)(7 downto 0),
+ threshold_highgain((ADCBITS-1) downto 8) => (others => '0'),
+ threshold_lowgain(7 downto 0) => register_A_S(index)(15 downto 8),
+ threshold_lowgain((ADCBITS-1) downto 8) => (others => '0'),
+ enable_highgain => enable_high_S(index),
+ enable_lowgain => enable_low_S(index),
+ IIRfilterBW => (others => '0'),
+ maxabovebaseline => "1010",
+ minpulselength => register_B_S(index)(7 downto 0),\r
+ pileuplength => register_B_S(index)(15 downto 8),\r
+ maxwavelength => register_B_S(index)(23 downto 16),\r
+ IdivMAX_discard => register_A_S(index)(IDIVMAXBITS+17 downto 18),\r
+ IdivMAX_pileup => register_A_S(index)(IDIVMAXBITS+23 downto 24),\r
+ fullsize_wave_highgain => register_B_S(index)(24),\r
+ fullsize_wave_lowgain => register_B_S(index)(25),\r
+ ADC_minus_baseline_highgain => open, -- testword0_S(idx)(14 downto 0),
+ ADC_minus_baseline_lowgain => open, -- testword0_S(idx)(30 downto 16),\r
+ pulsedata_allowed => pulsedata_allowed_S(index),\r
+ pulsedata_almostfull => pulsedata_almostfull_S(index),
+ pulsedata_write => pulsedata_write_S(index),\r
+ pulsedata_out => pulsedata_out_S(index),\r
+ pileupdata_allowed => pileupdata_allowed_S(index),\r
+ pileupdata_almostfull => pileupdata_almostfull_S(index),
+ pileupdata_write => pileupdata_write_S(index),\r
+ pileupdata_out => pileupdata_out_S(index),\r
+ pulsedetect => pulsedetect_S(index),
+ overflow => overflow_S(index),\r
+ testword0 => testword0_S(index),\r
+ testword1 => testword1_S(index),\r
+ testword2 => testword2_S(index));\r
+\r
+process(clock)\r
+type array_halfadc4bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(3 downto 0);\r
+variable prev_data_V : array_halfadc4bits_type;
+begin
+ if rising_edge(clock) then\r
+ dataerrors_S(index) <= '0';\r
+ if pileupdata_write_S(index)='1' then\r
+ case pileupdata_out_S(index)(35 downto 32) is\r
+ when "0000" =>\r
+ if (prev_data_V(index)/="0100") and (prev_data_V(index)/="0101") then\r
+ dataerrors_S(index) <= '1';\r
+ end if;\r
+ when "0001" =>\r
+ if (prev_data_V(index)/="0000") then\r
+ dataerrors_S(index) <= '1';\r
+ end if;\r
+ when "0010" =>\r
+ if (prev_data_V(index)/="0001") and (prev_data_V(index)/="0010") then\r
+ dataerrors_S(index) <= '1';\r
+ end if;\r
+ when "0100" =>\r
+ if (prev_data_V(index)/="0010") then\r
+ dataerrors_S(index) <= '1';\r
+ end if;\r
+ when "0101" =>\r
+ if (prev_data_V(index)/="0010") then\r
+ dataerrors_S(index) <= '1';\r
+ end if;\r
+ when others =>\r
+ dataerrors_S(index) <= '1';\r
+ end case;\r
+ prev_data_V(index) := pileupdata_out_S(index)(35 downto 32);\r
+ end if;\r
+ end if;
+end process;\r
+\r
+ end generate;\r
+overflow <= '1' when overflow_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';\r
+pulsedetect_S(NROFADCS/2 to NROFADCS-1) <= (others => '0');\r
+pulsedetect <= pulsedetect_S;\r
+\r
+FEE_sorting_mux1: FEE_sorting_mux port map(
+ clock => clock,
+ reset => reset,
+ data_in => pulsedata_out_S,
+ data_in_write => pulsedata_write_S,
+ data_in_allowed => pulsedata_allowed_S,
+ data_in_almostfull => pulsedata_almostfull_S,
+ data_out => pulsedata_out,
+ data_out_read => pulsedata_read,
+ data_out_available => pulsedata_available_S,
+ data_out_inpipe => pulsedata_inpipe_S,
+ error => open,\r
+ testword0 => open,
+ testword1 => open);\r
+pulsedata_available <= pulsedata_available_S;
+pulsedata_inpipe <= pulsedata_inpipe_S;\r
+\r
+-- FEE_sorting_wavemux_pileup: FEE_sorting_wavemux port map(\r
+FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
+ clock => clock,
+ reset => reset,
+ data_in => pileupdata_out_S,
+ data_in_write => pileupdata_write_S,
+ data_in_allowed => pileupdata_allowed_S,
+ data_in_almostfull => pileupdata_almostfull_S,
+ data_out => pileupdata_output_S,
+ data_out_read => pileupdata_read,
+ data_out_available => pileupdata_available_S,
+ data_out_inpipe => pileupdata_inpipe_S,
+ error => open,\r
+ testword0 => open,
+ testword1 => open);\r
+pileupdata_available <= pileupdata_available_S;
+pileupdata_out <= pileupdata_output_S;\r
+pileupdata_inpipe <= pileupdata_inpipe_S;\r
+\r
+\r
+\r
+--process(clock)
+--type array_16_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
+--type array_8_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
+--variable l1 : line;
+--variable l2 : line;
+--variable c : std_logic_vector(63 downto 0) := x"0000000000000000";
+--variable pulse_time_V : array_16_type;
+--variable pulse_sb_V : array_16_type;
+--variable pulse_energy_V : array_16_type;
+--variable pulse_chan_V : array_8_type;
+--variable wave_time_V : array_16_type;
+--variable wave_sb_V : array_16_type;
+--variable wave_chan_V : array_8_type;
+--file file0: text;
+--file file1: text;
+--begin
+-- if rising_edge(clock) then
+-- if c=x"0000000000000000" then
+-- file_open(file0,"D:\data\Panda\pulses.txt",WRITE_MODE);
+-- file_open(file1,"D:\data\Panda\waves.txt",WRITE_MODE);
+-- end if;
+-- c := c+1;\r
+-- for i in 0 to NROFADCS/2-1 loop\r
+-- if pulsedata_write_S(i)='1' then\r
+-- if pulsedata_out_S(i)(35 downto 34)="00" then\r
+-- pulse_sb_V(i) := pulsedata_out_S(i)(31 downto 16);\r
+-- pulse_time_V(i) := pulsedata_out_S(i)(15 downto 0);\r
+-- elsif pulsedata_out_S(i)(35 downto 34)="01" then\r
+-- pulse_chan_V(i) := pulsedata_out_S(i)(23 downto 16);\r
+-- pulse_energy_V(i) := pulsedata_out_S(i)(15 downto 0);\r
+-- hwrite(l1,c,right,16);
+-- write(l1," ");
+-- hwrite(l1,pulse_sb_V(i),right,4);
+-- write(l1," ");
+-- hwrite(l1,pulse_time_V(i),right,4);
+-- write(l1," ");
+-- hwrite(l1,pulse_chan_V(i),right,2);
+-- write(l1," ");
+-- hwrite(l1,pulse_energy_V(i),right,4);
+-- writeline(file0,l1);
+-- end if;\r
+-- end if;\r
+-- if pileupdata_write_S(i)='1' then\r
+-- if pileupdata_out_S(i)(35 downto 32) ="0000" then\r
+-- wave_sb_V(i) := pileupdata_out_S(i)(31 downto 16);\r
+-- wave_time_V(i) := pileupdata_out_S(i)(15 downto 0);\r
+-- elsif pileupdata_out_S(i)(35 downto 32) ="0001" then\r
+-- wave_chan_V(i) := pileupdata_out_S(i)(7 downto 0);\r
+-- hwrite(l2,c,right,16);
+-- write(l2," ");
+-- hwrite(l2,wave_sb_V(i),right,4);
+-- write(l2," ");
+-- hwrite(l2,wave_time_V(i),right,4);
+-- write(l2," ");
+-- hwrite(l2,wave_chan_V(i),right,2);
+-- writeline(file1,l2); \r
+-- end if;\r
+-- end if;
+-- end loop;\r
+-- end if;
+--end process;\r
+\r
+\r
+\r
+testword0(33 downto 0) <= testword0_S(testindex)(33 downto 0);\r
+testword0(35) <= testword0_S(testindex)(35);\r
+testword0(34) <= '1' when \r
+ (testword0_S(0)(35)='1') or\r
+ (testword0_S(1)(35)='1') or\r
+ (testword0_S(2)(35)='1') or\r
+ (testword0_S(3)(35)='1') or\r
+ (testword0_S(4)(35)='1') or\r
+ (testword0_S(5)(35)='1') or\r
+ (testword0_S(6)(35)='1') or\r
+ (testword0_S(7)(35)='1') or\r
+ (testword0_S(8)(35)='1') or\r
+ (testword0_S(9)(35)='1') or\r
+ (testword0_S(10)(35)='1') or\r
+ (testword0_S(11)(35)='1') or\r
+ (testword0_S(12)(35)='1') or\r
+ (testword0_S(13)(35)='1') or\r
+ (testword0_S(14)(35)='1') or\r
+ (testword0_S(15)(35)='1') else '0';\r
+\r
+\r
+\r
+\r
+testword1(15 downto 0) <= testword1_S(0)(15 downto 0);\r
+testword1(31 downto 16) <= dataerrors_S;\r
+testword1(32) <= '1' when dataerrors_S/=x"0000";\r
+testword1(35) <= testword0_S(testindex)(28);\r
+testword1(34) <= '1' when \r
+ (testword0_S(0)(35)='1') or\r
+ (testword0_S(1)(35)='1') or\r
+ (testword0_S(2)(35)='1') or\r
+ (testword0_S(3)(35)='1') or\r
+ (testword0_S(4)(35)='1') or\r
+ (testword0_S(5)(35)='1') or\r
+ (testword0_S(6)(35)='1') or\r
+ (testword0_S(7)(35)='1') or\r
+ (testword0_S(8)(35)='1') or\r
+ (testword0_S(9)(35)='1') or\r
+ (testword0_S(10)(35)='1') or\r
+ (testword0_S(11)(35)='1') or\r
+ (testword0_S(12)(35)='1') or\r
+ (testword0_S(13)(35)='1') or\r
+ (testword0_S(14)(35)='1') or\r
+ (testword0_S(15)(35)='1') else '0';\r
+ \r
+testword2(33 downto 0) <= testword2_S(testindex)(33 downto 0);\r
+testword2(35) <= testword0_S(testindex)(35);\r
+testword2(34) <= testword0_S(testindex)(28);\r
+--testword2(34) <= '1' when \r
+-- (testword0_S(0)(35)='1') or\r
+-- (testword0_S(1)(35)='1') or\r
+-- (testword0_S(2)(35)='1') or\r
+-- (testword0_S(3)(35)='1') or\r
+-- (testword0_S(4)(35)='1') or\r
+-- (testword0_S(5)(35)='1') or\r
+-- (testword0_S(6)(35)='1') or\r
+-- (testword0_S(7)(35)='1') or\r
+-- (testword0_S(8)(35)='1') or\r
+-- (testword0_S(9)(35)='1') or\r
+-- (testword0_S(10)(35)='1') or\r
+-- (testword0_S(11)(35)='1') or\r
+-- (testword0_S(12)(35)='1') or\r
+-- (testword0_S(13)(35)='1') or\r
+-- (testword0_S(14)(35)='1') or\r
+-- (testword0_S(15)(35)='1') else '0';\r
+\r
+ \r
+ \r
+end Behavioral;\r
+\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 31-01-2012
+-- Module Name: FEE_pulsewaveform_buffer
+-- Description: Buffers pulse waveforms
+-- Modifications:
+-- 08-09-2014 Removed waveform output in case of pulse detection
+-- 16-09-2014 name changed from pulsewaveform_buffer to FEE_pulsewaveform_buffer
+-- 10-10-2014 separated input for superburst
+-- 23-10-2014 space enough signal more accurate
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulsewaveform_buffer
+-- Buffers adc waveforms.
+-- Memory is configured as ring buffer: samples are written into this buffer when a pulse is being detected.
+-- Also, a timestamp is written into the memory.
+-- Data can be read when at least one waveform is written.
+--
+--
+-- generics
+-- ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
+-- WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- pulse_valid : input data is valid pulse data
+-- pulse_rising : the pulse has not yet reached its maximum
+-- pulse_detected : previous samples are regarded as valid pulse data
+-- pileup_detected : previous samples are regarded as pileup waveform data
+-- clear_waveform : previous samples do not give valid data, clear this data
+-- data_in : input data: adc values minus baseline: signed data
+-- superburst : superburst at the starting of the waveform
+-- timestamp : timestamp (within the superburst) at the starting of the waveform
+-- data_out_read : read data from the buffer memory
+--
+-- outputs
+-- data_out : data from the buffer memory
+-- bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform (combination superburst and clockcounter)
+-- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
+-- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
+-- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
+-- bits(35..32)="1111" : error, bits(31..0)=don't care
+-- data_out_available : data available from the buffer memory\r
+-- overflow : buffer overrun\r
+--
+--
+-- components
+-- blockmem : buffer memory, dual ported ram
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulsewaveform_buffer is
+ generic (
+ ADCBITS : natural := 14;
+ WAVEFORMBUFFERSIZE : natural := 10
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ pulse_valid : in std_logic;
+ pulse_rising : in std_logic;
+ pulse_detected : in std_logic;
+ pileup_detected : in std_logic;
+ clear_waveform : in std_logic;
+ data_in : in std_logic_vector(ADCBITS downto 0); -- signed data
+ superburst : in std_logic_vector(15 downto 0);
+ timestamp : in std_logic_vector(15 downto 0);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ overflow : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_pulsewaveform_buffer;
+
+architecture Behavioral of FEE_pulsewaveform_buffer is
+
+component blockmem is
+ generic (
+ ADDRESS_BITS : natural := WAVEFORMBUFFERSIZE;
+ DATA_BITS : natural := 36
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)
+ );
+end component;
+constant zeros : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal data_in_S : std_logic_vector(15 downto 0) := (others => '0');
+signal sample0_S : std_logic_vector(15 downto 0) := (others => '0');
+signal write_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := zeros(WAVEFORMBUFFERSIZE-1 downto 2) & "10";
+-- signal write_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := "00000010";
+signal write_enable_S : std_logic := '0';
+signal write_data_S : std_logic_vector(35 downto 0) := (others => '0');
+
+signal wavestart_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal nextstart_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+
+signal read_address_S : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+signal read_data_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_available_S : std_logic := '0';
+signal pileup_detected_S : std_logic := '0';
+signal pulse_rising_S : std_logic := '0';\r
+signal prev_pulse_valid_S : std_logic := '0';\r
+
+signal lastsample_even_S : std_logic := '0';
+signal space_enough_S : std_logic := '0';
+
+
+type writemode_type is (ACQUIRE_EVEN,ACQUIRE_ODD,TIMESTAMP0,SKIPPULSE);
+signal writemode_S : writemode_type := ACQUIRE_EVEN;
+
+
+begin\r
+\r
+overflow <= '1' when writemode_S=SKIPPULSE else '0';\r
+
+space_enough_S <= '1' when \r
+ (((conv_integer(unsigned(nextstart_address_S)))<(conv_integer(unsigned(read_address_S))))\r
+ and ((conv_integer(unsigned(nextstart_address_S))+130)<(conv_integer(unsigned(read_address_S))))) or \r
+ (((conv_integer(unsigned(nextstart_address_S)))>(conv_integer(unsigned(read_address_S))))\r
+ and ((conv_integer(unsigned(nextstart_address_S))+130)<(conv_integer(unsigned(read_address_S))+2**WAVEFORMBUFFERSIZE))) or\r
+ ((conv_integer(unsigned(nextstart_address_S)))=(conv_integer(unsigned(read_address_S))))\r
+ else '0';\r
+\r
+process(clock)
+begin\r
+ if rising_edge(clock) then
+ data_in_S(ADCBITS downto 0) <= data_in;
+ -- data_in_S(15 downto ADCBITS+1) <= (others => '0');
+ data_in_S(15) <= data_in_S(14);
+ pulse_rising_S <= pulse_rising;\r
+ end if;\r
+end process;
+
+blockmem1: blockmem port map(
+ clock => clock,
+ write_enable => write_enable_S,
+ write_address => write_address_S,
+ data_in => write_data_S,
+ read_address => read_address_S,
+ data_out => read_data_S);
+data_out <= read_data_S;
+
+write_data_S <= \r
+ "1000" & superburst & timestamp when ((writemode_S=TIMESTAMP0) and (pileup_detected_S='1')) else
+ "0100" & data_in_S & x"0000" when ((pileup_detected='1') and (writemode_S=ACQUIRE_EVEN)) else
+ "0101" & sample0_S & data_in_S when ((pileup_detected='1') and (writemode_S=ACQUIRE_ODD)) else
+ "0010" & sample0_S & data_in_S when ((pulse_valid='1') and (writemode_S=ACQUIRE_ODD)) else
+ (others => '1');\r
+
+
+write_enable_S <= '1'
+ when ((pulse_valid='1') and (writemode_S=ACQUIRE_ODD))
+ or ((writemode_S=ACQUIRE_EVEN) and (pileup_detected='1'))
+ or ((writemode_S=ACQUIRE_ODD) and (pileup_detected='1'))
+ or (writemode_S=TIMESTAMP0)
+ else '0';
+
+writeprocess: process(clock)
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then
+ write_address_S <= conv_std_logic_vector(2,WAVEFORMBUFFERSIZE);
+ wavestart_address_S <= (others => '0');
+ nextstart_address_S <= (others => '0');
+ pileup_detected_S <= '0';
+ lastsample_even_S <= '0';\r
+ writemode_S <= ACQUIRE_EVEN;
+ else\r
+ prev_pulse_valid_S <= pulse_valid;
+ case writemode_S is
+ when ACQUIRE_EVEN =>\r
+ if (pileup_detected='1') then
+ pileup_detected_S <= '1';
+ write_address_S <= wavestart_address_S; -- for timestamp
+ nextstart_address_S <= write_address_S+1;\r
+ lastsample_even_S <= '1';
+ writemode_S <= TIMESTAMP0;
+ elsif (clear_waveform='1') or (pulse_detected='1') then
+ write_address_S <= wavestart_address_S+1;
+ pileup_detected_S <= '0';
+ else
+ if pulse_valid='1' then\r
+ if (space_enough_S='1') or (prev_pulse_valid_S='1') then\r
+ sample0_S <= data_in_S;
+ writemode_S <= ACQUIRE_ODD;\r
+ else\r
+ writemode_S <= SKIPPULSE;\r
+ end if;\r
+ else
+ write_address_S <= wavestart_address_S+1; -- restart
+ end if;
+ pileup_detected_S <= '0';
+ end if;
+ when ACQUIRE_ODD =>\r
+ if (pileup_detected='1') then
+ pileup_detected_S <= '1';
+ write_address_S <= wavestart_address_S; -- for timestamp
+ nextstart_address_S <= write_address_S+1;
+ lastsample_even_S <= '0';
+ writemode_S <= TIMESTAMP0;
+ elsif (clear_waveform='1') or (pulse_detected='1') then
+ write_address_S <= wavestart_address_S+1;
+ pileup_detected_S <= '0';
+ else
+ if pulse_valid='1' then\r
+ writemode_S <= ACQUIRE_EVEN;
+ write_address_S <= write_address_S+1;
+ else
+ write_address_S <= wavestart_address_S+1; -- restart
+ writemode_S <= ACQUIRE_EVEN;
+ end if;
+ pileup_detected_S <= '0';
+ end if;
+ when TIMESTAMP0 =>
+ write_address_S <= nextstart_address_S+1;
+ wavestart_address_S <= nextstart_address_S;
+ if pulse_valid='1' then\r
+ if space_enough_S='1' then\r
+ sample0_S <= data_in_S;
+ writemode_S <= ACQUIRE_ODD;\r
+ else\r
+ writemode_S <= SKIPPULSE;\r
+ end if;\r
+ else\r
+ writemode_S <= ACQUIRE_EVEN;\r
+ end if;
+ when SKIPPULSE =>\r
+ if pulse_valid='0' then\r
+ writemode_S <= ACQUIRE_EVEN;\r
+ end if;\r
+ when others =>
+ writemode_S <= ACQUIRE_EVEN;
+ end case;
+ end if;
+ end if;
+end process;
+
+data_out_available_S <= '1'
+ when wavestart_address_S/=read_address_S
+ else '0';
+data_out_available <= data_out_available_S;
+
+readprocess: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ read_address_S <= (others => '0');
+ else
+ if (data_out_read='1') and (data_out_available_S='1') then
+ read_address_S <= read_address_S+1;
+ end if;
+ end if;
+ end if;
+end process;
+\r
+\r
+
+testword0(1 downto 0) <=
+ "00" when (writemode_S=ACQUIRE_EVEN) else
+ "01" when (writemode_S=ACQUIRE_ODD) else
+ "10" when (writemode_S=TIMESTAMP0) else
+ "11" when (writemode_S=SKIPPULSE) else
+ "11";
+
+testword0(2) <= space_enough_S;\r
+testword0(3) <= pulse_valid;
+testword0(4) <= pulse_detected;
+testword0(5) <= pileup_detected;
+testword0(6) <= clear_waveform;\r
+testword0(7) <= write_enable_S;\r
+testword0(15 downto 8) <= write_address_S(7 downto 0);
+testword0(19 downto 16) <= write_data_S(35 downto 32);
+\r
+\r
+testword0(27 downto 20) <= read_address_S(7 downto 0);
+testword0(31 downto 28) <= read_data_S(35 downto 32);
+testword0(32) <= data_out_read;\r
+testword0(33) <= data_out_available_S;\r
+testword0(34) <= '0';\r
+\r
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Michel Hevinga / Peter Schakel
+-- Create Date: 2010
+-- Module Name: FEE_rxBitLock
+-- Description: Module to lock receiving clock of GTP/GTX at the right phase\r
+-- Modifications:
+-- 18-11-2014 8 bits data instead of 16 bits
+-- 19-11-2014 name changed from rxBitLock to FEE_rxBitLock
+----------------------------------------------------------------------------------\r
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+--use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+\r
+----------------------------------------------------------------------------------
+-- FEE_rxBitLock
+-- Module to lock receiving clock of GTP/GTX at the right phase.\r
+-- First is checked if the resetDone input is high, (resetting is done)\r
+-- then if lossOfSync is low ('0'), (GTP/GTX loss of sync signal)\r
+-- If all these checks are allright the fmstatus will show that the GTP/GTX is locked on th incomming data.\r
+-- If one of these checks are not reached within a certain time (TIME_OUT_SYNC_MAX constant)\r
+-- the rxReset output is activated and checking is started again.\r
+-- Also, the lossOfSync is always checked during operation.\r
+--\r
+-- Library\r
+--\r
+-- Generics:\r
+--
+-- Inputs:
+-- clk : recovered clock from the GTP/GTX\r
+-- reset : reset\r
+-- resetDone : Reset is done, ready to check lock & synchronisation\r
+-- lossOfSync : Loss of Sync: "00" means synchronised\r
+-- rxPllLocked : Receiver PLL locked, not used at the moment\r
+--
+-- Outputs:\r
+-- rxReset : Reset GTP/GTX to try another lock\r
+-- fsmStatus : Status of the state machine:\r
+-- 00 : WAIT_RESET_DONE : waiting until ResetDone\r
+-- 01 : WAIT_TIME_OUT_SYNC : waiting for word aligned\r
+-- 10 : CHECK_LOSS_SYNC : running state : keep on checking for Loss of sync and bytes swapped\r
+-- 11 : RX_RESET : resetting for a new lock attempt\r
+-- \r
+-- Components:\r
+--
+----------------------------------------------------------------------------------
+entity FEE_rxBitLock is
+ port (\r
+ clk : in std_logic;
+ reset : in std_logic;
+ resetDone : in std_logic;
+ lossOfSync : in std_logic;\r
+ rxPllLocked : in std_logic;
+ rxReset : out std_logic;
+ fsmStatus : out std_logic_vector (1 downto 0));
+end FEE_rxBitLock;
+
+architecture Behavioral of FEE_rxBitLock is
+
+constant TIME_OUT_SYNC_MAX : integer range 0 to 500 := 500;
+
+signal rxReset_S : std_logic :='0';
+signal fsmStatus_S : std_logic_vector (1 downto 0) :="00";
+signal timeOutSynFlag_S : std_logic :='0';\r
+signal timeOutSyncCounter_I : integer range 0 to TIME_OUT_SYNC_MAX :=0;
+
+signal resettimeFlag_S : std_logic :='0'; -- counter & flag for reset extender
+signal resettimeCounter_I : integer range 0 to 15 :=0; -- counter & flag for reset extender
+
+
+type state_T is (WAIT_RESET_DONE, WAIT_TIME_OUT_SYNC, CHECK_LOSS_SYNC, RX_RESET);
+signal currentState_S,nextState_S : state_T := WAIT_RESET_DONE; \r
+
+begin
+
+rxReset <= rxReset_S;
+fsmStatus <= fsmStatus_S;\r
+
+fsmClk: process(clk, reset)
+begin
+ if (reset = '1')then
+ currentState_S <= RX_RESET;
+ else
+ if rising_edge(clk) then
+ currentState_S <= nextState_S;
+ end if;
+ end if;
+end process;
+
+fsmInput: process (currentState_S,resetDone, timeOutSynFlag_S, \r
+ lossOfSync, rxPllLocked, timeOutSynFlag_S, resettimeFlag_S)
+begin
+ case currentState_S is
+ when WAIT_RESET_DONE => if(resetDone = '1') then
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ else
+ nextState_S <= WAIT_RESET_DONE;
+ end if;
+ when WAIT_TIME_OUT_SYNC => if (timeOutSynFlag_S = '1') then
+ nextState_S <= RX_RESET;
+ else
+ if (lossOfSync = '0') then
+ nextState_S <= CHECK_LOSS_SYNC;
+ else
+ nextState_S <= WAIT_TIME_OUT_SYNC;
+ end if;
+ end if;
+ when CHECK_LOSS_SYNC => if (lossOfSync /= '0') then
+ nextState_S <= RX_RESET;
+ else
+ nextState_S <= CHECK_LOSS_SYNC;
+ end if;\r
+ when RX_RESET => if (resettimeFlag_S = '1') then -- reset long to prevent that resetDone signal is missed
+ nextState_S <= WAIT_RESET_DONE;
+ else
+ nextState_S <= RX_RESET;
+ end if;
+ when others => nextState_S <= RX_RESET;
+ end case;
+end process;
+
+fsmOutput: process (clk)
+begin
+if rising_edge(clk) then
+ case currentState_S is
+ when WAIT_RESET_DONE => fsmStatus_S <= "00";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ when WAIT_TIME_OUT_SYNC => fsmStatus_S <= "01";
+ rxReset_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+ if (timeOutSyncCounter_I < TIME_OUT_SYNC_MAX) then
+ timeOutSyncCounter_I <= timeOutSyncCounter_I+1;
+ timeOutSynFlag_S <= '0';
+ else
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '1';
+ end if;
+ when CHECK_LOSS_SYNC => fsmStatus_S <= "10";
+ rxReset_S <= '0';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ resettimeFlag_S <= '0';
+ resettimeCounter_I <= 0;
+
+ when RX_RESET => fsmStatus_S <= "11";
+ rxReset_S <= '1';
+ timeOutSyncCounter_I <= 0;
+ timeOutSynFlag_S <= '0';
+ if resettimeCounter_I<8 then -- peter : reset langer gemaakt om te voorkomen dat resetDone signaal wordt gemist
+ resettimeCounter_I <= resettimeCounter_I+1;
+ resettimeFlag_S <= '0';
+ else
+ resettimeCounter_I <= 0;
+ resettimeFlag_S <= '1';
+ end if;
+
+ when others =>
+ end case;
+end if;
+end process;
+
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 09-03-2011
+-- Module Name: FEE_slowcontrol_packet_receiver
+-- Description: Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board to Front End Electronics
+-- Modifications:
+-- 12-09-2014 New dataformat, name changed to FEE_slowcontrol_packet_receiver
+-- 22-09-2014 single clock
+-- 10-10-2014 bug with high rate of slow-control commands solved
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+\r
+----------------------------------------------------------------------------------\r
+-- FEE_slowcontrol_packet_receiver\r
+-- Gets packet data from the fiber receive module and analyses them.\r
+--\r
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+-- 0x5C address(7..0) replybit 0000000 data(31..24)
+-- data(23..0) CRC8(7..0)
+--\r
+-- The slow-control commands are written as byte-wise: \r
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+--\r
+-- Library\r
+--\r
+-- Generics:\r
+-- \r
+-- Inputs:\r
+-- clock : clock
+-- reset : reset\r
+-- enable : enable receiving\r
+-- packet_data_in : 32 bits data input from fiber module\r
+-- packet_data_present : data available from fiber module\r
+-- slowcontrol_fifofull : connected fifo is full\r
+-- clear_hamming_corrections : clear the counter for the hamming-code corrections\r
+--
+-- Outputs:\r
+-- packet_data_read : read signal to fiber module to read next data\r
+-- byte_data : 8-bits slowcontrol data:
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+-- byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read
+-- byte_request : request signal for reading data
+-- data_error : error in packet-data : CRC-error, hamming-code error, error in data bits
+-- overflow : buffer overflow: slowcontrol data loss\r
+--\r
+-- Components:\r
+-- crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words (only check here)
+-- sync_fifo_512x41 : fifo for slowcontrol commands
+--
+----------------------------------------------------------------------------------\r
+\r
+entity FEE_slowcontrol_packet_receiver is\r
+ Port ( \r
+ clock : in std_logic;\r
+ reset : in std_logic;\r
+ enable : in std_logic;\r
+ packet_data_in : in std_logic_vector (31 downto 0);\r
+ packet_data_present : in std_logic;\r
+ packet_data_read : out std_logic;\r
+ byte_data : out std_logic_vector(7 downto 0);
+ byte_write : out std_logic;
+ byte_request : out std_logic;
+ data_error : out std_logic;\r
+ overflow : out std_logic);\r
+end FEE_slowcontrol_packet_receiver;\r
+\r
+architecture Behavioral of FEE_slowcontrol_packet_receiver is\r
+\r
+component crc8_add_check32 is
+ PORT(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;\r
+ crc_error : out std_logic
+ );
+end component;
+\r
+component sync_fifo_512x41\r
+ port (\r
+ rst : in std_logic;\r
+ clk : in std_logic;\r
+ din : in std_logic_vector(40 downto 0);\r
+ wr_en : in std_logic;\r
+ rd_en : in std_logic;\r
+ dout : out std_logic_vector(40 downto 0);\r
+ full : out std_logic;\r
+ empty : out std_logic);\r
+end component;\r
+\r
+\r
+type rec_state_type is (init,expect_first,slow1);\r
+signal rec_state_S : rec_state_type := init;\r
+\r
+signal error_S : std_logic;\r
+signal enable_S : std_logic;\r
+\r
+signal packet_data_read_S : std_logic;\r
+signal packet_data_valid_S : std_logic;\r
+\r
+signal crc8_data_in_S : std_logic_vector (31 downto 0);
+signal crc8_data_in_valid_S : std_logic := '0';
+signal crc8_data_in_last_S : std_logic := '0';
+signal crc8_data_out_S : std_logic_vector (31 downto 0);
+signal crc8_data_out_valid_S : std_logic := '0';
+signal crc8_data_out_last_S : std_logic := '0';
+signal crc8_error_S : std_logic := '0';
+signal crc8_slowerror_S : std_logic := '0';\r
+signal crc8_reset_S : std_logic := '0';\r
+signal crc8_clear_S : std_logic := '0';\r
+\r
+signal slowpacketvalid_S : std_logic := '0';\r
+signal slowcontrol_data_S : std_logic_vector (31 downto 0);
+signal slowcontrol_address_S : std_logic_vector (7 downto 0);
+signal slowcontrol_request_S : std_logic := '0';\r
+signal slowcontrol_write_S : std_logic := '0';\r
+\r
+signal slowcontrol_read_S : std_logic := '0';\r
+signal slowcontrol_read_after1clk_S : std_logic := '0';\r
+signal slowcontrol_fifoempty_S : std_logic := '0';\r
+\r
+signal byte_index_S : integer range 0 to 4 := 0;\r
+ \r
+signal slowcontrol_dataout_S : std_logic_vector (31 downto 0);\r
+signal sfifo_in_S : std_logic_vector (40 downto 0);\r
+signal sfifo_out_S : std_logic_vector (40 downto 0);\r
+signal sfifo_full_S : std_logic := '0';\r
+\r
+begin\r
+
+data_error <= '1' when (crc8_slowerror_S='1') or (error_S='1') else '0';
+overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1')) else '0';\r
+\r
+packet_data_read <= packet_data_read_S;\r
+packet_data_read_S <= '1' when \r
+ (packet_data_present='1') and (reset='0') and (enable_S='1') and (rec_state_S/=init) else '0';\r
+\r
+process(clock)\r
+begin\r
+ if rising_edge(clock) then\r
+ enable_S <= enable;\r
+ end if;\r
+end process;\r
+\r
+crc8_data_in_S <= packet_data_in;\r
+crc8_data_in_valid_S <= '1' when (packet_data_valid_S='1') or (rec_state_S=init) else '0';\r
+crc8_data_in_last_S <= '1' when (rec_state_S=slow1) or (rec_state_S=init) else '0';\r
+crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
+crc8check: crc8_add_check32 port map(
+ clock => clock,
+ reset => crc8_reset_S,
+ data_in => crc8_data_in_S,
+ data_in_valid => crc8_data_in_valid_S,
+ data_in_last => crc8_data_in_last_S,
+ data_out => crc8_data_out_S,
+ data_out_valid => crc8_data_out_valid_S,
+ data_out_last => crc8_data_out_last_S,\r
+ crc_error => crc8_error_S);\r
+\r
+inputdatahandling: process(clock)\r
+variable timeoutcounter_V : integer range 0 to 15 := 0;\r
+begin\r
+\r
+ if rising_edge(clock) then
+ crc8_clear_S <= '0';\r
+ if reset='1' then\r
+ error_S <= '0';\r
+ crc8_clear_S <= '1';
+ timeoutcounter_V := 0;
+ rec_state_S <= init;\r
+ else
+ case rec_state_S is\r
+ when init =>\r
+ timeoutcounter_V := 0;\r
+ rec_state_S <= expect_first;
+ when expect_first =>
+ timeoutcounter_V := 0;
+ if enable_S='0' then
+ rec_state_S <= expect_first;
+ else
+ if packet_data_valid_S='1' then
+ if packet_data_in(31 downto 24)=x"5C" then -- slowcontrol
+ slowcontrol_address_S <= packet_data_in(23 downto 16);
+ slowcontrol_request_S <= packet_data_in(15);
+ slowcontrol_data_S(31 downto 24) <= packet_data_in(7 downto 0);
+ error_S <= '0';
+ rec_state_S <= slow1;
+ else -- error
+ error_S <= enable_S;
+ crc8_clear_S <= '1';
+ end if;
+ end if;
+ end if;
+ when slow1 =>
+ if packet_data_valid_S='1' then
+ timeoutcounter_V := 0;
+ slowcontrol_data_S(23 downto 0) <= packet_data_in(31 downto 8);
+ rec_state_S <= expect_first;
+ else
+ if timeoutcounter_V=15 then
+ error_S <= enable_S;
+ rec_state_S <= expect_first;
+ else
+ timeoutcounter_V := timeoutcounter_V+1;
+ rec_state_S <= slow1;
+ end if;
+ end if;
+ end case;\r
+ end if;\r
+ packet_data_valid_S <= packet_data_read_S;\r
+ end if;\r
+ \r
+end process inputdatahandling;\r
+
+slowcontrolpackethandling: process(clock)
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ slowcontrol_write_S <= '0';
+ slowpacketvalid_S <= '0';
+ crc8_slowerror_S <= '0';
+ else
+ if slowpacketvalid_S='0' then
+ slowcontrol_write_S <= '0';
+ crc8_slowerror_S <= '0';
+ if (rec_state_S=slow1) and (packet_data_valid_S='1') and (enable_S='1') then
+ slowpacketvalid_S <= '1';
+ end if;
+ else
+ slowpacketvalid_S <= '0';
+ if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
+ slowcontrol_write_S <= enable_S;
+ crc8_slowerror_S <= '0';
+ else
+ slowcontrol_write_S <= '0';
+ crc8_slowerror_S <= enable_S;
+ end if;
+ end if;
+ end if;
+ end if;
+end process slowcontrolpackethandling;
+
+sfifo_in_S(31 downto 0) <= slowcontrol_data_S;
+sfifo_in_S(39 downto 32) <= slowcontrol_address_S;
+sfifo_in_S(40) <= slowcontrol_request_S;
+
+sfifo: sync_fifo_512x41 port map(\r
+ rst => reset,\r
+ clk => clock,\r
+ din => sfifo_in_S,\r
+ wr_en => slowcontrol_write_S,\r
+ rd_en => slowcontrol_read_S,\r
+ dout => sfifo_out_S,\r
+ full => sfifo_full_S,\r
+ empty => slowcontrol_fifoempty_S);
+
+slowcontrol_read_S <= '1' when (slowcontrol_fifoempty_S='0') and ((byte_index_S=0) or (byte_index_S=4)) and (slowcontrol_read_after1clk_S='0') else '0';
+
+byteoutputprocess: process(clock)
+begin
+ if rising_edge(clock) then
+ byte_request <= '0';
+ byte_write <= '0';
+ if slowcontrol_read_after1clk_S='1' then
+ byte_data <= sfifo_out_S(39 downto 32); -- address
+ slowcontrol_dataout_S <= sfifo_out_S(31 downto 0); -- data
+ if sfifo_out_S(40)='1' then -- read request
+ byte_request <= '1';
+ byte_index_S <= 0;
+ else
+ byte_write <= '1';
+ byte_index_S <= 1;
+ end if;
+ elsif byte_index_S=1 then
+ byte_data <= slowcontrol_dataout_S(31 downto 24);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=2 then
+ byte_data <= slowcontrol_dataout_S(23 downto 16);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=3 then
+ byte_data <= slowcontrol_dataout_S(15 downto 8);
+ byte_write <= '1';
+ byte_index_S <= byte_index_S+1;
+ elsif byte_index_S=4 then
+ byte_data <= slowcontrol_dataout_S(7 downto 0);
+ byte_write <= '1';
+ byte_index_S <= 0;
+ else
+ byte_index_S <= 0;
+ end if;
+ slowcontrol_read_after1clk_S <= slowcontrol_read_S;
+ end if;
+end process;
+\r
+end Behavioral;\r
+\r
--- /dev/null
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 21-03-2011
+-- Module Name: FEE_slowcontrol_receive_from_cpu
+-- Description: Module to receive slowcontrol data from soft-core cpu
+-- Modifications:
+-- 12-09-2014 Reduce nrof Registers to 2, replaced channel by address
+-- 22-09-2014 single clock
+-- 08-10-2014 error signal removed
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- FEE_slowcontrol_receive_from_cpu
+-- Module to receive byte-wise data from soft-core cpu and translates it into parallel register data.
+-- The byte-wise input data is sent to all connected modules as packets of 5 bytes.
+-- Byte0 : adc index and register index
+-- Byte1,2,3,4 : 32-bits data, MSB first
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : clock input and output
+-- reset : synchronous reset
+-- address : base-address of channel
+-- byte_data : 8-bits slowcontrol data:
+-- Byte0 : bit7..4=index of the channel bit3..2=index of register
+-- Byte1,2,3,4 : 32-bits data, MSB first
+-- byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read\r
+-- byte_request : request signal for reading data, here only used for check and synchronization
+--
+-- Outputs:
+-- register_A : 32-bits output register A
+-- register_B : 32-bits output register B
+--
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_slowcontrol_receive_from_cpu is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(7 downto 0);
+ byte_data : in std_logic_vector(7 downto 0);
+ byte_write : in std_logic;
+ byte_request : in std_logic;
+ register_A : out std_logic_vector (31 downto 0);
+ register_B : out std_logic_vector (31 downto 0)
+ );
+end FEE_slowcontrol_receive_from_cpu;
+
+architecture Behavioral of FEE_slowcontrol_receive_from_cpu is
+
+
+signal byte_idx_S : integer range 0 to 4 := 0;
+signal selected_S : std_logic := '0';
+signal register_buf_S : std_logic_vector(31 downto 8);\r
+signal selected_reg_S : std_logic_vector(0 downto 0);\r
+\r
+signal register_A_S : std_logic_vector (31 downto 0) := x"12183264"; -- default FEE
+signal register_B_S : std_logic_vector (31 downto 0) := x"0C643208"; -- default FEE
+\r
+-- register_A(7..0) = threshold High
+-- register_A(15..8) = threshold Low
+-- register_A(16) = disable High
+-- register_A(17) = disable Low
+-- register_A(23..18) = I/Max discard
+-- register_A(29..24) = I/Max pileup
+-- register_B(7..0) = minimum pulselength
+-- register_B(15..8) = pileup length
+-- register_B(23..16) = maximum wavelength
+-- register_B(24) = fullsize High\r
+-- register_B(25) = fullsize Low\r
+-- register_B(29..26) = CF delay\r
+\r
+
+begin\r
+\r
+register_A <= register_A_S;\r
+register_B <= register_B_S;\r
+
+
+rd_process: process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ byte_idx_S <= 0;
+ selected_S <= '0';\r
+ else
+ if byte_idx_S=0 then\r
+ if (byte_write='1') then
+ if (byte_data(7 downto 1)=address(7 downto 1)) then
+ selected_S <= '1';
+ selected_reg_S <= byte_data(0 downto 0);
+ else
+ selected_S <= '0';
+ end if;
+ byte_idx_S <= 1;
+ else
+ selected_S <= '0';
+ end if;
+ elsif byte_request='1' then -- unexpected : synchronize\r
+ selected_S <= '0';\r
+ byte_idx_S <= 0;\r
+ else\r
+ if selected_S='1' then\r
+ case byte_idx_S is \r
+ when 1 => \r
+ register_buf_S(31 downto 24) <= byte_data;\r
+ when 2 => \r
+ register_buf_S(23 downto 16) <= byte_data;\r
+ when 3 => \r
+ register_buf_S(15 downto 8) <= byte_data;\r
+ when 4 => \r
+ case selected_reg_S is \r
+ when "0" => register_A_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when "1" => register_B_S <= register_buf_S(31 downto 8) & byte_data;\r
+ when others =>\r
+ end case;\r
+ when others =>\r
+ end case;\r
+ end if;\r
+ if byte_idx_S<4 then\r
+ byte_idx_S <= byte_idx_S+1;\r
+ else\r
+ byte_idx_S <= 0;\r
+ end if;\r
+ end if;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 05-03-2012
+-- Module Name: FEE_sorting_mux
+-- Description: Multiplexer for FEE data, sorting on timestamp
+-- 11-09-2014: Output FIFO now with First Word Fall Through
+-- 22-09-2014: single clock
+-- 11-10-2014: adc-channel number 8 bits
+-- 16-10-2014: inpipe check
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_sorting_mux
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the 32-bits timestamp.
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+-- NROFMUXINPUTS : number of input-channels\r
+--
+-- Inputs:
+-- inputclock : clock for input data (write side incomming fifo)
+-- MUXclock : clock for multiplexer part, between the fifos
+-- outputclock : clock for output data (read side outgoing fifo)
+-- reset : reset, must be long enough for all clocks
+-- data_in : array of input data streams, structure of each (three 36-bits words):
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_in_write : write signal for data_in (write into fifo)
+-- data_out_read : read signal for outgoing data (read from fifo)
+--
+-- Outputs:
+-- data_in_allowed : write to input data allowed (not full)
+-- data_in_almostfull : input fifo is too full for maximum length waveform
+-- data_out : output data (three 36-bits words):
+-- bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
+-- bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
+-- bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- data_out_available : data_out available (output fifo not empty)\r
+-- data_out_inpipe : more data on its way
+-- error : data error, index in data words incorrect
+--
+-- Components:\r
+-- FEE_mux_readfifo : read data from fifo and writes to next level\r
+-- FEE_mux2to1 : compares the data and passes the first in time on\r
+-- sync_fifo_progfull504_progempty128_512x36 : synchronous fifo with programmable full and empty
+-- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_sorting_mux is
+ generic(
+ NROFMUXINPUTS : natural := 8
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+ );
+end FEE_sorting_mux;
+
+
+architecture Behavioral of FEE_sorting_mux is\r
+\r
+component FEE_mux2to1 is\r
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;\r
+ data1_in : in std_logic_vector(35 downto 0); \r
+ data1_in_write : in std_logic;\r
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;\r
+ data2_in : in std_logic_vector(35 downto 0); \r
+ data2_in_write : in std_logic;\r
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;\r
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;
+\r
+component FEE_mux_readfifo is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);\r
+end component;
+\r
+component sync_fifo_progfull504_progempty128_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_full : out std_logic;
+ prog_empty : out std_logic);
+end component;
+
+component sync_fifo_FWFT_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+\r
+\r
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
+constant INPIPE_DELAY : integer := 63;
+constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+\r
+--type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;\r
+--constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);\r
+\r
+type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);\r
+type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;\r
+\r
+signal error_S : std_logic := '0';\r
+\r
+signal data_S : data_type;\r
+signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
+signal data_write_S : singlebit_type := (others => (others => '0'));
+signal data_allowed_S : singlebit_type := (others => (others => '0'));
+signal error_array_S : singlebit_type := (others => (others => '0'));\r
+\r
+signal reset_MUXclock_S : std_logic := '0';\r
+\r
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
+signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+\r
+signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');\r
+
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S : std_logic_vector (35 downto 0);\r
+signal tfifo_rd_S : std_logic := '0';
+signal tfifo_full_S : std_logic := '0';
+signal tfifo_empty_S : std_logic := '0';
+\r
+type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);\r
+signal testword0_S : testword_type;\r
+\r
+begin
+
+\r
+data_out_inpipe <= '1' \r
+ when dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')\r
+ else '0';\r
+\r
+
+MUX_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
+\r
+process(clock)\r
+type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;\r
+variable inpipe_counter_V : inpipe_counter_type := (others => 0);\r
+variable index_other : integer range 0 to NROFMUXINPUTS-1;\r
+begin\r
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ inpipe_counter_V(index) := 0;\r
+ delay_inpipe_S(index) <= '0';\r
+ else\r
+ index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));\r
+ if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or\r
+ ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))\r
+ then\r
+ inpipe_counter_V(index) := INPIPE_DELAY;\r
+ delay_inpipe_S(index) <= '1';\r
+ else \r
+ if inpipe_counter_V(index)/=0 then\r
+ inpipe_counter_V(index) := inpipe_counter_V(index)-1;\r
+ delay_inpipe_S(index) <= '1';\r
+ else\r
+ delay_inpipe_S(index) <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+
+dfifo: sync_fifo_progfull504_progempty128_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => data_in(index),
+ wr_en => dfifo_wr_S(index),
+ rd_en => dfifo_rd_S(index),
+ dout => dfifo_out_S(index),
+ full => dfifo_full_S(index),
+ empty => dfifo_empty_S(index),
+ prog_full => data_in_almostfull(index),
+ prog_empty => dfifo_prog_empty_S(index));
+ \r
+dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+\r
+data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';\r
+\r
+FEE_mux_readfifo1: FEE_mux_readfifo port map(
+ clock => clock,
+ reset => reset,
+ data_in => dfifo_out_S(index),
+ data_in_available => data_in_available_S(index),
+ data_in_read => dfifo_rd_S(index),\r
+ data_out => data_S(0,index),
+ data_out_write => data_write_S(0,index),
+ data_out_inpipe => read36_inpipe_S(index),
+ data_out_allowed => data_allowed_S(0,index));\r
+\r
+process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)\r
+--variable index_other : integer range 0 to NROFMUXINPUTS-1;\r
+begin\r
+-- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));\r
+-- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or\r
+-- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?\r
+ if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or\r
+ (dfifo_wr_S(index)='1') then\r
+ data_out_inpipe_S(0,index) <= '1';\r
+ else\r
+ data_out_inpipe_S(0,index) <= '0';\r
+ end if;\r
+end process;\r
+
+end generate;\r
+\r
+\r
+MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate \r
+\r
+ MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+ \r
+ FEE_mux2to1_1: FEE_mux2to1 port map(\r
+ clock => clock,
+ reset => reset,
+ data1_in => data_S(i1,i2*2),\r
+ data1_in_write => data_write_S(i1,i2*2),\r
+ data1_in_available => data_out_inpipe_S(i1,i2*2),
+ data1_in_allowed => data_allowed_S(i1,i2*2),\r
+ data2_in => data_S(i1,i2*2+1),\r
+ data2_in_write => data_write_S(i1,i2*2+1),\r
+ data2_in_available => data_out_inpipe_S(i1,i2*2+1),
+ data2_in_allowed => data_allowed_S(i1,i2*2+1),\r
+ data_out => data_S(i1+1,i2),\r
+ data_out_write => data_write_S(i1+1,i2),\r
+ data_out_available => data_out_inpipe_S(i1+1,i2),
+ data_out_allowed => data_allowed_S(i1+1,i2),\r
+ error => error_array_S(i1,i2),
+ testword0 => testword0_S(i1,i2));\r
+ \r
+ end generate;\r
+end generate;\r
+\r
+process(clock)\r
+begin
+ if (rising_edge(clock)) then \r
+ error_S <= '0';\r
+ for i1 in 0 to mux2to1_gen_max-1 loop \r
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
+ if error_array_S(i1,i2)='1' then\r
+ error_S <= '1';\r
+ end if;\r
+ end loop;\r
+ end loop;\r
+ end if;\r
+end process;
+error <= error_S;\r
+\r
+data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';\r
+tfifo_in_S <= data_S(mux2to1_gen_max,0);
+tfifo: sync_fifo_FWFT_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => tfifo_in_S,
+ wr_en => data_write_S(mux2to1_gen_max,0),
+ rd_en => tfifo_rd_S,
+ dout => data_out,
+ full => tfifo_full_S,
+ empty => tfifo_empty_S);\r
+\r
+
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';\r
+data_out_available <= '1' when tfifo_empty_S='0' else '0';\r
+\r
+\r
+\r
+\r
+--testword0(33 downto 0) <= data_in(0)(33 downto 0);
+--testword0(34) <= time_error_S;
+--testword0(35) <= idx_error_S;
+testword1(33 downto 0) <= data_in(1)(33 downto 0);
+testword1(34) <= '0';
+testword1(35) <= '0';
+\r
+\r
+\r
+
+gentest: for i in 0 to 7 generate
+testword0(i) <= dfifo_full_S(i);\r
+end generate;\r
+
+testword0(8) <= dfifo_rd_S(7);\r
+testword0(9) <= data_in_available_S(7);\r
+\r
+testword0(10) <= data_write_S(0,7);\r
+testword0(11) <= data_out_inpipe_S(0,7);\r
+testword0(12) <= data_allowed_S(0,7);\r
+\r
+testword0(13) <= data_write_S(1,3);\r
+testword0(14) <= data_out_inpipe_S(1,3);\r
+testword0(15) <= data_allowed_S(1,3);\r
+\r
+testword0(16) <= data_write_S(2,1);\r
+testword0(17) <= data_out_inpipe_S(2,1);\r
+testword0(18) <= data_allowed_S(2,1);\r
+\r
+testword0(19) <= data_write_S(3,0);\r
+testword0(20) <= data_out_inpipe_S(3,0);\r
+testword0(21) <= data_allowed_S(3,0);\r
+\r
+\r
+testword0(22) <= data_write_S(0,0);\r
+testword0(23) <= data_out_inpipe_S(0,0);\r
+testword0(24) <= data_allowed_S(0,0);\r
+\r
+testword0(25) <= data_write_S(1,0);\r
+testword0(26) <= data_out_inpipe_S(1,0);\r
+testword0(27) <= data_allowed_S(1,0);\r
+\r
+testword0(28) <= data_write_S(2,0);\r
+testword0(29) <= data_out_inpipe_S(2,0);\r
+testword0(30) <= data_allowed_S(2,0);\r
+\r
+
+testword0(31) <= data_write_S(mux2to1_gen_max,0);
+testword0(32) <= tfifo_full_S;
+testword0(33) <= tfifo_rd_S;
+testword0(34) <= error_S;\r
+testword0(35) <= '0';
+--\r
+--\r
+--\r
+--testword1 <= testword0_S(2,0);
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_sorting_wavemux
+-- Description: Multiplexer for FEE data, sorting on timestamp
+-- Modifications:
+-- 23-09-2014 single clock, remove fullness fifo,
+-- 16-10-2014 inpipe signals
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_sorting_wavemux
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the 32-bits timestamp.
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+-- NROFMUXINPUTS : number of input-channels\r
+--
+-- Inputs:
+-- clock : clock
+-- reset : reset, must be long enough for all clocks
+-- data_in : array of input data streams, structure of each:
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- data_in_write : write signal for data_in (write into fifo)
+-- data_out_read : read signal for outgoing data (read from fifo)
+--
+-- Outputs:
+-- data_in_allowed : write to input data allowed (not full)
+-- data_in_almostfull : input fifo is too full for maximum length waveform
+-- data_out : output data
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identification)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- data_out_available : data_out available (output fifo not empty)\r
+-- data_out_inpipe : more data on its way
+-- error : data error, index in data words incorrect
+--
+-- Components:\r
+-- FEE_wavemux_readfifo : read data from fifo and writes to next level\r
+-- FEE_wavemux2to1 : compares the data and passes the first in time on\r
+-- sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty
+-- sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_sorting_wavemux is
+ generic(
+ NROFMUXINPUTS : natural := 16
+ );
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in array_halfadc36bits_type;
+ data_in_write : in std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_allowed : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_in_almostfull : out std_logic_vector(0 to NROFMUXINPUTS-1);
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_read : in std_logic;
+ data_out_available : out std_logic;
+ data_out_inpipe : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0)
+);
+end FEE_sorting_wavemux;
+
+
+architecture Behavioral of FEE_sorting_wavemux is\r
+\r
+component FEE_wavemux2to1 is\r
+ generic(
+ TIMEOUTBITS : natural := 6
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;\r
+ data1_in : in std_logic_vector(35 downto 0); \r
+ data1_in_write : in std_logic;\r
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;\r
+ data2_in : in std_logic_vector(35 downto 0); \r
+ data2_in_write : in std_logic;\r
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;\r
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end component;
+\r
+component FEE_wavemux_readfifo is
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);\r
+end component;
+\r
+component sync_fifo_progfull364_progempty128_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic;
+ prog_full : out std_logic;
+ prog_empty : out std_logic);
+end component;
+\r
+component sync_fifo_FWFT_512x36
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ din : in std_logic_vector(35 downto 0);
+ wr_en : in std_logic;
+ rd_en : in std_logic;
+ dout : out std_logic_vector(35 downto 0);
+ full : out std_logic;
+ empty : out std_logic);
+end component;
+\r
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max : integer := twologarray(NROFMUXINPUTS); -- -1;
+constant INPIPE_DELAY : integer := 63;
+constant zeros : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ones : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+\r
+--type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;\r
+--constant mux2to1_gen : mux2to1_gen_type := (8,4,2,1);\r
+\r
+type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);\r
+type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;\r
+\r
+signal error_S : std_logic := '0';\r
+\r
+signal data_S : data_type;\r
+signal data_out_inpipe_S : singlebit_type := (others => (others => '0'));
+signal data_write_S : singlebit_type := (others => (others => '0'));
+signal data_allowed_S : singlebit_type := (others => (others => '0'));
+signal error_array_S : singlebit_type := (others => (others => '0'));\r
+\r
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S : array_halfadc36bits_type := (others => (others => '0'));
+signal dfifo_full_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_empty_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+signal delay_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_inpipe_S : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+-- signals for fifo from adc-mux to packet-composer
+signal tfifo_in_S : std_logic_vector (35 downto 0);\r
+signal tfifo_rd_S : std_logic := '0';
+signal tfifo_full_S : std_logic := '0';
+signal tfifo_empty_S : std_logic := '0';
+\r
+type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);\r
+signal testword0_S : testword_type;\r
+\r
+begin
+
+data_out_inpipe <= '1' \r
+ when (dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1)) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')\r
+ else '0';\r
+
+FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate
+
+process(clock)
+type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
+variable inpipe_counter_V : inpipe_counter_type := (others => 0);
+variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ inpipe_counter_V(index) := 0;
+ delay_inpipe_S(index) <= '0';
+ else
+ index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
+ if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
+ ((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
+ then
+ inpipe_counter_V(index) := INPIPE_DELAY;
+ delay_inpipe_S(index) <= '1';
+ else
+ if inpipe_counter_V(index)/=0 then
+ inpipe_counter_V(index) := inpipe_counter_V(index)-1;
+ delay_inpipe_S(index) <= '1';
+ else
+ delay_inpipe_S(index) <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+dfifo: sync_fifo_progfull364_progempty128_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => data_in(index),
+ wr_en => dfifo_wr_S(index),
+ rd_en => dfifo_rd_S(index),
+ dout => dfifo_out_S(index),
+ full => dfifo_full_S(index),
+ empty => dfifo_empty_S(index),
+ prog_full => data_in_almostfull(index),
+ prog_empty => dfifo_prog_empty_S(index));
+
+ dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+\r
+data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';\r
+\r
+FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(
+ clock => clock,
+ reset => reset,
+ data_in => dfifo_out_S(index),
+ data_in_available => data_in_available_S(index),
+ data_in_read => dfifo_rd_S(index),\r
+ data_out => data_S(0,index),
+ data_out_write => data_write_S(0,index),
+ data_out_inpipe => read36_inpipe_S(index),
+ data_out_allowed => data_allowed_S(0,index));\r
+
+process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
+--variable index_other : integer range 0 to NROFMUXINPUTS-1;
+begin
+-- index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
+-- if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
+-- (dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
+ if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
+ (dfifo_wr_S(index)='1') then
+ data_out_inpipe_S(0,index) <= '1';
+ else
+ data_out_inpipe_S(0,index) <= '0';
+ end if;
+end process;
+
+end generate;\r
+\r
+\r
+FEE_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate \r
+\r
+ FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate
+ \r
+ FEE_wavemux2to1_1: FEE_wavemux2to1 port map(\r
+ clock => clock,
+ reset => reset,
+ data1_in => data_S(i1,i2*2),\r
+ data1_in_write => data_write_S(i1,i2*2),\r
+ data1_in_available => data_out_inpipe_S(i1,i2*2),
+ data1_in_allowed => data_allowed_S(i1,i2*2),\r
+ data2_in => data_S(i1,i2*2+1),\r
+ data2_in_write => data_write_S(i1,i2*2+1),\r
+ data2_in_available => data_out_inpipe_S(i1,i2*2+1),
+ data2_in_allowed => data_allowed_S(i1,i2*2+1),\r
+ data_out => data_S(i1+1,i2),\r
+ data_out_write => data_write_S(i1+1,i2),\r
+ data_out_available => data_out_inpipe_S(i1+1,i2),
+ data_out_allowed => data_allowed_S(i1+1,i2),\r
+ error => error_array_S(i1,i2),
+ testword0 => testword0_S(i1,i2));\r
+ \r
+ end generate;\r
+end generate;\r
+\r
+process(clock)\r
+begin
+ if (rising_edge(clock)) then \r
+ error_S <= '0';\r
+ for i1 in 0 to mux2to1_gen_max-1 loop \r
+ for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop
+ if error_array_S(i1,i2)='1' then\r
+ error_S <= '1';\r
+ end if;\r
+ end loop;\r
+ end loop;\r
+ end if;\r
+end process;
+error <= error_S;\r
+\r
+data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';\r
+tfifo_in_S <= data_S(mux2to1_gen_max,0);
+tfifo: sync_fifo_FWFT_512x36 port map(
+ rst => reset,
+ clk => clock,
+ din => tfifo_in_S,
+ wr_en => data_write_S(mux2to1_gen_max,0),
+ rd_en => tfifo_rd_S,
+ dout => data_out,
+ full => tfifo_full_S,
+ empty => tfifo_empty_S);
+
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';\r
+data_out_available <= '1' when tfifo_empty_S='0' else '0';\r
+\r
+
+testword0 <= (others => '0');
+testword1 <= (others => '0');
+\r
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 01-02-2012
+-- Module Name: FEE_waveform_to_36bits
+-- Description: put waveform data in 36-bits wide data stream
+-- Modifications:
+-- 14-08-2014: bug in read signal, output 'overflow_out' added
+-- 16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits
+-- 11-10-2014: adc-channel number 8 bits
+-- 23-10-2014: finish actual waveform in case of almost full signal
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+use work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_waveform_to_36bits
+-- Put waveform data in 36-bits wide data stream
+-- Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.
+-- Output data is 36 bits wide with the four highest bits for identification
+--
+--
+-- generics
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- adcnumber : 8 bits indification of the adc channel
+-- data_in : data from adc waveform buffer:
+-- bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform
+-- bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
+-- bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
+-- bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
+-- bits(35..32)="1111" : error, bits(31..0)=don't care
+-- overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte
+-- pileupdata_allowed : writing of pile-up data allowed
+-- pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--
+-- outputs
+-- data_in_read : read signal to adc waveform buffer
+-- pileupdata_out : 36-bits data with pile-up waveform:
+-- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+-- bits(35..32)="0001" :
+-- bits(31..24) = statusbyte (bit6=overflow)
+-- bits(23..8) = 0
+-- bits(7..0) = adcnumber (channel identifaction)
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+-- pileupdata_write : write signal for pile-up data output
+-- overflow_out : buffer overflow: data skipped
+-- error : error in incoming data
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_waveform_to_36bits is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ adcnumber : in std_logic_vector(7 downto 0);
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ overflow_in : in std_logic;
+ pileupdata_out : out std_logic_vector(35 downto 0);
+ pileupdata_write : out std_logic;
+ pileupdata_allowed : in std_logic;
+ pileupdata_almostfull : in std_logic;
+ overflow_out : out std_logic;
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end FEE_waveform_to_36bits;
+
+architecture Behavioral of FEE_waveform_to_36bits is
+
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal pileupdata_write_S : std_logic := '0';
+signal pileupdata_trywrite_S : std_logic := '0';
+\r
+signal lastdata_S : std_logic := '0';
+signal lastdata0_S : std_logic := '0';
+signal lastdata1_S : std_logic := '0';
+
+signal writingadcnumber_S : std_logic := '0';
+signal writeadcnumber_S : std_logic := '0';
+signal overflow_occurred_S : std_logic := '0';\r
+signal clear_overflow_occurred_S : std_logic := '0';\r
+signal overflow_in_S : std_logic := '0';\r
+signal error1_S : std_logic := '0';
+signal pileupdata_out_S : std_logic_vector(35 downto 0) := (others => '0');
+
+begin
+
+overflow_out <= overflow_occurred_S;
+error <= error1_S;
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1'
+ when (data_in_available='1') and (writingadcnumber_S='0') and (pileupdata_allowed='1') and \r
+ ((pileupdata_almostfull='0') or (lastdata_S='0'))--and (prevent_reading_S='0')
+ else '0';
+\r
+lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 32)="010") else '0';\r
+lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';\r
+process(clock)
+begin
+ if rising_edge(clock) then\r
+ if reset='1' then\r
+ lastdata1_S <= '0';\r
+ else
+ if data_in_read_after1clk_S='1' then\r
+ lastdata1_S <= lastdata0_S;\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;
+
+writingadcnumber_S <= '1' when
+ (writeadcnumber_S='1')
+ or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000"))
+ else '0';
+
+pileupdata_out <= pileupdata_out_S;
+
+pileupdata_write <= pileupdata_write_S;
+pileupdata_write_S <= '1' when (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') else '0';
+
+readprocess: process(clock)
+variable statusbyte_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+ if rising_edge(clock) then\r
+ error1_S <= '0';\r
+ clear_overflow_occurred_S <= '0';
+ if reset='1' then
+ pileupdata_trywrite_S <= '0';
+ writeadcnumber_S <= '0';
+ statusbyte_V := (others => '0');
+ overflow_occurred_S <= '0';
+ data_in_read_after1clk_S <= '0';\r
+ overflow_in_S <= overflow_in;
+ else
+ if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then
+ overflow_occurred_S <= '1';\r
+ elsif clear_overflow_occurred_S='1' then\r
+ overflow_occurred_S <= '0';\r
+ end if;\r
+ overflow_in_S <= overflow_in;
+ data_in_read_after1clk_S <= data_in_read_S;
+ if data_in_read_after1clk_S='1' then
+ case data_in(35 downto 32) is
+ when "1000" =>
+ pileupdata_out_S <= "0000" & data_in(31 downto 0);
+ pileupdata_trywrite_S <= '1';
+ writeadcnumber_S <= '1';
+ when "0010" => -- samples
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when "0100" => -- last sample
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when "0101" => -- last samples
+ writeadcnumber_S <= '0';
+ pileupdata_out_S <= data_in;
+ pileupdata_trywrite_S <= '1';
+ when others =>
+ error1_S <= '1';
+ pileupdata_trywrite_S <= '0';
+ end case;
+ else -- not data_in_read_after1clk_S
+ if (writeadcnumber_S='1') and (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') then
+ if overflow_occurred_S='1' then\r
+ statusbyte_V := STATBYTE_FEEPULSESKIPPED;
+ clear_overflow_occurred_S <= '1';
+ else
+ statusbyte_V := (others => '0');
+ end if;
+ pileupdata_out_S <= "0001" & statusbyte_V & x"0000" & adcnumber;
+ pileupdata_trywrite_S <= '1';
+ writeadcnumber_S <= '0';
+ elsif (pileupdata_trywrite_S='1') and (pileupdata_allowed='0') then -- keep trying
+ pileupdata_trywrite_S <= '1';
+ elsif (writeadcnumber_S='1') then
+ writeadcnumber_S <= '0';
+ else
+ pileupdata_trywrite_S <= '0';
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+\r
+
+testword0(3 downto 0) <= data_in(35 downto 32);
+testword0(4) <= data_in_read_S;
+testword0(5) <= data_in_available;
+testword0(6) <= data_in_read_after1clk_S;
+testword0(7) <= data_in_read_S;
+testword0(11 downto 8) <= pileupdata_out_S(35 downto 32);
+testword0(12) <= pileupdata_write_S;
+testword0(13) <= pileupdata_trywrite_S;
+testword0(14) <= writingadcnumber_S;
+testword0(15) <= writeadcnumber_S;
+testword0(16) <= overflow_occurred_S;
+testword0(17) <= clear_overflow_occurred_S;
+testword0(18) <= overflow_in_S;
+testword0(19) <= error1_S;
+testword0(20) <= pileupdata_allowed;
+testword0(21) <= pileupdata_almostfull;
+testword0(22) <= writeadcnumber_S;
+\r
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_wavemux2to1
+-- Description: compare timestamp of 36bits data pass on first
+-- Modifications:
+-- 11-10-2014: adc-channel number 8 bits
+-- 23-10-2014: proper end of packet in case of timeout
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.ALL;\r
+use IEEE.std_logic_ARITH.ALL;\r
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+\r
+------------------------------------------------------------------------------------------------------\r
+-- FEE_wavemux2to1\r
+-- Compare timestamp of 36bits data and pass on first\r
+-- Timestamp is a combination of the superburst and a clockcounter\r
+-- If data from only one is available then this is passed on directly\r
+-- The 36-bits data contains waveforms in packets, starting with timestamp, ending with last sample:\r
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+--\r
+--\r
+-- generics\r
+-- \r
+-- inputs\r
+-- clock : ADC sampling clock \r
+-- reset : synchrounous reset\r
+-- data1_in : data from first 36-bits input\r
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- data1_in_write : write signal for data1_in\r
+-- data1_in_available : more data available: wait with timestamp check until the timestamp is read\r
+-- data2_in : data from second 36-bits input\r
+-- bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- data2_in_write : write signal for data2_in\r
+-- data2_in_available : more data available: wait with timestamp check until the timestamp is read\r
+-- data_out_allowed : writing of resulting data allowed\r
+-- \r
+-- outputs\r
+-- data1_in_allowed : signal to allow data input 1\r
+-- data2_in_allowed : signal to allow data input 2\r
+-- data_out : 36-bits data with valid pulse waveform:\r
+-- bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform\r
+-- bits(35..32)="0001" : \r
+-- bits(31..24) = statusbyte (bit6=overflow) \r
+-- bits(23..8) = 0\r
+-- bits(7..0) = adcnumber (channel identifaction)\r
+-- bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample\r
+-- bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0\r
+-- bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample\r
+-- data_out_write : write signal for 36-bits output data\r
+-- data_out_available : data available: in this module or at the input\r
+-- error : error in data bits 35..32\r
+--\r
+-- components\r
+--\r
+------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+entity FEE_wavemux2to1 is\r
+ generic(
+ TIMEOUTBITS : natural := 6
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;\r
+ data1_in : in std_logic_vector(35 downto 0); \r
+ data1_in_write : in std_logic;\r
+ data1_in_available : in std_logic;
+ data1_in_allowed : out std_logic;\r
+ data2_in : in std_logic_vector(35 downto 0); \r
+ data2_in_write : in std_logic;\r
+ data2_in_available : in std_logic;
+ data2_in_allowed : out std_logic;\r
+ data_out : out std_logic_vector(35 downto 0);\r
+ data_out_write : out std_logic;\r
+ data_out_available : out std_logic;
+ data_out_allowed : in std_logic;\r
+ error : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)\r
+ );\r
+end FEE_wavemux2to1;\r
+\r
+\r
+architecture Behavioral of FEE_wavemux2to1 is\r
+\r
+signal timeout_counter_S : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+
+signal error_S : std_logic := '0';
+signal read_pulse1_S : std_logic := '0';
+signal read_pulse2_S : std_logic := '0';
+signal data1_in_allowed_S : std_logic := '0';
+signal data2_in_allowed_S : std_logic := '0';\r
+signal data1_in_write_S : std_logic := '0';\r
+signal data2_in_write_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+signal data_out_write_S : std_logic := '0';
+signal data_out_available_S : std_logic := '0';
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data1_timestamp_valid_S : std_logic := '0';
+signal data2_timestamp_valid_S : std_logic := '0';
+
+begin\r
+\r
+error <= error_S;
+\r
+data_out_available <= data_out_available_S;\r
+data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1') \r
+ or (data_out_trywrite_S='1') \r
+ or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')\r
+ else '0';
+
+data_out <= data_out_S;
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data1_in_allowed <= data1_in_allowed_S;
+data1_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse1_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
+ else '0';
+
+data2_in_allowed <= data2_in_allowed_S;
+data2_in_allowed_S <= '1' when (data_out_allowed='1')
+ and ((read_pulse2_S='1')
+ or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+ else '0';
+
+--data2_in_allowed_S <= '1' when (data_out_allowed='1')
+-- and ((read_pulse2_S='1')
+-- or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0'))
+-- and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+-- else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';\r
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';\r
+
+readprocess: process(clock)\r
+variable data1_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data2_timestamp_V : std_logic_vector(31 downto 0) := (others => '0');
+variable data1_timestamp_valid_V : std_logic := '0';
+variable data2_timestamp_valid_V : std_logic := '0';
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_trywrite_S <= '0';
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data1_timestamp_valid_S <= '0';
+ data2_timestamp_valid_S <= '0';
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+ data_out_trywrite_S <= '1'; -- try again
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ if read_pulse1_S='1' then\r
+ data1_timestamp_valid_V := '0';\r
+ if data1_in_write_S='1' then\r
+ timeout_counter_S <= (others => '0');\r
+ if (data1_in(35 downto 32)="0001") or (data1_in(35 downto 32)="0010") then -- next data\r
+ error_S <= '0';\r
+ data_out_S <= data1_in;
+ data_out_trywrite_S <= '1';\r
+ elsif (data1_in(35 downto 33)="010") then -- last data\r
+ error_S <= '0';\r
+ data_out_S <= data1_in;\r
+ read_pulse1_S <= '0';
+ data_out_trywrite_S <= '1';\r
+ else -- error\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';\r
+ end if;\r
+ else\r
+ data_out_trywrite_S <= '0';\r
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then\r
+ data_out_S <= "0100" & x"00000000"; -- force last data\r
+ data_out_trywrite_S <= '1';\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ if data_out_allowed='1' then\r
+ if data_out_write_S='1' then\r
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ timeout_counter_S <= timeout_counter_S+1;\r
+ end if;\r
+ end if;\r
+ error_S <= '0';\r
+ end if;\r
+ end if;
+ elsif read_pulse2_S='1' then\r
+ data2_timestamp_valid_V := '0';\r
+ if data2_in_write_S='1' then\r
+ timeout_counter_S <= (others => '0');\r
+ if (data2_in(35 downto 32)="0001") or (data2_in(35 downto 32)="0010") then -- next data\r
+ error_S <= '0';\r
+ data_out_S <= data2_in;
+ data_out_trywrite_S <= '1';\r
+ elsif (data2_in(35 downto 33)="010") then -- last data\r
+ error_S <= '0';\r
+ data_out_S <= data2_in;\r
+ read_pulse2_S <= '0';
+ data_out_trywrite_S <= '1';\r
+ else -- error\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ data_out_trywrite_S <= '0';\r
+ end if;\r
+ else\r
+ data_out_trywrite_S <= '0';\r
+ if timeout_counter_S(TIMEOUTBITS-1)='1' then\r
+ data_out_S <= "0100" & x"00000000"; -- force last data\r
+ data_out_trywrite_S <= '1';\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ if data_out_allowed='1' then\r
+ if data_out_write_S='1' then\r
+ timeout_counter_S <= (others => '0');\r
+ else\r
+ timeout_counter_S <= timeout_counter_S+1;\r
+ end if;\r
+ end if;\r
+ error_S <= '0';\r
+ end if;\r
+ end if;\r
+ else\r
+ timeout_counter_S <= (others => '0');\r
+ if data1_in_write_S='1' then\r
+ if (data1_in(35 downto 32)="0000") then
+ data1_timestamp_V := data1_in(31 downto 0);\r
+ data1_timestamp_valid_V := '1';\r
+ else -- error\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;\r
+ end if;\r
+ if data2_in_write_S='1' then\r
+ if (data2_in(35 downto 32)="0000") then
+ data2_timestamp_V := data2_in(31 downto 0);\r
+ data2_timestamp_valid_V := '1';\r
+ else -- error\r
+ error_S <= '1';\r
+ read_pulse1_S <= '0';
+ read_pulse2_S <= '0';
+ data1_timestamp_valid_V := '0';
+ data2_timestamp_valid_V := '0';
+ end if;\r
+ end if;\r
+ if data1_timestamp_valid_V='1' then\r
+ if data2_timestamp_valid_V='1' then\r
+ if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
+ or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then\r
+ read_pulse1_S <= '1';\r
+ data1_timestamp_valid_V := '0';\r
+ data_out_trywrite_S <= '1'; \r
+ data_out_S <= "0000" & data1_timestamp_V;
+ else -- select 2\r
+ read_pulse2_S <= '1';\r
+ data2_timestamp_valid_V := '0';\r
+ data_out_trywrite_S <= '1'; \r
+ data_out_S <= "0000" & data2_timestamp_V;
+ end if;\r
+ elsif data2_in_available='1' then -- data expected: wait\r
+ data_out_trywrite_S <= '0';\r
+ else -- write 1\r
+ read_pulse1_S <= '1';\r
+ data1_timestamp_valid_V := '0';\r
+ data_out_trywrite_S <= '1'; \r
+ data_out_S <= "0000" & data1_timestamp_V; \r
+ end if;\r
+ elsif data2_timestamp_valid_V='1' then
+ if data1_in_available='1' then -- data expected: wait\r
+ data_out_trywrite_S <= '0';\r
+ else -- write 2\r
+ read_pulse2_S <= '1';\r
+ data2_timestamp_valid_V := '0';\r
+ data_out_trywrite_S <= '1'; \r
+ data_out_S <= "0000" & data2_timestamp_V; \r
+ end if;\r
+ else -- no valid timestamps\r
+ data_out_trywrite_S <= '0';\r
+ end if;\r
+ end if; \r
+ data1_timestamp_valid_S <= data1_timestamp_valid_V;
+ data2_timestamp_valid_S <= data2_timestamp_valid_V;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+
+
+-- testword0 <= (others => '0');
+
+testword0(0) <= data1_in_write;
+testword0(1) <= data1_in_available;
+testword0(2) <= data1_in_allowed_S;
+testword0(3) <= read_pulse1_S;
+testword0(4) <= data1_in_write_S;
+testword0(5) <= data1_timestamp_valid_S;
+testword0(9 downto 6) <= data1_in(35 downto 32);\r
+\r
+testword0(10) <= data2_in_write;
+testword0(11) <= data2_in_available;
+testword0(12) <= data2_in_allowed_S;
+testword0(13) <= read_pulse2_S;
+testword0(14) <= data2_in_write_S;
+testword0(15) <= data2_timestamp_valid_S;
+testword0(19 downto 16) <= data2_in(35 downto 32);\r
+
+
+testword0(20) <= data_out_trywrite_S;
+testword0(21) <= data_out_write_S;
+testword0(22) <= data_out_available_S;
+testword0(23) <= data_out_allowed;
+testword0(27 downto 24) <= data_out_S(35 downto 32);
+testword0(28) <= error_S;
+\r
+
+
+testword0(33 downto 29) <= timeout_counter_S(TIMEOUTBITS-1 downto TIMEOUTBITS-5);
+testword0(35 downto 34) <= (others => '0');
+
+
+end Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 03-02-2012
+-- Module Name: FEE_wavemux_readfifo
+-- Description: Read 36-bits data from fifo and write to next module
+-- Modifications:
+-- 16-10-2014: inpipe signal
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_wavemux_readfifo
+-- Read 36-bits data from fifo and write to next module.
+--
+-- Library:
+-- work.panda_package: constants and types
+--
+-- Generics:
+--
+-- Inputs:
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : 36-bits input data from fifo
+-- data_in_available : input fifo not empty
+-- data_out_allowed : allowed to write output data data
+--
+-- Outputs:
+-- data_in_read : read signal to input fifo
+-- data_out : 36-bits output data
+-- data_out_write : write signal for output data
+-- data_out_inpipe : data available, in this module or in input fifo
+--
+-- Components:
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_wavemux_readfifo is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(35 downto 0);
+ data_in_available : in std_logic;
+ data_in_read : out std_logic;
+ data_out : out std_logic_vector(35 downto 0);
+ data_out_write : out std_logic;
+ data_out_inpipe : out std_logic;
+ data_out_allowed : in std_logic);
+end FEE_wavemux_readfifo;
+
+
+architecture Behavioral of FEE_wavemux_readfifo is
+
+signal data_in_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_S : std_logic_vector(35 downto 0) := (others => '0');
+signal data_out_write_S : std_logic := '0';
+signal data_in_saved_S : std_logic := '0';
+signal data_in_read_S : std_logic := '0';
+signal data_in_read_after1clk_S : std_logic := '0';
+signal data_out_trywrite_S : std_logic := '0';
+
+
+begin
+
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+data_out <= data_out_S;
+
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if reset='1' then
+ data_in_read_after1clk_S <= '0';
+ data_out_trywrite_S <= '0';
+ data_in_saved_S <= '0';
+ else
+ if (data_out_write_S='0') and (data_out_trywrite_S='1') then -- unsuccesfull try again
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ end if;
+ elsif data_in_saved_S='1' then -- write saved data
+ data_out_S <= data_in_S;
+ data_out_trywrite_S <= '1';
+ if data_in_read_after1clk_S='1' then -- save next data
+ data_in_S <= data_in;
+ data_in_saved_S <= '1';
+ else
+ data_in_saved_S <= '0';
+ end if;
+ elsif data_in_read_after1clk_S='1' then -- next read
+ data_out_S <= data_in;
+ data_out_trywrite_S <= '1';
+ else
+ data_out_trywrite_S <= '0';
+ end if;
+ data_in_read_after1clk_S <= data_in_read_S;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
+
--- /dev/null
+----------------------------------------------------------------------------------\r
+-- Company: KVI/RUG/Groningen University\r
+-- Engineer: Peter Schakel\r
+-- Create Date: 04-03-2011\r
+-- Module Name: panda_package\r
+-- Description: Package with constants and function for Panda\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.all;\r
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;\r
+\r
+package panda_package is\r
+\r
+ constant NROFADCS : natural := 32;\r
+ constant NROFFIBERS : natural := 4;\r
+ constant ADCINDEXSHIFT : natural := 1;\r
+ constant NROFMUXREGS : natural := 14;\r
+ constant ADCBITS : natural := 14;\r
+ constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;\r
+ constant FEESLOWCONTROLADRESSES : natural := 2*NROFADCS/(ADCINDEXSHIFT+1)+4;
+ constant FEESLOWCONTROLBOARDADDRESS : natural := 2*NROFADCS/(ADCINDEXSHIFT+1);
+\r
+-- statusbyte in data stream :\r
+ constant STATBYTE_DCPULSESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
+ constant STATBYTE_DCWAVESKIPPED : std_logic_vector(7 downto 0) := "00000100";\r
+ constant STATBYTE_DCCOMBINEDHITS : std_logic_vector(7 downto 0) := "00000001";\r
+ constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";\r
+ constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";\r
+\r
+ constant STATBYTE_FEEPULSESKIPPED : std_logic_vector(7 downto 0) := "01000000";\r
+ constant STATBYTE_FEECFNOZEROCROSS : std_logic_vector(7 downto 0) := "00100000";\r
+ constant STATBYTE_FEECFERROR : std_logic_vector(7 downto 0) := "00010000";\r
+\r
+-- fiber constants\r
+constant KCHAR280 : std_logic_vector(7 downto 0) := "00011100"; -- 1C\r
+constant KCHAR281 : std_logic_vector(7 downto 0) := "00111100"; -- 3C\r
+constant KCHAR285 : std_logic_vector(7 downto 0) := "10111100"; -- BC\r
+-- constant KCHAR277 : std_logic_vector(7 downto 0) := "11111011"; -- FB\r
+constant KCHAR286 : std_logic_vector(7 downto 0) := x"DC";\r
+\r
+constant KCHARIDLE : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285; -- 3CBC peter: bytes different for word sync\r
+constant KCHARSODASTART : std_logic_vector(15 downto 0) := KCHAR280 & KCHAR280; -- 1C1C\r
+constant KCHARSODASTOP : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR281; -- 3C3C\r
+constant KCHARSODA : std_logic_vector(7 downto 0) := KCHAR286; -- DC\r
+ \r
+-- addresses slowcontrol commands for Multiplexer board\r
+ constant ADDRESS_MUX_FIBERMODULE_STATUS : std_logic_vector(23 downto 0) := x"800000";\r
+-- request : request status\r
+-- command: clear error bits, pulse skipped counter\r
+-- Reply, or in case of error: Status of the fibermodule:\r
+-- bit0 : error in slowcontrol to cpu occured\r
+-- bit1 : error if slowcontrol transmit data\r
+-- bit2 : error if fiber receive data\r
+-- bit3 : received character not in table: fiber error\r
+-- bit4 : pulse data skipped due to full multiplexer fifo\r
+-- bit5 : receiver locked\r
+-- bit15..8 : number of pulse data packets skipped due to full buffers\r
+-- bit31..16 : number of successful hamming code corrections\r
+ constant ADDRESS_MUX_MAXCFLUTS : std_logic_vector(23 downto 0) := x"800001";\r
+-- bit15..0 : data for the CF or MAX Look Up Table\r
+-- bit25..16 :offset for maximum correction LUT\r
+-- bit26 : write signal for maximum LUT\r
+-- bit27 : loading maximum correction LUT\r
+-- bit28 : enable maximum correction\r
+-- bit29 : write signal for Constant Fraction LUT\r
+-- bit30 : loading CF correction LUT\r
+-- bit31 : enable CF correction\r
+ constant ADDRESS_MUX_MULTIPLEXER_STATUS : std_logic_vector(23 downto 0) := x"800002";\r
+-- status/fullness of the multiplexer:\r
+-- bit 15..0 : number of words in input fifo of the multiplexer\r
+-- bit 15..0 : number of words in output fifo of the multiplexer, only for fiber index 0\r
+ constant ADDRESS_MUX_SODA_CONTROL : std_logic_vector(23 downto 0) := x"800003";\r
+-- settings for the SODA : \r
+-- bit0 : enable SODA packets\r
+-- bit1 : reset timestamp counters\r
+-- bit2 : Enable data taking \r
+-- bit3 : Disable data taking\r
+-- bit4 : Enable Aurora interface to Computer Node\r
+ constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004";\r
+-- settings for the histogram : \r
+-- bit0 : clear the histogram\r
+-- bit1 : start reading of the histogram\r
+-- bit10..8 : Binning of the histogram channels, scaling x-axis :\r
+-- 000 = no scaling\r
+-- 001 = div 2\r
+-- 010 = div 4\r
+-- 011 = div 8\r
+-- 100 = div 16\r
+-- 101 = div 32\r
+-- 110 = div 64\r
+-- 111 = div 128\r
+-- bit31..16 : Selected unique adc-number\r
+ constant ADDRESS_MUX_TIMESTAMP_ERRORS : std_logic_vector(23 downto 0) := x"800005";\r
+-- number of errors:\r
+-- bit 9..0 : number of timestamp mismatches\r
+-- bit 19..10 : number of skipped pulses\r
+-- bit 29..20 : number of data errors\r
+ constant ADDRESS_MUX_TIMESHIFT : std_logic_vector(23 downto 0) := x"800006";\r
+-- number of clockcycles (incl. constant fraction) to compensate for delay SODA to FEE\r
+-- bit 10..0 : compensation time, fractional part; number of bits for constant fraction, see CF_FRACTIONBIT\r
+-- bit 30..16 : compensation time, integer part\r
+-- bit 31 : load LUT mode, after set to 1 starts with ADC0 on each write, and so on\r
+ constant ADDRESS_MUX_EXTRACTWAVE : std_logic_vector(23 downto 0) := x"800007";\r
+-- start extracting waveform of 1 pileup pulse:\r
+-- bit 15..0 : selected adcnumber\r
+-- bit 16 : select 1 adc, otherwise take first data arriving\r
+-- bit 17 : select 1 low/high combination instead of 1 adc channel\r
+ constant ADDRESS_MUX_EXTRACTDATA : std_logic_vector(23 downto 0) := x"800008";\r
+-- start extracting data of 1 pulse:\r
+-- bit 15..0 : selected adcnumber\r
+-- bit 16 : select 1 adc, otherwise take first data arriving\r
+-- bit 17 : select 1 low/high combination instead of 1 adc channel\r
+ constant ADDRESS_MUX_SYSMON : std_logic_vector(23 downto 0) := x"80000c";\r
+-- write to FPGA system monitor\r
+-- bit 31 : slect read/write, write='0', read='1'\r
+-- bit 30 : reset/reconfigure FPGA system monitor\r
+-- bit 22..16 : 7-bits address of FPGA system monitor\r
+-- bit 15..0 : 16-bits data for FPGA system monitor\r
+-- read from FPGA system monitor, effective address is the last address at data bits 30..16 that was written\r
+-- bit 30..16 : 7-bits effective address of FPGA system monitor\r
+-- bit 15..0 : data from FPGA system monitor\r
+ constant ADDRESS_MUX_CROSSSWITCH : std_logic_vector(23 downto 0) := x"80000d";\r
+-- write to cross switch configuration\r
+-- bit 7..0 : selected multiplexer input\r
+-- bit 15..8 : ADC-channel to switch to selected multiplexer input (fibernr*NROFADCS+adcnumber or fibernr*NROFADCS/2+adcnumber/2 if high/low gain ADCs are used)\r
+-- bit 16 : select if selected multiplexer input will be combined with neighbour (only for even inputs)\r
+-- bit 31 : write to configuration register (extra check)\r
+ constant ADDRESS_MUX_ENERGYCORRECTION : std_logic_vector(23 downto 0) := x"80000e";\r
+-- energy correction Look Up Table\r
+-- bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)\r
+-- bit 30..16 : offset for energy\r
+-- bit 31 : loading LUT mode, after set to 1 starts with ADC0 on each write, and so on\r
+\r
+-- addresses slowcontrol commands for Multiplexer\r
+ constant ADDRESS_BOARDNUMBER : std_logic_vector(23 downto 0) := x"002000";\r
+-- bit11..0 = sets the unique boardnumber\r
+-- bit31 = initialize all FEE registers that have been set\r
+\r
+-- addresses slowcontrol commands for Front End Electronics board\r
+ constant ADDRESS_FEE_CONTROL : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS,8);\r
+-- bit0: reset all\r
+-- bit2: clear errors\r
+-- bit3: enable waveforms\r
+-- bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read\r
+-- bit 18 = reset/initializes FPGA System monitor\r
+ constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1,8);\r
+-- bit1 : Data Taken enabled (enable and disabled is done with SODA packets)\r
+-- bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare\r
+-- bit 15..6 = ADC value from FPGA System monitor\r
+-- bit23..16 : error occurred bits: in case of error a bit is set. Clearing is done with ADDRESS_FEE_CONTROL\r
+-- bit16 : error : NotInTable\r
+-- bit17 : error : receive data error (slowcontrol)\r
+-- bit18 : error : slowcontrol buffer overrun\r
+-- bit19 : error : not used\r
+-- bit20 : error : transmit data error, multipleser error\r
+-- bit21 : error : receive data buffer overrun\r
+-- bit22 : error : adc data buffer overrun\r
+-- bit23 : error : receive fiber not locked\r
+ constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2,8);\r
+-- data not important; this slowcontrol command indicates buffer full\r
+ constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3,8);\r
+-- bit31..0 : number of hits in one second\r
+ constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4,8);\r
+\r
+ type array_muxregister_type is array(0 to NROFMUXREGS-1) of std_logic_vector(31 downto 0);\r
+ \r
+ type array_adc_type is array(0 to NROFADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
+ type array_adc64bits_type is array(0 to NROFADCS-1) of std_logic_vector(63 downto 0);\r
+ type array_adc48bits_type is array(0 to NROFADCS-1) of std_logic_vector(47 downto 0);\r
+ type array_adc36bits_type is array(0 to NROFADCS-1) of std_logic_vector(35 downto 0);\r
+ type array_adc32bits_type is array(0 to NROFADCS-1) of std_logic_vector(31 downto 0);\r
+ type array_adc24bits_type is array(0 to NROFADCS-1) of std_logic_vector(23 downto 0);\r
+ type array_adc16bits_type is array(0 to NROFADCS-1) of std_logic_vector(15 downto 0);\r
+ type array_adc9bits_type is array(0 to NROFADCS-1) of std_logic_vector(8 downto 0);\r
+ type array_adc8bits_type is array(0 to NROFADCS-1) of std_logic_vector(7 downto 0);\r
+ type array_adc4bits_type is array(0 to NROFADCS-1) of std_logic_vector(3 downto 0);\r
+\r
+ type array_halfadc36bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(35 downto 0);
+ type array_halfadc32bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(31 downto 0);
+ type array_halfadc16bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
+ type array_halfadc9bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(8 downto 0);
+ type array_halfadc8bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);\r
+ \r
+ type array_fiber64bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(63 downto 0);\r
+ type array_fiber48bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(47 downto 0);\r
+ type array_fiber36bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(35 downto 0);\r
+ type array_fiber32bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(31 downto 0);\r
+ type array_fiber31bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(30 downto 0);\r
+ type array_fiber24bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(23 downto 0);\r
+ type array_fiber16bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(15 downto 0);\r
+ type array_fiber12bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(11 downto 0);\r
+ type array_fiber10bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(9 downto 0);\r
+ type array_fiber9bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(8 downto 0);\r
+ type array_fiber8bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(7 downto 0);\r
+ type array_fiber4bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(3 downto 0);\r
+\r
+ type array_DCadc36bits_type is array(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);\r
+ type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);\r
+ type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);\r
+ type twologarray_type is array(0 to 128) of natural;\r
+ constant twologarray : twologarray_type :=\r
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,\r
+6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);\r
+ type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);\r
+\r
+----------------------------------------------------------------------------------\r
+-- add_hamming_code_26_32\r
+-- Fills in Hamming code bits on positions 0,1,3,7,15,31 of a 32-bits word.\r
+-- The Hamming code is calculated with additional parity to be able to detect\r
+-- an error in 2 bits.\r
+-- \r
+-- Inputs:\r
+-- data_in : 32 bits data input, with 26 bits real data, the others will be filled with Hamming code\r
+-- \r
+-- Return:\r
+-- 32 bits data output, 26 bits original data and bits 0,1,3,7,15,31 filled with Hamming code\r
+-- \r
+----------------------------------------------------------------------------------\r
+ function add_hamming_code_26_32 (data_in : in std_logic_vector) return std_logic_vector;\r
+ \r
+\r
+----------------------------------------------------------------------------------\r
+-- calc_next_channel\r
+-- Calculates the next index in a std_logic_vector that has value '0';\r
+-- Used to determine the next ADC-channel to select in a multiplexer.\r
+-- If all values are '1' then the same index is returned.\r
+-- \r
+-- Inputs:\r
+-- adcreading : starting index in the std_logic_vector\r
+-- dfifo_empty : std_logic_vector to select the next index with value '0'\r
+-- \r
+-- Return:\r
+-- Next index in std_logic_vector with '0'\r
+-- \r
+----------------------------------------------------------------------------------\r
+ function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer;\r
+\r
+\r
+----------------------------------------------------------------------------------\r
+-- calc_next_channel\r
+-- Calculates the next index in a std_logic_vector that has value '1';\r
+-- Used to determine the next ADC-channel to select in a multiplexer.\r
+-- If all values are '0' then the same index is returned.\r
+-- \r
+-- Inputs:\r
+-- adcreading : starting index in the std_logic_vector\r
+-- data_available : std_logic_vector to select the next index with value '1'\r
+-- \r
+-- Return:\r
+-- Next index in std_logic_vector with '1'\r
+-- \r
+----------------------------------------------------------------------------------\r
+ function calc_next_channel_set(adcreading : integer; data_available : std_logic_vector) return integer;\r
+\r
+\r
+----------------------------------------------------------------------------------\r
+-- std_logic_vector_valid\r
+-- Checks if all bits in std_logic_vector are valid (0 or 1) to suppress conv_integer warnings during simulation\r
+-- \r
+-- Inputs:\r
+-- data : std_logic_vector to check\r
+-- \r
+-- Return:\r
+-- true if the std_logic_vector data is valid (only '0' and '1')\r
+-- \r
+----------------------------------------------------------------------------------\r
+ function std_logic_vector_valid(data : in std_logic_vector) return boolean;\r
+\r
+\r
+end panda_package;\r
+\r
+\r
+package body panda_package is\r
+\r
+function calc_next_channel(adcreading : integer; dfifo_empty : std_logic_vector) return integer is\r
+variable i : integer range 0 to dfifo_empty'high+1;\r
+variable c : integer range 0 to dfifo_empty'high;\r
+begin\r
+ i := 0;\r
+ if adcreading=dfifo_empty'high then\r
+ c := 0;\r
+ else\r
+ c := adcreading+1;\r
+ end if;\r
+ while (i/=dfifo_empty'high+1) and (dfifo_empty(c)='1') loop\r
+ i := i+1;\r
+ if (c<dfifo_empty'high) then \r
+ c := c+1;\r
+ else\r
+ c:=0;\r
+ end if;\r
+ end loop;\r
+ return c;\r
+end function;\r
+\r
+function calc_next_channel_set(adcreading : integer; data_available : std_logic_vector) return integer is\r
+variable i : integer range 0 to data_available'high+1;\r
+variable c : integer range 0 to data_available'high;\r
+begin\r
+ i := 0;\r
+ if adcreading=data_available'high then\r
+ c := 0;\r
+ else\r
+ c := adcreading+1;\r
+ end if;\r
+ while (i/=data_available'high+1) and (data_available(c)='0') loop\r
+ i := i+1;\r
+ if (c<data_available'high) then \r
+ c := c+1;\r
+ else\r
+ c:=0;\r
+ end if;\r
+ end loop;\r
+ return c;\r
+end function;\r
+\r
+\r
+function add_hamming_code_26_32 (data_in : in std_logic_vector) return std_logic_vector is\r
+variable din_S : std_logic_vector(25 downto 0);\r
+variable parity_S : std_logic_vector(5 downto 0);\r
+variable dout_S : std_logic_vector(31 downto 0);\r
+begin\r
+ din_S(0) := data_in(2);\r
+ din_S(1) := data_in(4);\r
+ din_S(2) := data_in(5);\r
+ din_S(3) := data_in(6);\r
+ din_S(4) := data_in(8);\r
+ din_S(5) := data_in(9);\r
+ din_S(6) := data_in(10);\r
+ din_S(7) := data_in(11);\r
+ din_S(8) := data_in(12);\r
+ din_S(9) := data_in(13);\r
+ din_S(10) := data_in(14);\r
+ din_S(11) := data_in(16);\r
+ din_S(12) := data_in(17);\r
+ din_S(13) := data_in(18);\r
+ din_S(14) := data_in(19);\r
+ din_S(15) := data_in(20);\r
+ din_S(16) := data_in(21);\r
+ din_S(17) := data_in(22);\r
+ din_S(18) := data_in(23);\r
+ din_S(19) := data_in(24);\r
+ din_S(20) := data_in(25);\r
+ din_S(21) := data_in(26);\r
+ din_S(22) := data_in(27);\r
+ din_S(23) := data_in(28);\r
+ din_S(24) := data_in(29);\r
+ din_S(25) := data_in(30);\r
+\r
+-- calculates the Hamming code parity bits\r
+parity_S(0) := din_S(0) xor din_S(1) xor din_S(3) xor din_S(4) xor din_S(6) xor din_S(8) xor din_S(10) xor din_S(11) \r
+ xor din_S(13) xor din_S(15) xor din_S(17) xor din_S(19) xor din_S(21) xor din_S(23) xor din_S(25);\r
+parity_S(1) := din_S(0) xor din_S(2) xor din_S(3) xor din_S(5) xor din_S(6) xor din_S(9) xor din_S(10) xor din_S(12) \r
+ xor din_S(13) xor din_S(16) xor din_S(17) xor din_S(20) xor din_S(21) xor din_S(24) xor din_S(25);\r
+parity_S(2) := din_S(1) xor din_S(2) xor din_S(3) xor din_S(7) xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(14) \r
+ xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);\r
+parity_S(3) := din_S(4) xor din_S(5) xor din_S(6) xor din_S(7) xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(18) \r
+ xor din_S(19) xor din_S(20) xor din_S(21) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);\r
+parity_S(4) := din_S(11) xor din_S(12) xor din_S(13) xor din_S(14) xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(18) \r
+ xor din_S(19) xor din_S(20) xor din_S(21) xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25);\r
+parity_S(5) := din_S(0) xor din_S(1) xor din_S(2) xor din_S(3) xor din_S(4) xor din_S(5) xor din_S(6) xor din_S(7) \r
+ xor din_S(8) xor din_S(9) xor din_S(10) xor din_S(11) xor din_S(12) xor din_S(13) xor din_S(14) \r
+ xor din_S(15) xor din_S(16) xor din_S(17) xor din_S(18) xor din_S(19) xor din_S(20) xor din_S(21) \r
+ xor din_S(22) xor din_S(23) xor din_S(24) xor din_S(25) xor parity_S(0) xor parity_S(1) xor parity_S(2) \r
+ xor parity_S(3) xor parity_S(4);\r
+\r
+-- collect the right bits\r
+ dout_S(0) := parity_S(0);\r
+ dout_S(1) := parity_S(1);\r
+ dout_S(3) := parity_S(2);\r
+ dout_S(7) := parity_S(3);\r
+ dout_S(15) := parity_S(4);\r
+ dout_S(31) := parity_S(5);\r
+\r
+ dout_S(2) := din_S(0);\r
+ dout_S(4) := din_S(1);\r
+ dout_S(5) := din_S(2);\r
+ dout_S(6) := din_S(3);\r
+ dout_S(8) := din_S(4);\r
+ dout_S(9) := din_S(5);\r
+ dout_S(10) := din_S(6);\r
+ dout_S(11) := din_S(7);\r
+ dout_S(12) := din_S(8);\r
+ dout_S(13) := din_S(9);\r
+ dout_S(14) := din_S(10);\r
+ dout_S(16) := din_S(11);\r
+ dout_S(17) := din_S(12);\r
+ dout_S(18) := din_S(13);\r
+ dout_S(19) := din_S(14);\r
+ dout_S(20) := din_S(15);\r
+ dout_S(21) := din_S(16);\r
+ dout_S(22) := din_S(17);\r
+ dout_S(23) := din_S(18);\r
+ dout_S(24) := din_S(19);\r
+ dout_S(25) := din_S(20);\r
+ dout_S(26) := din_S(21);\r
+ dout_S(27) := din_S(22);\r
+ dout_S(28) := din_S(23);\r
+ dout_S(29) := din_S(24);\r
+ dout_S(30) := din_S(25);\r
+ return dout_S;\r
+end function;\r
+\r
+\r
+function std_logic_vector_valid(data : in std_logic_vector) return boolean is\r
+variable i : integer range 0 to data'high;\r
+variable b : boolean;\r
+begin\r
+ i := 0;\r
+ b := true;\r
+ while i<data'high loop\r
+ if (data(i)='0') or (data(i)='1') then\r
+ else\r
+ b := false;\r
+ end if;\r
+ i := i+1;\r
+ end loop;\r
+ return b;\r
+end function;\r
+\r
+\r
+end panda_package;\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 31-01-2012
+-- Module Name: blockmem
+-- Description: Generic memory block
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+\r
+------------------------------------------------------------------------------------------------------
+-- blockmem
+-- Generic memory block with separated addresses for reading and writing
+--
+--
+-- generics
+-- ADDRESS_BITS : Number of bits for the address
+-- DATA_BITS : number of bits for data
+--
+-- inputs
+-- clock : clock
+-- write_enable : write to memory
+-- write_address : address to write to
+-- data_in : data to write into memory
+-- read_address : address to read from
+--
+-- outputs
+-- data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity blockmem is
+ generic (
+ ADDRESS_BITS : natural := 8;
+ DATA_BITS : natural := 18
+ );
+ port (
+ clock : in std_logic;
+ write_enable : in std_logic;
+ write_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_in : in std_logic_vector(DATA_BITS-1 downto 0);
+ read_address : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+ data_out : out std_logic_vector(DATA_BITS-1 downto 0)\r
+ );
+end blockmem;
+
+architecture behavioral of blockmem is
+ type mem_type is array (2**ADDRESS_BITS-1 downto 0) of std_logic_vector (DATA_BITS-1 downto 0);
+ signal mem_S : mem_type := (others => (others => '0'));
+
+begin
+
+ process (clock)
+ begin
+ if (clock'event and clock = '1') then
+ if (write_enable = '1') then
+ mem_S(conv_integer(write_address)) <= data_in;
+ end if;
+ data_out <= mem_S(conv_integer(read_address));
+ end if;
+ end process;\r
+
+
+end architecture behavioral;
\ No newline at end of file
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-02-2011
+-- Module Name: crc8_add_check32
+-- Description: Add and checks a CRC8 code to a stream of 32 bits data words
+----------------------------------------------------------------------------------\r
+
+LIBRARY IEEE ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+\r
+----------------------------------------------------------------------------------\r
+-- crc8_add_check32\r
+-- Checks and adds a CRC8 code to a stream of 32 bits data words.\r
+-- This module can be used to add a CRC8 code and/or checks the CRC8 code.\r
+-- \r
+-- The last byte (that is LSB of the 32-bits word) filled with the CRC8 code,\r
+-- overwriting the original data, and this original data is compared with the\r
+-- CRC8 code. If they are not the same the crc_error output bit is high.\r
+-- The CRC8 is calculated on all 32-bits data words, with the LSB of the last word\r
+-- set to "00000000";\r
+-- The CRC8 code is calculated with initialize code "00000000".\r
+-- An explanation can be found at www.ElectronicDesignworks.com\r
+--\r
+-- Library:\r
+-- \r
+-- Generics:\r
+--
+-- Inputs:\r
+-- clock : one clock is used\r
+-- reset : synchronous reset\r
+-- data_in : 32 bits data input, LSB last byte is CRC8 or becomes CRC8\r
+-- data_in_valid : data_in word is valid\r
+-- data_in_last : last data in the 32-bits stream; contains or will contain CRC8\r
+--
+-- Outputs:\r
+-- data_out : 32 bits data output, LSB last byte is CRC8\r
+-- data_out_valid : data_in word is valid\r
+-- data_out_last : last data in the 32-bits stream; contains CRC8\r
+-- crc_error : CRC8 code in original data_in was wrong, \r
+-- can be ignored if the module is used to add a CRC8\r
+--
+----------------------------------------------------------------------------------\r
+entity crc8_add_check32 is
+ port(
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(31 DOWNTO 0);
+ data_in_valid : in std_logic;
+ data_in_last : in std_logic;
+ data_out : out std_logic_vector(31 DOWNTO 0);
+ data_out_valid : out std_logic;
+ data_out_last : out std_logic;\r
+ crc_error : out std_logic\r
+ );
+end crc8_add_check32;
+
+architecture behaviour OF crc8_add_check32 IS
+ constant CRC_INIT : std_logic_vector(7 DOWNTO 0) := "00000000"; \r
+ signal crc_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal crc_aftr1clk_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal crc_feedback_S : std_logic_vector(7 DOWNTO 0) := "00000000";
+ signal start_on_next_S : std_logic := '0';
+ signal din_S : std_logic_vector(31 DOWNTO 0);\r
+
+begin
+
+crc_feedback_S <= CRC_INIT when ((start_on_next_S='1') and (data_in_valid='1')) else crc_aftr1clk_S;\r
+\r
+din_S(31 downto 8) <= data_in(31 downto 8);\r
+din_S(7 downto 0) <= data_in(7 downto 0) when data_in_last='0' else (others => '0');
+crc_S(0) <= din_S(0) XOR din_S(1) XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR \r
+ crc_feedback_S(3) XOR din_S(10) XOR din_S(19) XOR din_S(28) XOR crc_feedback_S(4);
+crc_S(1) <= din_S(0) XOR din_S(2) XOR din_S(11) XOR din_S(20) XOR din_S(29) XOR crc_feedback_S(5) \r
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(2) <= din_S(0) XOR din_S(3) XOR din_S(12) XOR din_S(21) XOR din_S(30) XOR crc_feedback_S(6) \r
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(3) <= din_S(0) XOR din_S(4) XOR din_S(13) XOR din_S(22) XOR din_S(31) XOR crc_feedback_S(7) \r
+ XOR din_S(9) XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(4) <= din_S(0) XOR din_S(5) XOR din_S(14) XOR din_S(23) XOR din_S(9) XOR din_S(18) XOR din_S(27) \r
+ XOR crc_feedback_S(3);
+crc_S(5) <= din_S(0) XOR din_S(6) XOR din_S(15) XOR din_S(24) XOR crc_feedback_S(0) XOR din_S(9) \r
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(6) <= din_S(0) XOR din_S(7) XOR din_S(16) XOR din_S(25) XOR crc_feedback_S(1) XOR din_S(9) \r
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+crc_S(7) <= din_S(0) XOR din_S(8) XOR din_S(17) XOR din_S(26) XOR crc_feedback_S(2) XOR din_S(9) \r
+ XOR din_S(18) XOR din_S(27) XOR crc_feedback_S(3);
+
+crc_process : process(clock, reset)
+begin\r
+ if (rising_edge(clock)) then
+ if (reset = '1') then
+ crc_error <= '0';
+ start_on_next_S <= '1';\r
+ data_out_valid <= '0';
+ data_out_last <= '0';\r
+ crc_aftr1clk_S <= "00000000" ;\r
+ else
+ if (data_in_valid = '1') then
+ crc_aftr1clk_S <= crc_S;
+ data_out_valid <= '1';
+ if (data_in_last = '1') then
+ start_on_next_S <= '1';\r
+ data_out_last <= '1';\r
+ data_out(31 downto 8) <= data_in(31 downto 8);
+ data_out(7 downto 0) <= crc_S;\r
+ if crc_S/=data_in(7 downto 0) then\r
+ crc_error <= '1';\r
+ else\r
+ crc_error <= '0';
+ end if;
+ else
+ data_out(31 downto 0) <= data_in(31 downto 0);
+ start_on_next_S <= '0';
+ crc_error <= '0';
+ data_out_last <= '0';\r
+ end if;\r
+ else
+ crc_error <= '0';
+ data_out_valid <= '0';
+ data_out_last <= '0';\r
+ end if; \r
+ end if;
+ end if;
+end process crc_process;
+
+
+end behaviour;
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+----------------------------------------
+-- Conditional adder
+-- op_a + op_b or only op_a depending on sel
+--
+----------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity cond_adder is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end cond_adder;
+
+architecture simple_arch of cond_adder is
+
+begin
+ anAdder: process (sel,op_a,op_b)
+ begin
+ if sel = '1' then
+ outp <= op_a + op_b;
+ else
+ outp <= op_a;
+ end if;
+ end process;
+end simple_arch;
+
--- /dev/null
+-----------------------------------------------------------------------
+---- Pipelined radix 4 Divisor based on Arch2 (half arch)
+---- A, and B naturals (non negative integers) with XBITS and YBITS width
+---- there is no restriction XBITS >= YBITS.
+---- Return quotient Q of XBITS and remainder R of NBITS
+---- GRAIN defines the amount of bits computed at each cycle.
+----
+---- The circuit captures operands at each cycle
+---- The algorithm needs XBITS/GRAIN/DEPTH + 1 cylcles to calculate the quotient
+---- and remainder (Latency). Its posible to obtain the result one cycle before.
+---- GRAIN = 2 for that radix 4 divider
+---- DEPTH (logic depth) every how many basic cell we register.
+---- DEPTH = 1 maximun pipeline
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity div_r4_pipe is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32;
+ GRAIN : natural := 2;
+ DEPTH : natural := 8
+ );
+ port (
+ A: in STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ B: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ clk: in STD_LOGIC;
+ Q: out STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ R: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+end div_r4_pipe;
+
+architecture simple_arch of div_r4_pipe is
+
+ component cond_adder is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ sel: in STD_LOGIC;
+ outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+ );
+ end component;
+
+ component nr_r4_half_cell is
+ generic (
+ XBITS : natural := XBITS;
+ YBITS : natural := YBITS
+ );
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+ end component;
+\r
+
+ type connectionmatrix is array (0 to GRAIN) of STD_LOGIC_VECTOR (YBITS downto 0);
+ Signal iR, reg_Y_rem: STD_LOGIC_VECTOR (YBITS-1 downto 0);
+ Signal iQ: STD_LOGIC_VECTOR (XBITS-1 downto 0);\r
+
+ type matrix_rem is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal rem_in, rem_out: matrix_rem := (others => (others => '0'));
+ type matrix_Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+ signal reg_Y: matrix_Y := (others => (others => '0'));
+ type matrix_3Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal reg_3Y: matrix_3Y := (others => (others => '0'));
+ type matrix_X is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_X: matrix_X := (others => (others => '0'));
+ type matrix_Q is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+ signal reg_Q: matrix_Q := (others => (others => '0'));
+
+signal rem_no_adj: STD_LOGIC_VECTOR (YBITS downto 0);
+
+--attribute keep_hierarchy: string;
+--attribute keep_hierarchy of low_level_arch: architecture is "yes";
+--attribute IOB: string;
+--attribute IOB of low_level_arch: architecture is "FALSE";
+
+begin
+
+ FF_0: process (clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ reg_Y(0) <= ('0' & B);
+ reg_3Y(0) <= ('0' & B) + ('0' & B & '0');
+ reg_X(0) <= A;
+ --Q <= not reg_Q(XBITS/GRAIN-1); --ito obtain the result a cycle before\r
+ Q <= iQ; iQ <= not reg_Q(XBITS/GRAIN-1);
+ rem_no_adj <= rem_out(XBITS/GRAIN-1);\r
+ reg_Y_rem <= reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0);
+ R <= iR;
+ end if;
+ end process;
+
+
+ rem_in(0) <= (others => '0');
+
+ g1: for i in 0 to XBITS/GRAIN -1 generate
+ cell: nr_r4_half_cell port map( op_r => rem_in(i),
+ op_y => reg_Y(i), op_3y => reg_3Y(i),
+ x_1 => reg_X(i)(XBITS-1-i*2), x_0 => reg_X(i)(XBITS-2-i*2),
+ n_qneg => reg_Q(i)(XBITS-1-i*2 downto XBITS-2-i*2), new_r => rem_out(i) );
+ end generate;
+
+ g2: for i in 0 to XBITS/GRAIN-2 generate
+ g2c: if (i+1) mod DEPTH /= 0 generate
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end generate;
+ g2FF: if (i+1) mod DEPTH = 0 generate
+ FFs: process(clk)
+ begin
+ if CLK'event and CLK='1' then --CLK rising edge
+ rem_in(i+1) <= rem_out(i);
+ reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+ reg_X(i+1) <= reg_X(i);
+ reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2);
+ end if;
+ end process;
+ end generate;
+ end generate;
+
+
+-- use this code to obtain the remainder a cycle before\r
+-- final_rem_Adjust: cond_adder port map (op_a => rem_out(XBITS/GRAIN-1)(YBITS-1 downto 0),
+-- op_b => reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0),\r
+-- sel => rem_out(XBITS/GRAIN-1)(YBITS), outp => iR);\r
+\r
+
+ final_rem_Adjust: cond_adder port map (op_a => rem_no_adj(YBITS-1 downto 0),
+ op_b => reg_Y_rem(YBITS-1 downto 0),
+ sel => rem_no_adj(YBITS), outp => iR);
+\r
+
+end simple_arch;
--- /dev/null
+-------------------------------------
+-- Defines the dataPath width
+--
+-------------------------------------
+package mypackage is
+ constant XBITS :INTEGER := 32;
+ constant YBITS :INTEGER := 32;
+ constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+ constant DEPTH :INTEGER := 1; --Every how much steps register
+end mypackage;
--- /dev/null
+--------------------------------------------------------
+--
+-- Basic cell radix 4 arch 2. divider
+--------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+use work.mypackage.all;
+
+entity nr_r4_half_cell is
+ generic (
+ XBITS : natural := 32;
+ YBITS : natural := 32
+ );
+ --generic(pos_x: integer:= 0; pos_y: integer := 0; agroup: string:= "cell_r4");
+ port (
+ op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+ op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ x_1: in STD_LOGIC;
+ x_0: in STD_LOGIC;
+ n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+ new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+ );
+end nr_r4_half_cell;
+
+architecture half of nr_r4_half_cell is
+ signal op_4r: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal a2_pm_b, a4_pm_b, a4_pm_3b: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+ signal sr: STD_LOGIC;
+begin
+ sr <= op_r(YBITS);
+ op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0;
+
+ a2_pm_b <= (op_r & x_1) + (op_y) when sr = '1' else (sr & op_y) + not (op_r & x_1);
+ a4_pm_3b <= (op_4r + op_3y) when sr = '1' else (op_4r) - (op_3y);
+ a4_pm_b <= (op_4r + op_y) when sr = '1' else (op_4r) - (sr & op_y);
+
+ mux_outps: process (a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if a2_pm_b(YBITS)= '1' then
+ new_r <= a4_pm_3b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_3b(YBITS);
+ else
+ new_r <= a4_pm_b(YBITS downto 0);
+ n_qneg(0) <= a4_pm_b(YBITS);
+ end if;
+ end process;
+
+ mux_nqb: process (sr,a2_pm_b, a4_pm_b, a4_pm_3b)
+ begin
+ if sr = '1' then --11
+ n_qneg(1) <= a2_pm_b(YBITS);
+ else
+ n_qneg(1) <= not a2_pm_b(YBITS);
+ end if;
+
+ end process;
+
+end half;
--- /dev/null
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 20-04-2008
+-- Module Name: iirfilter_1order_selectBW
+-- Description: First order Infinite respons filter
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+\r
+------------------------------------------------------------------------------------------------------
+-- iirfilter_1order_selectBW
+-- First order Infinite Impulse Response filter with inhibit
+-- Description can be found at http://www.beis.de/Elektronik/Filter/AnaDigFilt/AnaDigFilt.html
+--
+-- generics
+-- ADCBITS : number of ADC bits
+-- BWBITS : number of bits for the IIR filter bandwidth
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- data_in : ADC sampling data
+-- BWidx : factor for BW; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
+-- inhibit : freezes filter
+--
+-- outputs
+-- data_out : filtered output, rounded. Same number of bits as input
+--
+------------------------------------------------------------------------------------------------------
+
+
+entity iirfilter_1order_selectBW is
+ generic (
+ ADCBITS : natural := 16;
+ BWBITS : natural := 10
+ );
+ Port (\r
+ clock : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector ((ADCBITS-1) downto 0);
+ BWidx : in std_logic_vector (2 downto 0);
+ inhibit : in std_logic;
+ data_out : out std_logic_vector ((ADCBITS-1) downto 0));
+end iirfilter_1order_selectBW;
+
+architecture Behavioral of iirfilter_1order_selectBW is
+signal data_x_BW : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_out_multiplied : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal BWidx_i : integer range 0 to 7 := 0;
+
+begin
+
+process(clock)
+variable data_out_unscaled : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+begin
+ if rising_edge(clock) then
+ if reset='1' then
+ data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
+ data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
+ data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
+ data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ data_x_BW <= (others => '0');
+ data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+ data_out <= data_in;
+ else
+ if inhibit='0' then
+ data_out_unscaled := data_x_BW + data_out_unscaled_delayed-data_out_multiplied;
+
+ data_out_multiplied <= (others => '0');
+ data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
+
+ data_x_BW <= (others => '0');
+ data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+
+ data_out_unscaled_delayed <= data_out_unscaled;
+ data_out <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
+ end if;
+ end if;
+ end if;
+end process;\r
+
+BWidx_i <= conv_integer(unsigned(BWidx));
+
+end Behavioral;
+
--- /dev/null
+-----------------------------------------------------------------------------------\r
+-- posedge_to_pulse\r
+-- Makes pulse with duration 1 clock-cycle from positive edge\r
+-- \r
+-- inputs\r
+-- clock_in : clock input for input signal\r
+-- clock_out : clock input to synchronize to\r
+-- en_clk : clock enable\r
+-- signal_in : rising edge of this signal will result in pulse\r
+--\r
+-- output\r
+-- pulse : pulse output : one clock cycle '1'\r
+--\r
+-----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.all;\r
+use IEEE.STD_LOGIC_ARITH.all;\r
+use IEEE.STD_LOGIC_UNSIGNED.all;\r
+\r
+entity posedge_to_pulse is\r
+ port (\r
+ clock_in : in std_logic;\r
+ clock_out : in std_logic;\r
+ en_clk : in std_logic;\r
+ signal_in : in std_logic;\r
+ pulse : out std_logic\r
+ );\r
+end posedge_to_pulse;\r
+\r
+architecture behavioral of posedge_to_pulse is\r
+\r
+ signal resetff : std_logic := '0';\r
+ signal last_signal_in : std_logic := '0';\r
+ signal qff : std_logic := '0'; \r
+ signal qff1 : std_logic := '0'; \r
+ signal qff2 : std_logic := '0'; \r
+ signal qff3 : std_logic := '0'; \r
+begin \r
+\r
+process (clock_in)\r
+begin\r
+ if rising_edge(clock_in) then\r
+ if resetff='1' then\r
+ qff <= '0';\r
+ elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then \r
+ qff <= '1';\r
+ else\r
+ qff <= qff;\r
+ end if;\r
+ last_signal_in <= signal_in;\r
+ end if;\r
+end process;\r
+resetff <= qff2;\r
+\r
+process (clock_out)\r
+begin\r
+ if rising_edge(clock_out) then\r
+ if qff3='0' and qff2='1' then \r
+ pulse <= '1'; \r
+ else \r
+ pulse <= '0';\r
+ end if;\r
+ qff3 <= qff2;\r
+ qff2 <= qff1;\r
+ qff1 <= qff;\r
+ end if;\r
+end process; \r
+\r
+\r
+end behavioral;\r
+\r
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 22-02-2009
+-- Module Name: shift_register
+-- Description: Shifts data for an adjustable number of clock cycles
+----------------------------------------------------------------------------------\r
+\r
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+------------------------------------------------------------------------------------------------------
+-- shift_register
+-- Shifts data for an adjustable number of clock cycles
+--
+-- generics
+-- width : number of bits for the data to shift
+-- depthbits : number of bits for the number of clock cycles to shift
+--
+-- inputs
+-- clock : ADC sampling clock
+-- reset : synchrounous reset
+-- hold : hold all values
+-- data_in : data to shift
+-- depth : number of clock cycles to shift for
+--
+-- outputs
+-- data_out : shifted data
+--
+------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity shift_register is
+ generic (
+ width : natural := 16;
+ depthbits : natural := 9
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;
+ hold : in std_logic;
+ data_in : in std_logic_vector((width-1) downto 0);
+ depth : in std_logic_vector((depthbits-1) downto 0);
+ data_out : out std_logic_vector((width-1) downto 0));
+end shift_register;
+
+architecture behavior of shift_register is
+
+type arrtype is array((2**depthbits-1) downto 0) of std_logic_vector((width-1) downto 0);
+signal mem : arrtype; -- := (others => (others => '0'));
+signal outptr : std_logic_vector((depthbits-1) downto 0) := (others => '0');
+signal mem_out : std_logic_vector((width-1) downto 0) := (others => '0');
+signal lastreset : std_logic := '0';
+
+attribute syn_ramstyle : string;
+attribute syn_ramstyle of mem : signal is "block_ram";
+
+begin
+
+data_out <= mem_out;
+process (clock)
+begin
+ if rising_edge(clock) then\r
+ if hold='0' then
+ mem(conv_integer(unsigned(outptr + depth))) <= data_in;
+ if reset = '1' then
+ mem_out <= (others => '0');
+ if lastreset='0' then
+ outptr <= (others => '0');
+ else
+ outptr <= outptr+1;
+ end if;
+ else
+ mem_out <= mem(conv_integer(unsigned(outptr)));
+ outptr <= outptr+1;
+ end if;
+ lastreset <= reset;\r
+ end if;
+ end if;
+end process;
+
+end behavior;
--- /dev/null
+-----------------------------------------------------------------------------------------------\r
+-- © Copyright 2007 - 2009, Xilinx, Inc. All rights reserved.\r
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
+-- protected under U.S. and international copyright and other intellectual property laws.\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+-- Disclaimer:\r
+-- This disclaimer is not a license and does not grant any rights to the materials\r
+-- distributed herewith. Except as otherwise provided in a valid license issued to you\r
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+-- negligence, or under any other theory of liability) for any loss or damage of any\r
+-- kind or nature related to, arising under or in connection with these materials,\r
+-- including for any direct, or any indirect, special, incidental, or consequential\r
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
+-- damage suffered as a result of any action brought by a third party) even if such\r
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+--\r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
+-- application requiring fail-safe performance, such as life-support or safety devices\r
+-- or systems, Class III medical devices, nuclear facilities, applications related to\r
+-- the deployment of airbags, or any other applications that could lead to death,\r
+-- personal injury, or severe property or environmental damage (individually and\r
+-- collectively, "Critical Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical Applications, subject only to\r
+-- applicable laws and regulations governing limitations on product liability.\r
+--\r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
+--\r
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version: \r
+-- \ \ Filename: AdcClock.vhd\r
+-- / / Date Last Modified: 16 Jun 09\r
+-- /___/ /\ Date Created: 08/06/06\r
+-- \ \ / \\r
+-- \___\/\___\\r
+-- \r
+-- Device: Virtex-6\r
+-- Author: Marc Defossez\r
+-- Entity Name: AdcClock\r
+-- Purpose: High-speed local clock control for an interface between a FPGA and a\r
+-- Texas Instruments ADC.\r
+-- Tools: ISE - XST\r
+-- Limitations: none\r
+--\r
+-- Revision History:\r
+-- Rev. \r
+--\r
+-----------------------------------------------------------------------------------------------\r
+-- Naming Conventions:\r
+-- active low signals: "*_n"\r
+-- clock signals: "clk", "clk_div#", "clk_#x"\r
+-- reset signals: "rst", "rst_n"\r
+-- generics: "C_*"\r
+-- user defined types: "*_TYPE"\r
+-- state machine next state: "*_ns"\r
+-- state machine current state: "*_cs"\r
+-- combinatorial signals: "*_com"\r
+-- pipelined or register delay signals: "*_d#"\r
+-- counter signals: "*cnt*"\r
+-- clock enable signals: "*_ce"\r
+-- internal version of output port: "*_i"\r
+-- device pins: "*_pin"\r
+-- ports: "- Names begin with Uppercase"\r
+-- processes: "*_PROCESS"\r
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+library IEEE;\r
+ use IEEE.std_logic_1164.all;\r
+ use IEEE.std_logic_UNSIGNED.all;\r
+ use IEEE.std_logic_arith.all;\r
+library UNISIM;\r
+ use UNISIM.VCOMPONENTS.all;\r
+-----------------------------------------------------------------------------------------------\r
+-- Entity pin description\r
+-----------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------\r
+entity AdcClock is\r
+ generic (\r
+ C_BufioLoc : string := "BUFIODQS_X0Y12";\r
+ C_BufrLoc : string := "BUFR_X0Y6";\r
+ C_AdcBits : integer := 16;\r
+ C_StatTaps : integer := 16\r
+ );\r
+ port (\r
+ BitClk : in std_logic;\r
+ BitClkRst : in std_logic;\r
+ BitClkEna : in std_logic;\r
+ BitClkReSync : in std_logic;\r
+ BitClkDivReset : in std_logic;\r
+ BitClk_MonClkOut : out std_logic; -- CLK output\r
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input\r
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output\r
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input\r
+ BitClkAlignWarn : out std_logic;\r
+ BitClkInvrtd : out std_logic;\r
+ BitClkDone : out std_logic\r
+ );\r
+end AdcClock;\r
+-----------------------------------------------------------------------------------------------\r
+-- Arcitecture section\r
+-----------------------------------------------------------------------------------------------\r
+architecture AdcClock_struct of AdcClock is\r
+-----------------------------------------------------------------------------------------------\r
+-- Component Instantiation\r
+-----------------------------------------------------------------------------------------------\r
+-- Components are instantiated by means / through the use of library references.\r
+-----------------------------------------------------------------------------------------------\r
+-- Constants, Signals and Attributes Declarations\r
+-----------------------------------------------------------------------------------------------\r
+-- Constants\r
+constant Low : std_logic := '0';\r
+constant LowNibble : std_logic_vector(4 downto 0) := "00000";\r
+constant High : std_logic := '1';\r
+-- Signals\r
+signal IntBitClkRst : std_logic;\r
+---------- ISRDS signals ------------------\r
+signal IntClkCtrlDlyCe : std_logic;\r
+signal IntClkCtrlDlyInc : std_logic;\r
+signal IntClkCtrlDlyRst : std_logic;\r
+\r
+signal IntBitClk_Ddly : std_logic;\r
+signal IntBitClk : std_logic;\r
+signal IntClkCtrlIsrdsMtoS1 : std_logic;\r
+signal IntClkCtrlIsrdsMtoS2 : std_logic;\r
+signal IntClkCtrlOut : std_logic_vector(7 downto 0);\r
+---------- Controller signals -------------\r
+signal IntCal : std_logic;\r
+signal IntVal : std_logic;\r
+signal IntCalVal : std_logic_vector (1 downto 0);\r
+signal IntProceedCnt : std_logic_vector (2 downto 0);\r
+signal IntproceedCntTc : std_logic;\r
+signal IntproceedCntTc_d : std_logic;\r
+signal IntProceed : std_logic;\r
+signal IntProceedDone : std_logic;\r
+\r
+type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);\r
+signal State : StateType;\r
+signal ReturnState : StateType;\r
+\r
+signal PassedSubState : std_logic;\r
+signal IntNumIncDecIdly : std_logic_vector (3 downto 0);\r
+signal IntAction : std_logic_vector (1 downto 0);\r
+signal IntClkCtrlDone : std_logic;\r
+signal IntClkCtrlAlgnWrn : std_logic;\r
+signal IntClkCtrlInvrtd : std_logic;\r
+signal IntTurnAroundBit : std_logic;\r
+signal IntCalValReg : std_logic_vector (1 downto 0);\r
+signal IntTimeOutCnt : std_logic_vector (3 downto 0);\r
+signal IntStepCnt : std_logic_vector (3 downto 0);\r
+-- Attributes\r
+attribute LOC : string;\r
+ attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;\r
+-- The BUFR is generated through a generate statement and therefore the LOC attribute\r
+-- must be place into the generate statement.\r
+-- See the BUFR generation down in the source code.\r
+-----------------------------------------------------------------------------------------------\r
+signal reset_clockdiv_S : std_logic;\r
+ \r
+ \r
+begin\r
+-----------------------------------------------------------------------------------------------\r
+-- Bit clock capture ISERDES Master-Slave combination\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+AdcClock_I_Iodly : IODELAYE1\r
+ generic map (\r
+ SIGNAL_PATTERN => "CLOCK",\r
+ REFCLK_FREQUENCY => 200.0, \r
+ HIGH_PERFORMANCE_MODE => TRUE,\r
+ DELAY_SRC => "I",\r
+ CINVCTRL_SEL => FALSE,\r
+ IDELAY_TYPE => "VARIABLE",\r
+ IDELAY_VALUE => C_StatTaps,\r
+ ODELAY_TYPE => "FIXED",\r
+ ODELAY_VALUE => 0\r
+ )\r
+ port map (\r
+ DATAIN => Low, -- in input from FPGA fabric\r
+ IDATAIN => BitClk, -- in input from IOB\r
+ ODATAIN => Low, -- in input from I/O SERDES\r
+ CLKIN => Low, -- in input from BUFIO. BUFG, or BUFR\r
+ CE => IntClkCtrlDlyCe, -- in\r
+ INC => IntClkCtrlDlyInc, -- in\r
+ C => BitClk_RefClkIn, -- in\r
+ RST => IntClkCtrlDlyRst, -- in \r
+ T => Low, -- in\r
+ DATAOUT => IntBitClk_Ddly, -- out Delayed data\r
+ CINVCTRL => Low, -- in\r
+ CNTVALUEIN => LowNibble, -- in [4:0]\r
+ CNTVALUEOUT => open -- out [4:0]\r
+ );\r
+IntClkCtrlDlyRst <= BitClkRst;\r
+--\r
+AdcClock_I_Isrds_Master : ISERDESE1\r
+ generic map (\r
+ SERDES_MODE => "MASTER", -- \r
+ INTERFACE_TYPE => "NETWORKING",-- \r
+ IOBDELAY => "IBUF", -- \r
+ DATA_RATE => "SDR", -- \r
+ DATA_WIDTH => 8, --\r
+ DYN_CLKDIV_INV_EN => FALSE, -- \r
+ DYN_CLK_INV_EN => FALSE, -- \r
+ NUM_CE => 1, -- \r
+ OFB_USED => FALSE -- \r
+ )\r
+ port map (\r
+ D => BitClk, -- in Clock from clock input IBUFDS\r
+ DDLY => IntBitClk_Ddly, -- in\r
+ DYNCLKDIVSEL => Low, -- in\r
+ DYNCLKSEL => Low, -- in\r
+ OFB => Low, -- in\r
+ BITSLIP => Low, -- in !!!!!\r
+ CE1 => BitClkEna, -- in\r
+ CE2 => Low, -- in\r
+ RST => IntBitClkRst, -- in\r
+ CLK => BitClk_MonClkIn, -- in Clock from BUFIO.O = BitClk\r
+ CLKB => Low, -- in\r
+ CLKDIV => BitClk_RefClkIn, -- in Clock from BUFR.O = BitClkDiv\r
+ OCLK => Low, -- in\r
+ SHIFTOUT1 => IntClkCtrlIsrdsMtoS1,-- out\r
+ SHIFTOUT2 => IntClkCtrlIsrdsMtoS2,-- out\r
+ O => IntBitClk, -- out Clock to BUFIO.I\r
+ Q1 => IntClkCtrlOut(0), -- out\r
+ Q2 => IntClkCtrlOut(1), -- out\r
+ Q3 => IntClkCtrlOut(2), -- out\r
+ Q4 => IntClkCtrlOut(3), -- out\r
+ Q5 => IntClkCtrlOut(4), -- out\r
+ Q6 => IntClkCtrlOut(5), -- out\r
+ SHIFTIN1 => Low, -- in\r
+ SHIFTIN2 => Low -- in\r
+ );\r
+--\r
+AdcClock_I_Isrds_Slave : ISERDESE1\r
+ generic map (\r
+ SERDES_MODE => "SLAVE", -- \r
+ INTERFACE_TYPE => "NETWORKING",-- \r
+ IOBDELAY => "NONE", -- \r
+ DATA_RATE => "SDR", -- \r
+ DATA_WIDTH => 8, --\r
+ DYN_CLKDIV_INV_EN => FALSE, -- \r
+ DYN_CLK_INV_EN => FALSE, -- \r
+ NUM_CE => 1, -- \r
+ OFB_USED => FALSE -- \r
+ )\r
+ port map (\r
+ D => Low, -- in\r
+ DDLY => Low, -- in\r
+ DYNCLKDIVSEL => Low, -- in\r
+ DYNCLKSEL => Low, -- in\r
+ OFB => Low, -- in\r
+ BITSLIP => Low, -- in !!!!!\r
+ CE1 => BitClkEna, -- in\r
+ CE2 => Low, -- in\r
+ RST => IntBitClkRst, -- in\r
+ CLK => BitClk_MonClkIn, -- in\r
+ CLKB => Low, -- in\r
+ CLKDIV => BitClk_RefClkIn, -- in\r
+ OCLK => Low, -- in\r
+ SHIFTOUT1 => open, -- out\r
+ SHIFTOUT2 => open, -- out\r
+ O => open, -- out\r
+ Q1 => open, -- out\r
+ Q2 => open, -- out\r
+ Q3 => IntClkCtrlOut(6), -- out\r
+ Q4 => IntClkCtrlOut(7), -- out\r
+ Q5 => open, -- out\r
+ Q6 => open, -- out\r
+ SHIFTIN1 => IntClkCtrlIsrdsMtoS1,-- in\r
+ SHIFTIN2 => IntClkCtrlIsrdsMtoS2 -- in\r
+ );\r
+-- Input from ISERDES.O -- Output and CLK for all ISERDES\r
+AdcClock_I_Bufio : BUFIO\r
+ port map (I => IntBitClk, O => BitClk_MonClkOut);\r
+--\r
+Gen_Bufr_Div_3 : if (C_AdcBits = 12) generate\r
+ attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;\r
+begin\r
+ AdcClock_I_Bufr : BUFR\r
+ generic map (BUFR_DIVIDE => "3", SIM_DEVICE => "VIRTEX6") -- 12-bit = DIV by 3\r
+-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.\r
+ port map (I => IntBitClk, O => BitClk_RefClkOut,\r
+ CE => High, CLR => BitClkDivReset);\r
+end generate;\r
+--\r
+Gen_Bufr_Div_4 : if (C_AdcBits /= 12) generate\r
+ attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;\r
+begin\r
+ AdcClock_I_Bufr : BUFR\r
+ generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "VIRTEX6") -- 14- and 16-bit = DIV by 4\r
+-- ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.\r
+ port map (I => IntBitClk, O => BitClk_RefClkOut,\r
+ CE => High, CLR => BitClkDivReset);\r
+end generate;\r
+\r
+\r
+-----------------------------------------------------------------------------------------------\r
+-- Bit clock re-synchronizer\r
+-----------------------------------------------------------------------------------------------\r
+IntBitClkRst <= BitClkRst or BitClkReSync;\r
+-----------------------------------------------------------------------------------------------\r
+-- Bit clock controller for clock alignment input.\r
+-----------------------------------------------------------------------------------------------\r
+-- This input section makes sure 64 bits are captured before action is taken to pass to\r
+-- the statemachine for evaluation.\r
+-- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel\r
+-- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.\r
+-- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)\r
+-- into an intermediate register (IntCalVal).\r
+--\r
+-- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.\r
+-- IntVal = '1' when all outputs are '0' or '1'.\r
+--\r
+IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and\r
+ IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and\r
+ IntClkCtrlOut(1) and IntClkCtrlOut(0);\r
+IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';\r
+--\r
+AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)\r
+begin\r
+ if (IntBitClkRst = '1') then\r
+ IntProceedCnt <= (others => '0');\r
+ IntProceedCntTc_d <= '0';\r
+ IntCalVal <= (others => '0');\r
+ IntProceed <= '0';\r
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then\r
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then\r
+ IntProceedCnt <= IntProceedCnt + 1;\r
+ IntProceedCntTc_d <= IntProceedCntTc;\r
+ if (IntProceedCntTc_d = '1') then\r
+ IntCalVal <= IntCal & IntVal;\r
+ end if;\r
+ if (IntProceedCntTc_d = '1') then\r
+ IntProceed <= '1';\r
+ elsif (IntProceedDone = '1') then\r
+ IntProceed <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';\r
+-----------------------------------------------------------------------------------------------\r
+-- Bit clock controller for clock alignment state machine.\r
+-----------------------------------------------------------------------------------------------\r
+BitClkAlignWarn <= IntClkCtrlAlgnWrn;\r
+BitClkInvrtd <= IntClkCtrlInvrtd;\r
+BitClkDone <= IntClkCtrlDone;\r
+\r
+AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)\r
+subtype ActCalVal is std_logic_vector (4 downto 0);\r
+begin\r
+ if (IntBitClkRst = '1') then\r
+ State <= Idle;\r
+ ReturnState <= Idle;\r
+ PassedSubState <= '0';\r
+ --\r
+ IntNumIncDecIdly <= "0000"; -- Max. 16\r
+ IntAction <= "00"; \r
+ IntClkCtrlDlyInc <= '1';\r
+ IntClkCtrlDlyCe <= '0';\r
+ IntClkCtrlDone <= '0';\r
+ IntClkCtrlAlgnWrn <= '0';\r
+ IntClkCtrlInvrtd <= '0';\r
+ IntTurnAroundBit <= '0';\r
+ IntProceedDone <= '0';\r
+ IntClkCtrlDone <= '0';\r
+ IntCalValReg <= (others => '0'); -- 2-bit\r
+ IntTimeOutCnt <= (others => '0'); -- 4-bit\r
+ IntStepCnt <= (others => '0'); -- 4-bit (16)\r
+ elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then\r
+ if (BitClkEna = '1' and IntClkCtrlDone = '0') then\r
+ case State is \r
+ when Idle =>\r
+ IntProceedDone <= '0';\r
+ PassedSubState <= '0';\r
+ case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is\r
+ when "00001" => State <= A;\r
+ when "01001" => State <= B;\r
+ when "10001" => State <= B;\r
+ when "11001" => State <= B;\r
+ when "01111" => State <= C;\r
+ when "01101" => State <= D;\r
+ when "01011" => State <= D;\r
+ when "00011" => State <= E;\r
+ when "00101" => State <= E;\r
+ when "00111" => State <= E;\r
+ when "10011" => State <= F;\r
+ when "11011" => State <= F;\r
+ when "10101" => State <= F;\r
+ when "11101" => State <= F;\r
+ when "10111" => State <= F;\r
+ when "11111" => State <= F;\r
+ when others => State <= Idle;\r
+ end case;\r
+ when A => -- First time and sampling in jitter or cross area.\r
+ IntAction <= "01"; -- Set the action bits and go to next step.\r
+ State <= B;\r
+ when B => -- Input is samples in jitter or clock cross area.\r
+ if (PassedSubState = '1') then\r
+ PassedSubState <= '0'; -- Clear the pass through the substate bit.\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ State <= Idle; -- Return for a new sample of the input.\r
+ elsif (IntTimeOutCnt = "1111") then -- When arriving here something is wrong.\r
+ IntTimeOutCnt <= "0000"; -- Reset the counter.\r
+ IntAction <= "00"; -- reset the action bits.\r
+ IntClkCtrlAlgnWrn <= '1'; -- Raise a FLAG.\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ State <= Idle; -- Retry, return for new sample of input.\r
+ else\r
+ IntTimeOutCnt <= IntTimeOutCnt + 1;\r
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
+ ReturnState <= State; -- This state is the state to return too.\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
+ end if;\r
+ when C => -- After first sample, jitter or cross, is now high.\r
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
+ ReturnState <= Done; -- This state is the state to return too.\r
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement.\r
+ State <= IdlyIncDec;\r
+ when D => -- Same as C but with indication of 180-deg shift.\r
+ IntClkCtrlInvrtd <= '1';\r
+ State <= C;\r
+ when E => -- First saple with valid data.\r
+ IntCalValReg <= IntCalVal; -- Register the sampled value\r
+ IntAction <= "10";\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
+ ReturnState <= Idle; -- When increment is done return sampling.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment\r
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
+ when F => -- Next samples with valid data.\r
+ if (IntCalVal /= IntCalValReg) then\r
+ State <= G; -- The new CalVal value is different from the first.\r
+ else\r
+ if (IntStepCnt = "1111") then -- Step counter at the end, 15\r
+ if (IntTurnAroundBit = '0') then \r
+ State <= H; -- No edge found and first time here.\r
+ elsif (IntCalValReg = "11") then\r
+ State <= K; -- A turnaround already happend.\r
+ else -- No edge is found (large 1/2 period).\r
+ State <= K1; -- Move the clock edge to near the correct\r
+ end if; -- edge.\r
+ else\r
+ IntStepCnt <= IntStepCnt + 1;\r
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ ReturnState <= Idle; -- When increment is done return sampling.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment\r
+ State <= IdlyIncDec; -- Jump to Increment/decrement sub-state.\r
+ end if;\r
+ end if;\r
+ when G =>\r
+ if (IntCalValReg /= "01") then\r
+ IntClkCtrlInvrtd <= '1';\r
+ State <= G1;\r
+ else\r
+ State <= G1;\r
+ end if;\r
+ when G1 =>\r
+ if (IntTimeOutCnt = "00") then\r
+ State <= Done;\r
+ else\r
+ IntNumIncDecIdly <= "0010"; -- Number increments or decrements to do.\r
+ ReturnState <= Done; -- After decrement it's finished.\r
+ IntClkCtrlDlyInc <= '0'; -- Set for decrement\r
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
+ end if;\r
+ when H =>\r
+ IntTurnAroundBit <= '1'; -- Indicate that the Idelay jumps to 0.\r
+ IntStepCnt <= IntStepCnt + 1; -- Set all registers to zero.\r
+ IntAction <= "00"; -- Take one step, let the counter flow over \r
+ IntCalValReg <= "00"; -- The idelay turn over to 0.\r
+ IntTimeOutCnt <= "0000"; -- Start sampling from scratch.\r
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
+ IntProceedDone <= '1'; -- Reset the proceed bit.\r
+ ReturnState <= Idle; -- After increment go sampling for new.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
+ when K =>\r
+ IntNumIncDecIdly <= "1111"; -- Number increments or decrements to do.\r
+ ReturnState <= K2; -- After increment it is done.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
+ when K1 =>\r
+ IntNumIncDecIdly <= "1110"; -- Number increments or decrements to do.\r
+ ReturnState <= K2; -- After increment it is done.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
+ when K2 =>\r
+ IntNumIncDecIdly <= "0001"; -- Number increments or decrements to do.\r
+ ReturnState <= Done; -- After increment it is done.\r
+ IntClkCtrlDlyInc <= '1'; -- Set for increment.\r
+ State <= IdlyIncDec; -- Jump to the Increment/decrement sub-state.\r
+ --\r
+ when IdlyIncDec => -- Increment or decrement by enable.\r
+ if (IntNumIncDecIdly /= "0000") then -- Check number of tap jumps\r
+ IntNumIncDecIdly <= IntNumIncDecIdly - 1; -- If not 0 jump and decrement.\r
+ IntClkCtrlDlyCe <= '1'; -- Do the jump. enable it.\r
+ else\r
+ IntClkCtrlDlyCe <= '0'; -- when it is enabled, disbale it\r
+ PassedSubState <= '1'; -- Set a check bit "I've been here and passed".\r
+ State <= ReturnState; -- Return to origin.\r
+ end if;\r
+ when Done => -- Alignment done.\r
+ IntClkCtrlDone <= '1'; -- Alignment is done.\r
+ end case;\r
+ end if;\r
+ end if;\r
+end process;\r
+--\r
+------------------------------------------------------------------------------------------------\r
+end AdcClock_struct;
\ No newline at end of file
--- /dev/null
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+-- negligence, or under any other theory of liability) for any loss or damage of any
+-- kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or
+-- damage suffered as a result of any action brought by a third party) even if such
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any
+-- application requiring fail-safe performance, such as life-support or safety devices
+-- or systems, Class III medical devices, nuclear facilities, applications related to
+-- the deployment of airbags, or any other applications that could lead to death,
+-- personal injury, or severe property or environmental damage (individually and
+-- collectively, "Critical Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical Applications, subject only to
+-- applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version:
+-- \ \ Filename: AdcData.vhd
+-- / / Date Last Modified: 15 Feb 2011
+-- /___/ /\ Date Created: 18 Dec 2007
+-- \ \ / \
+-- \___\/\___\
+--
+-- Device: Virtex-6
+-- Author: Marc Defossez
+-- Entity Name: AdcData
+-- Purpose: 2-channel ADC data receiver interface.
+-- The output of this module is alwasy fprmatted in 32-bit.
+-- When the interface is for a 12-bit ADC then the output is formatted as:
+-- 32 ---------- 16 , 15 ----------- 0
+-- 0000 & (12-bit) , 0000 & (12-bit)
+-- When the interface is for 14-bit or 16-bit the the ouput is formatted as:
+-- 32 ---------- 16 , 15 ----------- 0
+-- ( 16-bit ) , ( 16-bit )
+-- In 1-wire mode the 32-bit output shows two channels
+-- In 2-wire mode the 32-bit output shows two words of the same channel.
+--
+-- Tools: ISE_11.2.xx
+-- Limitations: none
+--
+-- Revision History:
+-- Rev 21 Jun 09
+-- Adaption to Virtex-6
+-- Rev 20 Oct 09
+-- Removal of the input buffers.
+-- FPGA is placed in a different hierarchical level for easyness of portability.
+-- Rev 28 Oct 09
+-- Removal of two mode options.
+-- C_AdcBytOrBitMode and C_AdcMsbOrLsbFst are now coded as default BYTE MODE and MSB FIRST
+-- This can still be changed by making the generics again available at higher HDL levels.
+-- Rev 09 Dec 2010
+-- Made sure the output of the interface is always FFs with enable.
+-- Therefore instantiated the FFs in staid of using plain VHDL descriptions.
+-- Rev 15 Feb 2011
+-- Review of implementation of the AdcData hierarchical level.
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+-- active low signals: "*_n"
+-- clock signals: "clk", "clk_div#", "clk_#x"
+-- reset signals: "rst", "rst_n"
+-- generics: "C_*"
+-- user defined types: "*_TYPE"
+-- state machine next state: "*_ns"
+-- state machine current state: "*_cs"
+-- combinatorial signals: "*_com"
+-- pipelined or register delay signals: "*_d#"
+-- counter signals: "*cnt*"
+-- clock enable signals: "*_ce"
+-- internal version of output port: "*_i"
+-- device pins: "*_pin"
+-- ports: "- Names begin with Uppercase"
+-- processes: "*_PROCESS"
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+ use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+entity AdcData is
+ generic (
+ C_AdcBits : integer := 16; -- Can be 12, 14 or 16
+ C_AdcBytOrBitMode : integer := 0; -- 1 = BIT mode, 0 = BYTE mode,
+ C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
+ C_AdcWireInt : integer := 1 -- 1 = 1-wire, 2 = 2-wire.
+ );
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatBitSlip_p : in std_logic;
+ DatBitSlip_n : in std_logic;
+ DatSwapMux : in std_logic;
+ DatMsbRegEna : in std_logic;
+ DatLsbRegEna : in std_logic;
+ DatReSync : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end AdcData;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcData_struct of AdcData is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-- Components are instantiated through library naming.
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Functions
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
+function DatBits (Bits : integer) return integer is
+variable Temp : integer;
+begin
+ if (Bits = 12) then
+ Temp := 12;
+ elsif (Bits = 14) then
+ Temp := 16;
+ elsif (Bits = 16) then
+ Temp := 16;
+ end if;
+return Temp;
+end function DatBits;
+-- Constants
+constant IntIsrdsDataWidth : integer := DatBits(C_AdcBits)/4;
+constant Low : std_logic := '0';
+constant High : std_logic := '1';
+-- Signals
+signal IntDatClk : std_logic;
+signal IntDatClk_n : std_logic;
+--
+-- ADC resolution = 12-bit: IntDatSrds0Out(5 downto 0) and IntDatSrds1Out(5 downto 0)
+-- ADC resolution = 14-bit or 16-bit: IntDatSrds0Out(7 downto 0) and IntDatSrds1Out(7 downto 0)
+signal IntDatSrds0Out : std_logic_vector(7 downto 0);
+signal IntDatSrds1Out : std_logic_vector(7 downto 0);
+signal IntDatSrds0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDatSrds1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1 : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1Mux : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat0Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDat1Swp : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
+signal IntDatSwpBus : std_logic_vector(31 downto 0);
+signal IntDatDone : std_logic;
+signal IntDatEna : std_logic;
+-- Attributes
+-----------------------------------------------------------------------------------------------
+begin
+--
+-- DatRst en DatEna are synchronised to DatClkDiv on a higher hierarchical level.
+-- the higher level is "AdcToplevel".
+AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
+begin
+ if (DatRst = High) then
+ IntDatDone <= Low;
+ elsif (DatClkDiv'event and DatClkDiv = '1') then
+ IntDatDone <= DatDone;
+ end if;
+end process;
+-- "IntDatDone" enables the ISERDES.
+-- "IntDatEna" is the enable for the logic behind the ISERDES.
+--
+IntDatEna <= High when (IntDatDone = High and DatEna = High) else Low;
+-----------------------------------------------------------------------------------------------
+IntDatClk <= DatClk; -- CLOCK FOR P-side ISERDES
+IntDatClk_n <= not DatClk; -- CLOCK FOR N_side ISERDES
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ZERO
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D0_p : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD0_p, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_p,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(6), -- out (0)
+ Q2 => IntDatSrds0Out(4), -- out (2)
+ Q3 => IntDatSrds0Out(2), -- out (4)
+ Q4 => IntDatSrds0Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+AdcData_I_Isrds_D0_n : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD0_n, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_n,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds0Out(7), -- out (1)
+ Q2 => IntDatSrds0Out(5), -- out (3)
+ Q3 => IntDatSrds0Out(3), -- out (5)
+ Q4 => IntDatSrds0Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ONE
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D1_p : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD1_p, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_p,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(6), -- out (0)
+ Q2 => IntDatSrds1Out(4), -- out (2)
+ Q3 => IntDatSrds1Out(2), -- out (4)
+ Q4 => IntDatSrds1Out(0), -- out (6)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+AdcData_I_Isrds_D1_n : ISERDESE1
+ generic map (
+ SERDES_MODE => "MASTER", --
+ INTERFACE_TYPE => "NETWORKING", --
+ IOBDELAY => "NONE", --
+ DATA_RATE => "SDR", --
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits
+ DYN_CLKDIV_INV_EN => FALSE, --
+ DYN_CLK_INV_EN => FALSE, --
+ NUM_CE => 1, --
+ OFB_USED => FALSE --
+ )
+ port map (
+ D => DatD1_n, -- in
+ DDLY => Low, -- in
+ DYNCLKDIVSEL => Low, -- in
+ DYNCLKSEL => Low, -- in
+ OFB => Low, -- in
+ BITSLIP => DatBitSlip_n,-- in
+ CE1 => IntDatDone, -- in
+ CE2 => Low, -- in
+ RST => DatRst, -- in
+ CLK => IntDatClk_n, -- in
+ CLKB => Low, -- in
+ CLKDIV => DatClkDiv, -- in
+ OCLK => Low, -- in
+ SHIFTOUT1 => open, -- out
+ SHIFTOUT2 => open, -- out
+ O => open, -- out
+ Q1 => IntDatSrds1Out(7), -- out (1)
+ Q2 => IntDatSrds1Out(5), -- out (3)
+ Q3 => IntDatSrds1Out(3), -- out (5)
+ Q4 => IntDatSrds1Out(1), -- out (7)
+ Q5 => open, -- out
+ Q6 => open, -- out
+ SHIFTIN1 => Low, -- in
+ SHIFTIN2 => Low -- in
+ );
+-----------------------------------------------------------------------------------------------
+Gen_1_DatBus : if (DatBits(C_AdcBits)/2) = 6 generate
+begin
+ IntDatSrds0 <= not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+ not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+ not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+ IntDatSrds1 <= not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+ not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+ not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+end generate;
+Gen_2_DatBus : if (DatBits(C_AdcBits)/2) = 8 generate
+begin
+ IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
+ not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+ not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+ not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+ IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
+ not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+ not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+ not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+end generate;
+-----------------------------------------------------------------------------------------------
+-- DATA REGISTER
+-----------------------------------------------------------------------------------------------
+Gen_1_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcData_I_Fdce_Reg0 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat0(n));
+ AdcData_I_Fdce_Reg1 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat1(n));
+end generate Gen_1_DatReg;
+-----------------------------------------------------------------------------------------------
+-- BIT SWAP MULTIPLEXER and REGISTER
+-- Swap the bits in correct order when the pattern detected is bit swapped.
+-----------------------------------------------------------------------------------------------
+Gen_2_DatMux : for n in (DatBits(C_AdcBits)/4)-1 downto 0 generate
+begin
+ IntDat0Mux((n*2)+1) <= IntDat0(n*2) when (DatSwapMux = '1') else IntDat0((n*2)+1);
+ IntDat0Mux(n*2) <= IntDat0((n*2)+1) when (DatSwapMux = '1') else IntDat0(n*2);
+ IntDat1Mux((n*2)+1) <= IntDat1(n*2) when (DatSwapMux = '1') else IntDat1((n*2)+1);
+ IntDat1Mux(n*2) <= IntDat1((n*2)+1) when (DatSwapMux = '1') else IntDat1(n*2);
+end generate Gen_2_DatMux;
+Gen_3_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
+ AdcData_I_Fdce_Reg2 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat0Swp(n));
+ AdcData_I_Fdce_Reg3 : FDCE
+ generic map (INIT => '0') -- bit
+ port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
+ Q => IntDat1Swp(n));
+end generate Gen_3_DatReg;
+-----------------------------------------------------------------------------------------------
+-- 1-WIRE, 12x SERIALIZATION for 12-bit ADCs
+-- The data from one ADC will show up in the output of one interface channel. It is so that the
+-- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel and
+-- bits 15:0 show the lower channel.
+-----------------------------------------------------------------------------------------------
+Gen_1w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 1) generate
+ -- 1-wire mode is only coded for BIT wise operation.
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+-- -- MSB first.
+-- -- Output : 31 16 15 0
+-- -- : "0000" & MSB(5:0) & LSB(5:0) "0000" & MSB(5:0) & LSB(5:0)
+ IntDatSwpBus <= "0000" & IntDat1Swp(5 downto 0) & IntDat1Swp(5 downto 0) &
+ "0000" & IntDat0Swp(5 downto 0) & IntDat0Swp(5 downto 0);
+ Gen_1_H : for n in 6 to 15 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ Gen_1_L : for n in 0 to 5 generate
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_L;
+ end generate;
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- LSB first.
+ -- Output : 31 22 & 21 16 & 15 6 & 5 0
+ -- : "0000" & LSB(0:5) & MSB(0:5) "0000" & LSB(0:5) & MSB(0:5)
+ IntDatSwpBus <= "0000" & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 31-|
+ IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-22
+ IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 21-|
+ IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & -- |-16
+ "0000" & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 15-|
+ IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5) & -- |-6
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 5-|
+ IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5); -- |-0
+ Gen_1_H : for n in 6 to 15 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ Gen_1_L : for n in 0 to 5 generate
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_L;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 12x SERIALIZATION for 12-bit ADCs
+-- Only one of these options can be chosen at a time.
+-- 2-wire, Msb-Bit or Msb-Byte
+-- 2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+Gen_2w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 2) generate
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ -- Bit mode, MSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D10, D8, D6, D4, D2, D0
+ -- Channel 1 : D11, D9, D7, D5, D3, D1
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_5, 0_5, 1_4, 0_4, 1_3, 0_3, 1_2, 0_2, 1_1, 0_1, 1_0, 0_0
+ Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & "0000"
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ -- Byte mode, MSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D5, D4, D3, D2, D1, D0
+ -- Channel 1 : D11, D10, D9, D8, D7, D6
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_5, 1_4, 1_3, 1_2, 1_1, 1_0, 0_5, 0_4, 0_3, 0_2, 0_1, 0_0
+ Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
+ & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0)
+ & "0000"
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
+ & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ end generate;
+--
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- Bit mode, LSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D0, D2, D4, D6, D8, D10
+ -- Channel 1 : D1, D3, D5, D7, D9, D11
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_0, 0_0, 1_1, 0_1, 1_2, 0_2, 1_3, 0_3, 1_4, 0_4, 1_5, 0_5
+ Gen_1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
+ & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
+ & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5)
+ & "0000"
+ & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
+ & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
+ & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ -- Byte Mode, LSB First
+ -- Bit : 5 4 3 2 1 0
+ -- Channel 0 : D0, D1, D2, D3, D4, D5
+ -- Channel 1 : D6, D7, D8, D9, D10, D11
+ -- Output : 0 0 0 0, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0
+ -- : 0 0 0 0, 1_0, 1_1, 1_2, 1_3, 1_4, 1_5, 0_0, 0_1, 0_2, 0_3, 0_4, 0_5
+ Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode
+ IntDatSwpBus <= "0000"
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
+ & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5)
+ & "0000"
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
+ & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5);
+ Gen_1_HL : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 1-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- The data from one ADC will show up in the output of one interface channel. It is so that the
+-- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel (CH_1)
+-- and bits 15:0 show the lower (CH_0) channel.
+-----------------------------------------------------------------------------------------------
+Gen_1w_1416b : if (C_AdcBits /= 12 and C_AdcWireInt = 1) generate
+ -- 1-wire is only coded for BIT wise operation
+ Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ IntDatSwpBus <= IntDat1Swp(7 downto 0) & IntDat1Swp(7 downto 0) &
+ IntDat0Swp(7 downto 0) & IntDat0Swp(7 downto 0);
+ Gen_1_HL : for n in 0 to 7 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+24));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+8));
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+ Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
+ IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
+ IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
+ IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
+ IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7) &
+ IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
+ IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7);
+ Gen_1_HL : for n in 0 to 7 generate
+ I_Fdce_HH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+24));
+ I_Fdce_HL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+8));
+ I_Fdce_LH : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_LL : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_HL;
+ end generate;
+end generate;
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- Only one of these options can be chosen at a time.
+-- 2-wire, Msb-Bit or Msb-Byte
+-- 2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+Gen_1416Bit : if (C_AdcBits /= 12 and C_AdcWireInt = 2) generate
+-- Shift in order is assumed MSB first.
+ Gen_2_Msb : if C_AdcMsbOrLsbFst = 0 generate
+ -- Bit mode, MSB First, 14-bits (16-bits)
+ -- Bit : 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : 0/(D14), D12, D10, D8, D6, D4, D2, D0
+ -- Channel 1 : 0/(D15), D13, D11, D9, D7, D5, D3, D1
+ Gen1_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+ & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+ & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+ & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ -- Byte Mode, MSB First, 14-bits (16-bits)
+ -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0,
+ -- Channel 0 : D7, D6, D5, D4, D3, D2, D1, D0,
+ -- Channel 1 : 0/(D15), 0/(D14), D13, D12, D11, D10, D9, D8
+ Gen1_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
+ IntDatSwpBus <= IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
+ & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2)
+ & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
+ & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
+ & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
+ & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ end generate;
+-- Shift in order is assumed LSB first
+ Gen_2_Lsb : if C_AdcMsbOrLsbFst = 1 generate
+ -- Bit mode, LSB First, 14-bits (16-bit)
+ -- Data Bit ; 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : D0, D2, D4, D6, D8, D10, D12, 0/(D14)
+ -- Channel 1 : D1, D3, D5, D7, D9, D11, D13, 0/(D15)
+ Gen_2_Bit : if C_AdcBytOrBitMode = 1 generate -- Bit mode
+ IntDatSwpBus <= IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
+ & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
+ & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
+ & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5)
+ & IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
+ & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
+ & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
+ & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ -- Byte Mode, LSB First, 14-bits (16-bit)
+ -- Data Bit : 7, 6, 5, 4, 3, 2, 1, 0
+ -- Channel 0 : D0, D1, D2, D3, D4, D5, D6, D7
+ -- Channel 1 : D8, D9, D10, D11, D12, D13, 0/(D14), 0/(D15)
+ Gen_2_Byt : if C_AdcBytOrBitMode = 0 generate -- Byte Mode (not tested)
+ IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
+ & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
+ & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6)
+ & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
+ & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
+ & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3)
+ & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6);
+ Gen_1_H : for n in 0 to 15 generate
+ I_Fdce_H : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n+16));
+ I_Fdce_L : FDCE
+ generic map (INIT => '0')
+ port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
+ CLR => DatReSync, Q => DatOut(n));
+ end generate Gen_1_H;
+ end generate;
+ end generate;
+end generate;
+--
+-----------------------------------------------------------------------------------------------
+end AdcData_struct;
\ No newline at end of file
--- /dev/null
+-----------------------------------------------------------------------------------------------\r
+-- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.\r
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
+-- protected under U.S. and international copyright and other intellectual property laws.\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+-- Disclaimer:\r
+-- This disclaimer is not a license and does not grant any rights to the materials\r
+-- distributed herewith. Except as otherwise provided in a valid license issued to you\r
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+-- negligence, or under any other theory of liability) for any loss or damage of any\r
+-- kind or nature related to, arising under or in connection with these materials,\r
+-- including for any direct, or any indirect, special, incidental, or consequential\r
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
+-- damage suffered as a result of any action brought by a third party) even if such\r
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+--\r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
+-- application requiring fail-safe performance, such as life-support or safety devices\r
+-- or systems, Class III medical devices, nuclear facilities, applications related to\r
+-- the deployment of airbags, or any other applications that could lead to death,\r
+-- personal injury, or severe property or environmental damage (individually and\r
+-- collectively, "Critical Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical Applications, subject only to\r
+-- applicable laws and regulations governing limitations on product liability.\r
+--\r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
+--\r
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version: \r
+-- \ \ Filename: AdcFrame.vhd\r
+-- / / Date Last Modified: 29 Mar 11\r
+-- /___/ /\ Date Created: 05 Oct 07\r
+-- \ \ / \\r
+-- \___\/\___\\r
+-- \r
+-- Device: Virtex-6\r
+-- Author: Marc Defossez\r
+-- Entity Name: AdcFrame\r
+-- Purpose: This file is part of an FPGA interface for a Texas Instruments ADC.\r
+-- Tools: ISE_13.1\r
+-- Limitations: none\r
+--\r
+-- Revision History:\r
+-- Rev. 28 Oct 2009\r
+-- Corrected the circuit to check for "Bouble Nibble" at the output of the ISEDRES.\r
+-- Made the reaction of this circuit immediate (asynchrounous).\r
+-- Then synchronousity steps in after registering the signals.\r
+-- Rev. 16 feb 2011\r
+-- Replace HDL synthesized FFs by instantiated FFs for frame data path.\r
+-- Check implementation results is ISE_12.4 with PlanAhead through a AdcFrame_Toplevel.\r
+-- Rev 07 Mar 2011\r
+-- Modified the calculation of some "generate" parameters to be able to work in 1-wire\r
+-- and 2-wire mode. generate parameters to create sets of FFs.\r
+-- Rev 09 Mar 2011\r
+-- Problem solved with 1-wire interface not finding correct frame pattern.\r
+-- In the past 1-wire and 2-wire was selected with 0 and 1 while for recent interfaces\r
+-- this is changed to 1 and 2 (To reflect in the selection the interface type).\r
+-- The function calculating the frame pattern for use with the comparator still used\r
+-- the old selection style. Result was that 2-wire functioned normally and 1-wire\r
+-- returned a all zero compare pattern.\r
+-- Finalized the integration and documentation of the "DoubleNibbleDetect".\r
+-----------------------------------------------------------------------------------------------\r
+-- Naming Conventions:\r
+-- active low signals: "*_n"\r
+-- clock signals: "clk", "clk_div#", "clk_#x"\r
+-- reset signals: "rst", "rst_n"\r
+-- generics: "C_*"\r
+-- user defined types: "*_TYPE"\r
+-- state machine next state: "*_ns"\r
+-- state machine current state: "*_cs"\r
+-- combinatorial signals: "*_com"\r
+-- pipelined or register delay signals: "*_d#"\r
+-- counter signals: "*cnt*"\r
+-- clock enable signals: "*_ce"\r
+-- internal version of output port: "*_i"\r
+-- device pins: "*_pin"\r
+-- ports: "- Names begin with Uppercase"\r
+-- processes: "*_PROCESS"\r
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+library IEEE;\r
+ use IEEE.std_logic_1164.all;\r
+ use IEEE.std_logic_UNSIGNED.all;\r
+ use IEEE.std_logic_textio.all;\r
+ use std.textio.all;\r
+library UNISIM;\r
+ use UNISIM.VCOMPONENTS.all;\r
+library AdcFrame_lib;\r
+ use AdcFrame_lib.all;\r
+--library AdcMem;\r
+-- use AdcMem.all;\r
+ \r
+-----------------------------------------------------------------------------------------------\r
+-- Entity pin description\r
+-----------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------\r
+entity AdcFrame is\r
+ generic (\r
+ C_AdcBits : integer;\r
+ C_AdcWireInt : integer;\r
+ C_FrmPattern : string\r
+ );\r
+ port (\r
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT\r
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT\r
+ FrmClkRst : in std_logic;\r
+ FrmClkEna : in std_logic;\r
+ FrmClk : in std_logic;\r
+ FrmClkDiv : in std_logic;\r
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.\r
+ FrmClkReSync : in std_logic;\r
+ FrmClkBitSlip_p : out std_logic;\r
+ FrmClkBitSlip_n : out std_logic;\r
+ FrmClkSwapMux : out std_logic;\r
+ FrmClkMsbRegEna : out std_logic;\r
+ FrmClkLsbRegEna : out std_logic;\r
+ FrmClkReSyncOut : out std_logic;\r
+ FrmClkDat : out std_logic_vector(15 downto 0);\r
+ FrmClkSyncWarn : out std_logic;\r
+ Frame_out : out std_logic;\r
+ testOK : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end AdcFrame;\r
+-----------------------------------------------------------------------------------------------\r
+-- Architecture section\r
+-----------------------------------------------------------------------------------------------\r
+architecture AdcFrame_struct of AdcFrame is\r
+-----------------------------------------------------------------------------------------------\r
+-- Component Instantiation\r
+-----------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------\r
+-- Constants, Signals and Attributes Declarations\r
+-----------------------------------------------------------------------------------------------\r
+-- Functions\r
+-- A std_logic_vector is converted to a string.\r
+ function stdlvec_to_str(inp: std_logic_vector) return string is\r
+ variable temp: string(inp'left+1 downto 1) := (others => 'X');\r
+ begin\r
+ for i in inp'reverse_range loop\r
+ if (inp(i) = '1') then\r
+ temp(i+1) := '1';\r
+ elsif (inp(i) = '0') then\r
+ temp(i+1) := '0'; \r
+ end if;\r
+ end loop;\r
+ return temp;\r
+ end function stdlvec_to_str;\r
+--\r
+-- A string is converted to a std_logic_vector.\r
+ function str_to_stdlvec(Inp: string) return std_logic_vector is\r
+ variable Temp : std_logic_vector(Inp'range) := (others => 'X');\r
+ begin \r
+ for i in Inp'range loop\r
+ if (Inp(i) = '1') then\r
+ Temp(i) := '1';\r
+ elsif (Inp(i) = '0') then\r
+ Temp(i) := '0'; \r
+ end if;\r
+ end loop;\r
+ return Temp;\r
+ end function str_to_stdlvec;\r
+--\r
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.\r
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.\r
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.\r
+ function FrmBits (Bits : integer) return integer is\r
+ variable Temp : integer;\r
+ begin\r
+ if (Bits = 12) then\r
+ Temp := 12;\r
+ elsif (Bits = 14) then\r
+ Temp := 16;\r
+ elsif (Bits = 16) then\r
+ Temp := 16;\r
+ end if;\r
+ return Temp;\r
+ end function FrmBits;\r
+--\r
+-- Word symmetry check\r
+-- A word (16-bit) is checked for bit pair symmetry\r
+-- Example: In one byte there are 16 possible symmetry positions.\r
+-- 00000000, 00000011, 00001100, 00001111,\r
+-- 00110000, 00110011, 00111100, 00111111,\r
+-- 11000000, 11000011, 11001100, 11001111,\r
+-- 11110000, 11110011, 11111100, 11111111,\r
+-- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0\r
+ function SymChck (Inp: std_logic_vector) return std_logic is\r
+ variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');\r
+ variable Sym : std_logic := '0';\r
+ begin\r
+ for n in (Inp'left-1)/2 downto 0 loop\r
+ Temp(n) := Inp((n*2)+1) xor Inp(n*2);\r
+ Sym := Temp(n) or Sym;\r
+ end loop;\r
+ assert false\r
+ report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR\r
+ severity note;\r
+ return Sym;\r
+ end function SymChck;\r
+--\r
+-- When a symmetric byte, bit pattern is found, make the requested pattern rotate\r
+-- by one bit to become a non-symmetric pattern. \r
+ function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is\r
+ variable Temp : std_logic_vector (Inp'range):= (others => '0');\r
+ begin\r
+-- Bit shift all bits.\r
+-- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000\r
+-- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000\r
+ if (SymChck(Inp) = '0') then\r
+ if (Wire = 1 ) then -- 1-wire, shift 15-bits\r
+ for n in Inp'left downto 0 loop\r
+ if (n /= 0) then\r
+ Temp(n) := Inp(n-1);\r
+ elsif (n = 0) then\r
+ Temp(Temp'right) := Inp(Inp'left);\r
+ end if;\r
+ end loop;\r
+ else -- (Wire = 2) -- 2-wire, shift 8-bits\r
+ for n in (Inp'left-8) downto 0 loop\r
+ if (n /= 0) then\r
+ Temp(n) := Inp(n-1);\r
+ elsif (n = 0) then\r
+ Temp(Temp'right) := Inp(Inp'left-8);\r
+ end if;\r
+ end loop;\r
+ end if;\r
+ elsif (SymChck(Inp) = '1') then\r
+ -- Don't do anything, return the word as it came in.\r
+ Temp := Inp;\r
+ end if;\r
+ --\r
+ assert false\r
+ report CR &\r
+ " Pattern Shifted = " & stdlvec_to_str(Temp) & CR & \r
+ " Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &\r
+ " Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR\r
+ severity note;\r
+ return Temp;\r
+ end function BitShft;\r
+--\r
+-- Bit swap operation: \r
+-- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).\r
+-- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).\r
+-- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).\r
+-- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).\r
+-- and etcetera....\r
+-- This: Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.\r
+-- Results in: Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.\r
+ function BitSwap(Inp: std_logic_vector) return std_logic_vector is\r
+ variable Temp : std_logic_vector (Inp'range);\r
+ begin\r
+ for n in (Inp'left-1)/2 downto 0 loop\r
+ Temp((n*2)+1) := Inp(n*2);\r
+ Temp(n*2) := Inp((n*2)+1);\r
+ end loop;\r
+ assert false\r
+ report CR &\r
+ " Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &\r
+ " Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &\r
+ " Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0)) & CR \r
+ severity note;\r
+ return Temp;\r
+ end function BitSwap;\r
+--\r
+ function TermOrNot (Term : integer) return boolean is\r
+ begin\r
+ if (Term = 0) then\r
+ return FALSE;\r
+ else\r
+ return TRUE;\r
+ end if;\r
+ end TermOrNot;\r
+ \r
+component DoubleNibbleDetect is
+ port (
+ Clock : in std_logic;
+ RstIn : in std_logic;
+ Final : out std_logic;
+ DataIn : in std_logic_vector(3 downto 0);
+ DataOut : out std_logic_vector(3 downto 0)
+ );
+end component;
+
+component GenPulse is
+ port (
+ Clk : in std_logic;
+ Ena : in std_logic;
+ SigIn : in std_logic;
+ SigOut : out std_logic
+ );
+end component;\r
+\r
+--\r
+-- Constants\r
+-- Transform the pattern STRING into a std_logic_vector.\r
+constant IntPattern :\r
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := str_to_stdlvec(C_FrmPattern);\r
+-- Shift the pattern for one bit.\r
+constant IntPatternBitShifted :\r
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitShft(IntPattern, C_AdcWireInt);\r
+-- Bit swap the by one bit shifted pattern.\r
+constant IntPatternBitSwapped :\r
+ std_logic_vector(FrmBits(C_AdcBits)-1 downto 0) := BitSwap(IntPatternBitShifted);\r
+-- Define the bytes for pattern comparison.\r
+constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
+ IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);\r
+constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
+ IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
+ IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);\r
+constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=\r
+ IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+-- Calculate the data width for a ISERDES. \r
+constant IntIsrdsDataWidth : integer := FrmBits(C_AdcBits)/4;\r
+constant Low : std_logic := '0';\r
+constant High : std_logic := '1';\r
+attribute keep : string;\r
+-- Signals\r
+signal IntFrmClk : std_logic;\r
+signal IntFrmClk_n : std_logic;\r
+signal IntFrmSrdsOut : std_logic_vector (7 downto 0);\r
+--\r
+signal IntFrmSrdsDatEvn : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
+signal IntFrmSrdsDatOdd : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
+signal IntFrmSrdsDatEvn_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
+signal IntFrmSrdsDatOdd_d : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);\r
+signal IntFrmSrdsDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+signal IntFrmDat : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+signal IntFrmDatMux : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+signal IntFrmDatSwp : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);\r
+signal IntFrmDatSwpBus : std_logic_vector(15 downto 0);\r
+signal IntFrmClkDat : std_logic_vector(15 downto 0);\r
+--\r
+signal IntFrmDbleNibFnlEvn : std_logic;\r
+signal IntFrmDbleNibFnlEvn_d : std_logic;\r
+signal IntFrmDbleNibFnlOdd : std_logic;\r
+signal IntFrmDbleNibFnlOdd_d : std_logic;\r
+signal IntFrmDbleNibFnl : std_logic;\r
+--\r
+signal IntFrmEna : std_logic;\r
+signal IntFrmCmp : std_logic_vector(3 downto 0);\r
+signal IntFrmEquGte : std_logic;\r
+signal IntFrmEqu_d : std_logic;\r
+signal IntFrmSwapMux_d : std_logic;\r
+signal IntFrmSwapMux_d_Ena : std_logic;\r
+signal IntFrmLsbMsb_d : std_logic;\r
+signal IntFrmLsbMsb_d_Ena : std_logic;\r
+signal IntFrmMsbAllZero_d : std_logic;\r
+signal IntFrmMsbAllZero_d_Ena : std_logic;\r
+--\r
+signal IntFrmRegEna_d : std_logic;\r
+signal IntFrmMsbRegEna_d : std_logic;\r
+signal IntFrmLsbRegEna_d : std_logic;\r
+--\r
+signal IntFrmEvntCnt : std_logic_vector (3 downto 0); -- count event counter\r
+signal IntFrmEvntCntTc : std_logic;\r
+signal IntFrmEvntCntTc_d : std_logic;\r
+signal IntFrmSlipCnt : std_logic_vector (3 downto 0); -- count to 8\r
+signal IntFrmSlipCntTc : std_logic;\r
+signal IntFrmSlipCntTc_d : std_logic;\r
+signal IntFrmSlipCntTc_d1 : std_logic;\r
+signal IntFrmSlipCntTc_d2Ena : std_logic;\r
+signal IntFrmSlipCntTc_d2 : std_logic;\r
+signal IntFrmWarnCnt : std_logic_vector (2 downto 0);\r
+signal IntFrmWarnCntTc : std_logic;\r
+signal IntFrmWarnCntTc_d : std_logic;\r
+signal IntFrmClkReSync : std_logic;\r
+signal IntFrmReSyncOut : std_logic;\r
+--\r
+signal IntFrmBitSlip : std_logic_vector (5 downto 0);\r
+signal IntFrmEquSet_d : std_Logic;\r
+\r
+signal Frame_out_S : std_Logic;\r
+-- Attributes\r
+attribute keep of Frame_out_S : signal is "TRUE";\r
+-----------------------------------------------------------------------------------------------\r
+begin\r
+-----------------------------------------------------------------------------------------------\r
+-- ISERDES FOR FRAME CAPTURE\r
+-----------------------------------------------------------------------------------------------\r
+IntFrmClk <= FrmClk;\r
+IntFrmClk_n <= not FrmClk;\r
+--\r
+AdcFrame_I_Isrds_p : ISERDESE1\r
+ generic map (\r
+ SERDES_MODE => "MASTER", -- \r
+ INTERFACE_TYPE => "NETWORKING", -- \r
+ IOBDELAY => "NONE", -- \r
+ DATA_RATE => "SDR", -- \r
+ DATA_WIDTH => IntIsrdsDataWidth, -- <-- Number of bits\r
+ DYN_CLKDIV_INV_EN => FALSE, -- \r
+ DYN_CLK_INV_EN => FALSE, -- \r
+ NUM_CE => 1, -- \r
+ OFB_USED => FALSE -- \r
+ )\r
+ port map (\r
+ D => FrmClk_p, -- in\r
+ DDLY => Low, -- in\r
+ DYNCLKDIVSEL => Low, -- in\r
+ DYNCLKSEL => Low, -- in\r
+ OFB => Low, -- in\r
+ BITSLIP => IntFrmBitSlip(0),-- in\r
+ CE1 => IntFrmEna, -- in\r
+ CE2 => Low, -- in\r
+ RST => FrmClkRst, -- in\r
+ CLK => IntFrmClk, -- in\r
+ CLKB => Low, -- in\r
+ CLKDIV => FrmClkDiv, -- in\r
+ OCLK => Low, -- in\r
+ SHIFTOUT1 => open, -- out\r
+ SHIFTOUT2 => open, -- out\r
+ O => Frame_out_S, -- out\r
+ Q1 => IntFrmSrdsOut(6), -- out (0)\r
+ Q2 => IntFrmSrdsOut(4), -- out (2)\r
+ Q3 => IntFrmSrdsOut(2), -- out (4)\r
+ Q4 => IntFrmSrdsOut(0), -- out (6)\r
+ Q5 => open, -- out\r
+ Q6 => open, -- out\r
+ SHIFTIN1 => Low, -- in\r
+ SHIFTIN2 => Low -- in\r
+ );\r
+Frame_out <= Frame_out_S;\r
+\r
+AdcFrame_I_Isrds_n : ISERDESE1\r
+ generic map (\r
+ SERDES_MODE => "MASTER", -- \r
+ INTERFACE_TYPE => "NETWORKING", -- \r
+ IOBDELAY => "NONE", -- \r
+ DATA_RATE => "SDR", -- \r
+ DATA_WIDTH => IntIsrdsDataWidth, -- 12-bit = 3 and 14/16 b its = 4\r
+ DYN_CLKDIV_INV_EN => FALSE, -- \r
+ DYN_CLK_INV_EN => FALSE, -- \r
+ NUM_CE => 1, -- \r
+ OFB_USED => FALSE -- \r
+ )\r
+ port map (\r
+ D => FrmClk_n, -- in\r
+ DDLY => Low, -- in\r
+ DYNCLKDIVSEL => Low, -- in\r
+ DYNCLKSEL => Low, -- in\r
+ OFB => Low, -- in\r
+ BITSLIP => IntFrmBitSlip(1),-- in\r
+ CE1 => IntFrmEna, -- in\r
+ CE2 => Low, -- in\r
+ RST => FrmClkRst, -- in\r
+ CLK => IntFrmClk_n, -- in\r
+ CLKB => Low, -- in\r
+ CLKDIV => FrmClkDiv, -- in\r
+ OCLK => Low, -- in\r
+ SHIFTOUT1 => open, -- out\r
+ SHIFTOUT2 => open, -- out\r
+ O => open, -- out\r
+ Q1 => IntFrmSrdsOut(7), -- out (1)\r
+ Q2 => IntFrmSrdsOut(5), -- out (3)\r
+ Q3 => IntFrmSrdsOut(3), -- out (5)\r
+ Q4 => IntFrmSrdsOut(1), -- out (7)\r
+ Q5 => open, -- out\r
+ Q6 => open, -- out\r
+ SHIFTIN1 => Low, -- in\r
+ SHIFTIN2 => Low -- in\r
+ );\r
+-----------------------------------------------------------------------------------------------\r
+-- INVERT THE NEEDED BITS.\r
+-----------------------------------------------------------------------------------------------\r
+Gen_1_FrmBus : if (FrmBits(C_AdcBits)/2) = 6 generate\r
+ IntFrmSrdsDatEvn <= IntFrmSrdsOut(4) & IntFrmSrdsOut(2) & IntFrmSrdsOut(0);\r
+ IntFrmSrdsDatOdd <= not IntFrmSrdsOut(5) & not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); \r
+end generate Gen_1_FrmBus;\r
+Gen_2_FrmBus : if (FrmBits(C_AdcBits)/2) = 8 generate\r
+ IntFrmSrdsDatEvn <= IntFrmSrdsOut(6) & IntFrmSrdsOut(4) &\r
+ IntFrmSrdsOut(2) & IntFrmSrdsOut(0);\r
+ IntFrmSrdsDatOdd <= not IntFrmSrdsOut(7) & not IntFrmSrdsOut(5) &\r
+ not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); \r
+end generate Gen_2_FrmBus;\r
+-----------------------------------------------------------------------------------------------\r
+-- Double Nibble Detection.\r
+-- When the ADC is used in 1-wire mode the frame pattern is 12 or 16 bits long.\r
+-- It is captured in two ISERDES. One running at rising CLK and the orther runnsing at falling\r
+-- CLK. For some reason, afetr a bitslip a ISERDES can output twice the same nibble of data. \r
+-- This phenomenon is called ""Double nibble" and as written before happens after a\r
+-- Bitslip request.\r
+-- The output of each ISERDES is first checked for these double nibbles and if needed the\r
+-- ISERDES output is corrected. After that the data is passed into the franme pattern\r
+-- Recognition part of the design. \r
+-----------------------------------------------------------------------------------------------\r
+Gen_1_DbleNibChk : if (C_AdcWireInt = 1) generate\r
+ AdcFrame_I_DblNbblDtct_Evn : DoubleNibbleDetect\r
+ port map (\r
+ Clock => FrmClkDiv, -- in\r
+ RstIn => FrmClkRst, -- in\r
+ Final => IntFrmDbleNibFnlEvn, -- out\r
+ DataIn => IntFrmSrdsDatEvn, -- in [3:0]\r
+ DataOut => IntFrmSrdsDatEvn_d -- out [3:0]\r
+ );\r
+--\r
+ AdcFrame_I_DblNbblDtct_Odd : DoubleNibbleDetect\r
+ port map (\r
+ Clock => FrmClkDiv, -- in\r
+ RstIn => FrmClkRst, -- in\r
+ Final => IntFrmDbleNibFnlOdd, -- out\r
+ DataIn => IntFrmSrdsDatOdd, -- in [3:0]\r
+ DataOut => IntFrmSrdsDatOdd_d -- out [3:0]\r
+ );\r
+--\r
+ AdcFrame_DblNibFnl_PROCESS : process (FrmClkDiv)\r
+ begin\r
+ if (FrmClkRst = '1' ) then\r
+ IntFrmDbleNibFnlOdd_d <= '0';\r
+ IntFrmDbleNibFnlEvn_d <= '0';\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ if (IntFrmDbleNibFnlOdd = '1') then\r
+ IntFrmDbleNibFnlOdd_d <= '1';\r
+ else --(IntFrmDbleNibFnlOdd = '0')\r
+ IntFrmDbleNibFnlOdd_d <= '0';\r
+ end if;\r
+ if (IntFrmDbleNibFnlEvn = '1') then\r
+ IntFrmDbleNibFnlEvn_d <= '1';\r
+ else --(IntFrmDbleNibFnlOdd = '0')\r
+ IntFrmDbleNibFnlEvn_d <= '0';\r
+ end if;\r
+ end if;\r
+ end process AdcFrame_DblNibFnl_PROCESS;\r
+--\r
+ IntFrmDbleNibFnl <= IntFrmDbleNibFnlOdd_d and IntFrmDbleNibFnlEvn_d;\r
+end generate Gen_1_DbleNibChk;\r
+--\r
+Gen_2_DbleNibChk : if (C_AdcWireInt = 2) generate\r
+ IntFrmSrdsDatEvn_d <= IntFrmSrdsDatEvn;\r
+ IntFrmSrdsDatOdd_d <= IntFrmSrdsDatOdd;\r
+ IntFrmDbleNibFnl <= Low;\r
+end generate Gen_2_DbleNibChk;\r
+-----------------------------------------------------------------------------------------------\r
+-- DATA REGISTER\r
+-----------------------------------------------------------------------------------------------\r
+Gen_1_DatBus : for n in (FrmBits(C_AdcBits)/4) downto 1 generate\r
+ IntFrmSrdsDat((n*2)-1) <= IntFrmSrdsDatOdd_d(n-1);\r
+ IntFrmSrdsDat((n*2)-2) <= IntFrmSrdsDatEvn_d(n-1);\r
+end generate Gen_1_DatBus;\r
+--\r
+Gen_1_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate \r
+ AdcFrame_I_Fdce_Reg1 : FDCE\r
+ generic map (INIT => '0') -- bit\r
+ port map(D => IntFrmSrdsDat(n), CE => IntFrmEna, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmDat(n));\r
+end generate Gen_1_DatReg;\r
+-----------------------------------------------------------------------------------------------\r
+-- BIT SWAP MULTIPLEXER and REGISTER\r
+-- Swap the bits in correct order when the pattern detected is bit swapped.\r
+-----------------------------------------------------------------------------------------------\r
+Gen_2_DatMux : for n in (FrmBits(C_AdcBits)/4)-1 downto 0 generate\r
+begin\r
+ IntFrmDatMux((n*2)+1) <= IntFrmDat(n*2) when (IntFrmSwapMux_d = '1') else IntFrmDat((n*2)+1);\r
+ IntFrmDatMux(n*2) <= IntFrmDat((n*2)+1) when (IntFrmSwapMux_d = '1') else IntFrmDat(n*2);\r
+end generate Gen_2_DatMux;\r
+Gen_3_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate\r
+ AdcFrame_I_Fdce_Reg2 : FDCE\r
+ generic map (INIT => '0') -- bit\r
+ port map (D => IntFrmDatMux(n), C => FrmClkDiv, CE => IntFrmEna, CLR => IntFrmReSyncOut,\r
+ Q => IntFrmDatSwp(n));\r
+end generate Gen_3_DatReg;\r
+-----------------------------------------------------------------------------------------------\r
+-- FRAME OUTPUT REGISTERS\r
+-----------------------------------------------------------------------------------------------\r
+Gen_4_OutReg12 : if C_AdcBits = 12 generate\r
+ IntFrmDatSwpBus <= "0000" &\r
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
+ IntFrmDatSwp(1) & IntFrmDatSwp(0) &\r
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
+ IntFrmDatSwp(1) & IntFrmDatSwp(0);\r
+ Gen_4_H : for n in 6 to 15 generate\r
+ AdcFrame_I_Fdce_FrmClkDatMsb : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
+ end generate Gen_4_H;\r
+ Gen_4_L : for n in 0 to 5 generate\r
+ AdcFrame_I_Fdce_FrmClkDatLsb : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
+ end generate Gen_4_L;\r
+end generate Gen_4_OutReg12;\r
+--\r
+Gen_5_OutReg12n : if C_AdcBits /= 12 generate\r
+ IntFrmDatSwpBus <= IntFrmDatSwp(7) & IntFrmDatSwp(6) &\r
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
+ IntFrmDatSwp(1) & IntFrmDatSwp(0) &\r
+ IntFrmDatSwp(7) & IntFrmDatSwp(6) &\r
+ IntFrmDatSwp(5) & IntFrmDatSwp(4) &\r
+ IntFrmDatSwp(3) & IntFrmDatSwp(2) &\r
+ IntFrmDatSwp(1) & IntFrmDatSwp(0);\r
+ Gen_5_H : for n in 8 to 15 generate\r
+ AdcFrame_I_Fdce_FrmClkDatMsb : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
+ end generate Gen_5_H;\r
+ Gen_5_L : for n in 0 to 7 generate\r
+ AdcFrame_I_Fdce_FrmClkDatLsb : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));\r
+ end generate Gen_5_L;\r
+end generate Gen_5_OutReg12n;\r
+--\r
+FrmClkDat <= IntFrmClkDat;\r
+-----------------------------------------------------------------------------------------------\r
+-- FRAME PATTERN COMPARATOR \r
+-----------------------------------------------------------------------------------------------\r
+IntFrmCmp(2 downto 0) <= "101" when (IntFrmSrdsDat = IntPatternA) else -- Equ, , Msb\r
+ "100" when (IntFrmSrdsDat = IntPatternB) else -- Equ, , Lsb\r
+ "111" when (IntFrmSrdsDat = IntPatternC) else -- Equ, swpd, Msb\r
+ "110" when (IntFrmSrdsDat = IntPatternD) else -- Equ, Swpd, Lsb\r
+ "000";\r
+IntFrmCmp(3) <= High when (C_AdcWireInt = 2) else Low; -- Msb = all zero\r
+--\r
+-- When "Equ" goes high, one of the four patterns has been found.\r
+-- The other two signals will reflect (Msb or Lsb, bitswapped or not) what pattern has been\r
+-- found. WHen "Equ" thus goes high, store the status of all signals and make sure it can't\r
+-- be changed.\r
+--\r
+IntFrmEquGte <= (IntFrmCmp(2) or IntFrmEqu_d) and IntFrmEna;\r
+--\r
+AdcFrame_I_Fdce_FrmMsbAllZero_d : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmCmp(3), CE => IntFrmMsbAllZero_d_Ena, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmMsbAllZero_d);\r
+AdcFrame_I_Fdce_FrmEqu_d : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmEquGte, CE => High, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmEqu_d);\r
+AdcFrame_I_Fdce_FrmSwapMux_d : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmCmp(1), CE => IntFrmSwapMux_d_Ena, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmSwapMux_d);\r
+AdcFrame_I_Fdce_FrmLsbMsb_d : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmCmp(0), CE => IntFrmLsbMsb_d_Ena, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmLsbMsb_d);\r
+--\r
+IntFrmMsbAllZero_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;\r
+IntFrmSwapMux_d_Ena <= IntFrmCmp(2)and not IntFrmEqu_d;\r
+IntFrmLsbMsb_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;\r
+FrmClkSwapMux <= IntFrmSwapMux_d;\r
+-----------------------------------------------------------------------------------------------\r
+-- OUTPUT REGISTER ENABLER\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_EnaSel_PROCESS : process (FrmClkDiv, IntFrmMsbAllZero_d, IntFrmEqu_d)\r
+subtype IntFrmRegEnaCase is std_logic_vector(4 downto 0);\r
+begin\r
+ if (IntFrmMsbAllZero_d = High) then\r
+ IntFrmRegEna_d <= Low;\r
+ IntFrmMsbRegEna_d <= High;\r
+ IntFrmLsbRegEna_d <= High;\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ case IntFrmRegEnaCase'(IntFrmLsbMsb_d, IntFrmEqu_d, IntFrmRegEna_d,\r
+ IntFrmMsbRegEna_d, IntFrmLsbRegEna_d) is\r
+ when "00001" => IntFrmRegEna_d <= '0';\r
+ IntFrmMsbRegEna_d <= '0'; -- A\r
+ IntFrmLsbRegEna_d <= '1'; --\r
+ when "01001" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '0'; -- B\r
+ IntFrmLsbRegEna_d <= '1'; --\r
+ when "01101" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '1'; -- C\r
+ IntFrmLsbRegEna_d <= '0'; --\r
+ when "01110" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '0'; -- D, goto C \r
+ IntFrmLsbRegEna_d <= '1'; --\r
+ --\r
+ when "11001" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '1'; -- E\r
+ IntFrmLsbRegEna_d <= '0'; --\r
+ when "11110" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '0'; -- F\r
+ IntFrmLsbRegEna_d <= '1'; --\r
+ when "11101" => IntFrmRegEna_d <= '1';\r
+ IntFrmMsbRegEna_d <= '1'; -- G, goto F\r
+ IntFrmLsbRegEna_d <= '0'; --\r
+ --\r
+ when others => IntFrmRegEna_d <= '0';\r
+ IntFrmMsbRegEna_d <= '0';\r
+ IntFrmLsbRegEna_d <= '1';\r
+ end case;\r
+ end if;\r
+end process;\r
+FrmClkMsbRegEna <= IntFrmMsbRegEna_d;\r
+FrmClkLsbRegEna <= IntFrmLsbRegEna_d;\r
+-----------------------------------------------------------------------------------------------\r
+-- SAMPLE EVENT COUNTER\r
+-- Take a frame sample every 16 ClkDiv cycles.\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_EvntCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)\r
+begin\r
+ if (IntFrmReSyncOut = High) then\r
+ IntFrmEvntCnt <= (others => '0');\r
+ IntFrmEvntCntTc_d <= Low;\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ if (IntFrmEquSet_d = Low and IntFrmEna = High) then\r
+ IntFrmEvntCnt <= IntFrmEvntCnt + "01";\r
+ IntFrmEvntCntTc_d <= IntFrmEvntCntTc;\r
+ end if;\r
+ end if;\r
+end process;\r
+IntFrmEvntCntTc <= High when (IntFrmEvntCnt = "1110") else Low;\r
+--IntFrmEvntCntTc <= High when (IntFrmEvntCnt = ((2**IntFrmEvntCnt'length)-2)) else Low;\r
+-----------------------------------------------------------------------------------------------\r
+-- BITSLIP EVENT COUNTER\r
+-- Bitslip 8 times for a 8-bit ISERDES and 6 times for a 6-bit ISERDES.\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_SlipCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)\r
+begin\r
+ if (IntFrmReSyncOut = High) then\r
+ IntFrmSlipCnt <= (others => '0');\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ if (IntFrmEvntCntTc_d = High) then\r
+ IntFrmSlipCnt <= IntFrmSlipCnt + "01";\r
+ end if;\r
+ if (IntFrmEvntCntTc_d = High and IntFrmSlipCntTc = High) then\r
+ IntFrmSlipCntTc_d <= High;\r
+ else \r
+ IntFrmSlipCntTc_d <= Low;\r
+ end if;\r
+ end if;\r
+end process;\r
+--Terminal count points.\r
+AdcFrame_SlipCntTc_12 : if (FrmBits(C_AdcBits) = 12) generate\r
+ IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'\r
+end generate;\r
+AdcFrame_SlipCntTc_1_16 : if (FrmBits(C_AdcBits) = 16) generate\r
+ IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'\r
+end generate;\r
+--AdcFrame_SlipCntTc_1_12 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 12) generate\r
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'\r
+--end generate;\r
+--AdcFrame_SlipCntTc_2_12 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 12) generate\r
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0101") else Low; -- 5\r
+--end generate;\r
+--AdcFrame_SlipCntTc_1_16 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 16) generate\r
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'\r
+--end generate;\r
+--AdcFrame_SlipCntTc_2_16 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 16) generate\r
+-- IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0111") else Low; -- 7\r
+--end generate;\r
+AdcFrame_I_Fdce_SlipCntTc_1 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => High, CE => IntFrmSlipCntTc_d, C => FrmClkDiv,\r
+ CLR => IntFrmSlipCntTc_d2, Q => IntFrmSlipCntTc_d1);\r
+IntFrmSlipCntTc_d2Ena <= IntFrmSlipCntTc_d and IntFrmSlipCntTc_d1;\r
+AdcFrame_I_Fdce_SlipCntTc_2 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntFrmSlipCntTc_d2Ena, CE => High, C => FrmClkDiv,\r
+ CLR => IntFrmReSyncOut, Q => IntFrmSlipCntTc_d2);\r
+-----------------------------------------------------------------------------------------------\r
+-- WARNING EVENT COUNTER\r
+-- When this counter issues terminal count, sunchronisation was impossible for 8 times.\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_WarnCnt_PROCESS : process (FrmClkDiv, FrmClkRst)\r
+begin\r
+ if (FrmClkRst = High) then\r
+ IntFrmWarnCnt <= (others => '0');\r
+ IntFrmWarnCntTc_d <= Low;\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ if (IntFrmSlipCntTc_d = High) then\r
+ IntFrmWarnCnt <= IntFrmWarnCnt + "01";\r
+ IntFrmWarnCntTc_d <= IntFrmWarnCntTc;\r
+ end if;\r
+ end if;\r
+end process;\r
+IntFrmWarnCntTc <= High when (IntFrmWarnCnt = "110") else Low;\r
+FrmClkSyncWarn <= IntFrmWarnCntTc_d;\r
+-----------------------------------------------------------------------------------------------\r
+-- Enable, RESYNC or INTERNAL RESET\r
+-- This is the reset logic for the whole design.\r
+-- Whenever one of these signals (IntFrmSlipCntTc_d2, IntFrmDbleNibFnl, FrmClkReSync, FrmClkRst)\r
+-- is high the circuit is pulled int reset (call it a re-sync operation).\r
+-- \r
+-- The only components not influenced by this are the ISERDES and the Sync Warning Counter.\r
+-- they only act on the extrenal "FrmClkRst" input.\r
+-- \r
+-- A circuit enable "IntFrmEna" is generated when the inputs "FrmClkDone" and "FrmClkEna" are\r
+-- high and when the "IntFrmReSync" reset is released.\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_I_GenPulse_1 : GenPulse\r
+ port map (\r
+ Clk => FrmClkDiv, -- in\r
+ Ena => High, -- in\r
+ SigIn => FrmClkReSync, -- in\r
+ SigOut => IntFrmClkReSync -- out\r
+ );\r
+IntFrmReSyncOut <= IntFrmSlipCntTc_d2 or IntFrmDbleNibFnl or IntFrmClkReSync or FrmClkRst;\r
+FrmClkReSyncOut <= IntFrmReSyncOut;\r
+--\r
+AdcFrame_I_Fdce_Done : FDCE\r
+ generic map (INIT => '0') -- bit\r
+ port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => IntFrmReSyncOut,\r
+ Q => IntFrmEna);\r
+-----------------------------------------------------------------------------------------------\r
+-- BITSLIP STATE MACHINE.\r
+-----------------------------------------------------------------------------------------------\r
+AdcFrame_Bitslip_PROCESS : process (IntFrmReSyncOut, FrmClkDiv)\r
+subtype IntFrmBitSlipCase is std_logic_vector(5 downto 0);\r
+begin\r
+ if (IntFrmReSyncOut = High) then\r
+ IntFrmBitSlip <= (others => '0');\r
+ elsif (FrmClkDiv'event and FrmClkDiv = '1') then\r
+ if (IntFrmEna = High and IntFrmEquSet_d = Low) then\r
+ case IntFrmBitSlipCase'(IntFrmEqu_d, IntFrmEvntCntTc_d, IntFrmBitSlip(5),\r
+ IntFrmBitSlip(4), IntFrmBitSlip(3), IntFrmBitSlip(2)) is\r
+ when "000000" => IntFrmBitSlip <= "000000"; -- B \r
+ when "010000" => IntFrmBitSlip <= "000101"; -- C Slip_p\r
+ when "000001" => IntFrmBitSlip <= "000100"; -- D\r
+ when "010001" => IntFrmBitSlip <= "001010"; -- E Slip_n\r
+ when "000010" => IntFrmBitSlip <= "001000"; -- F\r
+ when "010010" => IntFrmBitSlip <= "000101"; -- G Slip_p and goto D\r
+ --\r
+ when "100000" => IntFrmBitSlip <= "000000"; -- H \r
+ when "110000" => IntFrmBitSlip <= "100101"; -- K Slip_p\r
+ when "101001" => IntFrmBitSlip <= "110000"; -- L EquSet\r
+ when "101100" => IntFrmBitSlip <= "110000"; -- M Halt\r
+ --\r
+ when "100001" => IntFrmBitSlip <= "000100"; -- N\r
+ when "110001" => IntFrmBitSlip <= "101010"; -- P Slip_n\r
+ when "101010" => IntFrmBitSlip <= "110000"; -- R EquSet goto M\r
+ --\r
+ when "100010" => IntFrmBitSlip <= "001000"; -- S\r
+ when "110010" => IntFrmBitSlip <= "100101"; -- T Slip_p goto L\r
+ --\r
+ when others => IntFrmBitSlip <= "110000";\r
+ end case;\r
+ end if;\r
+ end if;\r
+end process;\r
+FrmClkBitSlip_p <= IntFrmBitSlip(0);\r
+FrmClkBitSlip_n <= IntFrmBitSlip(1);\r
+IntFrmEquSet_d <= IntFrmBitSlip(4);\r
+\r
+\r
+testword0(7 downto 0) <= IntFrmSrdsOut;\r
+testOK <= '1' when IntFrmSrdsOut=x"A5" else '0';\r
+\r
+--\r
+-----------------------------------------------------------------------------------------------\r
+end AdcFrame_struct;\r
--- /dev/null
+----------------------------------------------------------------------------------------------\r
+-- Copyright 2010, Xilinx, Inc. All rights reserved.\r
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
+-- protected under U.S. and international copyright and other intellectual property laws.\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+-- Disclaimer:\r
+-- This disclaimer is not a license and does not grant any rights to the materials\r
+-- distributed herewith. Except as otherwise provided in a valid license issued to you\r
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+-- negligence, or under any other theory of liability) for any loss or damage of any\r
+-- kind or nature related to, arising under or in connection with these materials,\r
+-- including for any direct, or any indirect, special, incidental, or consequential\r
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
+-- damage suffered as a result of any action brought by a third party) even if such\r
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+--\r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
+-- application requiring fail-safe performance, such as life-support or safety devices\r
+-- or systems, Class III medical devices, nuclear facilities, applications related to\r
+-- the deployment of airbags, or any other applications that could lead to death,\r
+-- personal injury, or severe property or environmental damage (individually and\r
+-- collectively, "Critical Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical Applications, subject only to\r
+-- applicable laws and regulations governing limitations on product liability.\r
+--\r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
+--\r
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx Inc.\r
+-- \ \ \/ Version: \r
+-- \ \ \r
+-- / / Filename: AdcToplevel.vhd\r
+-- /___/ /\ Date Created: Nov 07\r
+-- \ \ / \ Date Last Modified: 7 Mar 2011\r
+-- \___\/\___\\r
+-- \r
+-- Device: Virtex-6\r
+-- Author: defossez\r
+-- Entity Name: AdcToplevel\r
+-- Purpose: Top level for an interface between a Virtex-6 FPGA and ADS6245 \r
+-- Tools: ISE_13.1 \r
+-- Limitations: none\r
+--\r
+-- Revision History:\r
+-- Rev. 20 Oct 09\r
+-- Made the ADC interface more generic, with speate FPGA IO file and etcetera.\r
+-- Rev. 27 Dec 10\r
+-- Retrived the file after accidental delete.\r
+-- Rev. 7 Mar 11\r
+-- - Adjustment of the range, in the entity declaration, of "AdcMemFlags" when\r
+-- used for 1 and 2 wire interface.\r
+-- - Brought the generic C_FrmPattern to the top level entity declaration. Now it is \r
+-- possible to provide the frame pattern to search for when the AdcToplevel component\r
+-- is instantiated.\r
+-- - Added extensive comments for teh top level entity generics and ports.\r
+-----------------------------------------------------------------------------------------------\r
+-- Naming Conventions:\r
+-- active low signals: "*_n"\r
+-- clock signals: "clk", "clk_div#", "clk_#x"\r
+-- reset signals: "rst", "rst_n"\r
+-- generics: "C_*"\r
+-- user defined types: "*_TYPE"\r
+-- state machine next state: "*_ns"\r
+-- state machine current state: "*_cs"\r
+-- combinatorial signals: "*_com"\r
+-- pipelined or register delay signals: "*_d#"\r
+-- counter signals: "*cnt*"\r
+-- clock enable signals: "*_ce"\r
+-- internal version of output port: "*_i"\r
+-- device pins: "*_pin"\r
+-- ports: "- Names begin with Uppercase"\r
+-- processes: "*_PROCESS"\r
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+library IEEE;\r
+ use IEEE.std_logic_1164.all;\r
+ use IEEE.std_logic_UNSIGNED.all;\r
+ use IEEE.std_logic_textio.all;\r
+ use std.textio.all;\r
+library UNISIM;\r
+ use UNISIM.VCOMPONENTS.all;\r
+-----------------------------------------------------------------------------------------------\r
+-- Entity pin description\r
+-----------------------------------------------------------------------------------------------\r
+-- GENERICS\r
+-- C_AdcChnls -- ADC Channels available in a package.\r
+-- C_AdcBits -- Value can be 12, 14, or 16 (14 is means 14-bit burried in 16-bit)\r
+-- C_AdcWireInt -- 0 = 1-wire, 1 = 2-wire\r
+-- C_FrmPattern -- Pattern to lock the frame to.\r
+--\r
+-- A 14 or 16 bit ADC in 2-wire mode has a 8-bit frame pattern. The C_FrmPattern parameter\r
+-- must be set to: C_FrmPattern ==> "0000000011110000".\r
+-- A 14 or 16 bit ADC in 1-wire mode has a 16-bit frame pattern. The C_FrmPattern parameter\r
+-- must be set to: C_FrmPattern ==> "1111111100000000".\r
+-- The same applies for a 12-bit ADC device.\r
+-- C_FrmPattern : string := "111111000000"; -- 1-wire, 12 bit.\r
+-- C_FrmPattern : string := "000000111000"; -- 2-wire, 12 bit.\r
+--\r
+-- C_StatTaps -- Number of taps the IDELAY starts from (Middle of the Tap chain).\r
+-- C_IdelayCtrlLoc -- Hard location of the IDELAYCTRL component.\r
+-- PORTS\r
+-- DATA_n -- I -- ADC data input signals from the ADC device.\r
+-- DATA_p -- I -- \r
+-- DCLK_n, DCLK_p -- I -- High speed clock from the ADC device.\r
+-- FCLK_n, FCLK_p -- I -- Word or frame clock from the ADC device.\r
+-- SysRefClk -- I -- Reference clock for IDELAYCTRL (200 MHz).\r
+-- AdcIntrfcRst -- I -- Reset for the interface from the application.\r
+-- AdcIntrfcEna -- I -- Enable signal for the interface from the application.\r
+-- AdcReSync -- I -- Signal to restart the resync process.\r
+-- AdcFrmSyncWrn -- O -- Warning from the sync logic, alignment is not possible\r
+-- AdcBitClkAlgnWrn -- O -- Status signal. BitClock adjusted.\r
+-- AdcBitClkInvrtd -- O -- Bit clock state, rising or falling\r
+-- AdcBitClkDone -- O -- Bit clock alignment done\r
+-- AdcIdlyCtrlRdy -- O -- IDELAYCTRL ready\r
+\r
+-----------------------------------------------------------------------------------------------\r
+entity AdcToplevel is\r
+ generic (\r
+ C_AdcChnls : integer := 4; -- Number of ADC in a package \r
+ C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface\r
+ C_BufioLoc : string := "BUFIODQS_X0Y12";\r
+ C_BufrLoc : string := "BUFR_X0Y6";\r
+ C_AdcBits : integer := 16;\r
+ C_StatTaps : integer := 16;\r
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes\r
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";\r
+ C_FrmPattern : string := "0000000011110000" -- Read above text!\r
+ );\r
+ port (\r
+ DCLK_p : in std_logic;\r
+ DCLK_n : in std_logic; -- Not used.\r
+ FCLK_p : in std_logic;\r
+ FCLK_n : in std_logic;\r
+ DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);\r
+ DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);\r
+ -- application connections\r
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application\r
+ AdcIntrfcRst : in std_logic;\r
+ AdcIntrfcEna : in std_logic;\r
+ AdcReSync : in std_logic;\r
+ AdcFrmSyncWrn : out std_logic;\r
+ AdcBitClkAlgnWrn : out std_logic;\r
+ AdcBitClkInvrtd : out std_logic;\r
+ AdcBitClkDone : out std_logic;\r
+ AdcIdlyCtrlRdy : out std_logic;\r
+\r
+ AdcClkDiv : out std_logic;\r
+ AdcDataClk : in std_logic;
+ AdcDataClkNot : in std_logic;
+ AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);\r
+ ADCs_ready : out std_logic;\r
+ testOK : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end AdcToplevel;\r
+-----------------------------------------------------------------------------------------------\r
+-- Arcitecture section\r
+-----------------------------------------------------------------------------------------------\r
+architecture AdcToplevel_struct of AdcToplevel is\r
+-----------------------------------------------------------------------------------------------\r
+-- Component Instantiation\r
+-----------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------\r
+-- Constants, Signals and Attributes Declarations\r
+-----------------------------------------------------------------------------------------------\r
+-- Functions\r
+function int_to_chr(int: integer) return character is\r
+ variable temp : character;\r
+begin\r
+ case int is\r
+ when 0 => temp := '0';\r
+ when 1 => temp := '1';\r
+ when 2 => temp := '2';\r
+ when 3 => temp := '3';\r
+ when 4 => temp := '4';\r
+ when 5 => temp := '5';\r
+ when 6 => temp := '6';\r
+ when 7 => temp := '7';\r
+ when 8 => temp := '8';\r
+ when 9 => temp := '9';\r
+ when 10 => temp := 'A';\r
+ when 11 => temp := 'B';\r
+ when 12 => temp := 'C';\r
+ when 13 => temp := 'D';\r
+ when 14 => temp := 'E';\r
+ when 15 => temp := 'F';\r
+ when 16 => temp := 'G';\r
+ when 17 => temp := 'H';\r
+ when 18 => temp := 'I';\r
+ when 19 => temp := 'J';\r
+ when 20 => temp := 'K';\r
+ when 21 => temp := 'L';\r
+ when 22 => temp := 'M';\r
+ when 23 => temp := 'N';\r
+ when 24 => temp := 'O';\r
+ when 25 => temp := 'P';\r
+ when 26 => temp := 'Q';\r
+ when 27 => temp := 'R';\r
+ when 28 => temp := 'S';\r
+ when 29 => temp := 'T';\r
+ when 30 => temp := 'U';\r
+ when 31 => temp := 'V';\r
+ when 32 => temp := 'W';\r
+ when 33 => temp := 'X';\r
+ when 34 => temp := 'Y';\r
+ when 35 => temp := 'Z';\r
+ when others => temp := '?';\r
+ end case;\r
+return temp;\r
+end function int_to_chr;\r
+--\r
+function int_to_str(int: integer; base: integer) return string is\r
+ variable temp: string(1 to 10);\r
+ variable num: integer;\r
+ variable abs_int: integer;\r
+ variable len: integer := 1;\r
+ variable power: integer := 1;\r
+begin\r
+ abs_int := abs(int); -- Negative numbers\r
+ num := abs_int;\r
+ \r
+ while num >= base loop -- Determine how many\r
+ len := len + 1; -- characters required\r
+ num := num / base; -- to represent the\r
+ end loop ; -- number.\r
+\r
+ for i in len downto 1 loop -- Convert the number to\r
+ temp(i) := int_to_chr(abs_int/power mod base); -- a string starting\r
+ power := power * base; -- with the right hand\r
+ end loop ; -- side.\r
+\r
+ -- return result and add sign if required\r
+ if int < 0 then\r
+ return '-'& temp(1 to len);\r
+ else\r
+ return temp(1 to len);\r
+ end if;\r
+end function int_to_str;\r
+-- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.\r
+-- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.\r
+-- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.\r
+function AdcBits (Bits : integer) return integer is\r
+variable Temp : integer;\r
+begin\r
+ if (Bits = 12) then\r
+ Temp := 12;\r
+ elsif (Bits = 14) then\r
+ Temp := 16;\r
+ elsif (Bits = 16) then\r
+ Temp := 16;\r
+ end if;\r
+return Temp;\r
+end function AdcBits;\r
+\r
+component AdcClock is\r
+ generic (\r
+ C_BufioLoc : string := C_BufioLoc;\r
+ C_BufrLoc : string := C_BufrLoc;\r
+ C_AdcBits : integer := C_AdcBits;\r
+ C_StatTaps : integer := C_StatTaps\r
+ );\r
+ port (\r
+ BitClk : in std_logic;\r
+ BitClkRst : in std_logic;\r
+ BitClkEna : in std_logic;\r
+ BitClkReSync : in std_logic;\r
+ BitClkDivReset : in std_logic;\r
+ BitClk_MonClkOut : out std_logic; -- CLK output\r
+ BitClk_MonClkIn : in std_logic; -- ISERDES.CLK input\r
+ BitClk_RefClkOut : out std_logic; -- CLKDIV & logic output\r
+ BitClk_RefClkIn : in std_logic; -- CLKDIV & logic input\r
+ BitClkAlignWarn : out std_logic;\r
+ BitClkInvrtd : out std_logic;\r
+ BitClkDone : out std_logic\r
+ );\r
+end component;\r
+\r
+component AdcFrame is\r
+ generic (\r
+ C_AdcBits : integer;\r
+ C_AdcWireInt : integer;\r
+ C_FrmPattern : string\r
+ );\r
+ port (\r
+ FrmClk_n : in std_logic; -- input n from IBUFDS_DIFF_OUT\r
+ FrmClk_p : in std_logic; -- input p from IBUFDS_DIFF_OUT\r
+ FrmClkRst : in std_logic;\r
+ FrmClkEna : in std_logic;\r
+ FrmClk : in std_logic;\r
+ FrmClkDiv : in std_logic;\r
+ FrmClkDone : in std_logic; -- Input from clock syncronisation.\r
+ FrmClkReSync : in std_logic;\r
+ FrmClkBitSlip_p : out std_logic;\r
+ FrmClkBitSlip_n : out std_logic;\r
+ FrmClkSwapMux : out std_logic;\r
+ FrmClkMsbRegEna : out std_logic;\r
+ FrmClkLsbRegEna : out std_logic;\r
+ FrmClkReSyncOut : out std_logic;\r
+ FrmClkDat : out std_logic_vector(15 downto 0);\r
+ FrmClkSyncWarn : out std_logic;\r
+ Frame_out : out std_logic;\r
+ testOK : out std_logic;\r
+ testword0 : out std_logic_vector(35 downto 0)
+ );\r
+end component;\r
+\r
+component AdcData is
+ generic (
+ C_AdcBits : integer := C_AdcBits; -- Can be 12, 14 or 16
+ C_AdcBytOrBitMode : integer := 1; -- 1 = BIT mode, 0 = BYTE mode,
+ C_AdcMsbOrLsbFst : integer := 0; -- 0 = MSB first, 1 = LSB first
+ C_AdcWireInt : integer := C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.
+ );
+ port (
+ DatD0_n : in std_logic;
+ DatD0_p : in std_logic;
+ DatD1_n : in std_logic;
+ DatD1_p : in std_logic;
+ DatClk : in std_logic;
+ DatClkDiv : in std_logic;
+ DatRst : in std_logic;
+ DatEna : in std_logic;
+ DatDone : in std_logic;
+ DatBitSlip_p : in std_logic;
+ DatBitSlip_n : in std_logic;
+ DatSwapMux : in std_logic;
+ DatMsbRegEna : in std_logic;
+ DatLsbRegEna : in std_logic;
+ DatReSync : in std_logic;
+ DatOut : out std_logic_vector(31 downto 0)
+ );
+end component;\r
+\r
+attribute keep : string;
+\r
+-- Constants\r
+constant Low : std_logic := '0';\r
+constant High : std_logic := '1';\r
+-- Signals\r
+signal IntIdlyCtrlRdy : std_logic := '0';\r
+signal IntRst0 : std_logic := '0';\r
+signal IntRst : std_logic := '0';\r
+signal IntEna_d : std_logic := '0';\r
+signal IntEna : std_logic := '0';\r
+--\r
+signal IntBitClkDone : std_logic := '0';\r
+signal IntClk : std_logic := '0';\r
+signal IntClkDiv : std_logic := '0';\r
+attribute keep of IntClkDiv : signal is "TRUE";
+signal IntClkBitSlip_p : std_logic := '0';\r
+signal IntClkBitSlip_n : std_logic := '0';\r
+signal IntClkSwapMux : std_logic := '0';\r
+signal IntClkMsbRegEna : std_logic := '0';\r
+signal IntClkLsbRegEna : std_logic := '0';\r
+signal IntFrmClkReSyncOut : std_logic := '0';\r
+signal IntDataOut : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');\r
+signal IntDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');\r
+-- Attributes\r
+attribute LOC : string;\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+signal AdcBitClkAlgnWrn_S : std_logic := '0';
+signal AdcBitClkInvrtd_S : std_logic := '0';
+signal adcfrmsyncwrn_S : std_logic := '0';
+signal AdcIdlyCtrlRdy_S : std_logic := '0';
+signal testOK_S : std_logic := '0';
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');\r
+signal AdcReSync_S : std_logic := '0';
+signal slipoccurred_S : std_logic := '0';\r
+signal slipsoccurred_S : std_logic := '0';\r
+signal slipcounter_S : integer range 0 to 255 := 0;\r
+signal IntBitClkDone_S : std_logic := '0';\r
+signal ClockResync_S : std_logic := '0';\r
+signal ClockResync0_S : std_logic := '0';\r
+\r
+signal IntEna_S : std_logic := '0';\r
+signal IntRst_S : std_logic := '0';\r
+signal frame_S : std_logic := '0';\r
+signal reset_clockdiv_S : std_logic := '0';\r
+\r
+signal AdcData_negedge : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+signal AdcDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+\r
+\r
+-- Attributes\r
+attribute keep of reset_clockdiv_S : signal is "TRUE";\r
+\r
+begin\r
+\r
+AdcClkDiv <= IntClkDiv;\r
+--AdcDataOut <= IntDataOut;\r
+
+--process(IntClkDiv)
+--begin
+-- if falling_edge(IntClkDiv) then
+-- AdcData_negedge <= IntDataOut;
+-- end if;
+--end process;\r
+\r
+process(IntClkDiv)
+begin
+ if rising_edge(IntClkDiv) then
+ IntDataOut_S <= IntDataOut;
+ end if;
+end process;\r
+\r
+process(AdcDataClkNot)
+begin
+ if rising_edge(AdcDataClkNot) then
+ AdcData_negedge <= IntDataOut_S;
+ end if;
+end process;\r
+
+process(AdcDataClk)
+begin
+ if rising_edge(AdcDataClk) then \r
+ AdcDataOut <= AdcDataOut_S;
+ AdcDataOut_S <= AdcData_negedge;
+ end if;
+end process;
+\r
+\r
+-----------------------------------------------------------------------------------------------\r
+-- IDELAYCTRL\r
+-- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole\r
+-- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.\r
+-- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL\r
+-- component is needed.\r
+-- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and\r
+-- enable for each ADC block.\r
+-- Don not forget to LOC the IDELAYCTRL components down.\r
+-----------------------------------------------------------------------------------------------\r
+Gen_0 : if C_AdcUseIdlyCtrl = 0 generate\r
+ AdcIdlyCtrlRdy_S <= High;\r
+end generate Gen_0;\r
+Gen_1 : if C_AdcUseIdlyCtrl = 1 generate\r
+attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;\r
+begin\r
+ AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL\r
+ port map (REFCLK => SysRefClk, RST => reset_clockdiv_S , RDY => AdcIdlyCtrlRdy_S);--peter AdcIntrfcRst\r
+end generate Gen_1;\r
+AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;\r
+-- IntRst and IntEna are the reset and enable signals to be used in the interafce.\r
+-- they are generated from the incomming system enable and reset.\r
+\r
+AdcToplevel_I_Fdpe_Rst : FDPE\r
+ generic map (INIT => '1')\r
+ port map (C => IntClkDiv, CE => High, PRE => reset_clockdiv_S, D => Low, Q => IntRst);--peter AdcIntrfcRst\r
+\r
+ \r
+\r
+AdcToplevel_I_Fdce_Ena_0 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => High, Q => IntEna_d);\r
+AdcToplevel_I_Fdce_Ena_1 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (C => IntClkDiv, CE => High, CLR => IntRst, D => IntEna_d, Q => IntEna);\r
+-----------------------------------------------------------------------------------------------\r
+-- C_AdcChnls = c\r
+-- C_AdcWireInt = w\r
+-- C_AdcBits = b\r
+-----------------------------------------------------------------------------------------------\r
+-- BIT CLOCK\r
+-- IntClk and IntClkDiv are the clock to be used in the interface.\r
+-----------------------------------------------------------------------------------------------\r
+-- There is no IBUFGDS used on this level of the design.\r
+-- The IBUFGDS can be found in the AdcIo level.\r
+-- That is this the reason why the DCLK_n is not used here.\r
+-- At the AdcIo level the DCLK_n output is connected to GND.\r
+AdcToplevel_I_AdcClock : AdcClock -- entity AdcClock.AdcClock\r
+generic map (\r
+ C_BufioLoc => C_BufioLoc, -- string \r
+ C_BufrLoc => C_BufrLoc, -- string\r
+ C_AdcBits => C_AdcBits, -- integer\r
+ C_StatTaps => C_StatTaps -- integer\r
+ )\r
+port map (\r
+ BitClk => DCLK_p, -- in\r
+ BitClkRst => IntRst, -- in\r
+ BitClkEna => '1', -- IntEna_S, -- in\r
+ BitClkReSync => ClockResync_S, -- AdcReSync_S, -- in\r
+ BitClkDivReset => reset_clockdiv_S,\r
+ BitClk_MonClkOut => IntClk, -- out -->--|---->----\r
+ BitClk_MonClkIn => IntClk, -- in --<--|\r
+ BitClk_RefClkOut => IntClkDiv, -- out -->----|-->----\r
+ BitClk_RefClkIn => IntClkDiv, -- in --<----|\r
+ BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out\r
+ BitClkInvrtd => AdcBitClkInvrtd_S, -- out\r
+ BitClkDone => IntBitClkDone -- out Enables the AdcFrame block.\r
+);\r
+AdcBitClkDone <= IntBitClkDone; -- IntBitClkDone_S;\r
+AdcBitClkInvrtd <= AdcBitClkInvrtd_S;
+AdcBitClkAlgnWrn <= AdcBitClkAlgnWrn_S;
+-----------------------------------------------------------------------------------------------\r
+-- WORD / FRAME CLOCK\r
+-----------------------------------------------------------------------------------------------\r
+AdcToplevel_I_AdcFrame : AdcFrame -- entity AdcFrame_Lib.AdcFrame\r
+generic map (\r
+ C_AdcBits => C_AdcBits, -- integer;\r
+ C_AdcWireInt => C_AdcWireInt, -- integer;\r
+ C_FrmPattern => C_FrmPattern -- string -- 1 or 2-wire, 12 or 16(14)-bit\r
+)\r
+port map (\r
+ FrmClk_n => FCLK_n, -- in input n from IBUFDS_DIFF_OUT\r
+ FrmClk_p => FCLK_p, -- in input p from IBUFDS_DIFF_OUT\r
+ FrmClkRst => IntRst_S, -- in\r
+ FrmClkEna => IntEna_S, -- in\r
+ FrmClk => IntClk, -- in\r
+ FrmClkDiv => IntClkDiv, -- in\r
+ FrmClkDone => IntBitClkDone, -- IntBitClkDone_S, -- in From AdcClock done.\r
+ FrmClkReSync => AdcReSync_S, -- in\r
+ FrmClkBitSlip_p => IntClkBitSlip_p, -- out\r
+ FrmClkBitSlip_n => IntClkBitSlip_n, -- out\r
+ FrmClkSwapMux => IntClkSwapMux, -- out\r
+ FrmClkMsbRegEna => IntClkMsbRegEna, -- out\r
+ FrmClkLsbRegEna => IntClkLsbRegEna, -- out\r
+ FrmClkReSyncOut => IntFrmClkReSyncOut, -- out\r
+ FrmClkDat => open, -- out\r
+ FrmClkSyncWarn => AdcFrmSyncWrn_S, -- out\r
+ Frame_out => frame_S,\r
+ testOK => testOK_S,\r
+ testword0 => testword0_S
+);\r
+adcfrmsyncwrn <= adcfrmsyncwrn_S;\r
+testOK <= testOK_S;
+-----------------------------------------------------------------------------------------------\r
+-- DATA INPUTS\r
+-- Default the interface is set in BYTE and MSB first mode.\r
+-- This is coded in the AdcData level and can be mnodified if wanted.\r
+-- Enable the generics and all selection possibilities are available. \r
+-----------------------------------------------------------------------------------------------\r
+Gen_2 : for cw in ((C_AdcChnls/2)*C_AdcWireInt)-1 downto 0 generate\r
+-- assert false\r
+-- report int_to_str((32*((cw+1)+(p*C_AdcChnls))),10)\r
+-- severity note;\r
+ AdcToplevel_I_AdcData : AdcData -- entity AdcData.AdcData\r
+ generic map (\r
+ C_AdcBits => C_AdcBits, -- Can be 12, 14 or 16\r
+ C_AdcWireInt => C_AdcWireInt -- 1 = 1-wire, 2 = 2-wire.\r
+ )\r
+ port map (\r
+ DatD0_n => DATA_n(cw*2), -- in \r
+ DatD0_p => DATA_p(cw*2), -- in \r
+ DatD1_n => DATA_n((cw*2)+1), -- in \r
+ DatD1_p => DATA_p((cw*2)+1), -- in \r
+ DatClk => IntClk, -- in \r
+ DatClkDiv => IntClkDiv, -- in \r
+ DatRst => IntRst_S, -- in \r
+ DatEna => IntEna_S, -- in \r
+ DatDone => IntBitClkDone, -- IntBitClkDone_S, -- in \r
+ DatBitSlip_p => IntClkBitSlip_p, -- in \r
+ DatBitSlip_n => IntClkBitSlip_n, -- in \r
+ DatSwapMux => IntClkSwapMux, -- in \r
+ DatMsbRegEna => IntClkMsbRegEna, -- in \r
+ DatLsbRegEna => IntClkLsbRegEna, -- in \r
+ DatReSync => IntFrmClkReSyncOut, -- in\r
+ DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)\r
+ );\r
+ \r
+ \r
+--AdcDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt)) <= IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt));\r
+\r
+\r
+\r
+end generate Gen_2;\r
+\r
+ \r
+process(IntClkDiv)\r
+begin\r
+ if (rising_edge(IntClkDiv)) then \r
+ AdcReSync_S <= AdcReSync;\r
+ end if;\r
+end process;\r
+\r
+-- reset_clockdiv_S <= '1' when (frame_S='0') and (reset_clockdiv0_S='1') else '0';\r
+reset_clockdiv : FDPE\r
+ generic map (INIT => '1')\r
+ port map (C => frame_S, CE => High, PRE => AdcIntrfcRst, D => Low, Q => reset_clockdiv_S);\r
+\r
+--process(SysRefClk)\r
+--begin\r
+-- if (rising_edge(SysRefClk)) then \r
+-- if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then\r
+-- reset_clockdiv0_S <= '1';\r
+-- elsif frame_S='1' then\r
+-- reset_clockdiv0_S <= '0';\r
+-- end if;\r
+-- end if;\r
+--end process;\r
+\r
+--process(IntClkDiv,reset_clockdiv0_S)\r
+--variable counter_V : integer range 0 to 3 := 0;\r
+--begin\r
+-- if reset_clockdiv0_S='1' then\r
+-- ClockResync_S <= '0';\r
+-- counter_V := 0;\r
+-- elsif (rising_edge(IntClkDiv)) then\r
+-- if counter_V<3 then\r
+-- counter_V := counter_V+1;\r
+-- ClockResync_S <= '1';\r
+-- else\r
+-- ClockResync_S <= '0';\r
+-- end if;\r
+-- end if;\r
+--end process;\r
+ClockResync_S <= ClockResync0_S;\r
+process(IntClkDiv,AdcIntrfcRst) -- reset_clockdiv_S)\r
+begin\r
+-- if reset_clockdiv_S='1' then\r
+ if AdcIntrfcRst='1' then\r
+ slipoccurred_S <= '0';\r
+ slipsoccurred_S <= '0';\r
+ slipcounter_S <= 0;\r
+ ClockResync0_S <= '0';\r
+ IntBitClkDone_S <= '0';\r
+ IntEna_S <= '0';\r
+ IntRst_S <= '0';\r
+ ADCs_ready <= '0';\r
+ elsif (rising_edge(IntClkDiv)) then\r
+ if (IntBitClkDone='0') or (ClockResync_S='1') then\r
+ slipcounter_S <= 0;\r
+ slipoccurred_S <= '0';\r
+ slipsoccurred_S <= '0';\r
+ ClockResync0_S <= '0';\r
+ IntBitClkDone_S <= '0';\r
+ IntEna_S <= '0';\r
+ IntRst_S <= '0';\r
+ ADCs_ready <= '0';\r
+ elsif slipcounter_S<2 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ ClockResync0_S <= '0';\r
+ slipoccurred_S <= '0';\r
+ slipsoccurred_S <= '0';\r
+ IntBitClkDone_S <= '0';\r
+ IntEna_S <= '0';\r
+ IntRst_S <= '0';\r
+ elsif slipcounter_S<31 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ ClockResync0_S <= '0';\r
+ slipoccurred_S <= '0';\r
+ slipsoccurred_S <= '0';\r
+ IntBitClkDone_S <= '0';\r
+ IntEna_S <= '0';\r
+ IntRst_S <= '0';\r
+ elsif slipcounter_S<33 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ IntRst_S <= '1';\r
+ elsif slipcounter_S<63 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ IntRst_S <= '0';\r
+ elsif slipcounter_S<95 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ IntEna_S <= '1';\r
+ elsif slipcounter_S<111 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ IntBitClkDone_S <= '1';\r
+ elsif slipcounter_S<254 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+ IntBitClkDone_S <= '1';\r
+ if (IntClkBitSlip_p='1') then\r
+ if slipoccurred_S='1' then \r
+ slipsoccurred_S <= '1';\r
+ end if;\r
+ slipoccurred_S <= '1';\r
+ end if;\r
+ if (IntClkBitSlip_n='1') then\r
+ slipsoccurred_S <= '1';\r
+ slipoccurred_S <= '1';\r
+ end if;\r
+ elsif slipcounter_S<255 then\r
+ slipcounter_S <= slipcounter_S+1;\r
+-- if (slipsoccurred_S='1') or (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkInvrtd_S='0') or (AdcBitClkAlgnWrn_S='1') then\r
+ if (slipsoccurred_S='1') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then\r
+-- if (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then\r
+ ClockResync0_S <= '1';\r
+ else\r
+ ADCs_ready <= '1';\r
+ end if;\r
+ else\r
+ ClockResync0_S <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+\r
+\r
+\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+\r
+--1000
+testword0(0) <= IntRst;
+testword0(1) <= AdcReSync_S;
+testword0(2) <= AdcBitClkAlgnWrn_S;
+testword0(3) <= AdcBitClkInvrtd_S;\r
+\r
+--0001
+testword0(4) <= IntBitClkDone;
+testword0(5) <= IntClkBitSlip_p;
+testword0(6) <= IntClkBitSlip_n;
+testword0(7) <= IntClkSwapMux;\r
+\r
+--0011
+testword0(8) <= IntRst_S; -- IntClkMsbRegEna;
+testword0(9) <= IntEna_S; -- IntClkLsbRegEna;
+testword0(10) <= IntFrmClkReSyncOut;
+testword0(11) <= AdcFrmSyncWrn_S;\r
+\r
+--1000
+testword0(12) <= AdcIntrfcRst;
+testword0(13) <= testOK_S;\r
+testword0(14) <= Frame_S;\r
+testword0(15) <= AdcIdlyCtrlRdy_S;\r
+\r
+testword0(16) <= AdcReSync_S;\r
+testword0(17) <= slipoccurred_S;\r
+testword0(18) <= slipsoccurred_S;\r
+testword0(19) <= IntBitClkDone_S;\r
+testword0(20) <= ClockResync_S;\r
+testword0(21) <= ClockResync0_S;\r
+testword0(22) <= reset_clockdiv_S;\r
+testword0(23) <= reset_clockdiv_S;\r
+\r
+\r
+-- testword0(23 downto 16) <= testword0_S(7 downto 0);\r
+
+testword0(35 downto 24) <= (others => '0');
+\r
+end AdcToplevel_struct;
\ No newline at end of file
--- /dev/null
+---------------------------------------------------------------------------------------------\r
+-- © Copyright 2011, Xilinx, Inc. All rights reserved.\r
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
+-- protected under U.S. and international copyright and other intellectual property laws.\r
+---------------------------------------------------------------------------------------------\r
+--\r
+-- Disclaimer:\r
+-- This disclaimer is not a license and does not grant any rights to the materials\r
+-- distributed herewith. Except as otherwise provided in a valid license issued to you\r
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+-- negligence, or under any other theory of liability) for any loss or damage of any\r
+-- kind or nature related to, arising under or in connection with these materials,\r
+-- including for any direct, or any indirect, special, incidental, or consequential\r
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
+-- damage suffered as a result of any action brought by a third party) even if such\r
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+--\r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
+-- application requiring fail-safe performance, such as life-support or safety devices\r
+-- or systems, Class III medical devices, nuclear facilities, applications related to\r
+-- the deployment of airbags, or any other applications that could lead to death,\r
+-- personal injury, or severe property or environmental damage (individually and\r
+-- collectively, "Critical Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical Applications, subject only to\r
+-- applicable laws and regulations governing limitations on product liability.\r
+--\r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.\r
+--\r
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx Inc.\r
+-- \ \ \/ Version:\r
+-- \ \ Filename: DoubleNibbleDetect.vhd\r
+-- / / Date Created: 16 March, 2011\r
+-- /___/ /\ Date Last Modified: 16 March, 2011\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Device: Virtex-6\r
+-- Author: defossez\r
+-- Entity Name: DoubleNibbleDetect\r
+-- Purpose: Create a on-off signal that already reacts at the combinatorial input.\r
+-- Tools: ISE_13.1\r
+-- Limitations: none\r
+--\r
+-- Revision History:\r
+-- Rev.\r
+--\r
+------------------------------------------------------------------------------\r
+-- Naming Conventions:\r
+-- active low signals: "*_n"\r
+-- clock signals: "clk", "clk_div#", "clk_#x"\r
+-- reset signals: "rst", "rst_n"\r
+-- generics: "C_*"\r
+-- user defined types: "*_TYPE"\r
+-- state machine next state: "*_ns"\r
+-- state machine current state: "*_cs"\r
+-- combinatorial signals: "*_com"\r
+-- pipelined or register delay signals: "*_d#"\r
+-- counter signals: "*cnt*"\r
+-- clock enable signals: "*_ce"\r
+-- internal version of output port: "*_i"\r
+-- device pins: "*_pin"\r
+-- ports: "- Names begin with Uppercase"\r
+-- processes: "*_PROCESS"\r
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
+---------------------------------------------------------------------------------------------\r
+library IEEE;\r
+ use IEEE.std_logic_1164.all;\r
+ use IEEE.std_logic_UNSIGNED.all;\r
+library UNISIM;\r
+ use UNISIM.vcomponents.all;\r
+---------------------------------------------------------------------------------------------\r
+-- Entity pin description\r
+---------------------------------------------------------------------------------------------\r
+-- Clock : Clock for the design.\r
+-- RstIn : Reset input. Resets the necessary logic at startup.\r
+-- Final : This circuit checks a nibble (4-bit) for appearing twice, when for rotations or\r
+-- slips are made, teh fifth ossurence resets the circuit. this is signalled ouside\r
+-- so that a upper layer of design can take action. \r
+-- DataIn : Nibble input.\r
+-- DataOut : Corrected nibble output.\r
+---------------------------------------------------------------------------------------------\r
+entity DoubleNibbleDetect is\r
+ port (\r
+ Clock : in std_logic;\r
+ RstIn : in std_logic;\r
+ Final : out std_logic;\r
+ DataIn : in std_logic_vector(3 downto 0);\r
+ DataOut : out std_logic_vector(3 downto 0)\r
+ );\r
+end DoubleNibbleDetect;\r
+---------------------------------------------------------------------------------------------\r
+-- Architecture section\r
+---------------------------------------------------------------------------------------------\r
+architecture DoubleNibbleDetect_struct of DoubleNibbleDetect is\r
+---------------------------------------------------------------------------------------------\r
+-- Component Instantiation\r
+---------------------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------------------\r
+-- Constants, Signals and Attributes Declarations\r
+---------------------------------------------------------------------------------------------\r
+-- Functions\r
+-- Constants\r
+constant Low : std_logic := '0';\r
+constant High : std_logic := '1';\r
+-- Signals\r
+signal IntRegOutIn : std_logic_vector(3 downto 0);\r
+signal IntAddr : std_logic_vector(4 downto 0);\r
+signal IntSrlOut : std_logic_vector(3 downto 0);\r
+--\r
+signal IntRegOutIn_s : std_logic_vector(3 downto 0);\r
+signal IntAddr_s : std_logic_vector(4 downto 0);\r
+signal IntSrlOut_s : std_logic_vector(3 downto 0);\r
+signal DataOut_s : std_logic_vector(3 downto 0);\r
+--\r
+signal IntEqu : std_logic;\r
+signal IntEqu_d : std_logic;\r
+signal IntPulse : std_logic;\r
+signal IntSlipCnt : std_logic_vector(3 downto 0);\r
+signal IntSlipCnt_d : std_logic_vector(3 downto 0);\r
+signal IntSlipCntRst : std_logic;\r
+signal IntEquCnt : std_logic_vector(3 downto 0);\r
+signal IntEquCnt_d : std_logic_vector(3 downto 0);\r
+--\r
+signal IntRstSet : std_logic;\r
+signal IntRstIn : std_logic;\r
+signal IntRstFf_d : std_logic_vector(7 downto 0) := X"00";\r
+signal IntRstIn_d : std_logic;\r
+--\r
+signal IntAddrSet : std_logic_vector(3 downto 0);\r
+-- Attributes\r
+attribute IOB : string;\r
+attribute HBLKNM : string;\r
+---------------------------------------------------------------------------------------------\r
+begin\r
+---------------------------------------------------------------------------------------------\r
+-- Delay the start of the ciruit after reset.\r
+---------------------------------------------------------------------------------------------\r
+IntRstIn <= RstIn or IntRstSet;\r
+--\r
+Gen_Rst : for n in 0 to 7 generate\r
+ Reg_Lsb : if n = 0 generate\r
+ DbleNibl_I_Fdse : FDSE -- Synchronous set\r
+ generic map (INIT => '0')\r
+ port map (D => Low, CE => High, C => Clock, S => IntRstSet, Q => IntRstFf_d(n));\r
+ end generate Reg_Lsb;\r
+ Reg_MidL : if n > 0 and n <= 5 generate\r
+ DbleNibl_I_Fdse : FDSE -- Synchronous set\r
+ generic map (INIT => '0')\r
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstSet,\r
+ Q => IntRstFf_d(n));\r
+ end generate Reg_MidL;\r
+ Reg_MidH : if n = 6 generate\r
+ DbleNibl_I_Fdse : FDSE -- Synchronous set\r
+ generic map (INIT => '0')\r
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,\r
+ Q => IntRstFf_d(n));\r
+ end generate Reg_MidH;\r
+ Reg_Msb : if n = 7 generate\r
+ DbleNibl_I_Fdse : FDSE -- Synchronous set\r
+ generic map (INIT => '0')\r
+ port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,\r
+ Q => IntRstFf_d(n));\r
+ --\r
+ IntRstIn_d <= IntRstFf_d(n);\r
+ end generate Reg_Msb;\r
+end generate Gen_Rst;\r
+---------------------------------------------------------------------------------------------\r
+-- Data path registers\r
+---------------------------------------------------------------------------------------------\r
+Gen_Reg : for n in 3 downto 0 generate\r
+ In_I_Fdce : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => DataIn(n), CE => High, C => Clock, CLR => IntRstIn_d,\r
+ Q => IntRegOutIn_s(n));\r
+IntRegOutIn(n) <= IntRegOutIn_s(n); -- after 100 ps;\r
+ DbleNibl_I_Srlc32e : SRLC32E\r
+ generic map (INIT => X"00000000")\r
+ port map (D => IntRegOutIn(n), A => IntAddr, CE => High, CLK => Clock, Q31 => open,\r
+ Q => IntSrlOut_s(n));\r
+IntSrlOut(n) <= IntSrlOut_s(n); -- after 100 ps;\r
+ Out_I_Fdce : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntSrlOut(n), CE => High, C => Clock, CLR => IntRstIn_d,\r
+ Q => DataOut_s(n));\r
+DataOut(n) <= DataOut_s(n); -- after 100 ps;\r
+end generate Gen_Reg;\r
+---------------------------------------------------------------------------------------------\r
+-- Compare present and past for equality.\r
+---------------------------------------------------------------------------------------------\r
+IntEqu <= '1' when (DataIn = IntRegOutIn) else '0';\r
+-----------------------------------------------------------------------------------------------\r
+-- Generate the SRL addresses\r
+---------------------------------------------------------------------------------------------\r
+IntAddr(3 downto 0) <= "0100" when (IntEquCnt_d = "0000" and IntSlipCnt_d = "0000") else\r
+ "0011" when (IntEquCnt_d = "0001" and IntSlipCnt_d = "0111") else\r
+ "0010" when (IntEquCnt_d = "0011" and IntSlipCnt_d = "0110") else\r
+ "0001" when (IntEquCnt_d = "0010" and IntSlipCnt_d = "0010") else\r
+ "0000" when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0011") else\r
+ "0100" when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001");\r
+IntAddr(4) <= Low;\r
+--IntRstSet <= '1' when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001") else '0';\r
+IntRstSet <= '1' when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0000" and IntPulse = '1')\r
+ else '0';\r
+Final <= IntRstSet;\r
+---------------------------------------------------------------------------------------------\r
+-- Equal/Double nibble detect counters\r
+---------------------------------------------------------------------------------------------\r
+IntPulse <= IntEqu or IntEqu_d;\r
+--\r
+DbleNibl_I_Fdce : FDCE -- Asynchronous reset\r
+ generic map (INIT => '0')\r
+ port map (D => High, CE => IntEqu, C => Clock, CLR => IntSlipCntRst, Q => IntEqu_d);\r
+-- When a double nibble is detected shift the pulse over four taps and reset the shifter\r
+-- at the fifth tap.\r
+---------------------------------------------------------------------------------------------\r
+-- Slip Counter\r
+-- When equality is detected, this counter counts till a preset number and then resets.\r
+---------------------------------------------------------------------------------------------\r
+IntSlipCntRst <= '1' when (IntRstIn_d = '1' or IntSlipCnt_d = "0101") else '0';\r
+--\r
+Gen_SlipCnt : for n in 3 downto 0 generate\r
+ attribute HBLKNM of Cnt_I_Fdre : label is "SlipCnt";\r
+ attribute IOB of Cnt_I_Fdre : label is "FALSE";\r
+ begin\r
+ Cnt_I_Fdre : FDRE -- Synchronous reset\r
+ generic map (INIT => '0')\r
+ port map (D => IntSlipCnt(n), CE => IntPulse, C => Clock, R => IntSlipCntRst,\r
+ Q => IntSlipCnt_d(n));\r
+end generate Gen_SlipCnt;\r
+-- These ar the "SlipCnt" states, orginized in Gray mode\r
+DbleNibl_SlipCnt_PROCESS : process (IntSlipCnt_d)\r
+begin\r
+ case IntSlipCnt_d(3 downto 0) is\r
+ when "0000" => IntSlipCnt <= "0001"; -- after 100 ps;\r
+ when "0001" => IntSlipCnt <= "0011"; -- after 100 ps;\r
+ when "0011" => IntSlipCnt <= "0010"; -- after 100 ps;\r
+ when "0010" => IntSlipCnt <= "0110"; -- after 100 ps;\r
+ when "0110" => IntSlipCnt <= "0111"; -- after 100 ps;\r
+ when "0111" => IntSlipCnt <= "0101"; -- after 100 ps;\r
+ when "0101" => IntSlipCnt <= "0000"; -- after 100 ps;\r
+ when others => IntSlipCnt <= "0000"; -- after 100 ps;\r
+ end case;\r
+end process;\r
+---------------------------------------------------------------------------------------------\r
+-- Equ Counter\r
+-- Count how many times a double nibble is detected.\r
+-- becuase a nibble of data is taken, it can only be four times.\r
+-- When equality is detected for the fift time the system is reset.\r
+---------------------------------------------------------------------------------------------\r
+Gen_EquCnt : for n in 3 downto 0 generate\r
+ attribute HBLKNM of Equ_I_Fdre : label is "EquCnt";\r
+ attribute IOB of Equ_I_Fdre : label is "FALSE";\r
+ begin\r
+ Equ_I_Fdre : FDRE -- Synchronous reset\r
+ generic map (INIT => '0')\r
+ port map (D => IntEquCnt(n), CE => IntEqu, C => Clock, R => IntRstIn_d,\r
+ Q => IntEquCnt_d(n));\r
+end generate Gen_EquCnt;\r
+--\r
+DbleNibl_EquCnt_PROCESS : process (IntEquCnt_d)\r
+begin\r
+ case IntEquCnt_d(3 downto 0) is\r
+ when "0000" => IntEquCnt <= "0001"; -- after 100 ps;\r
+ when "0001" => IntEquCnt <= "0011"; -- after 100 ps;\r
+ when "0011" => IntEquCnt <= "0010"; -- after 100 ps;\r
+ when "0010" => IntEquCnt <= "0110"; -- after 100 ps;\r
+ when "0110" => IntEquCnt <= "0111"; -- after 100 ps;\r
+ when "0111" => IntEquCnt <= "0101"; -- after 100 ps;\r
+ when "0101" => IntEquCnt <= "0100"; -- after 100 ps;\r
+ when "0100" => IntEquCnt <= "1100"; -- after 100 ps;\r
+ when "1100" => IntEquCnt <= "1101"; -- after 100 ps;\r
+ when "1101" => IntEquCnt <= "1111"; -- after 100 ps;\r
+ when "1111" => IntEquCnt <= "1110"; -- after 100 ps;\r
+ when "1110" => IntEquCnt <= "1010"; -- after 100 ps;\r
+ when "1010" => IntEquCnt <= "1011"; -- after 100 ps;\r
+ when "1011" => IntEquCnt <= "1001"; -- after 100 ps;\r
+ when "1001" => IntEquCnt <= "1000"; -- after 100 ps;\r
+ when "1000" => IntEquCnt <= "0000"; -- after 100 ps;\r
+ when others => IntEquCnt <= "0000"; -- after 100 ps;\r
+ end case;\r
+end process;\r
+--\r
+---------------------------------------------------------------------------------------------\r
+end DoubleNibbleDetect_struct;\r
--- /dev/null
+-----------------------------------------------------------------------------------------------\r
+-- © Copyright 2008 - 2009, Xilinx, Inc. All rights reserved.\r
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is\r
+-- protected under U.S. and international copyright and other intellectual property laws.\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+-- Disclaimer:\r
+-- This disclaimer is not a license and does not grant any rights to the materials\r
+-- distributed herewith. Except as otherwise provided in a valid license issued to you\r
+-- by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS\r
+-- ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL\r
+-- WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED\r
+-- TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR\r
+-- PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including\r
+-- negligence, or under any other theory of liability) for any loss or damage of any\r
+-- kind or nature related to, arising under or in connection with these materials,\r
+-- including for any direct, or any indirect, special, incidental, or consequential\r
+-- loss or damage (including loss of data, profits, goodwill, or any type of loss or\r
+-- damage suffered as a result of any action brought by a third party) even if such\r
+-- damage or loss was reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+--\r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any\r
+-- application requiring fail-safe performance, such as life-support or safety devices\r
+-- or systems, Class III medical devices, nuclear facilities, applications related to\r
+-- the deployment of airbags, or any other applications that could lead to death,\r
+-- personal injury, or severe property or environmental damage (individually and\r
+-- collectively, "Critical Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical Applications, subject only to\r
+-- applicable laws and regulations governing limitations on product liability.\r
+--\r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. \r
+--\r
+-- Contact: e-mail hotline@xilinx.com phone + 1 800 255 7778\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version: \r
+-- \ \ Filename: GenPulse.vhd\r
+-- / / Date Last Modified: \r
+-- /___/ /\ Date Created: 08 Mar 08 \r
+-- \ \ / \\r
+-- \___\/\___\\r
+-- \r
+-- Device: \r
+-- Author: Marc Defossez\r
+-- Entity Name: GenPulse\r
+-- Purpose: Generate a clock cycle wide pulse from a wide high input\r
+-- Tools: ISE_10.1\r
+-- Limitations: none\r
+--\r
+-- Revision History:\r
+-- Rev. \r
+--\r
+-----------------------------------------------------------------------------------------------\r
+-- Naming Conventions:\r
+-- active low signals: "*_n"\r
+-- clock signals: "clk", "clk_div#", "clk_#x"\r
+-- reset signals: "rst", "rst_n"\r
+-- generics: "C_*"\r
+-- user defined types: "*_TYPE"\r
+-- state machine next state: "*_ns"\r
+-- state machine current state: "*_cs"\r
+-- combinatorial signals: "*_com"\r
+-- pipelined or register delay signals: "*_d#"\r
+-- counter signals: "*cnt*"\r
+-- clock enable signals: "*_ce"\r
+-- internal version of output port: "*_i"\r
+-- device pins: "*_pin"\r
+-- ports: "- Names begin with Uppercase"\r
+-- processes: "*_PROCESS"\r
+-- component instantiations: "<ENTITY_>I_<#|FUNC>"\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+library IEEE;\r
+ use IEEE.std_logic_1164.all;\r
+ use IEEE.std_logic_UNSIGNED.all;\r
+library UNISIM;\r
+ use UNISIM.VCOMPONENTS.all;\r
+-----------------------------------------------------------------------------------------------\r
+-- Entity pin description\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+-----------------------------------------------------------------------------------------------\r
+entity GenPulse is\r
+ port (\r
+ Clk : in std_logic;\r
+ Ena : in std_logic;\r
+ SigIn : in std_logic;\r
+ SigOut : out std_logic\r
+ );\r
+end GenPulse;\r
+\r
+-----------------------------------------------------------------------------------------------\r
+-- Arcitecture section\r
+-----------------------------------------------------------------------------------------------\r
+architecture GenPulse_struct of GenPulse is\r
+-----------------------------------------------------------------------------------------------\r
+-- Component Instantiation\r
+-----------------------------------------------------------------------------------------------\r
+-----------------------------------------------------------------------------------------------\r
+-- Constants, Signals and Attributes Declarations\r
+-----------------------------------------------------------------------------------------------\r
+-- Functions\r
+-- Constants\r
+-- constant Low : std_logic := '0';\r
+-- constant High : std_logic := '1';\r
+-- Signals\r
+signal IntSigOut : std_logic;\r
+signal IntSigIn_n : std_logic;\r
+signal IntSigClr : std_logic;\r
+-- Attributes\r
+-----------------------------------------------------------------------------------------------\r
+--\r
+begin\r
+--\r
+GenPulse_I_Fdce_1 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => SigIn, C => Clk, CLR => IntSigClr, CE => Ena, Q => IntSigOut);\r
+--\r
+IntSigIn_n <= not SigIn;\r
+--\r
+GenPulse_I_Fdce_2 : FDCE\r
+ generic map (INIT => '0')\r
+ port map (D => IntSigOut, C => Clk, CLR => IntSigIn_n, CE => IntSigOut, Q => IntSigClr);\r
+--\r
+SigOut <= IntSigOut;\r
+--\r
+-----------------------------------------------------------------------------------------------\r
+end GenPulse_struct;\r
+--
\ No newline at end of file
--- /dev/null
+---------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 23-9-2014
+-- Module Name: FEE_ADCinput_module
+-- Description: Module to convert serial data from ADCs (LTM9009-14) to parallel
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_ADCinput_module
+-- Module to convert serial data from ADCs (LTM9009-14) to parallel
+-- Based on Xilinx serial ADC reference design
+--
+--
+-- Library:
+--
+-- Generics:
+--
+-- Inputs:
+-- clock200MHz : 200MHz clock input for IODELAYCTRL
+-- reset : reset ADCs\r
+-- ADCs_enable : enable signal for ADCs
+-- AD*_P : serial data links from ADCs, LVDS positive
+-- AD*_N : serial data links from ADCs, LVDS negative
+-- DCO*_P : data clock from ADCs, LVDS positive
+-- DCO*_N : data clock from ADCs, LVDS negative
+-- FRA*_P : frame start signals from ADCs, LVDS positive
+-- FRA*_N : frame start signals from ADCs, LVDS negative
+--
+-- Outputs:
+-- ADC_clk : clock for parallel ADC data
+-- adcdata : parallel ADC data
+--
+-- Components:
+-- AdcToplevel : top-level module from Xilinx serial ADC reference design
+--
+----------------------------------------------------------------------------------
+
+entity FEE_ADCinput_module is
+ port (
+ clock200MHz : in std_logic;
+ reset : in std_logic;
+ ADCs_enable : in std_logic;
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+ ADC_clk : out std_logic;
+ ADCs_ready : out std_logic;\r
+ adcdata : out array_adc_type
+ );
+end FEE_ADCinput_module;
+
+architecture Behavioral of FEE_ADCinput_module is
+
+
+
+component AdcToplevel is
+ generic (
+ C_AdcChnls : integer := 4; -- Number of ADC in a package
+ C_AdcWireInt : integer := 2; -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc : string := "BUFIODQS_X1Y15";
+ C_BufrLoc : string := "BUFR_X0Y6";
+ C_AdcBits : integer := 16;
+ C_StatTaps : integer := 16;
+ C_AdcUseIdlyCtrl : integer := 1; -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc : string := "IDELAYCTRL_X0Y3";
+ C_FrmPattern : string := "0000000000001111" -- "0000000011110000" -- Read above text!
+ );
+ port (
+ DCLK_p : in std_logic;
+ DCLK_n : in std_logic; -- Not used.
+ FCLK_p : in std_logic;
+ FCLK_n : in std_logic;
+ DATA_p : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ DATA_n : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
+ -- application connections
+ SysRefClk : in std_logic; -- 200 MHz for IODELAYCTRL from application
+ AdcIntrfcRst : in std_logic;
+ AdcIntrfcEna : in std_logic;
+ AdcReSync : in std_logic;
+ AdcFrmSyncWrn : out std_logic;
+ AdcBitClkAlgnWrn : out std_logic;
+ AdcBitClkInvrtd : out std_logic;
+ AdcBitClkDone : out std_logic;
+ AdcIdlyCtrlRdy : out std_logic;
+
+ AdcClkDiv : out std_logic;
+ AdcDataClk : in std_logic;
+ AdcDataClkNot : in std_logic;
+ AdcDataOut : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
+ ADCs_ready : out std_logic;\r
+ testOK : out std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;\r
+
+component FEE_clockbuf80MHz\r
+ port(\r
+ CLK_IN1 : in std_logic;\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic\r
+ );\r
+end component;\r
+\r
+function TermOrNot (Term : integer) return boolean is
+begin
+ if (Term = 0) then
+ return FALSE;
+ else
+ return TRUE;
+ end if;
+end TermOrNot;
+\r
+constant C_OnChipLvdsTerm : integer := 1;\r
+
+--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0);
+
+signal adcdata1458_P : adcdataserial_type;
+signal adcdata1458_N : adcdataserial_type;
+signal adcdata2367_P : adcdataserial_type;
+signal adcdata2367_N : adcdataserial_type;
+
+signal DCOA1_P_S : std_logic;
+signal DCOA1_N_S : std_logic;
+signal DCOA2_P_S : std_logic;
+signal DCOA2_N_S : std_logic;
+signal DCOA3_P_S : std_logic;
+signal DCOA3_N_S : std_logic;
+signal DCOA4_P_S : std_logic;
+signal DCOA4_N_S : std_logic;
+
+signal DCOB1_P_S : std_logic;
+signal DCOB1_N_S : std_logic;
+signal DCOB2_P_S : std_logic;
+signal DCOB2_N_S : std_logic;
+signal DCOB3_P_S : std_logic;
+signal DCOB3_N_S : std_logic;
+signal DCOB4_P_S : std_logic;
+signal DCOB4_N_S : std_logic;
+
+signal FRA1_P_S : std_logic;
+signal FRA1_N_S : std_logic;
+signal FRA2_P_S : std_logic;
+signal FRA2_N_S : std_logic;
+signal FRA3_P_S : std_logic;
+signal FRA3_N_S : std_logic;
+signal FRA4_P_S : std_logic;
+signal FRA4_N_S : std_logic;
+
+signal FRB1_P_S : std_logic;
+signal FRB1_N_S : std_logic;
+signal FRB2_P_S : std_logic;
+signal FRB2_N_S : std_logic;
+signal FRB3_P_S : std_logic;
+signal FRB3_N_S : std_logic;
+signal FRB4_P_S : std_logic;
+signal FRB4_N_S : std_logic;
+
+signal AdcFrmSyncWrnA_S : std_logic_vector(0 to 3);
+signal AdcBitClkAlgnWrnA_S : std_logic_vector(0 to 3);
+signal AdcBitClkDoneA_S : std_logic_vector(0 to 3);
+signal AdcIdlyCtrlRdyA_S : std_logic_vector(0 to 3);
+signal AdcBitClkInvrtdA_S : std_logic_vector(0 to 3);
+signal adcclockA_S : std_logic_vector(0 to 3);
+signal AdcDataOutA_S : AdcDataOut_type;
+
+signal AdcFrmSyncWrnB_S : std_logic_vector(0 to 3);
+signal AdcBitClkAlgnWrnB_S : std_logic_vector(0 to 3);
+signal AdcBitClkDoneB_S : std_logic_vector(0 to 3);
+signal AdcIdlyCtrlRdyB_S : std_logic_vector(0 to 3);
+signal AdcBitClkInvrtdB_S : std_logic_vector(0 to 3);
+signal adcclockB_S : std_logic_vector(0 to 3);
+signal AdcDataOutB_S : AdcDataOut_type;
+\r
+signal ADCs_ready_S : std_logic_vector(0 to 7);
+
+signal adcdata0_S : array_adc_type;
+signal adcdata1_S : array_adc_type;
+
+signal ADC_clk_S : std_logic;\r
+signal ADC_clknot_S : std_logic;\r
+
+attribute keep : string;\r
+attribute keep of ADC_clk_S : signal is "TRUE";\r
+attribute keep of ADC_clknot_S: signal is "TRUE";\r
+
+begin
+
+ADC_clk <= ADC_clk_S;
+ADCs_ready <= '1' when (ADCs_ready_S=x"ff") and (reset='0') else '0';\r
+\r
+
+-- ADC inputs ----------------------------------------------------------------------
+---- B and A swopped !!!
+adcdata1458_0B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD11B_P, IB => AD11B_N, O => adcdata1458_P(0)(0), OB => adcdata1458_N(0)(0));
+adcdata1458_0A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD11A_P, IB => AD11A_N, O => adcdata1458_P(0)(1), OB => adcdata1458_N(0)(1));
+adcdata1458_0B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD14B_P, IB => AD14B_N, O => adcdata1458_P(0)(2), OB => adcdata1458_N(0)(2));
+adcdata1458_0A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD14A_P, IB => AD14A_N, O => adcdata1458_P(0)(3), OB => adcdata1458_N(0)(3));
+adcdata1458_0B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD15B_P, IB => AD15B_N, O => adcdata1458_P(0)(4), OB => adcdata1458_N(0)(4));
+adcdata1458_0A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD15A_P, IB => AD15A_N, O => adcdata1458_P(0)(5), OB => adcdata1458_N(0)(5));
+adcdata1458_0B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD18B_P, IB => AD18B_N, O => adcdata1458_P(0)(6), OB => adcdata1458_N(0)(6));
+adcdata1458_0A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD18A_P, IB => AD18A_N, O => adcdata1458_P(0)(7), OB => adcdata1458_N(0)(7));
+
+adcdata2367_0B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD12B_P, IB => AD12B_N, O => adcdata2367_P(0)(0), OB => adcdata2367_N(0)(0));
+adcdata2367_0A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD12A_P, IB => AD12A_N, O => adcdata2367_P(0)(1), OB => adcdata2367_N(0)(1));
+adcdata2367_0B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD13B_P, IB => AD13B_N, O => adcdata2367_P(0)(2), OB => adcdata2367_N(0)(2));
+adcdata2367_0A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD13A_P, IB => AD13A_N, O => adcdata2367_P(0)(3), OB => adcdata2367_N(0)(3));
+adcdata2367_0B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD16B_P, IB => AD16B_N, O => adcdata2367_P(0)(4), OB => adcdata2367_N(0)(4));
+adcdata2367_0A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD16A_P, IB => AD16A_N, O => adcdata2367_P(0)(5), OB => adcdata2367_N(0)(5));
+adcdata2367_0B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD17B_P, IB => AD17B_N, O => adcdata2367_P(0)(6), OB => adcdata2367_N(0)(6));
+adcdata2367_0A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD17A_P, IB => AD17A_N, O => adcdata2367_P(0)(7), OB => adcdata2367_N(0)(7));
+
+adcdata1458_1B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD21B_P, IB => AD21B_N, O => adcdata1458_P(1)(0), OB => adcdata1458_N(1)(0));
+adcdata1458_1A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD21A_P, IB => AD21A_N, O => adcdata1458_P(1)(1), OB => adcdata1458_N(1)(1));
+adcdata1458_1B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD24B_P, IB => AD24B_N, O => adcdata1458_P(1)(2), OB => adcdata1458_N(1)(2));
+adcdata1458_1A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD24A_P, IB => AD24A_N, O => adcdata1458_P(1)(3), OB => adcdata1458_N(1)(3));
+adcdata1458_1B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD25B_P, IB => AD25B_N, O => adcdata1458_P(1)(4), OB => adcdata1458_N(1)(4));
+adcdata1458_1A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD25A_P, IB => AD25A_N, O => adcdata1458_P(1)(5), OB => adcdata1458_N(1)(5));
+adcdata1458_1B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD28B_P, IB => AD28B_N, O => adcdata1458_P(1)(6), OB => adcdata1458_N(1)(6));
+adcdata1458_1A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD28A_P, IB => AD28A_N, O => adcdata1458_P(1)(7), OB => adcdata1458_N(1)(7));
+
+adcdata2367_1B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD22B_P, IB => AD22B_N, O => adcdata2367_P(1)(0), OB => adcdata2367_N(1)(0));
+adcdata2367_1A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD22A_P, IB => AD22A_N, O => adcdata2367_P(1)(1), OB => adcdata2367_N(1)(1));
+adcdata2367_1B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD23B_P, IB => AD23B_N, O => adcdata2367_P(1)(2), OB => adcdata2367_N(1)(2));
+adcdata2367_1A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD23A_P, IB => AD23A_N, O => adcdata2367_P(1)(3), OB => adcdata2367_N(1)(3));
+adcdata2367_1B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD26B_P, IB => AD26B_N, O => adcdata2367_P(1)(4), OB => adcdata2367_N(1)(4));
+adcdata2367_1A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD26A_P, IB => AD26A_N, O => adcdata2367_P(1)(5), OB => adcdata2367_N(1)(5));
+adcdata2367_1B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD27B_P, IB => AD27B_N, O => adcdata2367_P(1)(6), OB => adcdata2367_N(1)(6));
+adcdata2367_1A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD27A_P, IB => AD27A_N, O => adcdata2367_P(1)(7), OB => adcdata2367_N(1)(7));
+
+adcdata1458_2B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD31B_P, IB => AD31B_N, O => adcdata1458_P(2)(0), OB => adcdata1458_N(2)(0));
+adcdata1458_2A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD31A_P, IB => AD31A_N, O => adcdata1458_P(2)(1), OB => adcdata1458_N(2)(1));
+adcdata1458_2B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD34B_P, IB => AD34B_N, O => adcdata1458_P(2)(2), OB => adcdata1458_N(2)(2));
+adcdata1458_2A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD34A_P, IB => AD34A_N, O => adcdata1458_P(2)(3), OB => adcdata1458_N(2)(3));
+adcdata1458_2B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD35B_P, IB => AD35B_N, O => adcdata1458_P(2)(4), OB => adcdata1458_N(2)(4));
+adcdata1458_2A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD35A_P, IB => AD35A_N, O => adcdata1458_P(2)(5), OB => adcdata1458_N(2)(5));
+adcdata1458_2B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD38B_P, IB => AD38B_N, O => adcdata1458_P(2)(6), OB => adcdata1458_N(2)(6));
+adcdata1458_2A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD38A_P, IB => AD38A_N, O => adcdata1458_P(2)(7), OB => adcdata1458_N(2)(7));
+
+adcdata2367_2B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD32B_P, IB => AD32B_N, O => adcdata2367_P(2)(0), OB => adcdata2367_N(2)(0));
+adcdata2367_2A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD32A_P, IB => AD32A_N, O => adcdata2367_P(2)(1), OB => adcdata2367_N(2)(1));
+adcdata2367_2B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD33B_P, IB => AD33B_N, O => adcdata2367_P(2)(2), OB => adcdata2367_N(2)(2));
+adcdata2367_2A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD33A_P, IB => AD33A_N, O => adcdata2367_P(2)(3), OB => adcdata2367_N(2)(3));
+adcdata2367_2B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD36B_P, IB => AD36B_N, O => adcdata2367_P(2)(4), OB => adcdata2367_N(2)(4));
+adcdata2367_2A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD36A_P, IB => AD36A_N, O => adcdata2367_P(2)(5), OB => adcdata2367_N(2)(5));
+adcdata2367_2B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD37B_P, IB => AD37B_N, O => adcdata2367_P(2)(6), OB => adcdata2367_N(2)(6));
+adcdata2367_2A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD37A_P, IB => AD37A_N, O => adcdata2367_P(2)(7), OB => adcdata2367_N(2)(7));
+
+adcdata1458_3B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD41B_P, IB => AD41B_N, O => adcdata1458_P(3)(0), OB => adcdata1458_N(3)(0));
+adcdata1458_3A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD41A_P, IB => AD41A_N, O => adcdata1458_P(3)(1), OB => adcdata1458_N(3)(1));
+adcdata1458_3B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD44B_P, IB => AD44B_N, O => adcdata1458_P(3)(2), OB => adcdata1458_N(3)(2));
+adcdata1458_3A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD44A_P, IB => AD44A_N, O => adcdata1458_P(3)(3), OB => adcdata1458_N(3)(3));
+adcdata1458_3B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD45B_P, IB => AD45B_N, O => adcdata1458_P(3)(4), OB => adcdata1458_N(3)(4));
+adcdata1458_3A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD45A_P, IB => AD45A_N, O => adcdata1458_P(3)(5), OB => adcdata1458_N(3)(5));
+adcdata1458_3B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD48B_P, IB => AD48B_N, O => adcdata1458_P(3)(6), OB => adcdata1458_N(3)(6));
+adcdata1458_3A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD48A_P, IB => AD48A_N, O => adcdata1458_P(3)(7), OB => adcdata1458_N(3)(7));
+
+adcdata2367_3B0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD42B_P, IB => AD42B_N, O => adcdata2367_P(3)(0), OB => adcdata2367_N(3)(0));
+adcdata2367_3A0 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD42A_P, IB => AD42A_N, O => adcdata2367_P(3)(1), OB => adcdata2367_N(3)(1));
+adcdata2367_3B1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD43B_P, IB => AD43B_N, O => adcdata2367_P(3)(2), OB => adcdata2367_N(3)(2));
+adcdata2367_3A1 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD43A_P, IB => AD43A_N, O => adcdata2367_P(3)(3), OB => adcdata2367_N(3)(3));
+adcdata2367_3B2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD46B_P, IB => AD46B_N, O => adcdata2367_P(3)(4), OB => adcdata2367_N(3)(4));
+adcdata2367_3A2 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD46A_P, IB => AD46A_N, O => adcdata2367_P(3)(5), OB => adcdata2367_N(3)(5));
+adcdata2367_3B3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD47B_P, IB => AD47B_N, O => adcdata2367_P(3)(6), OB => adcdata2367_N(3)(6));
+adcdata2367_3A3 : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => AD47A_P, IB => AD47A_N, O => adcdata2367_P(3)(7), OB => adcdata2367_N(3)(7));
+
+DCOA1_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA1_P, IB => DCOA1_N, O => DCOA1_P_S);
+DCOA1_N_S <= '0';
+DCOA2_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA2_P, IB => DCOA2_N, O => DCOA2_P_S);
+DCOA2_N_S <= '0';
+DCOA3_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA3_P, IB => DCOA3_N, O => DCOA3_P_S);
+DCOA3_N_S <= '0';
+DCOA4_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOA4_P, IB => DCOA4_N, O => DCOA4_P_S);
+DCOA4_N_S <= '0';
+
+DCOB1_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB1_P, IB => DCOB1_N, O => DCOB1_P_S);
+DCOB1_N_S <= '0';
+DCOB2_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB2_P, IB => DCOB2_N, O => DCOB2_P_S);
+DCOB2_N_S <= '0';
+DCOB3_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB3_P, IB => DCOB3_N, O => DCOB3_P_S);
+DCOB3_N_S <= '0';
+DCOB4_buf : IBUFGDS
+ generic map (DIFF_TERM => TermOrNot(C_OnChipLvdsTerm), IOSTANDARD => "LVDS_25")
+ port map (I => DCOB4_P, IB => DCOB4_N, O => DCOB4_P_S);
+DCOB4_N_S <= '0';
+
+FRA1_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA1_P, IB => FRA1_N, O => FRA1_P_S, OB => FRA1_N_S);
+FRA2_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA2_P, IB => FRA2_N, O => FRA2_P_S, OB => FRA2_N_S);
+FRA3_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA3_P, IB => FRA3_N, O => FRA3_P_S, OB => FRA3_N_S);
+FRA4_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRA4_P, IB => FRA4_N, O => FRA4_P_S, OB => FRA4_N_S);
+
+
+FRB1_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB1_P, IB => FRB1_N, O => FRB1_P_S, OB => FRB1_N_S);
+FRB2_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB2_P, IB => FRB2_N, O => FRB2_P_S, OB => FRB2_N_S);
+FRB3_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB3_P, IB => FRB3_N, O => FRB3_P_S, OB => FRB3_N_S);
+FRB4_buf : IBUFDS_DIFF_OUT
+ generic map (IOSTANDARD => "LVDS_25", DIFF_TERM => TermOrNot(C_OnChipLvdsTerm))
+ port map (I => FRB4_P, IB => FRB4_N, O => FRB4_P_S, OB => FRB4_N_S);
+
+
+ AdcToplevel1458_1: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X1Y14",
+ C_BufrLoc => "BUFR_X1Y7",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA1_P_S,
+ DCLK_n => DCOA1_N_S,
+ FCLK_p => FRA1_P_S,
+ FCLK_n => FRA1_N_S,
+ DATA_p => adcdata1458_P(0),
+ DATA_n => adcdata1458_n(0),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(0),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(0),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(0),
+ AdcBitClkDone => AdcBitClkDoneA_S(0),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(0),
+ AdcClkDiv => adcclockA_S(0),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(0),
+ ADCs_ready => ADCs_ready_S(0),\r
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_1: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X1Y13",
+ C_BufrLoc => "BUFR_X1Y6",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3"
+ )
+ port map(
+ DCLK_p => DCOB1_P_S,
+ DCLK_n => DCOB1_N_S,
+ FCLK_p => FRB1_P_S,
+ FCLK_n => FRB1_N_S,
+ DATA_p => adcdata2367_P(0),
+ DATA_n => adcdata2367_N(0),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(0),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(0),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(0),
+ AdcBitClkDone => AdcBitClkDoneB_S(0),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(0),
+ AdcClkDiv => adcclockB_S(0),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(0),
+ ADCs_ready => ADCs_ready_S(1),\r
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_2: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y13",
+ C_BufrLoc => "BUFR_X0Y6",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA2_P_S,
+ DCLK_n => DCOA2_N_S,
+ FCLK_p => FRA2_P_S,
+ FCLK_n => FRA2_N_S,
+ DATA_p => adcdata1458_P(1),
+ DATA_n => adcdata1458_n(1),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(1),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(1),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(1),
+ AdcBitClkDone => AdcBitClkDoneA_S(1),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(1),
+ AdcClkDiv => adcclockA_S(1),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(1),
+ ADCs_ready => ADCs_ready_S(2),\r
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_2: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y14",
+ C_BufrLoc => "BUFR_X0Y7",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
+ )
+ port map(
+ DCLK_p => DCOB2_P_S,
+ DCLK_n => DCOB2_N_S,
+ FCLK_p => FRB2_P_S,
+ FCLK_n => FRB2_N_S,
+ DATA_p => adcdata2367_P(1),
+ DATA_n => adcdata2367_N(1),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(1),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(1),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(1),
+ AdcBitClkDone => AdcBitClkDoneB_S(1),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(1),
+ AdcClkDiv => adcclockB_S(1),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(1),
+ ADCs_ready => ADCs_ready_S(3),\r
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_3: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y10",
+ C_BufrLoc => "BUFR_X0Y5",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA3_P_S,
+ DCLK_n => DCOA3_N_S,
+ FCLK_p => FRA3_P_S,
+ FCLK_n => FRA3_N_S,
+ DATA_p => adcdata1458_P(2),
+ DATA_n => adcdata1458_n(2),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(2),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(2),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(2),
+ AdcBitClkDone => AdcBitClkDoneA_S(2),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(2),
+ AdcClkDiv => adcclockA_S(2),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(2),
+ ADCs_ready => ADCs_ready_S(4),\r
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_3: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X0Y9",
+ C_BufrLoc => "BUFR_X0Y4",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2"
+ )
+ port map(
+ DCLK_p => DCOB3_P_S,
+ DCLK_n => DCOB3_N_S,
+ FCLK_p => FRB3_P_S,
+ FCLK_n => FRB3_N_S,
+ DATA_p => adcdata2367_P(2),
+ DATA_n => adcdata2367_N(2),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(2),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(2),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(2),
+ AdcBitClkDone => AdcBitClkDoneB_S(2),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(2),
+ AdcClkDiv => adcclockB_S(2),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(2),
+ ADCs_ready => ADCs_ready_S(5),\r
+ testOK => open,
+ testword0 => open);
+
+
+ AdcToplevel1458_4: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X2Y9",
+ C_BufrLoc => "BUFR_X2Y4",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 1, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" --IDELAYCTRL_X2Y3
+ )
+ port map(
+ DCLK_p => DCOA4_P_S,
+ DCLK_n => DCOA4_N_S,
+ FCLK_p => FRA4_P_S,
+ FCLK_n => FRA4_N_S,
+ DATA_p => adcdata1458_P(3),
+ DATA_n => adcdata1458_n(3),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnA_S(3),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(3),
+ AdcBitClkInvrtd => AdcBitClkInvrtdA_S(3),
+ AdcBitClkDone => AdcBitClkDoneA_S(3),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(3),
+ AdcClkDiv => adcclockA_S(3),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutA_S(3),
+ ADCs_ready => ADCs_ready_S(6),\r
+ testOK => open,
+ testword0 => open);
+
+ AdcToplevel2356_4: AdcToplevel
+ generic map(
+ C_AdcChnls => 4,
+ C_AdcWireInt =>2, -- 2 = 2-wire, 1 = 1-wire interface
+ C_BufioLoc => "BUFIODQS_X2Y10",
+ C_BufrLoc => "BUFR_X2Y5",
+ C_AdcBits => 16,
+-- C_StatTaps => 16,
+ C_AdcUseIdlyCtrl => 0, -- 0 = No, 1 = Yes
+ C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2"
+ )
+ port map(
+ DCLK_p => DCOB4_P_S,
+ DCLK_n => DCOB4_N_S,
+ FCLK_p => FRB4_P_S,
+ FCLK_n => FRB4_N_S,
+ DATA_p => adcdata2367_P(3),
+ DATA_n => adcdata2367_N(3),
+ -- application connections
+ SysRefClk => clock200MHz,
+ AdcIntrfcRst => reset,
+ AdcIntrfcEna => ADCs_enable,
+ AdcReSync => '0',
+ AdcFrmSyncWrn => AdcFrmSyncWrnB_S(3),
+ AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(3),
+ AdcBitClkInvrtd => AdcBitClkInvrtdB_S(3),
+ AdcBitClkDone => AdcBitClkDoneB_S(3),
+ AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(3),
+ AdcClkDiv => adcclockB_S(3),
+ adcdataclk => ADC_clk_S,
+ adcdataclknot => ADC_clknot_S,
+ AdcDataOut => AdcDataOutB_S(3),
+ ADCs_ready => ADCs_ready_S(7),\r
+ testOK => open,
+ testword0 => open);
+
+--ADCclkbuf : BUFG port map (
+-- O => ADC_clk_S,
+-- I => adcclockB_S(0));\r
+ \r
+FEE_clockbuf80MHz1: FEE_clockbuf80MHz port map(\r
+ CLK_IN1 => adcclockA_S(0),\r
+ CLK_OUT1 => ADC_clk_S,\r
+ CLK_OUT2 => ADC_clknot_S);\r
+
+gen_adcpar1: for chipnr in 0 to 3 generate\r
+
+adcdata0_S((3-chipnr)*8+1) <= AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10);
+adcdata0_S((3-chipnr)*8+2) <= not (AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((3-chipnr)*8+5) <= AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10);
+adcdata0_S((3-chipnr)*8+6) <= not (AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+
+adcdata0_S((3-chipnr)*8+0) <= not (AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((3-chipnr)*8+3) <= AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10);
+adcdata0_S((3-chipnr)*8+4) <= not (AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((3-chipnr)*8+7) <= AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10);
+
+end generate;
+
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+ if (rising_edge(ADC_clk_S)) then
+ adcdata1_S <= adcdata0_S;
+ adcdata <= adcdata1_S;
+ end if;
+end process;
+
+end Behavioral;
--- /dev/null
+-----------------------------------------------------------
+-- LMK03033 CONTROL UNIT --
+-- --
+-- uWIRE configuration Loader --
+-----------------------------------------------------------
+-- Device: xc5vlx50t-3ff665 --
+-- ISE 11.4 --
+-- created 15 Nov 2011 by Walter Puccio --
+-- Uppsala University, IRFU --
+-- Modified 23 Jan 2011 by P. Marciniewski --
+-- Uppsala University, Dept of Physics and Astronomy --
+-----------------------------------------------------------
+\r
+\r
+-- LMK03806:\r
+-- refclock/R = VCO/(P*N)\r
+-- CLKout = VCO/Divide\r
+--\r
+-- refclock : reference input clock\r
+-- R = R-divider (register 28)\r
+-- VCO = Voltage Controlled Oscillator = 2370..2600 MHz\r
+-- P = Prescaler : 2..8\r
+-- N = N-divider\r
+-- CLKout = Clock outputs (CLKout0..11)\r
+-- Divide = outputclock divider\r
+--\r
+-- 80MHz -> 80 MHz :\r
+-- R=1, VCO=2560, P=2, N=16, divide=32\r
+--
+-- 40MHz -> 80 MHz :\r
+-- R=1, VCO=2560, P=2, N=32, divide=32\r
+-- 40MHz -> 80 MHz :\r
+-- R=1, VCO=2560, P=4, N=16, divide=32\r
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+--use work.util_pack.ALL;
+
+entity LMK03806 is
+ generic(
+ CLK_DIV : integer := 6; -- slow down transfer
+ ADCCLOCKFREQUENCY : natural := 62500000
+ );
+ PORT(
+ clock : in std_logic; --Master clock
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDn : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high
+ reset_GTX : out std_logic; --delayed reset for GTX
+ reset_ADCs : out std_logic; --delayed reset for ADCs
+ booting : out std_logic; --busy signal \r
+ testwordin : in std_logic_vector(15 downto 0)
+ );
+end LMK03806;
+
+
+----------------------------------------------------------------
+
+architecture Behavioral of LMK03806 is
+constant NROFREGS : integer := 23+1+6;
+type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
+type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
+-- parameters based on 'Clock design tool' from National Semiconductor
+CONSTANT TAB80M : RomType :=
+-- 80MHz reference to 80MHz\r
+ (
+ x"00020000", -- R0 (Reset=1)
+ x"00020000", -- R0 (Reset=1)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+ x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+ x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+ x"55555549", -- R9 (fixed pattern)
+ x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+ x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+ x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+ x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+ x"0300000E", -- R14 (GPout1=weak pulldown)
+ x"C1550410", -- R16 (fixed pattern)
+ x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+ x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+ x"0010001C", -- R28 (R_divider=1
+ x"0080041D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=32
+ x"0200041E", -- R30 (N_prescaler=2 N_divider=32)
+ x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+ ); \r
+\r
+\r
+CONSTANT TAB80M_orig : RomType :=
+-- 80MHz reference to 80MHz
+ (
+ x"00020000", -- R0 (Reset=1)
+ x"00020000", -- R0 (Reset=1)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000401", --R1 (Div=40 OUT2,3 80MHz)
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000404", --R4 (Div=40 OUT8,9 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ X"00000405", --R5 (Div=40 OUT10,11 80MHz)
+ x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+ x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+ x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+ x"55555549", -- R9 (fixed pattern)
+ x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+ x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+ x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+ x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+ x"0300000E", -- R14 (GPout1=weak pulldown)
+ x"C1550410", -- R16 (fixed pattern)
+ x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+ x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+ x"0010001C", -- R28 (R_divider=1 ????????? :2
+ x"0180021D", -- R29 (OSCin=63MHz..127MHz N_CALdivider=16
+ x"0200021E", -- R30 (N_prescaler=2 N_divider=16)
+ x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+ );
+\r
+--CONSTANT TAB62M5 : RomType :=
+---- 62.5MHz reference to 62.5MHz\r
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
+-- X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
+-- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
+-- X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
+-- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
+-- X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
+-- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
+-- X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
+-- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
+-- X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
+-- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
+-- X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"1000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"7B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"DD000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+-- x"83A8001A", -- R26 (reffrequ=normal chargepump=100uA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1 ????????? :2
+-- x"0080029D", -- R29 (OSCin=0..63MHz N_CALdivider=20
+-- x"0200029E", -- R30 (N_prescaler=2 N_divider=20)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+-- (
+-- X"000204c0", --R0 (Reset=1, Div=38 OUT0,1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
+-- X"00000163", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"11110006", --R6 (OUT3,2,1,0 : LVDS)
+-- X"11110007", --R7 (OUT7,6,5,4 : LVDS)
+-- X"11110008", --R8 (OUT11,10,9,8 : LVDS)
+-- X"55555549", --R9 (fixed)
+-- X"1002400a", --R10 (OSCout0=700mV OSCout1=off OSCout=disabled OSC0,1=bypass_divider OSCoutDIV=2)
+-- X"3400000b", --R11 (SYNC=enabled, active=high, externalXTAL=disabled)
+-- X"138c006c", --R12 (LD_MUX=PLL_DLD, LD_TYPE=output, Force sync)
+-- X"7b03800d", --R13 (READ_BACK=pushpull, GPout0=weak pulldown)
+-- X"0300000e", --R14 (GPout1=weak pulldown)
+-- X"c1550410", --R16 (fixed)
+-- X"00000018", --R24 (LoopFilter: C4=10pF, C3=10pF, R4=200Ohm, R3=200Ohm)
+-- X"8fa8001a", --R26 (reffrequ=normal, chargepump=3.2mA, PLL_DLD_CNT=8192 ???????????)
+-- X"0010001c", --R28 (R_divider=1,
+-- X"0080027d", --R29 (OSCin=0..63MHz, N_CALdivider=19 ?????????????)
+-- X"0100027e", --R30 (N_prescaler=2, N_divider=19)
+-- X"0000001f" --R31 (ReadbackReg=0, Regs:unlocked)
+-- );
+
+-- (
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"343f100B", -- R11 (SYNC=enabled active=low, pulldownR externalXTAL=disabled) -- peter, was 3401100B
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync) -- peter, was 130C006C
+-- x"3B03800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) -- peter, was 3B03826D
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=2 -- peter, was 0010001C
+-- x"0180021D", -- R29 (OSCin=127..255Hz N_CALdivider=16 ?????????????) -- peter, was 0280011D
+-- x"0200021E", -- R30 (N_prescaler=2 N_divider=16) -- peter, was 0200011E
+-- x"001F001F" -- R31 (ReadbackReg=31 Regs:unlocked)
+-- );
+
+-- ( -- Pawel
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000400", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000401", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000202", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000203", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000404", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000405", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9102400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=high externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1
+-- x"0080021D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
+-- x"0200021E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
+-- );
+
+-- ( -- Pawel
+-- x"80020140", -- R0 (Reset=1 Div=10 OUT0..1 -> PWD)
+-- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"00000500", -- R0 (Div=32 OUT0..1 -> 77.76 MHz ADC)
+-- x"00000501", -- R1 (Div=32 OUT2..3 -> 77.76 MHz ADC)
+-- x"00000282", -- R2 (Div=16 OUT4..5 -> 155.52 MHz GTX0)
+-- x"00000283", -- R3 (Div=16 OUT6..7 -> 155.52 MHz GTX1)
+-- x"00000504", -- R4 (Div=32 OUT8..9 -> 77.76 MHz ADC)
+-- x"00000505", -- R5 (Div=32 OUT10 11 -> 77.76 MHz ADC)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"130C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0020001C", -- R28 (R_divider=2
+-- x"0180051D", -- R29 (OSCin=0..63MHz N_CALdivider=40 ?????????????)
+-- x"0200051E", -- R30 (N_prescaler=2 N_divider=40)
+-- x"001F001F" -- R31 (ReadbackReg=0 Regs:unlocked)
+-- );
+
+
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
+-- X"000004c2", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS)
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+-- x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+------ x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+-- x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
+------ x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+-- x"0300000E", -- R14 (GPout1=weak pulldown)
+------ x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"00000018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm)
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0010001C", -- R28 (R_divider=1 ????????? :2
+-- x"0080027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????)
+-- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+
+-- (
+-- x"00020000", -- R0 (Reset=1)
+-- x"00020000", -- R0 (Reset=1)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
+-- X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
+-- x"11110006", -- R6 (OUT 3,2,1,0 : LVDS)
+-- x"11110007", -- R7 (OUT 7,6,5,4 : LVDS) 11110007
+-- x"11110008", -- R8 (OUT 11,10,9,8 : LVDS)
+-- x"55555549", -- R9 (fixed pattern)
+------ x"9002400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"9000400A", -- R10 (OSCout1=LVPECL-1600mV OSCout0=LVDS OSCout1..0=disabled OSC0..1=bypass_divider OSCoutDIV=2)
+-- x"3401100B", -- R11 (SYNC=enabled active=low externalXTAL=disabled)
+-- x"138C006C", -- R12 (LD_MUX=PLL_DLD LD_TYPE=output Force sync)
+------ x"3B03826D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown) 130C006C
+-- x"7B02800D", -- R13 (READ_BACK=pushpull GPout0=weak pulldown)
+------ x"0300000E", -- R14 (GPout1=weak pulldown)
+-- x"0200000E", -- R14 (GPout1=weak pulldown)
+-- x"C1550410", -- R16 (fixed pattern)
+-- x"77110018", -- R24 (LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm) 00000018
+-- x"8FA8001A", -- R26 (reffrequ=normal chargepump=3.2mA PLL_DLD_CNT=8192 ???????????)
+-- x"0020001C", -- R28 (R_divider=1 ????????? :2
+-- x"0180027D", -- R29 (OSCin=0..63MHz N_CALdivider=19 ?????????????) 0080027D
+-- x"0200027E", -- R30 (N_prescaler=2 N_divider=19)
+-- x"0002001F" -- R31 (ReadbackReg=0 Regs:unlocked) 001F001F
+-- );
+
+
+\r
+\r
+
+
+
+signal tab : RomType;
+signal SHIFT_REG : std_logic_vector(31 downto 0);
+signal PLLbootstate : std_logic_vector(3 downto 0);
+signal bit_cnt : std_logic_vector(6 downto 0);
+signal cnt_dly : std_logic_vector(3 downto 0);
+signal ptr : std_logic_vector(4 downto 0);
+
+signal boot_dly_cnt : std_logic_vector(31 downto 0) := (others => '0');
+signal pll_res : std_logic;
+
+signal pll_boot : std_logic;
+signal pll_clk : std_logic;
+signal pll_data : std_logic;
+signal pll_le : std_logic;
+signal pll_sync : std_logic;
+signal pll_reset_GTX : std_logic;
+signal pll_reset_ADCs : std_logic;
+
+signal reset_counter_V1 : std_logic_vector(15 downto 0);
+signal reset_counter_V2 : std_logic_vector(7 downto 0);
+
+--------------------------------------------------------------------
+BEGIN
+
+tab <= TAB80M;-- when ADCCLOCKFREQUENCY=80000000 else TAB62M5;\r
+
+--******************************************************************
+-- RESET SEQUENCER
+--******************************************************************
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if PLLbootstate /= x"0" then
+ reset_counter_V1 <= (others => '0');
+ pll_reset_ADCs <= '1';
+ pll_reset_GTX <= '1';
+ booting <= '1';
+ else
+ booting <= '0';
+ if reset_counter_V1 < x"ffff" then
+ reset_counter_V1 <= reset_counter_V1 + 1;
+ else
+ pll_reset_ADCs <= '0';
+ pll_reset_GTX <= '0';
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(clock)
+begin
+ if rising_edge(clock) then
+ if reset_counter_V2 < x"ff" then
+ reset_counter_V2 <= reset_counter_V2 + 1;
+ pll_res <= '1';
+ else
+ pll_res <= '0';
+ end if;
+ end if;
+end process;
+
+
+--******************************************************************
+-- PLL BOOT STATEMACHINE
+--******************************************************************
+
+process(clock, pll_res)
+begin
+ if pll_res = '1' then
+ PLLbootstate <= (others => '0');
+ pll_sync <= '1';
+ --GOE <= '0';
+ pll_clk <= '0';
+ pll_le <= '0';
+ ptr <= (others => '0');
+
+ elsif rising_edge(clock) then
+
+ pll_boot <= BOOT_PLL;
+
+ case PLLbootstate is
+ when x"0" => --IDLE here until BOOT_DLY goes High
+ pll_sync <= '1';
+ --GOE <= '0';
+ pll_clk <= '0';
+ pll_le <= '0';
+ ptr <= (others => '0');
+ if pll_boot = '1' then PLLbootstate <= x"1";
+ end if;
+
+--*******Start
+ when x"1" => --Set up for TX
+ pll_le <= '0';
+ pll_clk <= '0';\r
+if ptr=24 then\r
+SHIFT_REG(15 downto 0) <= x"0018";\r
+SHIFT_REG(31 downto 16) <= testwordin;\r
+else
+ SHIFT_REG <= tab(conv_integer(ptr));\r
+end if;
+ bit_cnt <= (others => '0');
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"2";
+
+ when x"2" => --CLK low
+ pll_clk <= '0';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"3";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"3" => --CLK high
+ pll_clk <= '1';
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ bit_cnt <= bit_cnt + 1;
+ PLLbootstate <= x"4";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"4" => --Loop through all bits and regs
+ pll_clk <= '0';
+ cnt_dly <= (others => '0');
+ SHIFT_REG <= SHIFT_REG(30 downto 0) & '0';
+ if bit_cnt > 31 then --32 bits
+ pll_le <= '1';
+ if conv_integer(ptr) < NROFREGS-1 then --nr of regs
+ ptr <= ptr + 1;
+ PLLbootstate <= x"5";
+ else
+----peter pll_sync <= '0';
+ PLLbootstate <= x"6";
+ end if;
+ else PLLbootstate <= x"2";
+ end if;
+
+ when x"5" => --Latch Delay
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"1";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"6" => --pll_sync Delay
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"7";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+
+ when x"7" => --SYNC
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"8";
+ pll_sync <= '0';
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+ pll_le <= '0';
+
+ when x"8" => --SYNC
+ if cnt_dly > CLK_DIV then
+ cnt_dly <= (others => '0');
+ PLLbootstate <= x"9";
+ else cnt_dly <= cnt_dly + 1;
+ end if;
+ pll_le <= '0';
+
+ when x"9" => --IDLE here until BOOT_PLL goes low
+ pll_sync <= '1';
+ pll_le <= '0';
+ if pll_boot = '0' then PLLbootstate <= x"0";
+ end if;
+
+ when others => -- make sure other states wont lock up.
+ PLLbootstate <= (others => '0');
+ end case;
+ end if;
+end process;
+
+--Shift out bits, MSB first
+pll_data <= SHIFT_REG(31);
+
+
+CLKu <= pll_clk;
+DATAu <= pll_data;
+LEu <= pll_le;
+SYNC <= pll_sync;
+reset_GTX <= pll_reset_GTX;
+reset_ADCs <= pll_reset_ADCs;
+
+
+END Behavioral;
+
+
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date: 10-10-2012
+-- Module Name: SystemMonitorModule
+-- Description: Reads FPGA system parameters
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- SystemMonitorModule\r
+-- Reads FPGA system parameters: temperature and voltages
+-- The Xilinx System Monitor measures several FPGA physical operating parameters.\r
+-- For further information see Xilinx documentation
+-- The settings and parameters are accessable with a 16-bits data bus and 7 bits address bus.
+-- This module initializes the System Monitor so that the main parameters are continuously measured.
+-- This behaviour can bechanged because all settings are accessable.\r
+--\r
+--\r
+-- The main settings addresses and their initialize value are:\r
+-- 0x40 : 1000 -- average 16
+-- 0x41 : 2000 -- enable sequence & alarms, no calibration
+-- 0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
+-- 0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
+-- 0x49 : 0000 -- not Vaux
+-- 0x4a : 3700 -- enable averaging
+-- 0x4b : 0000 -- disable averaging Vau\r
+-- 0x4c : 0000 -- unipolar inputs\r
+-- 0x4d : 0000 -- unipolar inputs\r
+-- 0x4e : 0000 -- default Acquisition Time\r
+-- 0x4f : 0000 -- default Acquisition Time\r
+--\r
+--\r
+-- The system parameters are measured with an 10 bits ADC:\r
+--\r
+-- For die Temperature (address 0) :\r
+-- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15\r
+--\r
+-- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) : \r
+-- Supply Voltage (Volts) = (ADCcode / 1024) x 3V\r
+--\r
+-- For VrefN(0.0V, address=5) :\r
+-- Voltage (Volts) = ADCcode(2-complement) * 977uV\r
+--\r
+--
+--
+-- Library:
+--
+-- Generics:
+--\r
+-- Inputs:
+-- clock : clock for the system monitor (must not exceed 100MHz)
+-- reset : reset
+-- address : six bit address
+-- data_write : write signal for data to be set
+-- data_in : 16 bits data to be written
+-- data_read : read signal for reading data, data becomes available 3 clock cycles after this read signal!!
+--
+-- Outputs:
+-- data_out : data from the System Monitor, data becomes available 3 clock cycles after this read signal!!
+-- alarms :
+-- bit0 = user settable temperature
+-- bit1 = alarm on VCCint voltage
+-- bit2 = alarm on VCCaux voltage
+-- bit3 = alarm on over temperature
+-- bit7..4 = "0000" not yet used
+--
+-- Components:
+-- SystemMonitorVirtex : IP core generator module for Virtex
+--
+----------------------------------------------------------------------------------
+
+entity SystemMonitorModule is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(6 downto 0);\r
+ data_write : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);\r
+ data_read : in std_logic;\r
+ data_out : out std_logic_vector(15 downto 0);\r
+ alarms : out std_logic_vector(7 downto 0);
+ testword0 : out std_logic_vector(35 downto 0));
+end SystemMonitorModule;
+
+
+architecture Behavioral of SystemMonitorModule is
+
+component SystemMonitorVirtex\r
+ port (\r
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
+ VN_IN : in STD_LOGIC\r
+);\r
+end component;
+constant NROFREGISTERS : natural :=11;\r
+type registerarray_type is array (0 to NROFREGISTERS-1)
+ of std_logic_vector (23 downto 0);
+\r
+constant REGISTERARRAY : registerarray_type := (\r
+x"401000", -- average 16\r
+x"412000", -- enable sequence & alarms, no calibration
+x"421400", -- clock division = 20 : 50MHz/2.5MHz
+x"483700", -- select temp,VCCint,VCCaux,VrefP,VrefN
+x"490000", -- not Vaux
+x"4a3700", -- enable averaging
+x"4b0000", -- disable averaging Vau\r
+x"4c0000", -- unipolar inputs\r
+x"4d0000", -- unipolar inputs\r
+x"4e0000", -- default Acquisition Time\r
+x"4f0000"); -- default Acquisition Time\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ \r
+--0x40 : 1000 -- average 16
+--0x41 : 2000 -- enable sequence & alarms, no calibration
+--0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
+--0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
+--0x49 : 0000 -- not Vaux
+--0x4a : 3700 -- enable averaging
+--0x4b : 0000 -- disable averaging Vau\r
+--0x4c : 0000 -- unipolar inputs\r
+--0x4d : 0000 -- unipolar inputs\r
+--0x4e : 0000 -- default Acquisition Time\r
+--0x4f : 0000 -- default Acquisition Time\r
+\r
+\r
+signal registerindex_S : integer range 0 to NROFREGISTERS;
+signal accesscounter_S : integer range 0 to 7;
+signal delaycounter_S : std_logic_vector(11 downto 0);
+signal sysmon_active_S : std_logic := '0';
+
+signal DR_address_S : std_logic_vector(6 downto 0);
+signal DR_address_init_S : std_logic_vector(6 downto 0);
+signal DR_enable_S : std_logic := '0';
+signal DR_data_in_S : std_logic_vector(15 downto 0);\r
+signal DR_data_init_S : std_logic_vector(15 downto 0);\r
+
+signal DR_write_S : std_logic := '0';
+signal DR_write_init_S : std_logic := '0';
+signal ADC_busy_S : std_logic := '0';
+
+signal channel_S : std_logic_vector(4 downto 0);
+signal DR_data_out_S : std_logic_vector(15 downto 0);
+signal DR_ready_S : std_logic := '0';
+signal EndofConversion_S : std_logic := '0';
+signal EndofSequence_S : std_logic := '0';
+
+signal OverTemperatur_alarm_S : std_logic := '0';
+signal VCCaux_alarm_S : std_logic := '0';
+signal VCCint_alarm_S : std_logic := '0';
+signal USERtemp_alarm_S : std_logic := '0';
+\r
+\r
+
+begin\r
+\r
+\r
+SystemMonitorVirtex1: SystemMonitorVirtex port map ( \r
+ DADDR_IN => DR_address_S,\r
+ DCLK_IN => clock,\r
+ DEN_IN => DR_enable_S,\r
+ DI_IN => DR_data_in_S,\r
+ DWE_IN => DR_write_S,\r
+ RESET_IN => reset,\r
+ BUSY_OUT => ADC_busy_S,\r
+ CHANNEL_OUT => channel_S,\r
+ DO_OUT => DR_data_out_S,\r
+ DRDY_OUT => DR_ready_S,\r
+ EOC_OUT => EndofConversion_S,\r
+ EOS_OUT => EndofSequence_S,\r
+ JTAGBUSY_OUT => open,\r
+ JTAGLOCKED_OUT => open,\r
+ JTAGMODIFIED_OUT => open,\r
+ OT_OUT => OverTemperatur_alarm_S,\r
+ VCCAUX_ALARM_OUT => VCCaux_alarm_S,\r
+ VCCINT_ALARM_OUT => VCCint_alarm_S,\r
+ USER_TEMP_ALARM_OUT => USERtemp_alarm_S,\r
+ VP_IN => '0',\r
+ VN_IN => '0'\r
+ );\r
+\r
+alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;\r
+alarms(7 downto 4) <= (others => '0');\r
+\r
+DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;\r
+DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';\r
+data_out <= DR_data_out_S;\r
+\r
+DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';\r
+DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;\r
+\r
+process(clock)
+begin
+ if (rising_edge(clock)) then
+ if (reset = '1') and (sysmon_active_S='1') then \r
+ DR_write_init_S <= '0';\r
+ sysmon_active_S <= '0';\r
+ registerindex_S <= 0;\r
+ accesscounter_S <= 0;\r
+ delaycounter_S <= (others => '0');
+ else\r
+ if sysmon_active_S='0' then\r
+ if delaycounter_S(delaycounter_S'left)='0' then \r
+ delaycounter_S <= delaycounter_S+1;\r
+ DR_write_init_S <= '0';\r
+ registerindex_S <= 0;\r
+ accesscounter_S <= 0;\r
+ DR_address_init_S <= (others => '0');\r
+ else\r
+ if accesscounter_S<7 then\r
+ if accesscounter_S=0 then\r
+ DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);\r
+ DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);\r
+ DR_write_init_S <= '1';\r
+ else\r
+ DR_write_init_S <= '0';\r
+ end if;\r
+ accesscounter_S <= accesscounter_S+1;\r
+ else\r
+ accesscounter_S <= 0;\r
+ DR_write_init_S <= '0';\r
+ if registerindex_S<NROFREGISTERS then\r
+ registerindex_S <= registerindex_S+1;\r
+ else\r
+ DR_address_init_S <= (others => '0');\r
+ DR_data_init_S <= (others => '0');\r
+ registerindex_S <= 0;\r
+ sysmon_active_S <= '1';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ else\r
+ accesscounter_S <= 0;\r
+ DR_write_init_S <= '0';\r
+ end if;\r
+ end if;
+ end if;
+end process;
+
+testword0(15 downto 0) <= DR_data_out_S;
+testword0(22 downto 16) <= DR_address_S;
+testword0(23) <= sysmon_active_S;
+testword0(24) <= '0';
+testword0(25) <= DR_enable_S;
+testword0(26) <= ADC_busy_S;
+testword0(27) <= DR_ready_S;
+testword0(28) <= EndofConversion_S;
+testword0(29) <= EndofSequence_S;
+testword0(30) <= '1' when OverTemperatur_alarm_S='1' or VCCaux_alarm_S='1' or VCCint_alarm_S='1' or USERtemp_alarm_S='1' else '0';
+testword0(35 downto 31) <= channel_S;
+
+end Behavioral;
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_ADC32board.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema"/>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+NET "AD11A_N" DIFF_TERM = "TRUE";\r
+NET "AD11A_N" IOSTANDARD = LVDS_25;\r
+NET "AD11A_N" LOC = C17;\r
+NET "AD11A_P" DIFF_TERM = "TRUE";\r
+NET "AD11A_P" IOSTANDARD = LVDS_25;\r
+NET "AD11A_P" LOC = C16;\r
+NET "AD11B_N" DIFF_TERM = "TRUE";\r
+NET "AD11B_N" IOSTANDARD = LVDS_25;\r
+NET "AD11B_N" LOC = A18;\r
+NET "AD11B_P" DIFF_TERM = "TRUE";\r
+NET "AD11B_P" IOSTANDARD = LVDS_25;\r
+NET "AD11B_P" LOC = A17;\r
+NET "AD12A_N" DIFF_TERM = "TRUE";\r
+NET "AD12A_N" IOSTANDARD = LVDS_25;\r
+NET "AD12A_N" LOC = D18;\r
+NET "AD12A_P" DIFF_TERM = "TRUE";\r
+NET "AD12A_P" IOSTANDARD = LVDS_25;\r
+NET "AD12A_P" LOC = D17;\r
+NET "AD12B_N" DIFF_TERM = "TRUE";\r
+NET "AD12B_N" IOSTANDARD = LVDS_25;\r
+NET "AD12B_N" LOC = C18;\r
+NET "AD12B_P" DIFF_TERM = "TRUE";\r
+NET "AD12B_P" IOSTANDARD = LVDS_25;\r
+NET "AD12B_P" LOC = B18;\r
+NET "AD13A_N" DIFF_TERM = "TRUE";\r
+NET "AD13A_N" IOSTANDARD = LVDS_25;\r
+NET "AD13A_N" LOC = F17;\r
+NET "AD13A_P" DIFF_TERM = "TRUE";\r
+NET "AD13A_P" IOSTANDARD = LVDS_25;\r
+NET "AD13A_P" LOC = E17;\r
+NET "AD13B_N" DIFF_TERM = "TRUE";\r
+NET "AD13B_N" IOSTANDARD = LVDS_25;\r
+NET "AD13B_N" LOC = H15;\r
+NET "AD13B_P" DIFF_TERM = "TRUE";\r
+NET "AD13B_P" IOSTANDARD = LVDS_25;\r
+NET "AD13B_P" LOC = G15;\r
+NET "AD14A_N" DIFF_TERM = "TRUE";\r
+NET "AD14A_N" IOSTANDARD = LVDS_25;\r
+NET "AD14A_N" LOC = H16;\r
+NET "AD14A_P" DIFF_TERM = "TRUE";\r
+NET "AD14A_P" IOSTANDARD = LVDS_25;\r
+NET "AD14A_P" LOC = G16;\r
+NET "AD14B_N" DIFF_TERM = "TRUE";\r
+NET "AD14B_N" IOSTANDARD = LVDS_25;\r
+NET "AD14B_N" LOC = B16;\r
+NET "AD14B_P" DIFF_TERM = "TRUE";\r
+NET "AD14B_P" IOSTANDARD = LVDS_25;\r
+NET "AD14B_P" LOC = A16;\r
+NET "AD15A_N" DIFF_TERM = "TRUE";\r
+NET "AD15A_N" IOSTANDARD = LVDS_25;\r
+NET "AD15A_N" LOC = F14;\r
+NET "AD15A_P" DIFF_TERM = "TRUE";\r
+NET "AD15A_P" IOSTANDARD = LVDS_25;\r
+NET "AD15A_P" LOC = G14;\r
+NET "AD15B_N" DIFF_TERM = "TRUE";\r
+NET "AD15B_N" IOSTANDARD = LVDS_25;\r
+NET "AD15B_N" LOC = B14;\r
+NET "AD15B_P" DIFF_TERM = "TRUE";\r
+NET "AD15B_P" IOSTANDARD = LVDS_25;\r
+NET "AD15B_P" LOC = A14;\r
+NET "AD16A_N" DIFF_TERM = "TRUE";\r
+NET "AD16A_N" IOSTANDARD = LVDS_25;\r
+NET "AD16A_N" LOC = E14;\r
+NET "AD16A_P" DIFF_TERM = "TRUE";\r
+NET "AD16A_P" IOSTANDARD = LVDS_25;\r
+NET "AD16A_P" LOC = D14;\r
+NET "AD16B_N" DIFF_TERM = "TRUE";\r
+NET "AD16B_N" IOSTANDARD = LVDS_25;\r
+NET "AD16B_N" LOC = G13;\r
+NET "AD16B_P" DIFF_TERM = "TRUE";\r
+NET "AD16B_P" IOSTANDARD = LVDS_25;\r
+NET "AD16B_P" LOC = F13;\r
+NET "AD17A_N" DIFF_TERM = "TRUE";\r
+NET "AD17A_N" IOSTANDARD = LVDS_25;\r
+NET "AD17A_N" LOC = D13;\r
+NET "AD17A_P" DIFF_TERM = "TRUE";\r
+NET "AD17A_P" IOSTANDARD = LVDS_25;\r
+NET "AD17A_P" LOC = C13;\r
+NET "AD17B_N" DIFF_TERM = "TRUE";\r
+NET "AD17B_N" IOSTANDARD = LVDS_25;\r
+NET "AD17B_N" LOC = E12;\r
+NET "AD17B_P" DIFF_TERM = "TRUE";\r
+NET "AD17B_P" IOSTANDARD = LVDS_25;\r
+NET "AD17B_P" LOC = F12;\r
+NET "AD18A_N" DIFF_TERM = "TRUE";\r
+NET "AD18A_N" IOSTANDARD = LVDS_25;\r
+NET "AD18A_N" LOC = B13;\r
+NET "AD18A_P" DIFF_TERM = "TRUE";\r
+NET "AD18A_P" IOSTANDARD = LVDS_25;\r
+NET "AD18A_P" LOC = A13;\r
+NET "AD18B_N" DIFF_TERM = "TRUE";\r
+NET "AD18B_N" IOSTANDARD = LVDS_25;\r
+NET "AD18B_N" LOC = H13;\r
+NET "AD18B_P" DIFF_TERM = "TRUE";\r
+NET "AD18B_P" IOSTANDARD = LVDS_25;\r
+NET "AD18B_P" LOC = H12;\r
+\r
+NET "AD21A_N" DIFF_TERM = "TRUE";\r
+NET "AD21A_N" IOSTANDARD = LVDS_25;\r
+NET "AD21A_N" LOC = H22;\r
+NET "AD21A_P" DIFF_TERM = "TRUE";\r
+NET "AD21A_P" IOSTANDARD = LVDS_25;\r
+NET "AD21A_P" LOC = J22;\r
+NET "AD21B_N" DIFF_TERM = "TRUE";\r
+NET "AD21B_N" IOSTANDARD = LVDS_25;\r
+NET "AD21B_N" LOC = K22;\r
+NET "AD21B_P" DIFF_TERM = "TRUE";\r
+NET "AD21B_P" IOSTANDARD = LVDS_25;\r
+NET "AD21B_P" LOC = K21;\r
+NET "AD22A_N" DIFF_TERM = "TRUE";\r
+NET "AD22A_N" IOSTANDARD = LVDS_25;\r
+NET "AD22A_N" LOC = L17;\r
+NET "AD22A_P" DIFF_TERM = "TRUE";\r
+NET "AD22A_P" IOSTANDARD = LVDS_25;\r
+NET "AD22A_P" LOC = K17;\r
+NET "AD22B_N" DIFF_TERM = "TRUE";\r
+NET "AD22B_N" IOSTANDARD = LVDS_25;\r
+NET "AD22B_N" LOC = L19;\r
+NET "AD22B_P" DIFF_TERM = "TRUE";\r
+NET "AD22B_P" IOSTANDARD = LVDS_25;\r
+NET "AD22B_P" LOC = L18;\r
+NET "AD23A_N" DIFF_TERM = "TRUE";\r
+NET "AD23A_N" IOSTANDARD = LVDS_25;\r
+NET "AD23A_N" LOC = K20;\r
+NET "AD23A_P" DIFF_TERM = "TRUE";\r
+NET "AD23A_P" IOSTANDARD = LVDS_25;\r
+NET "AD23A_P" LOC = J20;\r
+NET "AD23B_N" DIFF_TERM = "TRUE";\r
+NET "AD23B_N" IOSTANDARD = LVDS_25;\r
+NET "AD23B_N" LOC = J17;\r
+NET "AD23B_P" DIFF_TERM = "TRUE";\r
+NET "AD23B_P" IOSTANDARD = LVDS_25;\r
+NET "AD23B_P" LOC = J18;\r
+NET "AD24A_N" DIFF_TERM = "TRUE";\r
+NET "AD24A_N" IOSTANDARD = LVDS_25;\r
+NET "AD24A_N" LOC = J19;\r
+NET "AD24A_P" DIFF_TERM = "TRUE";\r
+NET "AD24A_P" IOSTANDARD = LVDS_25;\r
+NET "AD24A_P" LOC = K19;\r
+NET "AD24B_N" DIFF_TERM = "TRUE";\r
+NET "AD24B_N" IOSTANDARD = LVDS_25;\r
+NET "AD24B_N" LOC = H21;\r
+NET "AD24B_P" DIFF_TERM = "TRUE";\r
+NET "AD24B_P" IOSTANDARD = LVDS_25;\r
+NET "AD24B_P" LOC = G21;\r
+NET "AD25A_N" DIFF_TERM = "TRUE";\r
+NET "AD25A_N" IOSTANDARD = LVDS_25;\r
+NET "AD25A_N" LOC = H18;\r
+NET "AD25A_P" DIFF_TERM = "TRUE";\r
+NET "AD25A_P" IOSTANDARD = LVDS_25;\r
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+NET "AD25B_N" DIFF_TERM = "TRUE";\r
+NET "AD25B_N" IOSTANDARD = LVDS_25;\r
+NET "AD25B_N" LOC = F19;\r
+NET "AD25B_P" DIFF_TERM = "TRUE";\r
+NET "AD25B_P" IOSTANDARD = LVDS_25;\r
+NET "AD25B_P" LOC = G19;\r
+NET "AD26A_N" DIFF_TERM = "TRUE";\r
+NET "AD26A_N" IOSTANDARD = LVDS_25;\r
+NET "AD26A_N" LOC = E22;\r
+NET "AD26A_P" DIFF_TERM = "TRUE";\r
+NET "AD26A_P" IOSTANDARD = LVDS_25;\r
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+NET "AD26B_N" DIFF_TERM = "TRUE";\r
+NET "AD26B_N" IOSTANDARD = LVDS_25;\r
+NET "AD26B_N" LOC = D19;\r
+NET "AD26B_P" DIFF_TERM = "TRUE";\r
+NET "AD26B_P" IOSTANDARD = LVDS_25;\r
+NET "AD26B_P" LOC = E19;\r
+NET "AD27A_N" DIFF_TERM = "TRUE";\r
+NET "AD27A_N" IOSTANDARD = LVDS_25;\r
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+NET "AD27A_P" DIFF_TERM = "TRUE";\r
+NET "AD27A_P" IOSTANDARD = LVDS_25;\r
+NET "AD27A_P" LOC = B20;\r
+NET "AD27B_N" DIFF_TERM = "TRUE";\r
+NET "AD27B_N" IOSTANDARD = LVDS_25;\r
+NET "AD27B_N" LOC = B21;\r
+NET "AD27B_P" DIFF_TERM = "TRUE";\r
+NET "AD27B_P" IOSTANDARD = LVDS_25;\r
+NET "AD27B_P" LOC = A21;\r
+NET "AD28A_N" DIFF_TERM = "TRUE";\r
+NET "AD28A_N" IOSTANDARD = LVDS_25;\r
+NET "AD28A_N" LOC = F18;\r
+NET "AD28A_P" DIFF_TERM = "TRUE";\r
+NET "AD28A_P" IOSTANDARD = LVDS_25;\r
+NET "AD28A_P" LOC = G18;\r
+NET "AD28B_N" DIFF_TERM = "TRUE";\r
+NET "AD28B_N" IOSTANDARD = LVDS_25;\r
+NET "AD28B_N" LOC = C21;\r
+NET "AD28B_P" DIFF_TERM = "TRUE";\r
+NET "AD28B_P" IOSTANDARD = LVDS_25;\r
+NET "AD28B_P" LOC = B22;\r
+\r
+NET "AD31A_N" DIFF_TERM = "TRUE";\r
+NET "AD31A_N" IOSTANDARD = LVDS_25;\r
+NET "AD31A_N" LOC = T21;\r
+NET "AD31A_P" DIFF_TERM = "TRUE";\r
+NET "AD31A_P" IOSTANDARD = LVDS_25;\r
+NET "AD31A_P" LOC = U21;\r
+NET "AD31B_N" DIFF_TERM = "TRUE";\r
+NET "AD31B_N" IOSTANDARD = LVDS_25;\r
+NET "AD31B_N" LOC = Y21;\r
+NET "AD31B_P" DIFF_TERM = "TRUE";\r
+NET "AD31B_P" IOSTANDARD = LVDS_25;\r
+NET "AD31B_P" LOC = AA21;\r
+NET "AD32A_N" DIFF_TERM = "TRUE";\r
+NET "AD32A_N" IOSTANDARD = LVDS_25;\r
+NET "AD32A_N" LOC = AB21;\r
+NET "AD32A_P" DIFF_TERM = "TRUE";\r
+NET "AD32A_P" IOSTANDARD = LVDS_25;\r
+NET "AD32A_P" LOC = AB20;\r
+NET "AD32B_N" DIFF_TERM = "TRUE";\r
+NET "AD32B_N" IOSTANDARD = LVDS_25;\r
+NET "AD32B_N" LOC = U20;\r
+NET "AD32B_P" DIFF_TERM = "TRUE";\r
+NET "AD32B_P" IOSTANDARD = LVDS_25;\r
+NET "AD32B_P" LOC = U19;\r
+NET "AD33A_N" DIFF_TERM = "TRUE";\r
+NET "AD33A_N" IOSTANDARD = LVDS_25;\r
+NET "AD33A_N" LOC = W20;\r
+NET "AD33A_P" DIFF_TERM = "TRUE";\r
+NET "AD33A_P" IOSTANDARD = LVDS_25;\r
+NET "AD33A_P" LOC = Y20;\r
+NET "AD33B_N" DIFF_TERM = "TRUE";\r
+NET "AD33B_N" IOSTANDARD = LVDS_25;\r
+NET "AD33B_N" LOC = V21;\r
+NET "AD33B_P" DIFF_TERM = "TRUE";\r
+NET "AD33B_P" IOSTANDARD = LVDS_25;\r
+NET "AD33B_P" LOC = V20;\r
+NET "AD34A_N" DIFF_TERM = "TRUE";\r
+NET "AD34A_N" IOSTANDARD = LVDS_25;\r
+NET "AD34A_N" LOC = AA22;\r
+NET "AD34A_P" DIFF_TERM = "TRUE";\r
+NET "AD34A_P" IOSTANDARD = LVDS_25;\r
+NET "AD34A_P" LOC = Y22;\r
+NET "AD34B_N" DIFF_TERM = "TRUE";\r
+NET "AD34B_N" IOSTANDARD = LVDS_25;\r
+NET "AD34B_N" LOC = T19;\r
+NET "AD34B_P" DIFF_TERM = "TRUE";\r
+NET "AD34B_P" IOSTANDARD = LVDS_25;\r
+NET "AD34B_P" LOC = T18;\r
+NET "AD35A_N" DIFF_TERM = "TRUE";\r
+NET "AD35A_N" IOSTANDARD = LVDS_25;\r
+NET "AD35A_N" LOC = R20;\r
+NET "AD35A_P" DIFF_TERM = "TRUE";\r
+NET "AD35A_P" IOSTANDARD = LVDS_25;\r
+NET "AD35A_P" LOC = R19;\r
+NET "AD35B_N" DIFF_TERM = "TRUE";\r
+NET "AD35B_N" IOSTANDARD = LVDS_25;\r
+NET "AD35B_N" LOC = P17;\r
+NET "AD35B_P" DIFF_TERM = "TRUE";\r
+NET "AD35B_P" IOSTANDARD = LVDS_25;\r
+NET "AD35B_P" LOC = N17;\r
+NET "AD36A_N" DIFF_TERM = "TRUE";\r
+NET "AD36A_N" IOSTANDARD = LVDS_25;\r
+NET "AD36A_N" LOC = R22;\r
+NET "AD36A_P" DIFF_TERM = "TRUE";\r
+NET "AD36A_P" IOSTANDARD = LVDS_25;\r
+NET "AD36A_P" LOC = P22;\r
+NET "AD36B_N" DIFF_TERM = "TRUE";\r
+NET "AD36B_N" IOSTANDARD = LVDS_25;\r
+NET "AD36B_N" LOC = N21;\r
+NET "AD36B_P" DIFF_TERM = "TRUE";\r
+NET "AD36B_P" IOSTANDARD = LVDS_25;\r
+NET "AD36B_P" LOC = N22;\r
+NET "AD37A_N" DIFF_TERM = "TRUE";\r
+NET "AD37A_N" IOSTANDARD = LVDS_25;\r
+NET "AD37A_N" LOC = M19;\r
+NET "AD37A_P" DIFF_TERM = "TRUE";\r
+NET "AD37A_P" IOSTANDARD = LVDS_25;\r
+NET "AD37A_P" LOC = M20;\r
+NET "AD37B_N" DIFF_TERM = "TRUE";\r
+NET "AD37B_N" IOSTANDARD = LVDS_25;\r
+NET "AD37B_N" LOC = L21;\r
+NET "AD37B_P" DIFF_TERM = "TRUE";\r
+NET "AD37B_P" IOSTANDARD = LVDS_25;\r
+NET "AD37B_P" LOC = L22;\r
+NET "AD38A_N" DIFF_TERM = "TRUE";\r
+NET "AD38A_N" IOSTANDARD = LVDS_25;\r
+NET "AD38A_N" LOC = N18;\r
+NET "AD38A_P" DIFF_TERM = "TRUE";\r
+NET "AD38A_P" IOSTANDARD = LVDS_25;\r
+NET "AD38A_P" LOC = M18;\r
+NET "AD38B_N" DIFF_TERM = "TRUE";\r
+NET "AD38B_N" IOSTANDARD = LVDS_25;\r
+NET "AD38B_N" LOC = N20;\r
+NET "AD38B_P" DIFF_TERM = "TRUE";\r
+NET "AD38B_P" IOSTANDARD = LVDS_25;\r
+NET "AD38B_P" LOC = M21;\r
+\r
+NET "AD41A_N" DIFF_TERM = "TRUE";\r
+NET "AD41A_N" IOSTANDARD = LVDS_25;\r
+NET "AD41A_N" LOC = U8;\r
+NET "AD41A_P" DIFF_TERM = "TRUE";\r
+NET "AD41A_P" IOSTANDARD = LVDS_25;\r
+NET "AD41A_P" LOC = V8;\r
+NET "AD41B_N" DIFF_TERM = "TRUE";\r
+NET "AD41B_N" IOSTANDARD = LVDS_25;\r
+NET "AD41B_N" LOC = Y7;\r
+NET "AD41B_P" DIFF_TERM = "TRUE";\r
+NET "AD41B_P" IOSTANDARD = LVDS_25;\r
+NET "AD41B_P" LOC = Y6;\r
+NET "AD42A_N" DIFF_TERM = "TRUE";\r
+NET "AD42A_N" IOSTANDARD = LVDS_25;\r
+NET "AD42A_N" LOC = T7;\r
+NET "AD42A_P" DIFF_TERM = "TRUE";\r
+NET "AD42A_P" IOSTANDARD = LVDS_25;\r
+NET "AD42A_P" LOC = T6;\r
+NET "AD42B_N" DIFF_TERM = "TRUE";\r
+NET "AD42B_N" IOSTANDARD = LVDS_25;\r
+NET "AD42B_N" LOC = AA6;\r
+NET "AD42B_P" DIFF_TERM = "TRUE";\r
+NET "AD42B_P" IOSTANDARD = LVDS_25;\r
+NET "AD42B_P" LOC = AB6;\r
+NET "AD43A_N" DIFF_TERM = "TRUE";\r
+NET "AD43A_N" IOSTANDARD = LVDS_25;\r
+NET "AD43A_N" LOC = W7;\r
+NET "AD43A_P" DIFF_TERM = "TRUE";\r
+NET "AD43A_P" IOSTANDARD = LVDS_25;\r
+NET "AD43A_P" LOC = V7;\r
+NET "AD43B_N" DIFF_TERM = "TRUE";\r
+NET "AD43B_N" IOSTANDARD = LVDS_25;\r
+NET "AD43B_N" LOC = AB8;\r
+NET "AD43B_P" DIFF_TERM = "TRUE";\r
+NET "AD43B_P" IOSTANDARD = LVDS_25;\r
+NET "AD43B_P" LOC = AB9;\r
+NET "AD44A_N" DIFF_TERM = "TRUE";\r
+NET "AD44A_N" IOSTANDARD = LVDS_25;\r
+NET "AD44A_N" LOC = V6;\r
+NET "AD44A_P" DIFF_TERM = "TRUE";\r
+NET "AD44A_P" IOSTANDARD = LVDS_25;\r
+NET "AD44A_P" LOC = U6;\r
+NET "AD44B_N" DIFF_TERM = "TRUE";\r
+NET "AD44B_N" IOSTANDARD = LVDS_25;\r
+NET "AD44B_N" LOC = W8;\r
+NET "AD44B_P" DIFF_TERM = "TRUE";\r
+NET "AD44B_P" IOSTANDARD = LVDS_25;\r
+NET "AD44B_P" LOC = W9;\r
+NET "AD45A_N" DIFF_TERM = "TRUE";\r
+NET "AD45A_N" IOSTANDARD = LVDS_25;\r
+NET "AD45A_N" LOC = T8;\r
+NET "AD45A_P" DIFF_TERM = "TRUE";\r
+NET "AD45A_P" IOSTANDARD = LVDS_25;\r
+NET "AD45A_P" LOC = R9;\r
+NET "AD45B_N" DIFF_TERM = "TRUE";\r
+NET "AD45B_N" IOSTANDARD = LVDS_25;\r
+NET "AD45B_N" LOC = Y11;\r
+NET "AD45B_P" DIFF_TERM = "TRUE";\r
+NET "AD45B_P" IOSTANDARD = LVDS_25;\r
+NET "AD45B_P" LOC = AA11;\r
+NET "AD46A_N" DIFF_TERM = "TRUE";\r
+NET "AD46A_N" IOSTANDARD = LVDS_25;\r
+NET "AD46A_N" LOC = Y10;\r
+NET "AD46A_P" DIFF_TERM = "TRUE";\r
+NET "AD46A_P" IOSTANDARD = LVDS_25;\r
+NET "AD46A_P" LOC = W10;\r
+NET "AD46B_N" DIFF_TERM = "TRUE";\r
+NET "AD46B_N" IOSTANDARD = LVDS_25;\r
+NET "AD46B_N" LOC = V11;\r
+NET "AD46B_P" DIFF_TERM = "TRUE";\r
+NET "AD46B_P" IOSTANDARD = LVDS_25;\r
+NET "AD46B_P" LOC = U11;\r
+NET "AD47A_N" DIFF_TERM = "TRUE";\r
+NET "AD47A_N" IOSTANDARD = LVDS_25;\r
+NET "AD47A_N" LOC = T11;\r
+NET "AD47A_P" DIFF_TERM = "TRUE";\r
+NET "AD47A_P" IOSTANDARD = LVDS_25;\r
+NET "AD47A_P" LOC = T12;\r
+NET "AD47B_N" DIFF_TERM = "TRUE";\r
+NET "AD47B_N" IOSTANDARD = LVDS_25;\r
+NET "AD47B_N" LOC = W12;\r
+NET "AD47B_P" DIFF_TERM = "TRUE";\r
+NET "AD47B_P" IOSTANDARD = LVDS_25;\r
+NET "AD47B_P" LOC = V12;\r
+NET "AD48A_N" DIFF_TERM = "TRUE";\r
+NET "AD48A_N" IOSTANDARD = LVDS_25;\r
+NET "AD48A_N" LOC = U10;\r
+NET "AD48A_P" DIFF_TERM = "TRUE";\r
+NET "AD48A_P" IOSTANDARD = LVDS_25;\r
+NET "AD48A_P" LOC = T9;\r
+NET "AD48B_N" DIFF_TERM = "TRUE";\r
+NET "AD48B_N" IOSTANDARD = LVDS_25;\r
+NET "AD48B_N" LOC = AA12;\r
+NET "AD48B_P" DIFF_TERM = "TRUE";\r
+NET "AD48B_P" IOSTANDARD = LVDS_25;\r
+NET "AD48B_P" LOC = Y12;\r
+\r
+NET "DATAu" LOC = B10;
+NET "CLKu" LOC = A11;
+NET "RDu" LOC = C10;
+NET "LEu" LOC = A12;
+NET "SYNC" LOC = G11;
+
+NET "S_CTRL" LOC = W14;
+NET "T_CTRL" LOC = Y14;
+NET "GEO" LOC = AB13;\r
+\r
+#\r
+NET "SCK" LOC = W17;\r
+NET "SDI" LOC = W18;\r
+NET "CSA[1]" LOC = AA17;\r
+NET "CSA[2]" LOC = AB18;\r
+NET "CSA[3]" LOC = V18;\r
+NET "CSA[4]" LOC = T16;\r
+NET "CSB[1]" LOC = Y17;\r
+NET "CSB[2]" LOC = AA18;\r
+NET "CSB[3]" LOC = V17;\r
+NET "CSB[4]" LOC = R16;\r
+\r
+NET "SDOA[1]" LOC = Y16;\r
+NET "SDOA[2]" LOC = AA19;\r
+NET "SDOA[3]" LOC = V13;\r
+NET "SDOA[4]" LOC = T17;\r
+NET "SDOB[1]" LOC = AA16;\r
+NET "SDOB[2]" LOC = AB19;\r
+NET "SDOB[3]" LOC = W13;\r
+NET "SDOB[4]" LOC = U18;\r
+\r
+#\r
+#NET "D<0>" LOC = "V15";\r
+#NET "D<1>" LOC = "U15";\r
+#NET "D<2>" LOC = "R15";\r
+#NET "D<3>" LOC = "R14";\r
+#NET "D<4>" LOC = "Y19";\r
+#NET "D<5>" LOC = "W19";\r
+#NET "D<6>" LOC = "U16";\r
+#NET "D<7>" LOC = "V16";\r
+NET "DCOA1_N" DIFF_TERM = "TRUE";\r
+NET "DCOA1_N" IOSTANDARD = LVDS_25;\r
+NET "DCOA1_N" LOC = F16;\r
+NET "DCOA1_P" DIFF_TERM = "TRUE";\r
+NET "DCOA1_P" IOSTANDARD = LVDS_25;\r
+NET "DCOA1_P" LOC = E16;\r
+NET "DCOA2_N" DIFF_TERM = "TRUE";\r
+NET "DCOA2_N" IOSTANDARD = LVDS_25;\r
+NET "DCOA2_N" LOC = D22;\r
+NET "DCOA2_P" DIFF_TERM = "TRUE";\r
+NET "DCOA2_P" IOSTANDARD = LVDS_25;\r
+NET "DCOA2_P" LOC = C22;\r
+NET "DCOA3_N" DIFF_TERM = "TRUE";\r
+NET "DCOA3_N" IOSTANDARD = LVDS_25;\r
+NET "DCOA3_N" LOC = P20;\r
+NET "DCOA3_P" DIFF_TERM = "TRUE";\r
+NET "DCOA3_P" IOSTANDARD = LVDS_25;\r
+NET "DCOA3_P" LOC = P19;\r
+NET "DCOA4_N" DIFF_TERM = "TRUE";\r
+NET "DCOA4_N" IOSTANDARD = LVDS_25;\r
+NET "DCOA4_N" LOC = Y9;\r
+NET "DCOA4_P" DIFF_TERM = "TRUE";\r
+NET "DCOA4_P" IOSTANDARD = LVDS_25;\r
+NET "DCOA4_P" LOC = AA9;\r
+NET "DCOB1_N" DIFF_TERM = "TRUE";\r
+NET "DCOB1_N" IOSTANDARD = LVDS_25;\r
+NET "DCOB1_N" LOC = B19;\r
+NET "DCOB1_P" DIFF_TERM = "TRUE";\r
+NET "DCOB1_P" IOSTANDARD = LVDS_25;\r
+NET "DCOB1_P" LOC = A19;\r
+NET "DCOB2_N" DIFF_TERM = "TRUE";\r
+NET "DCOB2_N" IOSTANDARD = LVDS_25;\r
+NET "DCOB2_N" LOC = E20;\r
+NET "DCOB2_P" DIFF_TERM = "TRUE";\r
+NET "DCOB2_P" IOSTANDARD = LVDS_25;\r
+NET "DCOB2_P" LOC = D20;\r
+NET "DCOB3_N" DIFF_TERM = "TRUE";\r
+NET "DCOB3_N" IOSTANDARD = LVDS_25;\r
+NET "DCOB3_N" LOC = V22;\r
+NET "DCOB3_P" DIFF_TERM = "TRUE";\r
+NET "DCOB3_P" IOSTANDARD = LVDS_25;\r
+NET "DCOB3_P" LOC = W22;\r
+NET "DCOB4_N" DIFF_TERM = "TRUE";\r
+NET "DCOB4_N" IOSTANDARD = LVDS_25;\r
+NET "DCOB4_N" LOC = AA8;\r
+NET "DCOB4_P" DIFF_TERM = "TRUE";\r
+NET "DCOB4_P" IOSTANDARD = LVDS_25;\r
+NET "DCOB4_P" LOC = AA7;\r
+\r
+NET "FRA1_N" DIFF_TERM = "TRUE";\r
+NET "FRA1_N" IOSTANDARD = LVDS_25;\r
+NET "FRA1_N" LOC = C15;\r
+NET "FRA1_P" DIFF_TERM = "TRUE";\r
+NET "FRA1_P" IOSTANDARD = LVDS_25;\r
+NET "FRA1_P" LOC = B15;\r
+NET "FRA2_N" DIFF_TERM = "TRUE";\r
+NET "FRA2_N" IOSTANDARD = LVDS_25;\r
+NET "FRA2_N" LOC = G20;\r
+NET "FRA2_P" DIFF_TERM = "TRUE";\r
+NET "FRA2_P" IOSTANDARD = LVDS_25;\r
+NET "FRA2_P" LOC = H20;\r
+NET "FRA3_N" DIFF_TERM = "TRUE";\r
+NET "FRA3_N" IOSTANDARD = LVDS_25;\r
+NET "FRA3_N" LOC = R17;\r
+NET "FRA3_P" DIFF_TERM = "TRUE";\r
+NET "FRA3_P" IOSTANDARD = LVDS_25;\r
+NET "FRA3_P" LOC = P18;\r
+NET "FRA4_N" DIFF_TERM = "TRUE";\r
+NET "FRA4_N" IOSTANDARD = LVDS_25;\r
+NET "FRA4_N" LOC = U9;\r
+NET "FRA4_P" DIFF_TERM = "TRUE";\r
+NET "FRA4_P" IOSTANDARD = LVDS_25;\r
+NET "FRA4_P" LOC = V10;\r
+NET "FRB1_N" DIFF_TERM = "TRUE";\r
+NET "FRB1_N" IOSTANDARD = LVDS_25;\r
+NET "FRB1_N" LOC = E15;\r
+NET "FRB1_P" DIFF_TERM = "TRUE";\r
+NET "FRB1_P" IOSTANDARD = LVDS_25;\r
+NET "FRB1_P" LOC = D15;\r
+NET "FRB2_N" DIFF_TERM = "TRUE";\r
+NET "FRB2_N" IOSTANDARD = LVDS_25;\r
+NET "FRB2_N" LOC = F22;\r
+NET "FRB2_P" DIFF_TERM = "TRUE";\r
+NET "FRB2_P" IOSTANDARD = LVDS_25;\r
+NET "FRB2_P" LOC = F21;\r
+NET "FRB3_N" DIFF_TERM = "TRUE";\r
+NET "FRB3_N" IOSTANDARD = LVDS_25;\r
+NET "FRB3_N" LOC = T22;\r
+NET "FRB3_P" DIFF_TERM = "TRUE";\r
+NET "FRB3_P" IOSTANDARD = LVDS_25;\r
+NET "FRB3_P" LOC = R21;\r
+NET "FRB4_N" DIFF_TERM = "TRUE";\r
+NET "FRB4_N" IOSTANDARD = LVDS_25;\r
+NET "FRB4_N" LOC = AB10;\r
+NET "FRB4_P" DIFF_TERM = "TRUE";\r
+NET "FRB4_P" IOSTANDARD = LVDS_25;\r
+NET "FRB4_P" LOC = AB11;\r
+\r
+NET "GCLK_N" DIFF_TERM = "TRUE";\r
+NET "GCLK_N" IOSTANDARD = LVDS_25;\r
+NET "GCLK_N" LOC = U13;\r
+NET "GCLK_P" DIFF_TERM = "TRUE";\r
+NET "GCLK_P" IOSTANDARD = LVDS_25;\r
+NET "GCLK_P" LOC = T13;\r
+\r
+\r
+NET "INTCOM0_N" LOC = "A6";\r
+NET "INTCOM0_P" LOC = "A7";\r
+NET "INTCOM1_N" LOC = "B6";\r
+NET "INTCOM1_P" LOC = "C6";\r
+NET "INTCOM2_N" LOC = "H10";\r
+NET "INTCOM2_P" LOC = "G10";\r
+NET "INTCOM3_N" LOC = "D9";\r
+NET "INTCOM3_P" LOC = "E9";\r
+NET "INTCOM4_N" LOC = "G9";\r
+NET "INTCOM4_P" LOC = "F9";\r
+NET "INTCOM5_N" LOC = "E6";\r
+NET "INTCOM5_P" LOC = "E7";\r
+NET "INTCOM6_N" LOC = "F11";\r
+NET "INTCOM6_P" LOC = "E11";\r
+NET "INTCOM7_N" LOC = "F7";\r
+NET "INTCOM7_P" LOC = "F8";\r
+\r
+NET "INTCOMC1_N" LOC = "C7";\r
+#NET "INTCOMC1_N" DIFF_TERM = "TRUE";\r
+#NET "INTCOMC1_N" IOSTANDARD = BLVDS_25;\r
+NET "INTCOMC1_P" LOC = "C8";\r
+#NET "INTCOMC1_P" DIFF_TERM = "TRUE";\r
+#NET "INTCOMC1_P" IOSTANDARD = BLVDS_25;\r
+NET "INTCOMC2_N" LOC = "D7";\r
+#NET "INTCOMC2_N" DIFF_TERM = "TRUE";\r
+#NET "INTCOMC2_N" IOSTANDARD = BLVDS_25;\r
+NET "INTCOMC2_P" LOC = "D8";\r
+#NET "INTCOMC2_P" DIFF_TERM = "TRUE";\r
+#NET "INTCOMC2_P" IOSTANDARD = BLVDS_25;\r
+\r
+\r
+NET "TCK_F" LOC = "AA14";\r
+NET "TDI_F" LOC = "AB16";\r
+NET "TDO_F" LOC = "AB15";\r
+NET "TMS_F" LOC = "AB14";\r
+\r
+\r
+\r
+#\r
+#NET "SM0_N" LOC = "B11";\r
+#NET "SM0_P" LOC = "C11";\r
+NET "SM1_N" LOC = "B9";\r
+NET "SM1_P" LOC = "A9";\r
+#NET "SM2_N" LOC = "E10";\r
+#NET "SM2_P" LOC = "D10";\r
+NET "SM3_N" LOC = "B8";\r
+NET "SM3_P" LOC = "A8";\r
+#\r
+#\r
+#NET "TEMP_IN" LOC = "U14";\r
+#NET "TEMP_OUT" LOC = "T14";\r
+#\r
+#NET "RX_N" LOC = "T2";\r
+#NET "RX_P" LOC = "T1";\r
+#NET "TX_N" LOC = "V2";\r
+#NET "TX_P" LOC = "V1";\r
+NET "MOD_DEF[0]" LOC = G8;\r
+NET "MOD_DEF[1]" LOC = H8;\r
+NET "MOD_DEF[2]" LOC = D12;\r
+NET "TX_DIS" LOC = H11;\r
+NET "LOS" LOC = C12;\r
+\r
+NET "MGTREFCLK_N" LOC = L3;\r
+NET "MGTREFCLK_P" LOC = L4;\r
+NET "RCV_CLK_N" LOC = Y15;\r
+NET "RCV_CLK_P" LOC = W15;\r
+NET "ST_CLK_N" LOC = G6;\r
+NET "ST_CLK_P" LOC = F6;\r
+NET "RX_N" LOC = G4;\r
+NET "RX_P" LOC = G3;\r
+NET "TX_N" LOC = K2;\r
+NET "TX_P" LOC = K1;\r
+\r
+#NET "PROGRAM_B" LOC = F5;\r
+\r
+#\r
+#NET "XRX0_N" LOC = "E4";\r
+#NET "XRX0_P" LOC = "E3";\r
+#NET "XRX1_N" LOC = "C4";\r
+#NET "XRX1_P" LOC = "C3";\r
+#NET "XTX0_N" LOC = "H2";\r
+#NET "XTX0_P" LOC = "H1";\r
+#NET "XTX1_N" LOC = "F2";\r
+#NET "XTX1_P" LOC = "F1";\r
+#Created by Constraints Editor (xc6vlx130t-ff484-3) - 2012/07/23\r
+#NET "DCOA1_P" TNM_NET = DCOA1_P;\r
+#TIMESPEC TS_DCOA1_P = PERIOD "DCOA1_P" 3.125 ns HIGH 50%;\r
+#NET "DCOA2_P" TNM_NET = DCOA2_P;\r
+#TIMESPEC TS_DCOA2_P = PERIOD "DCOA2_P" 3.125 ns HIGH 50%;\r
+#NET "DCOA3_P" TNM_NET = DCOA3_P;\r
+#TIMESPEC TS_DCOA3_P = PERIOD "DCOA3_P" 3.125 ns HIGH 50%;\r
+#NET "DCOA4_P" TNM_NET = DCOA4_P;\r
+#TIMESPEC TS_DCOA4_P = PERIOD "DCOA4_P" 3.125 HIGH 50%;\r
+#NET "DCOB1_P" TNM_NET = DCOB1_P;\r
+#TIMESPEC TS_DCOB1_P = PERIOD "DCOB1_P" 3.125 ns HIGH 50%;\r
+#NET "DCOB2_P" TNM_NET = DCOB2_P;\r
+#TIMESPEC TS_DCOB2_P = PERIOD "DCOB2_P" 3.125 ns HIGH 50%;\r
+#NET "DCOB3_P" TNM_NET = DCOB3_P;\r
+#TIMESPEC TS_DCOB3_P = PERIOD "DCOB3_P" 3.125 ns HIGH 50%;\r
+#NET "DCOB4_P" TNM_NET = DCOB4_P;\r
+#TIMESPEC TS_DCOB4_P = PERIOD "DCOB4_P" 3.125 ns HIGH 50%;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXSKEW = 100 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXDELAY = 500 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXDELAY = 500 ps;\r
+\r
+#390\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" MAXDELAY = 750 ps;\r
+\r
+# half of real frequency because of synchronisation with falling edge\r
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel1458_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel2356_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#\r
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel1458_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel2356_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#\r
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel1458_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel2356_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#\r
+#NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel1458_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" 12.5 ns HIGH 50 %;\r
+#NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv";\r
+#TIMESPEC TS_AdcToplevel2356_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" 12.5 ns HIGH 50 %;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";\r
+TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";\r
+TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";\r
+TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";\r
+TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";\r
+TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";\r
+TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";\r
+TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";\r
+TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;\r
+\r
+\r
+#NET "ADC_clk_S" TNM_NET = "ADC_clk_S";\r
+#TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;\r
+#NET "ADC_clk_S" MAXDELAY = 1.6 ns;
+#NET "ADC_clk_S" MAXSKEW = 1.6 ns;
+#NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "FEE_ADCinput_module1/ADC_clknot_S";\r
+#TIMESPEC TS_clknot_S = PERIOD "FEE_ADCinput_module1/ADC_clknot_S" 12.5 ns HIGH 50 %;\r
+#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.6 ns;\r
+#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1.6 ns;\r
+#
+#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;\r
+#\r
+#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
+#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;\r
+\r
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S_clk";\r
+TIMESPEC TS_ADC_clk_S_clk = PERIOD "ADC_clk_S_clk" 12.5 ns HIGH 50 %;\r
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S_net";\r
+NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_clk";\r
+TIMESPEC TS_ADC_clknot_S_clk = PERIOD "ADC_clknot_S_clk" 12.5 ns HIGH 50 %;\r
+NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_net";\r
+\r
+NET "ADC_clk_S" MAXDELAY = 1.6 ns;\r
+NET "ADC_clk_S" MAXSKEW = 1 ns;\r
+NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.4 ns;\r
+NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1 ns;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_per";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_per";\r
+\r
+TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_per = PERIOD "IntClkDiv1458_1_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_per = PERIOD "IntClkDiv1458_2_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_per = PERIOD "IntClkDiv1458_3_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_per = PERIOD "IntClkDiv1458_4_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_per = PERIOD "IntClkDiv2356_1_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_per = PERIOD "IntClkDiv2356_2_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_per = PERIOD "IntClkDiv2356_3_per" 12.5 ns HIGH 50 %;\r
+TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_per = PERIOD "IntClkDiv2356_4_per" 12.5 ns HIGH 50 %;\r
+\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_net";\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_net";\r
+\r
+TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_net = FROM "IntClkDiv1458_1_net" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_net = FROM "IntClkDiv1458_2_net" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_net = FROM "IntClkDiv1458_3_per" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_net = FROM "IntClkDiv1458_4_per" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_net = FROM "IntClkDiv2356_1_per" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_net = FROM "IntClkDiv2356_2_per" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_net = FROM "IntClkDiv2356_3_per" TO "ADC_clknot_S_net" 4 ns;\r
+TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_net = FROM "IntClkDiv2356_4_per" TO "ADC_clknot_S_net" 4 ns;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;\r
+\r
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXSKEW = 250 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXSKEW = 250 ps;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXDELAY = 750 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXDELAY = 850 ps;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXDELAY = 850 ps;
+\r
+\r
+NET "FEE_ADCinput_module1/FRA1_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA1_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA2_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA2_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA3_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA3_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA4_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRA4_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB1_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB1_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB2_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB2_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB3_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB3_N_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB4_P_S" MAXDELAY = 20 ps;
+NET "FEE_ADCinput_module1/FRB4_N_S" MAXDELAY = 20 ps;
+\r
+NET "ST_CLK_P" TNM_NET = "ST_CLK_P";\r
+TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;\r
+NET "ST_CLK_N" TNM_NET = "ST_CLK_N";\r
+TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;\r
+\r
+INST "*AdcClock/AdcClock_I_Isrds_*" TNM = FFS "AdcClk_Isrds";\r
+INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM = FFS "AdcFrm_Isrds";\r
+INST "*AdcData/AdcData_I_Isrds_*" TNM = FFS "AdcDat_Isrds";\r
+INST "*AdcClock/*" TNM = FFS "AdcClk_Ffs";\r
+INST "*AdcFrame/*" TNM = FFS "AdcFrm_Ffs";\r
+INST "*AdcData/*" TNM = FFS "AdcDat_Ffs";\r
+TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 2.4 ns;\r
+TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 2.4 ns;\r
+TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 2.4 ns;\r
+\r
+NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_clk";\r
+TIMESPEC TS_clock_ADCref_S_clk = PERIOD "clock_ADCref_S_clk" 12.5 ns HIGH 50 %;\r
+NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_net";\r
+\r
+NET "ST_CLK_S" TNM_NET = "ST_CLK_S_clk";\r
+TIMESPEC TS_ST_CLK_S_clk = PERIOD "ST_CLK_S_clk" 6.43 ns HIGH 50 %;\r
+NET "ST_CLK_S" TNM_NET = "ST_CLK_S_net";\r
+\r
+NET "GCLK_S" TNM_NET = "GCLK_S_clk";\r
+TIMESPEC TS_GCLK_S_clk = PERIOD "GCLK_S_clk" 12.5 ns HIGH 50 %;\r
+NET "GCLK_S" TNM_NET = "GCLK_S_net";\r
+\r
+#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";\r
+#TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;\r
+#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S_net";\r
+\r
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S";\r
+TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;\r
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S_net";\r
+\r
+\r
+TIMESPEC TS_ADC_to_ADC = FROM "clock_ADCref_S_net" TO "clock_ADCref_S_net" 12.5 ns;\r
+TIMESPEC TS_ST_to_ST = FROM "ST_CLK_S_net" TO "ST_CLK_S_net" 6.43 ns;\r
+TIMESPEC TS_G_to_G = FROM "GCLK_S_net" TO "GCLK_S_net" 12.5 ns;\r
+TIMESPEC TS_SODA_to_SODA = FROM "rxSodaClk_S_net" TO "rxSodaClk_S_net" 6.25 ns;\r
+\r
+\r
+TIMESPEC TS_ADC_to_ST = FROM "clock_ADCref_S_net" TO "ST_CLK_S_net" TIG;\r
+TIMESPEC TS_ST_to_ADC = FROM "ST_CLK_S_net" TO "clock_ADCref_S_net" TIG;\r
+TIMESPEC TS_G_to_ST = FROM "GCLK_S_net" TO "ST_CLK_S_net" TIG;\r
+TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S_net" TO "ST_CLK_S_net" TIG;\r
+TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S_net" TO "GCLK_S_net" TIG;\r
+TIMESPEC TS_SODA_to_ADC = FROM "rxSodaClk_S_net" TO "clock_ADCref_S_net" TIG;\r
+\r
+#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";\r
+#NET "GCLK_S" TNM_NET = "GCLK_S";
+#NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S";
+##NET "clock125Mhz_S" TNM_NET = "clock125MHz_S";
+#NET "clock200Mhz_S" TNM_NET = "clock200MHz_S";
+##NET "clock100Mhz_S" TNM_NET = "clock100MHz_S";
+#
+##TIMESPEC TS_125M_to_ref = FROM "clock125MHz_S" TO "clock_ADCref_S" TIG;
+##TIMESPEC TS_ref_to_125M = FROM "clock_ADCref_S" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_GCLK_to_ref = FROM "GCLK_S" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_ref_to_GCLK = FROM "clock_ADCref_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_GCLK_to_125M = FROM "GCLK_S" TO "clock125MHz_S" TIG;
+##TIMESPEC TS_125M_to_GCLK = FROM "clock125MHz_S" TO "GCLK_S" TIG;
+#\r
+#
+##TIMESPEC TS_62M5_to_100M = FROM "clock62M5Hz_S" TO "clock100MHz_S" TIG;
+##TIMESPEC TS_100M_to_62M5 = FROM "clock100MHz_S" TO "clock62M5Hz_S" TIG;
+##TIMESPEC TS_125M_to_100M = FROM "clock125MHz_S" TO "clock100MHz_S" TIG;
+##TIMESPEC TS_100M_to_125M = FROM "clock100MHz_S" TO "clock125MHz_S" TIG;
+#
+#TIMESPEC TS_ref_to_200M = FROM "clock62M5Hz_S" TO "clock200MHz_S" TIG;
+#TIMESPEC TS_200M_to_ref = FROM "clock200MHz_S" TO "clock62M5Hz_S" TIG;
+#TIMESPEC TS_GCLK_to_200M = FROM "GCLK_S" TO "clock200MHz_S" TIG;
+#TIMESPEC TS_200M_to_GCLK = FROM "clock200MHz_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_200M = FROM "clock125MHz_S" TO "clock200MHz_S" TIG;
+##TIMESPEC TS_200M_to_125M = FROM "clock200MHz_S" TO "clock125MHz_S" TIG;
+#
+#TIMESPEC TS_ref_to_ST_CLK = FROM "clock_ADCref_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_ref = FROM "ST_CLK_S" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_GCLK_to_ST_CLK = FROM "GCLK_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_GCLK = FROM "ST_CLK_S" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_ST_CLK = FROM "clock125MHz_S" TO "ST_CLK_S" TIG;
+##TIMESPEC TS_ST_CLK_to_125M = FROM "ST_CLK_S" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_200M_to_ST_CLK = FROM "clock200MHz_S" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_ST_CLK_to_200M = FROM "ST_CLK_S" TO "clock200MHz_S" TIG;
+#\r
+#NET "ST_CLK_S_BUFG" TNM_NET = "ST_CLK_S_BUFG";
+#TIMESPEC TS_ref_to_ST_CLK_BUFG = FROM "clock_ADCref_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_ref = FROM "ST_CLK_S_BUFG" TO "clock_ADCref_S" TIG;
+#TIMESPEC TS_GCLK_to_ST_CLK_BUFG = FROM "GCLK_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_GCLK = FROM "ST_CLK_S_BUFG" TO "GCLK_S" TIG;
+##TIMESPEC TS_125M_to_ST_CLK_BUFG = FROM "clock125MHz_S" TO "ST_CLK_S_BUFG" TIG;
+##TIMESPEC TS_ST_CLK_BUFG_to_125M = FROM "ST_CLK_S_BUFG" TO "clock125MHz_S" TIG;
+#TIMESPEC TS_200M_to_ST_CLK_BUFG = FROM "clock200MHz_S" TO "ST_CLK_S_BUFG" TIG;
+#TIMESPEC TS_ST_CLK_BUFG_to_200M = FROM "ST_CLK_S_BUFG" TO "clock200MHz_S" TIG;\r
+\r
+#TIMESPEC TS_62M5_to_txUsrClk2 = FROM "clock62M5Hz_S" TO "FEE_gtxModule1/txUsrClk2_S" 20 ns;\r
+#TIMESPEC TS_txUsrClk2_to_62M5 = FROM "FEE_gtxModule1/txUsrClk2_S" TO "clock62M5Hz_S" 20 ns;\r
+\r
+NET "GCLK_P" TNM_NET = "GCLK_P";\r
+TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;\r
+NET "GCLK_N" TNM_NET = "GCLK_N";\r
+TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;\r
+\r
+NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";\r
+TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;\r
+NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";\r
+TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;\r
+\r
+NET "FEE_gtxModule1/txUsrClk_S" TNM_NET = "FEE_gtxModule1/txUsrClk_S";\r
+TIMESPEC TS_FEE_gtxModule1_txUsrClk_S = PERIOD "FEE_gtxModule1/txUsrClk_S" 5 ns HIGH 50 %;\r
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S";\r
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" 5 ns HIGH 50 %;\r
+NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" TNM_NET = FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S;\r
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" 12.5 ns HIGH 50%;\r
+#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i/gtx0_gtxVirtex6FEE_i/gtxe1_i LOC=GTXE1_X0Y12;
+#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i LOC=GTXE1_X0Y12;
+\r
+#TIMESPEC TS_RXCLK_to_TXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/txUsrClk2_S" 3 ns;\r
+#TIMESPEC TS_TXCLK_to_RXCLK = FROM "FEE_gtxModule1/txUsrClk2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;\r
+#TIMESPEC TS_RXCLK_to_TXCLK0 = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" 3 ns;\r
+#TIMESPEC TS_TXCLK0_to_RXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;\r
+\r
+\r
+NET "GEO" IOSTANDARD = LVCMOS25;\r
+#NET "GEO" DRIVE = 12;\r
+NET "GEO" SLEW = SLOW;\r
+NET "GEO" PULLUP;\r
+net "GEO" TIG;\r
+#NET "S_CTRL" TIG;\r
+#NET "T_CTRL_S" TIG;\r
+\r
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_A1;
+#AREA_GROUP "pblock_adc_A1" RANGE=SLICE_X30Y140:SLICE_X35Y159;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_B1;
+#AREA_GROUP "pblock_adc_B1" RANGE=SLICE_X30Y120:SLICE_X35Y139;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_A2;
+#AREA_GROUP "pblock_adc_A2" RANGE=SLICE_X0Y120:SLICE_X5Y139;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_B2;
+#AREA_GROUP "pblock_adc_B2" RANGE=SLICE_X0Y140:SLICE_X5Y159;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_A3;
+#AREA_GROUP "pblock_adc_A3" RANGE=SLICE_X0Y100:SLICE_X5Y119;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_B3;
+#AREA_GROUP "pblock_adc_B3" RANGE=SLICE_X0Y80:SLICE_X5Y99;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_A4;
+#AREA_GROUP "pblock_adc_A4" RANGE=SLICE_X64Y100:SLICE_X69Y119;
+#
+#INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_B4;
+#AREA_GROUP "pblock_adc_B4" RANGE=SLICE_X64Y80:SLICE_X69Y99;
+\r
+\r
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_1;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_1;
+AREA_GROUP "pblock_adc_1" RANGE=SLICE_X30Y120:SLICE_X35Y159;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_2;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_2;
+AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y120:SLICE_X5Y159;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_3;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_3;
+AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y80:SLICE_X5Y119;
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_4;
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_4;
+AREA_GROUP "pblock_adc_4" RANGE=SLICE_X64Y80:SLICE_X69Y119;
+\r
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="../FEE_modules/FEE_pulse_and_pileup_waveforms.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_sorting_wavemux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_wavemux_readfifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_wavemux2to1.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/shift_register.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/iirfilter_1order_selectBW.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_combine_data.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/blockmem.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="253"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/posedge_to_pulse.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="254"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/crc8_add_check32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="255"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_sorting_mux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="256"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_extract_pulse.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="259"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_pulse2to1_pulse.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="260"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_mux2to1.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="269"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/div_pipe_r4_arch2/mypack.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="268"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_adc32_module.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="270"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_baselinefollower_eventdetector.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="271"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_board_slowcontrol.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="272"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_dual_pulse_waveform.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_eventdetector.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="274"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_mux_readfifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="275"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_pileup_check.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="276"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_pulsewaveform_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="277"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_slowcontrol_packet_receiver.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="278"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_waveform_to_36bits.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="279"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/Panda_package.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="../FEE_modules/FEE_measure_frequency.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_SODAfrequencydiv5.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_fifo8to32_SODA.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_fifo32to8_SODA.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_rxBitLock.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_gtxModule.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../FEE_modules/FEE_gtxWrapper_Virtex6.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="FEE_ADC32board.ucf" xil_pn:type="FILE_UCF">
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+ </file>
+ <file xil_pn:name="FEE_ADC32board_top.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="ipcore_dir/clockmodule80M.xco" xil_pn:type="FILE_COREGEN">
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+ <file xil_pn:name="../modules/FEE_ADCinput_module.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/LMK03806.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/SystemMonitorModule.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="ipcore_dir/icon0.xco" xil_pn:type="FILE_COREGEN">
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+ <file xil_pn:name="ipcore_dir/ila36.xco" xil_pn:type="FILE_COREGEN">
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+ <file xil_pn:name="ipcore_dir/ila128.xco" xil_pn:type="FILE_COREGEN">
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+ <file xil_pn:name="ipcore_dir/SystemMonitorVirtex.xco" xil_pn:type="FILE_COREGEN">
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+ <file xil_pn:name="../../SODA/soda_FEE_endpoint.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
+ </file>
+ <file xil_pn:name="../../SODA/soda_packet_handler.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
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+ <file xil_pn:name="../../SODA/soda_reply_pkt_builder.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
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+ <file xil_pn:name="../../SODA/soda_d8crc8.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
+ </file>
+ <file xil_pn:name="../modules/ADCrefdesign/AdcClock.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/ADCrefdesign/AdcData.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/ADCrefdesign/AdcFrame.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/ADCrefdesign/AdcToplevel.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/ADCrefdesign/DoubleNibbleDetect.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../modules/ADCrefdesign/GenPulse.vhd" xil_pn:type="FILE_VHDL">
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+ <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="FEE_ADC32board_top.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;C:/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.top" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.top" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_physicalsynthesis2.xds" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="iMPACT Project File" xil_pn:value="FEE_V2_ADC32board.ipf" xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|sim_SODA2_tb|behavior" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="FEE_test_ADC32" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-20T09:50:16" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA4862807094468B9C6DDA953391E7F7" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+library work;
+use work.panda_package.all;
+--use work.panda_pkg.all;
+
+entity top is
+ Port ( \r
+ GEO : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2\r
+ GCLK_P : in std_logic; -- clock equal to GTX refclock (62.5MHz or 80MHz)
+ GCLK_N : in std_logic;\r
+ \r
+ ST_CLK_P : in std_logic; -- 155.52MHz\r
+ ST_CLK_N : in std_logic;\r
+\r
+\r
+----ADC1--------------------------------------------- \r
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;\r
+ \r
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+ \r
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;\r
+\r
+----ADC2--------------------------------------------- \r
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;\r
+\r
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+ \r
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;\r
+\r
+----ADC3--------------------------------------------- \r
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;\r
+\r
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+ \r
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;\r
+\r
+----ADC4--------------------------------------------- \r
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic; \r
+ \r
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+ \r
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;\r
+ \r
+----ADCconfiguration--------------------------------------------- \r
+ SCK : out std_logic;\r
+ SDI : out std_logic;\r
+ CSA : out std_logic_vector(1 to 4);\r
+ CSB : out std_logic_vector(1 to 4);\r
+ SDOA : inout std_logic_vector(1 to 4);\r
+ SDOB : inout std_logic_vector(1 to 4);\r
+\r
+----GTX--------------------------------------------- \r
+ MOD_DEF : in std_logic_vector(2 downto 0);\r
+ LOS : in std_logic;\r
+ TX_DIS : out std_logic;\r
+ MGTREFCLK_P : in std_logic;\r
+ MGTREFCLK_N : in std_logic;\r
+\r
+ RX_P : in std_logic;\r
+ RX_N : in std_logic;\r
+ TX_P : out std_logic;\r
+ TX_N : out std_logic;\r
+\r
+----PLL--------------------------------------------- \r
+\r
+ S_CTRL : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG\r
+ T_CTRL : out std_logic; -- T_CTRL from FPGA1<>FPGA2 : FPGA1 controls PLL&JTAG\r
+\r
+ RDu : in std_logic;\r
+ CLKu : out std_logic;\r
+ DATAu : out std_logic;\r
+ LEu : out std_logic;\r
+ SYNC : out std_logic;\r
+ RCV_CLK_P : out std_logic; -- ref clock for PLL LMK03806\r
+ RCV_CLK_N : out std_logic;\r
+ \r
+----TMP104--------------------------------------------- \r
+-- TEMP_IN : out std_logic;\r
+-- TEMP_OUT : in std_logic;\r
+ \r
+----test---------------------------------------------
+ SM1_P : out std_logic;
+ SM1_N : out std_logic;
+ SM3_P : in std_logic;
+ SM3_N : in std_logic;
+\r
+ INTCOMC1_P : inout std_logic;
+ INTCOMC1_N : inout std_logic;
+ INTCOMC2_P : inout std_logic;
+ INTCOMC2_N : inout std_logic;
+\r
+ INTCOM0_P : inout std_logic;
+ INTCOM0_N : inout std_logic;
+ INTCOM1_P : inout std_logic;
+ INTCOM1_N : inout std_logic;\r
+ INTCOM2_P : inout std_logic;
+ INTCOM2_N : inout std_logic;\r
+ INTCOM3_P : inout std_logic;
+ INTCOM3_N : inout std_logic;
+ INTCOM4_P : inout std_logic;
+ INTCOM4_N : inout std_logic;\r
+ INTCOM5_P : inout std_logic;
+ INTCOM5_N : inout std_logic;\r
+ INTCOM6_P : inout std_logic;
+ INTCOM6_N : inout std_logic;
+ INTCOM7_P : inout std_logic;
+ INTCOM7_N : inout std_logic;\r
+\r
+ TCK_F : in std_logic;\r
+ TDI_F : in std_logic;\r
+ TDO_F : in std_logic;\r
+ TMS_F : in std_logic\r
+-- PROGRAM_B : inout std_logic
+\r
+\r
+-- D : in std_logic_VECTOR (7 downto 0)
+ );
+end top;
+\r
+\r
+
+architecture Behavioral of top is
+\r
+component clockmodule80M
+port (
+ CLK_IN1 : in std_logic;
+ CLK_OUT1 : out std_logic;
+ LOCKED : out std_logic
+ );
+end component;\r
+\r
+component clock155to200MHz
+port(
+ CLK_IN1 : in std_logic;
+ CLK_IN2 : in std_logic;
+ CLK_IN_SEL : in std_logic;
+ CLK_OUT1 : out std_logic;
+ RESET : in std_logic;
+ LOCKED : out std_logic
+ );
+end component;\r
+\r
+component clockmodule80to80M\r
+port(\r
+ CLK_IN1 : in std_logic;\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ CLK_OUT3 : out std_logic;\r
+ CLK_OUT4 : out std_logic;\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+component clockmodule40to80\r
+port(\r
+ CLK_IN1 : in std_logic;\r
+ CLK_OUT1 : out std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+component clockmodule40switch\r
+port(\r
+ CLK_IN1 : in std_logic;\r
+ CLK_IN2 : in std_logic;\r
+ CLK_IN_SEL : in std_logic;\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+component LMK03806 is
+ generic(
+ CLK_DIV : integer := 6; -- slow down transfer
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY
+ );
+ PORT( \r
+ clock : in std_logic; --Master clock
+ CLKu : out std_logic; --Clk to LMK
+ DATAu : out std_logic; --Data to LMK
+ LEu : out std_logic; --Data Latch to LMK
+ RDn : in std_logic; --Read back
+ SYNC : out std_logic; --Sync CLK outputs LMK
+ boot_PLL : in std_logic; --Start booting when set high\r
+ reset_GTX : out std_logic; --delayed reset for GTX
+ reset_ADCs : out std_logic; --delayed reset for ADCs \r
+ booting : out std_logic; --busy signal \r
+ testwordin : in std_logic_vector(15 downto 0)
+ );
+end component;
+\r
+component FEE_ADCinput_module is
+ port (
+ clock200MHz : in std_logic;
+ reset : in std_logic;
+ ADCs_enable : in std_logic;
+----ADC1---------------------------------------------
+ AD11A_P : in std_logic;
+ AD11A_N : in std_logic;
+ AD11B_P : in std_logic;
+ AD11B_N : in std_logic;
+ AD12A_P : in std_logic;
+ AD12A_N : in std_logic;
+ AD12B_P : in std_logic;
+ AD12B_N : in std_logic;
+ AD13A_P : in std_logic;
+ AD13A_N : in std_logic;
+ AD13B_P : in std_logic;
+ AD13B_N : in std_logic;
+ AD14A_P : in std_logic;
+ AD14A_N : in std_logic;
+ AD14B_P : in std_logic;
+ AD14B_N : in std_logic;
+ AD15A_P : in std_logic;
+ AD15A_N : in std_logic;
+ AD15B_P : in std_logic;
+ AD15B_N : in std_logic;
+ AD16A_P : in std_logic;
+ AD16A_N : in std_logic;
+ AD16B_P : in std_logic;
+ AD16B_N : in std_logic;
+ AD17A_P : in std_logic;
+ AD17A_N : in std_logic;
+ AD17B_P : in std_logic;
+ AD17B_N : in std_logic;
+ AD18A_P : in std_logic;
+ AD18A_N : in std_logic;
+ AD18B_P : in std_logic;
+ AD18B_N : in std_logic;
+
+ DCOA1_P : in std_logic;
+ DCOA1_N : in std_logic;
+ DCOB1_P : in std_logic;
+ DCOB1_N : in std_logic;
+
+ FRA1_P : in std_logic;
+ FRA1_N : in std_logic;
+ FRB1_P : in std_logic;
+ FRB1_N : in std_logic;
+
+----ADC2---------------------------------------------
+ AD21A_P : in std_logic;
+ AD21A_N : in std_logic;
+ AD21B_P : in std_logic;
+ AD21B_N : in std_logic;
+ AD22A_P : in std_logic;
+ AD22A_N : in std_logic;
+ AD22B_P : in std_logic;
+ AD22B_N : in std_logic;
+ AD23A_P : in std_logic;
+ AD23A_N : in std_logic;
+ AD23B_P : in std_logic;
+ AD23B_N : in std_logic;
+ AD24A_P : in std_logic;
+ AD24A_N : in std_logic;
+ AD24B_P : in std_logic;
+ AD24B_N : in std_logic;
+ AD25A_P : in std_logic;
+ AD25A_N : in std_logic;
+ AD25B_P : in std_logic;
+ AD25B_N : in std_logic;
+ AD26A_P : in std_logic;
+ AD26A_N : in std_logic;
+ AD26B_P : in std_logic;
+ AD26B_N : in std_logic;
+ AD27A_P : in std_logic;
+ AD27A_N : in std_logic;
+ AD27B_P : in std_logic;
+ AD27B_N : in std_logic;
+ AD28A_P : in std_logic;
+ AD28A_N : in std_logic;
+ AD28B_P : in std_logic;
+ AD28B_N : in std_logic;
+
+ DCOA2_P : in std_logic;
+ DCOA2_N : in std_logic;
+ DCOB2_P : in std_logic;
+ DCOB2_N : in std_logic;
+
+ FRA2_P : in std_logic;
+ FRA2_N : in std_logic;
+ FRB2_P : in std_logic;
+ FRB2_N : in std_logic;
+
+----ADC3---------------------------------------------
+ AD31A_P : in std_logic;
+ AD31A_N : in std_logic;
+ AD31B_P : in std_logic;
+ AD31B_N : in std_logic;
+ AD32A_P : in std_logic;
+ AD32A_N : in std_logic;
+ AD32B_P : in std_logic;
+ AD32B_N : in std_logic;
+ AD33A_P : in std_logic;
+ AD33A_N : in std_logic;
+ AD33B_P : in std_logic;
+ AD33B_N : in std_logic;
+ AD34A_P : in std_logic;
+ AD34A_N : in std_logic;
+ AD34B_P : in std_logic;
+ AD34B_N : in std_logic;
+ AD35A_P : in std_logic;
+ AD35A_N : in std_logic;
+ AD35B_P : in std_logic;
+ AD35B_N : in std_logic;
+ AD36A_P : in std_logic;
+ AD36A_N : in std_logic;
+ AD36B_P : in std_logic;
+ AD36B_N : in std_logic;
+ AD37A_P : in std_logic;
+ AD37A_N : in std_logic;
+ AD37B_P : in std_logic;
+ AD37B_N : in std_logic;
+ AD38A_P : in std_logic;
+ AD38A_N : in std_logic;
+ AD38B_P : in std_logic;
+ AD38B_N : in std_logic;
+
+ DCOA3_P : in std_logic;
+ DCOA3_N : in std_logic;
+ DCOB3_P : in std_logic;
+ DCOB3_N : in std_logic;
+
+ FRA3_P : in std_logic;
+ FRA3_N : in std_logic;
+ FRB3_P : in std_logic;
+ FRB3_N : in std_logic;
+
+----ADC4---------------------------------------------
+ AD41A_P : in std_logic;
+ AD41A_N : in std_logic;
+ AD41B_P : in std_logic;
+ AD41B_N : in std_logic;
+ AD42A_P : in std_logic;
+ AD42A_N : in std_logic;
+ AD42B_P : in std_logic;
+ AD42B_N : in std_logic;
+ AD43A_P : in std_logic;
+ AD43A_N : in std_logic;
+ AD43B_P : in std_logic;
+ AD43B_N : in std_logic;
+ AD44A_P : in std_logic;
+ AD44A_N : in std_logic;
+ AD44B_P : in std_logic;
+ AD44B_N : in std_logic;
+ AD45A_P : in std_logic;
+ AD45A_N : in std_logic;
+ AD45B_P : in std_logic;
+ AD45B_N : in std_logic;
+ AD46A_P : in std_logic;
+ AD46A_N : in std_logic;
+ AD46B_P : in std_logic;
+ AD46B_N : in std_logic;
+ AD47A_P : in std_logic;
+ AD47A_N : in std_logic;
+ AD47B_P : in std_logic;
+ AD47B_N : in std_logic;
+ AD48A_P : in std_logic;
+ AD48A_N : in std_logic;
+ AD48B_P : in std_logic;
+ AD48B_N : in std_logic;
+
+ DCOA4_P : in std_logic;
+ DCOA4_N : in std_logic;
+ DCOB4_P : in std_logic;
+ DCOB4_N : in std_logic;
+
+ FRA4_P : in std_logic;
+ FRA4_N : in std_logic;
+ FRB4_P : in std_logic;
+ FRB4_N : in std_logic;
+ ADC_clk : out std_logic;
+ ADCs_ready : out std_logic;\r
+ adcdata : out array_adc_type
+ );
+end component;
+\r
+component FEE_adc32_module is
+ generic (
+ NROFADCS : natural := NROFADCS;
+ ADCBITS : natural := 14;
+ BASELINE_BWBITS : natural := 10;
+ WAVEFORMBUFFERSIZE : natural := 10;
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY;
+ CF_DELAYBITS : natural := 4;
+ CF_FRACTIONBIT : natural := 11;
+ IDIVMAXBITS : natural := 6;
+ INTEGRALRATIOBITS : natural := 3
+ );
+ port (
+ clock : in std_logic;
+ reset : in std_logic;\r
+ enable_data : in std_logic;
+ ADCdata : in array_adc_type;\r
+ superburst_start : in std_logic;
+ superburst_received : in std_logic_vector(30 downto 0);
+ onesecondpulse : in std_logic;
+ rxNotInTable : in std_logic;
+ startupready : in std_logic;
+ request_init : in std_logic;
+ packet_in_data : in std_logic_vector (31 downto 0);
+ packet_in_present : in std_logic;
+ packet_in_read : out std_logic;\r
+ packet_out_data : out std_logic_vector(31 downto 0);
+ packet_out_last : out std_logic;
+ packet_out_write : out std_logic;
+ packet_out_fifofull : in std_logic;\r
+ errorbyte_out : out std_logic_vector(7 downto 0);\r
+ errorbyte_in : in std_logic_vector(7 downto 0);\r
+ smaart_in : in std_logic;
+ smaart_out : out std_logic;\r
+ sysmon_data : in std_logic_vector(15 downto 0);\r
+ sysmon_reset : out std_logic;\r
+ sysmon_address : out std_logic_vector(6 downto 0);\r
+ sysmon_read : out std_logic;\r
+ testindex : in integer range 0 to NROFADCS/2-1;\r
+ testword0 : out std_logic_vector(35 downto 0);
+ testword1 : out std_logic_vector(35 downto 0);\r
+ testword2 : out std_logic_vector(35 downto 0)\r
+ );
+end component; \r
+\r
+component FEE_gtxModule is
+ generic(
+ ADCCLOCKFREQUENCY : natural := ADCCLOCKFREQUENCY -- 80000000 -- 62500000
+ );
+ Port (
+ gtpClk : in std_logic;
+ asyncclk : in std_logic;\r
+ reset : in std_logic;
+ disable_GTX_reset : in std_logic;\r
+
+ TX_DLM : in std_logic;
+ TX_DLM_WORD : in std_logic_vector(7 downto 0);
+ RX_DLM : out std_logic;
+ RX_DLM_WORD : out std_logic_vector(7 downto 0);\r
+ \r
+ txAsyncClk : in std_logic;
+ txAsyncData : in std_logic_vector(31 downto 0);
+ txAsyncDataWrite : in std_logic;
+ txAsyncLastData : in std_logic;
+ txAsyncFifoFull : out std_logic;
+ txUsrClk : out std_logic;\r
+ txLocked : out std_logic;
+
+ rxAsyncClk : in std_logic;
+ rxAsyncData : out std_logic_vector(31 downto 0);
+ rxAsyncDataRead : in std_logic;
+ rxNotInTable : out std_logic;
+ rxAsyncDataOverflow : out std_logic;
+ rxAsyncDataPresent : out std_logic;
+ rxSodaClk : out std_logic;
+ rxSodaClk40 : out std_logic;
+ rxLocked : out std_logic;\r
+
+ gtpTxP0 : out std_logic;
+ gtpTxN0 : out std_logic;
+ gtpRxP0 : in std_logic;
+ gtpRxN0 : in std_logic;
+ testword0 : out std_logic_vector(35 downto 0)
+ );
+end component;
+\r
+component soda_FEE_endpoint is
+ generic(
+ SODA_16BIT_INTERFACE : boolean := FALSE
+ );
+ port(
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+
+ RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
+ RX_DLM_IN : in std_logic;
+ TX_DLM_OUT : out std_logic;
+ TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
+
+
+ START_OF_SUPERBURST : out std_logic := '0';
+ SUPER_BURST_NR : out std_logic_vector(30 downto 0) := (others => '0');
+ SODA_CMD_VALID : out std_logic := '0';
+ SODA_CMD_WORD : out std_logic_vector(30 downto 0) := (others => '0');
+
+ STAT : out std_logic_vector(31 downto 0) := (others => '0') -- DEBUG
+ );
+end component;\r
+\r
+component SystemMonitorModule is
+ Port (
+ clock : in std_logic;
+ reset : in std_logic;
+ address : in std_logic_vector(6 downto 0);
+ data_write : in std_logic;
+ data_in : in std_logic_vector(15 downto 0);
+ data_read : in std_logic;
+ data_out : out std_logic_vector(15 downto 0);
+ alarms : out std_logic_vector(7 downto 0);
+ testword0 : out std_logic_vector(35 downto 0));
+end component;\r
+\r
+component posedge_to_pulse is\r
+ port (\r
+ clock_in : in std_logic;\r
+ clock_out : in std_logic;\r
+ en_clk : in std_logic;\r
+ signal_in : in std_logic;\r
+ pulse : out std_logic\r
+ );\r
+end component;\r
+\r
+component posedge_async_to_pulse is\r
+ port (\r
+ clock_out : in std_logic;\r
+ signal_in : in std_logic;\r
+ pulse : out std_logic\r
+ );\r
+end component;\r
+\r
+component icon0
+ port (
+ CONTROL0 : inout std_logic_vector(35 downto 0);
+ CONTROL1 : inout std_logic_vector(35 downto 0);
+ CONTROL2 : inout std_logic_vector(35 downto 0);
+ CONTROL3 : inout std_logic_vector(35 downto 0);
+ CONTROL4 : inout std_logic_vector(35 downto 0));
+end component;
+
+component ila36
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(35 downto 0));
+end component;
+
+component ila128
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ CLK : in std_logic;
+ TRIG0 : in std_logic_vector(127 downto 0));
+end component;
+
+component vio36
+ port (
+ CONTROL : inout std_logic_vector(35 downto 0);
+ ASYNC_OUT : out std_logic_vector(35 downto 0));
+end component;
+\r
+attribute keep : string;\r
+constant DEBUG : boolean := false;\r
+-- clocking\r
+signal ST_CLK_S : std_logic;\r
+attribute keep of ST_CLK_S : signal is "TRUE";\r
+signal clock_ADCrefdiv2_S : std_logic;
+signal clock_ADCref_S : std_logic; -- 62.5 or 80 MHz
+attribute keep of clock_ADCref_S : signal is "TRUE";\r
+signal clock100MHz_S : std_logic;
+signal clock200MHz_S : std_logic;\r
+signal clock80MHz_PLL1_S : std_logic;\r
+signal GCLK_S : std_logic;\r
+attribute keep of GCLK_S : signal is "TRUE";\r
+signal gtpClk_S : std_logic;\r
+signal RCV_CLK_P_S : std_logic;\r
+signal RCV_CLK_S : std_logic;
+signal RCV_CLK_not_S : std_logic;\r
+signal RCV_CLKref_S : std_logic;\r
+signal RCV_CLKrx_S : std_logic;\r
+signal ADC_clk_S : std_logic;\r
+attribute keep of ADC_clk_S : signal is "TRUE";\r
+signal txUsrClk_S : std_logic;\r
+\r
+\r
+signal clockPLL1_locked_S : std_logic;\r
+signal clockPLL2_reset_S : std_logic;\r
+signal clockmodule_locked_S : std_logic;\r
+signal clockswitch_locked_S : std_logic;\r
+ \r
+-- resetting\r
+signal coldstart_counter_S : std_logic_vector(7 downto 0) := (others => '0');
+signal coldstart_S : std_logic := '0';\r
+signal reset_S : std_logic := '0';\r
+signal reset_FEE_S : std_logic := '0';\r
+signal reset_FEE_ADCclk_S : std_logic := '0';\r
+signal resetting_S : std_logic := '0';
+signal resetting_stclk_S : std_logic := '0';
+signal IcontrolPLL_S : std_logic := '0';
+signal otherFPGAnotconfigured0_S : std_logic := '0';
+signal otherFPGAnotconfigured_S : std_logic := '0';
+signal PLLconfigured_S : std_logic := '0';
+signal startupready_S : std_logic := '0';
+signal selectPLLclk_S : std_logic := '0';
+signal selectPLLclk_stclk_S : std_logic := '0';
+signal disable_GTX_reset_S : std_logic := '0';\r
+signal GEO_S : std_logic := '0';
+signal GEO_stclk_S : std_logic := '0';
+signal T_CTRL_S : std_logic := '0';
+signal S_CTRL0_S : std_logic := '0';
+signal phaseSYNC_S : std_logic := '0';\r
+signal boot_PLL_S : std_logic := '0';\r
+signal PLL_booting_S : std_logic := '0';
+signal adcintrfcena_s : std_logic := '0';\r
+signal reset_ADCs_S : std_logic := '0';
+signal ADCs_enable_S : std_logic := '0';\r
+signal reset_GTX_S : std_logic := '0';\r
+signal reset_counter_S : integer range 0 to 65535 := 0;
+signal timeout_counter_S : integer range 0 to 65535 := 0;
+signal external_sync_out_S : std_logic := '0';\r
+signal external_sync_in0_S : std_logic := '0';\r
+signal external_sync_in_S : std_logic := '0';\r
+signal reset_rxSodaClk_S : std_logic;\r
+signal ADCs_ready_S : std_logic;\r
+\r
+\r
+-- SODA\r
+signal EnableDataTaking_S : std_logic := '0';\r
+signal DisableDataTaking_S : std_logic := '0';\r
+signal enable_data_S : std_logic := '0';\r
+signal DataTaking_enabled_out_S : std_logic := '0';\r
+signal DataTaking_enabled_in_S : std_logic := '0';\r
+signal SODA_cmd_valid_S : std_logic := '0';\r
+signal SODA_cmd_word_S : std_logic_vector(30 downto 0);\r
+signal superburst_out_S : std_logic_vector(30 downto 0);
+signal superburst_in_S : std_logic_vector(30 downto 0);
+signal superburst_start0_S : std_logic;\r
+signal superburst_start1_S : std_logic;\r
+signal superburst_start_S : std_logic;\r
+signal superburst_startout0_S : std_logic;\r
+signal superburst_startout_S : std_logic;\r
+signal TX_DLM_S : std_logic;
+signal TX_DLM_WORD_S : std_logic_vector(7 downto 0);
+signal RX_DLM_S : std_logic;
+signal RX_DLM_WORD_S : std_logic_vector(7 downto 0);
+
+-- fiber data\r
+signal packet_in_data_S : std_logic_vector(31 downto 0);\r
+signal packet_out_data_S : std_logic_vector(31 downto 0) := (others => '0');\r
+signal packet_in_present_S : std_logic := '0';
+signal packet_in_read_S : std_logic := '0';
+signal packet_out_last_S : std_logic := '0';
+signal packet_out_write_S : std_logic := '0';
+signal packet_out_fifofull_S : std_logic := '0';
+signal rxNotInTable0_S : std_logic;
+signal rxNotInTable_S : std_logic;
+\r
+\r
+-- clock check\r
+signal GCLKdiv10_S : std_logic := '0';
+signal GCLKdiv10_prev1_S : std_logic := '0';
+signal GCLKdiv10_prev2_S : std_logic := '0';
+signal PLLfrequencyERROR_S : std_logic := '0';
+\r
+-- lmk03806\r
+signal CLKu_S : std_logic := '0';
+signal DATAu_S : std_logic := '0';
+signal LEu_S : std_logic := '0';
+signal SYNC_S : std_logic := '0';
+signal SYNC0_S : std_logic := '0';
+signal SYNC1_S : std_logic := '0';
+signal SYNC2_S : std_logic := '0';
+signal debug_sync_S : std_logic := '0';
+\r
+-- ADCs\r
+signal adcdata_S : array_adc_type;
+\r
+-- GTX\r
+signal LOS_S : std_logic;\r
+signal rxSodaClk_S : std_logic;\r
+attribute keep of rxSodaClk_S : signal is "TRUE";
+signal rxSodaClk40_S : std_logic;\r
+signal rxSodaClk40b_S : std_logic;\r
+signal rxSodaClk80_S : std_logic;\r
+signal rxLocked_S : std_logic;\r
+signal rxLocked0_S : std_logic;\r
+signal rxLocked_sync_S : std_logic;\r
+\r
+-- phasedet\r
+signal phasedet_S : std_logic;\r
+signal GCLKdiv2_S : std_logic;\r
+signal GCLKdiv4_S : std_logic;\r
+signal rxSodaClkdiv4_S : std_logic;\r
+signal phaseerr_max_S : integer range 0 to 1023 := 0;
+signal phasedet_count_S : integer range 0 to 1023 := 0;
+signal phaseerr_count_S : integer range 0 to 1023 := 0;
+signal phasecheck_ready_S : std_logic := '0';
+signal phasecheck_ready1_S : std_logic := '0';
+signal phaseSYNCpulse_S : std_logic := '0';
+signal phasecheckcounter_S : integer range 0 to 255 := 0;
+\r
+\r
+-- timestamp reset\r
+--signal ResetToZero_S : std_logic;\r
+signal onesecondpulse_S : std_logic;\r
+ \r
+signal SYNC_stclk_S : std_logic;\r
+signal SYNC_stclk2_S : std_logic;\r
+signal SYNC_adcclk_S : std_logic;\r
+signal SYNC_adcclk2_S : std_logic;\r
+signal SYNC_soda_S : std_logic;\r
+signal SYNC_soda2_S : std_logic;\r
+\r
+-- system monitor\r
+signal sysmon_data_S : std_logic_vector(15 downto 0);\r
+signal sysmon_reset_S : std_logic;\r
+signal sysmon_address_S : std_logic_vector(6 downto 0);\r
+signal sysmon_read_S : std_logic;\r
+
+-- test compare feature extraction results
+constant SECOND_FE_MODULE : boolean := false;\r
+signal adcdata2_S : array_adc_type;
+signal request_init_S : std_logic := '0';
+signal reset_FEE_ADCclk2_S : std_logic := '0';
+signal reset_FEE_ADCclk2a_S : std_logic := '0';
+signal packet_out_data2_S : std_logic_vector(31 downto 0);\r
+signal packet_in_read2_S : std_logic;
+signal packet_out_last2_S : std_logic;
+signal packet_out_write2_S : std_logic;
+signal unequal_counter_S : std_logic_vector(31 downto 0) := (others => '0');\r
+signal unequal_time_S : std_logic_vector(31 downto 0) := (others => '0');\r
+signal zero_data_S : std_logic;
+signal unequal_S : std_logic;
+signal errorbyte_S : std_logic_vector(7 downto 0) := (others => '0');
+\r
+\r
+-- test
+signal control0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control1_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control2_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control3_S : std_logic_vector(35 downto 0) := (others => '0');
+signal control4_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0a_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0b_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword1_S : std_logic_vector(35 downto 0) := (others => '0');\r
+signal testwordb_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testword2_S : std_logic_vector(127 downto 0) := (others => '0');\r
+signal vioword_S : std_logic_vector(35 downto 0) := (others => '0');
+signal vioword2_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testwordA0_S : std_logic_vector(35 downto 0) := (others => '0');
+signal testwordB0_S : std_logic_vector(35 downto 0) := (others => '0');
+
+signal selectnr_S : integer range 0 to 3 := 0;
+signal testclockDiv2_S : std_logic_vector(7 downto 0) := (others => '0');
+signal forced_reset_S : std_logic := '0';
+signal test_resetadc_s : std_logic := '0';\r
+signal testclocks_S : std_logic_vector(8 downto 0) := (others => '0');
+signal testclockDiv100_S : std_logic_vector(8 downto 0) := (others => '0');
+
+begin\r
+-- GEO=0:this is FPGA1, GEO=1:this is FPGA2
+-- S_CTRL=1 : FPGA1 controls PLL&JTAG
+-- S_CTRL=0 : FPGA2 controls PLL&JTAG
+
+-- T_CTRL1 T_CTRL2 PLL_controlled_by S_CTRL
+-- 0 0 0 = FPGA2 0
+-- 1 0 1 = FPGA1 1
+-- 0 1 1 = FPGA1 1
+-- 1 1 0 = FPGA2 0
+
+IcontrolPLL_S <= '1' when (GEO/=S_CTRL) else '0'; -- '1' when this FPGA controls the PLL
+
+coldstartprocess: process(ST_CLK_S)
+begin
+ if rising_edge(ST_CLK_S) then
+ if coldstart_counter_S/=x"ff" then
+ coldstart_S <= '0';
+ coldstart_counter_S <= coldstart_counter_S+1;
+ else
+ coldstart_S <= '1';
+ end if;
+ end if;
+end process;
+
+
+T_CTRL <= T_CTRL_S;
+T_CTRL_S <=
+ coldstart_S when GEO='1' -- PLL_controlled_by FPGA2
+ else '0' when PLLconfigured_S='0' -- PLL_controlled_by FPGA1 during booting
+ else '1'; -- PLL_controlled_by FPGA2, but reference frequency from FPGA1
+PLLconfigured_S <= '1' when (PLL_booting_S='0') and (resetting_S='0') else '0';
+process(clock_ADCref_S)\r
+begin
+ if rising_edge(clock_ADCref_S) then
+ if GEO='0' then
+ if T_CTRL_S=S_CTRL then
+ if otherFPGAnotconfigured0_S='1' then
+ otherFPGAnotconfigured_S <= '1';
+ end if;
+ otherFPGAnotconfigured0_S <= '1';
+ else
+ otherFPGAnotconfigured0_S <= '0';
+ otherFPGAnotconfigured_S <= '0';
+ end if;
+ else
+ otherFPGAnotconfigured0_S <= '0';
+ otherFPGAnotconfigured_S <= '0';
+ end if;
+ end if;
+end process;
+ \r
+sysclk_buf : IBUFGDS
+ port map ( I => GCLK_P,
+ IB => GCLK_N,
+ O => GCLK_S);
+ST_CLK_buf : IBUFGDS
+ port map ( I => ST_CLK_P,
+ IB => ST_CLK_N,
+ O => ST_CLK_S);\r
+\r
+clockmodule80Ma: clockmodule80M port map(
+ CLK_IN1 => ST_CLK_S,
+ CLK_OUT1 => clock80MHz_PLL1_S,
+ LOCKED => clockPLL1_locked_S);\r
+clockmodule80to80Ma: clockmodule80to80M port map(
+ CLK_IN1 => clock80MHz_PLL1_S,
+ CLK_OUT1 => clock_ADCrefdiv2_S, -- 40MHz
+ CLK_OUT2 => clock_ADCref_S, -- 80MHz
+ CLK_OUT3 => clock100MHz_S,
+ CLK_OUT4 => clock200MHz_S,\r
+ RESET => clockPLL2_reset_S,
+ LOCKED => clockmodule_locked_S);\r
+clockPLL2_reset_S <= '1' when clockPLL1_locked_S='0' else '0';\r
+
+\r
+reset_S <= '1' when (clockmodule_locked_S='0') or (forced_reset_S='1') else '0';\r
+resetprocess: process(clock_ADCref_S,reset_S,GEO)\r
+variable resetFEE_count_V : integer range 0 to 16 := 0;
+begin
+ if reset_S='1' then
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';\r
+ resetting_S <= '1';\r
+ rxLocked_sync_S <= '0';\r
+ GEO_S <= GEO;\r
+ resetFEE_count_V := 0;\r
+ reset_FEE_S <= '1';
+ disable_GTX_reset_S <= '0';\r
+ elsif rising_edge(clock_ADCref_S) then\r
+ rxLocked_sync_S <= rxLocked_S;\r
+ if resetFEE_count_V<16 then\r
+ resetFEE_count_V := resetFEE_count_V+1; \r
+ reset_FEE_S <= '1';\r
+ else\r
+ reset_FEE_S <= '0';\r
+ end if;\r
+ GEO_S <= GEO;\r
+ if GEO_S='0' then -- FPGA1\r
+ if ((PLLfrequencyERROR_S='1') and (selectPLLclk_S='1')) or (otherFPGAnotconfigured_S='1') then -- restart all\r
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';\r
+ resetting_S <= '1';
+ startupready_S <= '0';\r
+ disable_GTX_reset_S <= '0';\r
+ elsif reset_counter_S=1000 then -- start PLL boot
+ reset_counter_S <= reset_counter_S+1;\r
+ boot_PLL_S <= '1';\r
+ timeout_counter_S <= 0;\r
+ elsif reset_counter_S=1002 then -- wait for PLL boot finished\r
+ boot_PLL_S <= '0';\r
+ if PLL_booting_S='1' then\r
+ if timeout_counter_S<65535 then\r
+ timeout_counter_S <= timeout_counter_S+1;\r
+ else\r
+ timeout_counter_S <= 0;\r
+ end if;
+ else\r
+ reset_counter_S <= reset_counter_S+1;
+ timeout_counter_S <= 0;\r
+ end if;\r
+ elsif reset_counter_S=10000 then -- reset GTX\r
+ resetting_S <= '0';\r
+ reset_GTX_S <= '1';\r
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=10001 then -- wait for rx-locked\r
+ resetting_S <= '0';
+ startupready_S <= '0';\r
+ reset_GTX_S <= '0';\r
+ if rxLocked_sync_S='1' then\r
+ reset_counter_S <= reset_counter_S+1;
+ end if;\r
+ elsif reset_counter_S=11000 then -- disable resetting in GTX\r
+ disable_GTX_reset_S <= '1';\r
+ reset_counter_S <= reset_counter_S+1;\r
+ elsif reset_counter_S=11010 then -- switch reference clock\r
+ startupready_S <= '1';\r
+ reset_counter_S <= reset_counter_S+1;\r
+ elsif reset_counter_S=11080 then -- enable resetting in GTX\r
+ disable_GTX_reset_S <= '0';\r
+ reset_counter_S <= reset_counter_S+1;\r
+ else\r
+ if reset_counter_S/=65535 then
+ reset_counter_S <= reset_counter_S+1;\r
+ else -- final state\r
+ resetting_S <= '0';
+ startupready_S <= '1';\r
+ end if;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '0';\r
+ end if;\r
+ else -- GEO=1\r
+ disable_GTX_reset_S <= '0';\r
+ if (S_CTRL0_S='1') or (otherFPGAnotconfigured_S='1') then\r
+ reset_counter_S <= 0;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '1';\r
+ resetting_S <= '1';
+ startupready_S <= '0';\r
+ elsif reset_counter_S=10000 then -- reset GTX
+ resetting_S <= '0';
+ reset_GTX_S <= '1';\r
+ reset_counter_S <= reset_counter_S+1;
+ elsif reset_counter_S=10001 then -- wait for rx-locked\r
+ resetting_S <= '0';
+ startupready_S <= '0';\r
+ reset_GTX_S <= '0';\r
+ if rxLocked_sync_S='1' then\r
+ reset_counter_S <= reset_counter_S+1;
+ end if;\r
+ elsif reset_counter_S=11000 then -- switch reference clock\r
+ startupready_S <= '1';\r
+ reset_counter_S <= reset_counter_S+1;\r
+ else\r
+ if reset_counter_S/=65535 then
+ reset_counter_S <= reset_counter_S+1;\r
+ else\r
+ resetting_S <= '0';
+ startupready_S <= '1';\r
+ end if;
+ boot_PLL_S <= '0';
+ reset_GTX_S <= '0';\r
+ if startupready_S='1' then\r
+ if rxLocked_sync_S='0' then \r
+ end if;\r
+ end if;\r
+ end if;\r
+ end if;
+ S_CTRL0_S <= S_CTRL;
+ end if;
+end process;\r
+\r
+ -- ICAP_VIRTEX6: Internal Configuration Access Port
+ -- Virtex-6
+ -- Xilinx HDL Language Template, version 13.3
+
+-- ICAP_VIRTEX6_inst : ICAP_VIRTEX6
+-- generic map (
+-- DEVICE_ID => X"4244093", -- Specifies the pre-programmed Device ID value
+-- ICAP_WIDTH => "X8", -- Specifies the input and output data width to be used with the
+-- -- ICAP_VIRTEX6.
+-- SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
+-- -- model
+-- )
+-- port map (
+-- BUSY => BUSY, -- 1-bit output: Busy/Ready output
+-- O => O, -- 32-bit output: Configuration data output bus
+-- CLK => CLK, -- 1-bit input: Clock Input
+-- CSB => CSB, -- 1-bit input: Active-Low ICAP input Enable
+-- I => I, -- 32-bit input: Configuration data input bus
+-- RDWRB => RDWRB -- 1-bit input: Read/Write Select input
+-- );
+\r
+resync_pulse1: posedge_to_pulse port map(\r
+ clock_in => ST_CLK_S,\r
+ clock_out => ST_CLK_S, -- clock_ADCref_S,\r
+ en_clk => '1',\r
+ signal_in => phaseSYNC_S,\r
+ pulse => phaseSYNCpulse_S);\r
+\r
+syncpulse_proc: process(ST_CLK_S)
+variable synccount_V : integer range 0 to 15 := 0;\r
+begin
+ if rising_edge(ST_CLK_S) then\r
+ if synccount_V<15 then\r
+ synccount_V := synccount_V+1;\r
+ external_sync_out_S <= '1';\r
+ else\r
+ external_sync_out_S <= '0';\r
+ if (phaseSYNCpulse_S='1') then\r
+ synccount_V := 0;\r
+ end if; \r
+ end if;\r
+ end if;\r
+end process;
+
+ADCresetprocess: process(clock_ADCref_S)
+variable adcreset_counter_V : integer range 0 to 65535 := 0;
+begin
+ if rising_edge(clock_ADCref_S) then
+ if (resetting_S='1') or ((PLL_booting_S='1') and (GEO_S='0')) or (startupready_S='0') or\r
+ (test_resetADC_S='1') or (external_sync_out_S='1') or (external_sync_in_S='1') or\r
+ ((phasecheck_ready1_S='0') and (GEO_S='0')) or\r
+ ((rxLocked_sync_S='0') and (GEO_S='0'))\r
+ then
+ reset_ADCs_S <= '1';
+ AdcIntrfcEna_S <= '0';
+ adcreset_counter_V := 0;\r
+ elsif adcreset_counter_V=65335 then -- wait for lock\r
+ if rxLocked_sync_S='1' then\r
+ adcreset_counter_V := adcreset_counter_V+1;
+ reset_ADCs_S <= '0';
+ end if;\r
+ elsif adcreset_counter_V=65535 then
+ reset_ADCs_S <= '0';
+ AdcIntrfcEna_S <= '1';
+ else
+ adcreset_counter_V := adcreset_counter_V+1;
+ end if;\r
+ if GEO='1' then\r
+ external_sync_in_S <= external_sync_in0_S;
+ else\r
+ external_sync_in_S <= '0';\r
+ end if;\r
+ if (SYNC0_S='0') or (external_sync_in_S='1') or (debug_sync_S='1') then\r
+ SYNC1_S <= '1';\r
+ else\r
+ SYNC1_S <= '0';\r
+ end if;
+ phasecheck_ready1_S <= phasecheck_ready_S;\r
+ end if;
+end process;
+\r
+\r
+--syncbuf1: IOBUFDS\r
+-- generic map (\r
+-- IOSTANDARD => "BLVDS_25"\r
+-- )
+-- port map (
+-- O => external_sync_in0_S, -- Buffer output
+-- IO => INTCOMC1_P, -- Diff_p inout (connect directly to top-level port)
+-- IOB => INTCOMC1_N, -- Diff_n inout (connect directly to top-level port)
+-- I => external_sync_out_S, -- Buffer input
+-- T => GEO -- 3-state enable input, high=input, low=output
+-- );\r
+--\r
+--startsuperburst1: IOBUFDS\r
+-- generic map (\r
+-- IOSTANDARD => "BLVDS_25"\r
+-- )
+-- port map (
+-- O => superburst_start0_S,
+-- IO => INTCOMC2_P,
+-- IOB => INTCOMC2_N,
+-- I => superburst_startout_S,
+-- T => GEO
+-- );\r
+\r
+IOBUF1 : IOBUF port map (
+ O => external_sync_in0_S, -- Buffer output
+ IO => INTCOMC1_P, -- Buffer inout port (connect directly to top-level port)
+ I => external_sync_out_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ );\r
+ \r
+IOBUF2 : IOBUF port map (
+ O => superburst_start0_S, -- Buffer output
+ IO => INTCOMC1_N, -- Buffer inout port (connect directly to top-level port)
+ I => superburst_startout_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ ); \r
+ \r
+IOBUF3 : IOBUF port map (
+ O => DataTaking_enabled_in_S, -- Buffer output
+ IO => INTCOMC2_N, -- Buffer inout port (connect directly to top-level port)
+ I => DataTaking_enabled_out_S, -- Buffer input
+ T => GEO -- 3-state enable input, high=input, low=output
+ ); \r
+\r
+--INTCOMC1_P <= external_sync_out_S when GEO='0' else 'Z';\r
+--external_sync_in0_S <= INTCOMC1_P;\r
+--INTCOMC1_N <= superburst_startout_S when GEO='0' else 'Z';\r
+--superburst_start0_S <= INTCOMC1_N;\r
+--INTCOMC2_N <= DataTaking_enabled_out_S when GEO='0' else 'Z';\r
+--DataTaking_enabled_in_S <= INTCOMC2_N;\r
+\r
+
+process(ADC_clk_S,startupready_S)\r
+variable enable_data_V : std_logic := '0';\r
+variable DataTaking_enabled_V : std_logic := '0';\r
+begin\r
+ if (startupready_S='0') then\r
+ enable_data_V := '0';\r
+ enable_data_S <= '0';
+ elsif (rising_edge(ADC_clk_S)) then\r
+ enable_data_S <= DataTaking_enabled_V;\r
+ DataTaking_enabled_V := DataTaking_enabled_in_S;\r
+ end if;\r
+end process;\r
+\r
+process(ADC_clk_S)\r
+begin\r
+ if (rising_edge(ADC_clk_S)) then\r
+ superburst_start1_S <= superburst_start0_S;\r
+ end if;\r
+end process;\r
+\r
+sync_startofsuperburst: posedge_to_pulse port map(\r
+ clock_in => ADC_clk_S,\r
+ clock_out => ADC_clk_S,\r
+ en_clk => '1',\r
+ signal_in => superburst_start1_S,\r
+ pulse => superburst_start_S);\r
+\r
+INTCOM0_P <= superburst_out_S(0) when GEO='0' else 'Z';\r
+INTCOM0_N <= superburst_out_S(1) when GEO='0' else 'Z';\r
+INTCOM1_P <= superburst_out_S(2) when GEO='0' else 'Z';\r
+INTCOM1_N <= superburst_out_S(3) when GEO='0' else 'Z';\r
+INTCOM2_P <= superburst_out_S(4) when GEO='0' else 'Z';\r
+INTCOM2_N <= superburst_out_S(5) when GEO='0' else 'Z';\r
+INTCOM3_P <= superburst_out_S(6) when GEO='0' else 'Z';\r
+INTCOM3_N <= superburst_out_S(7) when GEO='0' else 'Z';\r
+INTCOM4_P <= superburst_out_S(8) when GEO='0' else 'Z';\r
+INTCOM4_N <= superburst_out_S(9) when GEO='0' else 'Z';\r
+INTCOM5_P <= superburst_out_S(10) when GEO='0' else 'Z';\r
+INTCOM5_N <= superburst_out_S(11) when GEO='0' else 'Z';\r
+INTCOM6_P <= superburst_out_S(12) when GEO='0' else 'Z';\r
+INTCOM6_N <= superburst_out_S(13) when GEO='0' else 'Z';\r
+INTCOM7_P <= superburst_out_S(14) when GEO='0' else 'Z';\r
+INTCOM7_N <= superburst_out_S(15) when GEO='0' else 'Z';\r
+\r
+superburst_in_S(0) <= INTCOM0_P;\r
+superburst_in_S(1) <= INTCOM0_N;\r
+superburst_in_S(2) <= INTCOM1_P;\r
+superburst_in_S(3) <= INTCOM1_N;\r
+superburst_in_S(4) <= INTCOM2_P;\r
+superburst_in_S(5) <= INTCOM2_N;\r
+superburst_in_S(6) <= INTCOM3_P;\r
+superburst_in_S(7) <= INTCOM3_N;\r
+superburst_in_S(8) <= INTCOM4_P;\r
+superburst_in_S(9) <= INTCOM4_N;\r
+superburst_in_S(10) <= INTCOM5_P;\r
+superburst_in_S(11) <= INTCOM5_N;\r
+superburst_in_S(12) <= INTCOM6_P;\r
+superburst_in_S(13) <= INTCOM6_N;\r
+superburst_in_S(14) <= INTCOM7_P;\r
+superburst_in_S(15) <= INTCOM7_N;\r
+superburst_in_S(30 downto 16) <= (others => '0');\r
+ \r
+sync_SYNC_stclk_S: posedge_to_pulse port map(\r
+ clock_in => clock_ADCref_S,\r
+ clock_out => ST_CLK_S,\r
+ en_clk => '1',\r
+ signal_in => SYNC1_S,\r
+ pulse => SYNC2_S);\r
+\r
+SYNC <= not SYNC2_S;\r
+\r
+\r
+process(rxSodaClk40_S)
+begin
+ if (rising_edge(rxSodaClk40_S)) then
+ rxSodaClkdiv4_S <= not rxSodaClkdiv4_S;
+ end if;
+end process;\r
+process(GCLK_S)\r
+begin
+ if (rising_edge(GCLK_S)) then\r
+ if GCLKdiv2_S='1' then
+ GCLKdiv4_S <= not GCLKdiv4_S;\r
+ end if;
+ GCLKdiv2_S <= not GCLKdiv2_S;\r
+ end if;
+end process;\r
+phaseerr_max_S <= 50 when vioword_S(23 downto 16)=x"00" else conv_integer(unsigned(vioword_S(23 downto 16)));\r
+phasedet_S <= '1' when GCLKdiv4_S/=rxSodaClkdiv4_S else '0';\r
+process(ST_CLK_S)\r
+variable waitcounter_V : integer range 0 to 155520 := 0;\r
+begin
+ if (rising_edge(ST_CLK_S)) then
+ if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then\r
+ waitcounter_V := 0;\r
+ phasedet_count_S <= 0;\r
+ phaseerr_count_S <= 0;\r
+ phasecheckcounter_S <= 0;\r
+ phaseSYNC_S <= '0';\r
+ elsif (waitcounter_V<155520) then -- *(1+conv_integer(unsigned(vioword_S(27 downto 24))))) then\r
+ waitcounter_V := waitcounter_V+1;\r
+ phasedet_count_S <= 0;\r
+ phaseerr_count_S <= 0;\r
+ phasecheckcounter_S <= 0;\r
+ phaseSYNC_S <= '0';\r
+ elsif (waitcounter_V=155520) then -- always one syncpulse\r
+ waitcounter_V := waitcounter_V+1;\r
+ phasedet_count_S <= 0;\r
+ phaseerr_count_S <= 0;\r
+ phasecheckcounter_S <= 0;\r
+ phaseSYNC_S <= '1';\r
+ else\r
+ if phasedet_count_S=1023 then\r
+ if phasecheckcounter_S<255 then\r
+ phasecheck_ready_S <= '0';
+ phasecheckcounter_S <= phasecheckcounter_S+1;\r
+ if (phaseerr_count_S>phaseerr_max_S) then\r
+ if vioword_S(5)='0' then\r
+ phaseSYNC_S <= '1';\r
+ waitcounter_V := 0;\r
+ else\r
+ phaseSYNC_S <= '0';\r
+ end if;\r
+ else\r
+ phaseSYNC_S <= '0';\r
+ end if;
+ else
+ phasecheck_ready_S <= '1';\r
+ if (phaseerr_count_S>200) then\r
+-- if (phaseerr_count_S>400) then\r
+ if vioword_S(5)='0' then\r
+ phaseSYNC_S <= '1';\r
+ waitcounter_V := 0;\r
+ else\r
+ phaseSYNC_S <= '0';\r
+ end if;
+ else\r
+ phaseSYNC_S <= '0';\r
+ end if;\r
+ end if;\r
+ phasedet_count_S <= 0;\r
+ if phasedet_S='1' then\r
+ phaseerr_count_S <= 1;\r
+ else\r
+ phaseerr_count_S <= 0;\r
+ end if;\r
+ else\r
+ phaseSYNC_S <= '0';\r
+ phasedet_count_S <= phasedet_count_S+1;\r
+ if phasedet_S='1' then\r
+ phaseerr_count_S <= phaseerr_count_S+1;\r
+ end if;\r
+ end if;\r
+ end if;\r
+ resetting_stclk_S <= resetting_S;
+ selectPLLclk_stclk_S <= selectPLLclk_S;
+ GEO_stclk_S <= GEO;
+ end if;
+end process;\r
+
+
+gclk_div10_process: process(GCLK_S)
+variable counter_V : integer range 0 to 99 := 0;
+begin
+ if (rising_edge(GCLK_S)) then
+ if counter_V<49 then -- 99 for 125MHz
+ counter_V := counter_V+1;
+ else
+ counter_V := 0;
+ GCLKdiv10_S <= not GCLKdiv10_S;
+ end if;
+ end if;
+end process;
+checkfrequency_process: process(ST_CLK_S)
+variable counter_V : integer range 0 to 255 := 0;
+variable first_check_V : integer range 0 to 7 := 0;
+begin
+ if (rising_edge(ST_CLK_S)) then
+ if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
+ PLLfrequencyERROR_S <= '0';
+ first_check_V := 0;
+ else
+ if GCLKdiv10_prev1_S/=GCLKdiv10_prev2_S then
+ if (((counter_V>=122) or (counter_V<=125)) and (ADCCLOCKFREQUENCY=62500000)) or \r
+ (((counter_V>=96) or (counter_V<=99)) and (ADCCLOCKFREQUENCY=80000000)) then \r
+ PLLfrequencyERROR_S <= '0';
+ if first_check_V/=7 then
+ first_check_V := first_check_V+1;\r
+ end if;\r
+ else
+ if first_check_V=7 then
+ PLLfrequencyERROR_S <= '1';\r
+ first_check_V := 0;\r
+ else
+ first_check_V := first_check_V+1;\r
+ end if;
+ end if;
+ counter_V := 0;
+ elsif counter_V<255 then
+ counter_V := counter_V+1;
+ end if;
+ end if;
+ GCLKdiv10_prev2_S <= GCLKdiv10_prev1_S;
+ GCLKdiv10_prev1_S <= GCLKdiv10_S;
+ end if;
+end process;
+\r
+external_PLL: LMK03806 port map(
+ clock => clock_ADCref_S,
+ CLKu => CLKu_S,
+ DATAu => DATAu_S,
+ LEu => LEu_S,
+ RDn => RDu,
+ SYNC => SYNC0_S,
+ boot_PLL => boot_PLL_S,
+ reset_GTX => open, -- reset_GTX_S,
+ reset_ADCs => open, -- reset_ADCs0_S,
+ booting => PLL_booting_S,\r
+ testwordin => vioword2_S(15 downto 0));
+CLKu <= CLKu_S;
+DATAu <= DATAu_S;
+LEu <= LEu_S;\r
+\r
+-- ADC configuration --------------------------------------------------------------\r
+ SCK <= '0'; -- 2-lane 16-bits serialization\r
+ SDI <= '0'; -- normal mode (not sleeping)\r
+ CSA <= (others => '0'); -- 2-lane 16-bits serialization\r
+ CSB <= (others => '0'); -- 2-lane 16-bits serialization\r
+ SDOA <= (others => '0'); -- no internal termination\r
+ SDOB <= (others => '0'); -- no internal termination\r
+\r
+\r
+
+GTX_refclock: IBUFDS_GTXE1 port map(
+ O => gtpClk_S,
+ ODIV2 => open,
+ CEB => '0',
+ I => MGTREFCLK_P,
+ IB => MGTREFCLK_N);
+
+--select_RCV_CLK : BUFGMUX_CTRL port map(
+-- O => RCV_CLK_S,
+-- I0 => clock_ADCref_S,
+-- I1 => rxSodaClk80_S,
+-- S => selectPLLclk_S); ---- rxLocked_S);\r
+--RCV_CLK_S <= clock_ADCref_S; \r
+process (clock_ADCref_S)\r
+begin
+ if (rising_edge(clock_ADCref_S)) then \r
+ if vioword_S(11)='0' then\r
+ if (startupready_S='1') and (rxLocked_S='1') then
+ selectPLLclk_S <= '1';\r
+ else \r
+ selectPLLclk_S <= '0';\r
+ end if;\r
+ else\r
+ selectPLLclk_S <= vioword_S(10); --//\r
+ end if;\r
+ end if;
+end process;\r
+
+--rxRecClk40_BUFG: BUFG port map(
+-- I => rxSodaClk40_S,
+-- O => rxSodaClk40b_S);
+--clockmodule40to80_1: clockmodule40to80 port map(\r
+-- CLK_IN1 => rxSodaClk40b_S,\r
+-- CLK_OUT1 => rxSodaClk80_S,\r
+-- LOCKED => open);\r
+\r
+clockmodule40switch1: clockmodule40switch port map(\r
+ CLK_IN1 => rxSodaClk40_S,\r
+ CLK_IN2 => clock_ADCrefdiv2_S,\r
+ CLK_IN_SEL => selectPLLclk_S,\r
+ CLK_OUT1 => RCV_CLK_S,\r
+ CLK_OUT2 => open,\r
+ RESET => '0',\r
+ LOCKED => clockswitch_locked_S);\r
+\r
+--process (clock_ADCref_S)\r
+--begin
+-- if (rising_edge(clock_ADCref_S)) then
+-- RCV_CLKref_S <= not RCV_CLKref_S;\r
+-- end if;\r
+--end process;\r
+--process (rxSodaClk80_S)\r
+--begin
+-- if (rising_edge(rxSodaClk80_S)) then
+-- RCV_CLKrx_S <= not RCV_CLKrx_S;\r
+-- end if;
+--end process;\r
+--RCV_CLK_S <= RCV_CLKrx_S when selectPLLclk_S='1' else RCV_CLKref_S; \r
+--\r
+--U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
+-- I => RCV_CLK_S,
+-- O => RCV_CLK_P,
+-- OB => RCV_CLK_N);\r
+ \r
+
+RCV_CLK_not_S <= not RCV_CLK_S;
+U1 : FDDRRSE port map(\r
+ Q => RCV_CLK_P_S,
+ C0 => RCV_CLK_S,
+ C1 => RCV_CLK_not_S,
+ CE => '1', -- 1 for fpga1 not GEO, --
+ D0 => '1', -- 1 for fpga1 not GEO, --
+ D1 => '0',
+ R => '0',
+ S => '0');
+U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
+ I => RCV_CLK_P_S,
+ O => RCV_CLK_P,
+ OB => RCV_CLK_N);\r
+ \r
+\r
+\r
+LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
+TX_DIS <= '0'; -- SFP always enabled
+\r
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+ if (rising_edge(ADC_clk_S)) then
+ reset_FEE_ADCclk_S <= reset_FEE_S;
+ ADCs_enable_S <= AdcIntrfcEna_S;\r
+ end if;
+end process;\r
+\r
+FEE_ADCinput_module1: FEE_ADCinput_module port map(
+ clock200MHz => clock200MHz_S,
+ reset => reset_ADCs_S,
+ ADCs_enable => ADCs_enable_S,
+----ADC1---------------------------------------------
+ AD11A_P => AD11A_P,
+ AD11A_N => AD11A_N,
+ AD11B_P => AD11B_P,
+ AD11B_N => AD11B_N,
+ AD12A_P => AD12A_P,
+ AD12A_N => AD12A_N,
+ AD12B_P => AD12B_P,
+ AD12B_N => AD12B_N,
+ AD13A_P => AD13A_P,
+ AD13A_N => AD13A_N,
+ AD13B_P => AD13B_P,
+ AD13B_N => AD13B_N,
+ AD14A_P => AD14A_P,
+ AD14A_N => AD14A_N,
+ AD14B_P => AD14B_P,
+ AD14B_N => AD14B_N,
+ AD15A_P => AD15A_P,
+ AD15A_N => AD15A_N,
+ AD15B_P => AD15B_P,
+ AD15B_N => AD15B_N,
+ AD16A_P => AD16A_P,
+ AD16A_N => AD16A_N,
+ AD16B_P => AD16B_P,
+ AD16B_N => AD16B_N,
+ AD17A_P => AD17A_P,
+ AD17A_N => AD17A_N,
+ AD17B_P => AD17B_P,
+ AD17B_N => AD17B_N,
+ AD18A_P => AD18A_P,
+ AD18A_N => AD18A_N,
+ AD18B_P => AD18B_P,
+ AD18B_N => AD18B_N,
+
+ DCOA1_P => DCOA1_P,
+ DCOA1_N => DCOA1_N,
+ DCOB1_P => DCOB1_P,
+ DCOB1_N => DCOB1_N,
+
+ FRA1_P => FRA1_P ,
+ FRA1_N => FRA1_N ,
+ FRB1_P => FRB1_P ,
+ FRB1_N => FRB1_N ,
+
+ ----ADC2---------------------------------------------
+ AD21A_P => AD21A_P,
+ AD21A_N => AD21A_N,
+ AD21B_P => AD21B_P,
+ AD21B_N => AD21B_N,
+ AD22A_P => AD22A_P,
+ AD22A_N => AD22A_N,
+ AD22B_P => AD22B_P,
+ AD22B_N => AD22B_N,
+ AD23A_P => AD23A_P,
+ AD23A_N => AD23A_N,
+ AD23B_P => AD23B_P,
+ AD23B_N => AD23B_N,
+ AD24A_P => AD24A_P,
+ AD24A_N => AD24A_N,
+ AD24B_P => AD24B_P,
+ AD24B_N => AD24B_N,
+ AD25A_P => AD25A_P,
+ AD25A_N => AD25A_N,
+ AD25B_P => AD25B_P,
+ AD25B_N => AD25B_N,
+ AD26A_P => AD26A_P,
+ AD26A_N => AD26A_N,
+ AD26B_P => AD26B_P,
+ AD26B_N => AD26B_N,
+ AD27A_P => AD27A_P,
+ AD27A_N => AD27A_N,
+ AD27B_P => AD27B_P,
+ AD27B_N => AD27B_N,
+ AD28A_P => AD28A_P,
+ AD28A_N => AD28A_N,
+ AD28B_P => AD28B_P,
+ AD28B_N => AD28B_N,
+
+ DCOA2_P => DCOA2_P,
+ DCOA2_N => DCOA2_N,
+ DCOB2_P => DCOB2_P,
+ DCOB2_N => DCOB2_N,
+
+ FRA2_P => FRA2_P ,
+ FRA2_N => FRA2_N ,
+ FRB2_P => FRB2_P ,
+ FRB2_N => FRB2_N ,
+
+ ----ADC3---------------------------------------------
+ AD31A_P => AD31A_P,
+ AD31A_N => AD31A_N,
+ AD31B_P => AD31B_P,
+ AD31B_N => AD31B_N,
+ AD32A_P => AD32A_P,
+ AD32A_N => AD32A_N,
+ AD32B_P => AD32B_P,
+ AD32B_N => AD32B_N,
+ AD33A_P => AD33A_P,
+ AD33A_N => AD33A_N,
+ AD33B_P => AD33B_P,
+ AD33B_N => AD33B_N,
+ AD34A_P => AD34A_P,
+ AD34A_N => AD34A_N,
+ AD34B_P => AD34B_P,
+ AD34B_N => AD34B_N,
+ AD35A_P => AD35A_P,
+ AD35A_N => AD35A_N,
+ AD35B_P => AD35B_P,
+ AD35B_N => AD35B_N,
+ AD36A_P => AD36A_P,
+ AD36A_N => AD36A_N,
+ AD36B_P => AD36B_P,
+ AD36B_N => AD36B_N,
+ AD37A_P => AD37A_P,
+ AD37A_N => AD37A_N,
+ AD37B_P => AD37B_P,
+ AD37B_N => AD37B_N,
+ AD38A_P => AD38A_P,
+ AD38A_N => AD38A_N,
+ AD38B_P => AD38B_P,
+ AD38B_N => AD38B_N,
+
+ DCOA3_P => DCOA3_P,
+ DCOA3_N => DCOA3_N,
+ DCOB3_P => DCOB3_P,
+ DCOB3_N => DCOB3_N,
+
+ FRA3_P => FRA3_P ,
+ FRA3_N => FRA3_N ,
+ FRB3_P => FRB3_P ,
+ FRB3_N => FRB3_N ,
+
+ ----ADC4---------------------------------------------
+ AD41A_P => AD41A_P,
+ AD41A_N => AD41A_N,
+ AD41B_P => AD41B_P,
+ AD41B_N => AD41B_N,
+ AD42A_P => AD42A_P,
+ AD42A_N => AD42A_N,
+ AD42B_P => AD42B_P,
+ AD42B_N => AD42B_N,
+ AD43A_P => AD43A_P,
+ AD43A_N => AD43A_N,
+ AD43B_P => AD43B_P,
+ AD43B_N => AD43B_N,
+ AD44A_P => AD44A_P,
+ AD44A_N => AD44A_N,
+ AD44B_P => AD44B_P,
+ AD44B_N => AD44B_N,
+ AD45A_P => AD45A_P,
+ AD45A_N => AD45A_N,
+ AD45B_P => AD45B_P,
+ AD45B_N => AD45B_N,
+ AD46A_P => AD46A_P,
+ AD46A_N => AD46A_N,
+ AD46B_P => AD46B_P,
+ AD46B_N => AD46B_N,
+ AD47A_P => AD47A_P,
+ AD47A_N => AD47A_N,
+ AD47B_P => AD47B_P,
+ AD47B_N => AD47B_N,
+ AD48A_P => AD48A_P,
+ AD48A_N => AD48A_N,
+ AD48B_P => AD48B_P,
+ AD48B_N => AD48B_N,
+
+ DCOA4_P => DCOA4_P,
+ DCOA4_N => DCOA4_N,
+ DCOB4_P => DCOB4_P,
+ DCOB4_N => DCOB4_N,
+
+ FRA4_P => FRA4_P ,
+ FRA4_N => FRA4_N ,
+ FRB4_P => FRB4_P ,
+ FRB4_N => FRB4_N ,
+
+ ADC_clk => ADC_clk_S,
+ ADCs_ready => ADCs_ready_S,\r
+ adcdata => adcdata_S
+ );
+\r
+gen_FEE: if DEBUG=false generate\r
+FEE_module1: FEE_adc32_module port map(
+ clock => ADC_clk_S,
+ reset => reset_FEE_ADCclk_S,
+ enable_data => enable_data_S,
+ ADCdata => adcdata_S,
+ superburst_start => superburst_start_S,
+ superburst_received => superburst_in_S,\r
+ onesecondpulse => onesecondpulse_S,
+ rxNotInTable => rxNotInTable_S,
+ startupready => startupready_S,
+ request_init => request_init_S,
+ packet_in_data => packet_in_data_S,
+ packet_in_present => packet_in_present_S,
+ packet_in_read => packet_in_read_S,
+ packet_out_data => packet_out_data_S,
+ packet_out_last => packet_out_last_S,
+ packet_out_write => packet_out_write_S,
+ packet_out_fifofull => packet_out_fifofull_S,\r
+ errorbyte_out => errorbyte_S,\r
+ errorbyte_in => errorbyte_S,\r
+ smaart_in => '0', -- TEMP_OUT,
+ smaart_out => open,\r
+ sysmon_data => sysmon_data_S,\r
+ sysmon_reset => sysmon_reset_S,\r
+ sysmon_address => sysmon_address_S,\r
+ sysmon_read => sysmon_read_S,\r
+ testindex => conv_integer(unsigned(vioword_S(15 downto 12))),\r
+ testword0 => open,
+ testword1 => open,
+ testword2 => open
+ ); -- TEMP_IN);
+end generate;\r
+
+gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
+
+\r
+ FEE_module2: FEE_adc32_module port map(
+ clock => ADC_clk_S,
+ reset => reset_FEE_ADCclk2_S,
+ enable_data => enable_data_S,
+ ADCdata => adcdata2_S,
+ superburst_start => superburst_start_S,
+ superburst_received => superburst_in_S,
+ onesecondpulse => onesecondpulse_S,
+ rxNotInTable => rxNotInTable_S,
+ startupready => startupready_S,
+ request_init => request_init_S,
+ packet_in_data => packet_in_data_S,
+ packet_in_present => packet_in_present_S,
+ packet_in_read => packet_in_read2_S,
+ packet_out_data => packet_out_data2_S,
+ packet_out_last => packet_out_last2_S,
+ packet_out_write => packet_out_write2_S,
+ packet_out_fifofull => packet_out_fifofull_S,\r
+ errorbyte_out => open,\r
+ errorbyte_in => errorbyte_S,\r
+ smaart_in => '0', -- TEMP_OUT,
+ smaart_out => open,\r
+ sysmon_data => sysmon_data_S,\r
+ sysmon_reset => open,\r
+ sysmon_address => open,\r
+ sysmon_read => open,\r
+ testindex => conv_integer(unsigned(vioword_S(15 downto 12))),\r
+ testword0 => open,
+ testword1 => testword0b_S, -- testword0_S,
+ testword2 => open
+ ); -- TEMP_IN);
+\r
+ reset_FEE_ADCclk2_S <= '1' when (reset_FEE_ADCclk_S='1') or (reset_FEE_ADCclk2a_S='1') else '0';\r
+ zero_data_S <= '1' when (vioword_S(9)='1') else '0';\r
+ adcdata2_S <= adcdata_S when zero_data_S='0' else (others => (others => '0'));
+\r
+ process(ADC_clk_S)
+ begin
+ if (rising_edge(ADC_clk_S)) then
+ unequal_S <= '0';\r
+ request_init_S <= '0';
+ if (zero_data_S='1') or (reset_FEE_ADCclk_S='1') or (vioword_S(8)='1') then\r
+ unequal_counter_S <= (others => '0');\r
+ reset_FEE_ADCclk2a_S <= '1';\r
+ unequal_time_S <= (others => '0');\r
+ else
+ if unequal_counter_S(31 downto 0)=x"0000000f" then
+ reset_FEE_ADCclk2a_S <= '0';\r
+ end if;\r
+ if unequal_counter_S=x"000000ff" then
+ request_init_S <= '1';
+ end if;\r
+ if (packet_in_read2_S/=packet_in_read_S) or \r
+ (packet_out_data2_S/=packet_out_data_S) or \r
+ (packet_out_last2_S/=packet_out_last_S) or \r
+ (packet_out_write2_S/=packet_out_write_S) then\r
+ unequal_time_S <= unequal_counter_S;\r
+ unequal_S <= '1';\r
+ end if;\r
+ if unequal_counter_S/=x"ffffffff" then\r
+ unequal_counter_S <= unequal_counter_S+1;\r
+ end if;\r
+ end if;
+ end if;
+ end process;\r
+
+end generate;\r
+\r
+process(ADC_clk_S)\r
+variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
+begin
+ if (rising_edge(ADC_clk_S)) then \r
+ if counter/=0 then\r
+ counter := counter-1;\r
+ onesecondpulse_S <= '0';\r
+ else\r
+ counter := ADCCLOCKFREQUENCY-1;\r
+ onesecondpulse_S <= '1';\r
+ end if;\r
+ end if;\r
+end process;\r
+
+FEE_gtxModule1: FEE_gtxModule port map(
+ gtpClk => gtpClk_S,
+ asyncclk => clock_ADCref_S,\r
+ reset => reset_GTX_S,\r
+ disable_GTX_reset => disable_GTX_reset_S,
+ TX_DLM => TX_DLM_S,
+ TX_DLM_WORD => TX_DLM_WORD_S,
+ RX_DLM => RX_DLM_S,
+ RX_DLM_WORD => RX_DLM_WORD_S,
+ txAsyncClk => ADC_clk_S,
+ txAsyncData => packet_out_data_S,
+ txAsyncDataWrite => packet_out_write_S,
+ txAsyncLastData => packet_out_last_S,
+ txAsyncFifoFull => packet_out_fifofull_S,
+ txUsrClk => txUsrClk_S,\r
+ txLocked => open,
+ rxAsyncClk => ADC_clk_S,
+ rxAsyncData => packet_in_data_S,
+ rxAsyncDataRead => packet_in_read_S,
+ rxNotInTable => rxNotInTable0_S,
+ rxAsyncDataOverflow => open,
+ rxAsyncDataPresent => packet_in_present_S,
+ rxSodaClk => rxSodaClk_S,
+ rxSodaClk40 => rxSodaClk40_S,
+ rxLocked => rxLocked0_S,
+ gtpTxP0 => TX_P,
+ gtpTxN0 => TX_N,
+ gtpRxP0 => RX_P,
+ gtpRxN0 => RX_N,
+ testword0 => testwordb_S -- testword0(35 downto 0)\r
+ );
+\r
+posedge_to_pulse_notintable: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => rxNotInTable0_S,
+ pulse => rxNotInTable_S);\r
+\r
+rxLocked_S <= '1' when ((rxLocked0_S='1') or (disable_GTX_reset_S='1')) and (LOS_S='0') else '0';
+\r
+\r
+datatakingprocess: process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ if DisableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '0';
+ elsif EnableDataTaking_S='1' then
+ DataTaking_enabled_out_S <= '1';
+ end if;
+ end if;
+end process;
+\r
+\r
+process(rxSodaClk_S)\r
+begin\r
+ if (rising_edge(rxSodaClk_S)) then\r
+ reset_rxSodaClk_S <= reset_S;\r
+ end if;\r
+end process;\r
+\r
+ \r
+posedge_to_pulse_superburst_startout: posedge_to_pulse port map(
+ clock_in => rxSodaClk_S,
+ clock_out => ADC_clk_S,
+ en_clk => '1',
+ signal_in => superburst_startout0_S,
+ pulse => superburst_startout_S);\r
+
+soda_FEE_endpoint1: soda_FEE_endpoint port map(
+ SYSCLK => rxSodaClk_S,
+ RESET => reset_rxSodaClk_S,
+ CLEAR => '0',
+ CLK_EN => '1',
+ RX_DLM_WORD_IN => RX_DLM_WORD_S,
+ RX_DLM_IN => RX_DLM_S,
+ TX_DLM_OUT => TX_DLM_S,
+ TX_DLM_WORD_OUT => TX_DLM_WORD_S,
+ START_OF_SUPERBURST => superburst_startout0_S,
+ SUPER_BURST_NR => superburst_out_S,
+ SODA_CMD_VALID => SODA_cmd_valid_S,
+ SODA_CMD_WORD => SODA_cmd_word_S,
+ STAT => open);
+--ResetToZero_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(30)='1') else '0'; -- reset timestamp to I/O pin\r
+EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';\r
+DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';\r
+\r
+SystemMonitorModule1: SystemMonitorModule port map(
+ clock => ADC_clk_S,
+ reset => sysmon_reset_S,
+ address => sysmon_address_S,
+ data_write => '0',
+ data_in => (others => '0'),
+ data_read => sysmon_read_S,
+ data_out => sysmon_data_S,
+ alarms => open,
+ testword0 => open);\r
+\r
+\r
+icon1: icon0 port map(
+ CONTROL0 => control0_S,
+ CONTROL1 => control1_S,
+ CONTROL2 => control2_S,
+ CONTROL3 => control3_S,
+ CONTROL4 => control4_S);
+
+ila36_1: ila36 port map(
+ CONTROL => control0_S,
+ CLK => txUsrClk_S, -- ADC_clk_S, -- ST_CLK_S,
+ TRIG0 => testword1_S); -- testword0_S
+\r
+ila36_2: ila36 port map(
+ CONTROL => control1_S,
+ CLK => rxSodaClk_S, -- clock_ADCref_S, -- ADC_clk_S, ,clock_ADCref_S
+ TRIG0 => testword1_S);\r
+
+ila128_1: ila128 port map(
+ CONTROL => control2_S,
+ CLK => clock_ADCref_S, -- ADC_clk_S,
+ TRIG0 => testword2_S); -- (others => '0')); --
+\r
+vio36_1: vio36 port map (\r
+ CONTROL => control3_S,
+ ASYNC_OUT => vioword_S);\r
+
+vio36_2: vio36 port map (\r
+ CONTROL => control4_S,
+ ASYNC_OUT => vioword2_S);\r
+
+--testword0_S(31 downto 0) <= unequal_time_S;\r
+--testword0_S(32) <= reset_FEE_ADCclk2_S;\r
+--testword0_S(33) <= zero_data_S;\r
+--testword0_S(34) <= unequal_S;\r
+--testword0_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';\r
+\r
+-- testword0_S <= testword0a_S when vioword_S(10)='0' else testword0b_S;\r
+\r
+testclocks_S(0) <= clock_ADCref_S;\r
+testclocks_S(1) <= clock_ADCrefdiv2_S;\r
+testclocks_S(2) <= clock100MHz_S;\r
+testclocks_S(3) <= clock200MHz_S;\r
+testclocks_S(4) <= RCV_CLK_S;\r
+testclocks_S(5) <= GCLK_S;\r
+testclocks_S(6) <= rxSodaClk_S;
+testclocks_S(7) <= rxSodaClk40_S;
+testclocks_S(8) <= ADC_clk_S;\r
+gen_testclocks: for i in 0 to 8 generate\r
+process(testclocks_S(i))
+variable cnt_V : integer range 0 to 99 := 0;
+begin
+ if (rising_edge(testclocks_S(i))) then
+ if cnt_V<99 then
+ cnt_V := cnt_V+1;
+ else
+ cnt_V := 0;
+ testclockDiv100_S(i) <= not testclockDiv100_S(i);
+ end if;
+ end if;
+end process;
+end generate;\r
+--testword0_S(8 downto 0) <= testclockDiv100_S;\r
+--testword0_S(9) <= LOS_S;\r
+--testword0_S(10) <= rxLocked_S;\r
+--testword0_S(11) <= rxLocked0_S;\r
+--testword0_S(12) <= rxLocked_sync_S;\r
+--testword0_S(13) <= selectPLLclk_S;\r
+--testword0_S(14) <= rxLocked_S;\r
+--testword0_S(23 downto 16) <= RX_DLM_WORD_S;\r
+--testword0_S(24) <= RX_DLM_S;\r
+--testword0_S(32 downto 25) <= TX_DLM_WORD_S;\r
+--testword0_S(33) <= TX_DLM_S;\r
+--testword0_S(34) <= superburst_startout_S;\r
+--testword0_S(35) <= SODA_cmd_valid_S;\r
+\r
+testword0_S(15 downto 0) <= superburst_out_S(15 downto 0);\r
+testword0_S(31 downto 16) <= superburst_in_S(15 downto 0);
+testword0_S(32) <= superburst_startout_S;\r
+testword0_S(33) <= superburst_start0_S;\r
+testword0_S(34) <= superburst_start1_S;\r
+testword0_S(35) <= superburst_start_S;\r
+\r
+\r
+--testword2_S(31 downto 0) <= unequal_time_S;\r
+--testword2_S(32) <= reset_FEE_ADCclk2_S;\r
+--testword2_S(33) <= zero_data_S;\r
+--testword2_S(34) <= unequal_S;\r
+--testword2_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';\r
+--testword2_S(67 downto 36) <= packet_out_data_S;\r
+--testword2_S(68) <= packet_out_write_S;\r
+--testword2_S(69) <= packet_out_last_S;\r
+--testword2_S(70) <= packet_out_fifofull_S;\r
+--testword2_S(71) <= '0';\r
+--testword2_S(103 downto 72) <= packet_out_data2_S;\r
+--testword2_S(104) <= packet_out_write2_S;\r
+--testword2_S(105) <= packet_out_last2_S;\r
+--testword2_S(106) <= packet_out_fifofull_S;\r
+--testword2_S(107) <= '0';\r
+\r
+testword1_S(30 downto 0) <= testwordb_S(30 downto 0); \r
+testword1_S(31) <= errorbyte_S(0); \r
+testword1_S(32) <= errorbyte_S(1); \r
+testword1_S(33) <= errorbyte_S(2); \r
+testword1_S(34) <= errorbyte_S(4); \r
+testword1_S(35) <= errorbyte_S(6); \r
+\r
+testword2_S(0) <= rxLocked_sync_S; -- coldstart_S;\r
+testword2_S(1) <= reset_S;\r
+testword2_S(2) <= resetting_S;\r
+testword2_S(3) <= reset_GTX_S; -- IcontrolPLL_S;\r
+testword2_S(4) <= reset_ADCs_S; -- otherFPGAnotconfigured0_S;\r
+testword2_S(5) <= otherFPGAnotconfigured_S;\r
+testword2_S(6) <= PLLconfigured_S;\r
+testword2_S(7) <= selectPLLclk_S;\r
+testword2_S(8) <= startupready_S; -- T_CTRL_S;\r
+testword2_S(9) <= external_sync_in_S; \r
+testword2_S(10) <= rxLocked_S;\r
+testword2_S(11) <= S_CTRL0_S;\r
+testword2_S(12) <= boot_PLL_S;\r
+testword2_S(13) <= PLL_booting_S;\r
+testword2_S(14) <= adcintrfcena_s;\r
+testword2_S(15) <= phasecheck_ready1_S;\r
+testword2_S(16) <= GCLKdiv4_S; --reset_GTX_S;\r
+testword2_S(17) <= rxSodaClkdiv4_S; --ADCs_ready_S;\r
+testword2_S(18) <= '1' when phasedet_count_S=1023 else '0'; --GEO;\r
+testword2_S(19) <= '1' when phasecheckcounter_S<255 else '0'; -- PLLfrequencyERROR_S;\r
+testword2_S(20) <= SYNC_S;\r
+testword2_S(21) <= PLLfrequencyERROR_S;\r
+testword2_S(22) <= phasedet_S;\r
+testword2_S(23) <= phaseSYNC_S;\r
+testword2_S(24) <= clockswitch_locked_S;\r
+testword2_S(25) <= phaseSYNCpulse_S;\r
+testword2_S(35 downto 26) <= conv_std_logic_vector(phaseerr_count_S,10);
+\r
+selectnr_S <= conv_integer(vioword_S(35 downto 34));\r
+
+generatetest1 : for index in 0 to 7 generate
+-- testword2_S(index*16+13 downto index*16+0) <= adcdata_S(selectnr_S*8+index)(13 downto 0);
+-- testword2_S(index*16+15 downto index*16+14) <= (others => '0');
+end generate;
+
+forced_reset_S <= vioword_S(0);
+\r
+process(clock_ADCref_S)
+variable prev_vioword2 : std_logic := '0';
+variable prev_vioword3 : std_logic := '0';
+begin
+ if (rising_edge(clock_ADCref_S)) then
+ if prev_vioword2 /= vioword_S(2) then
+ test_resetADC_S <= '1';
+ else
+ test_resetADC_S <= '0';
+ end if;
+ prev_vioword2 := vioword_S(2);
+ if prev_vioword3 /= vioword_S(3) then
+ debug_sync_S <= '1';
+ else
+ debug_sync_S <= '0';
+ end if;
+ prev_vioword3 := vioword_S(3);
+ end if;
+end process;\r
+\r
+process(ST_CLK_S)
+begin
+ if (rising_edge(ST_CLK_S)) then
+ testclockDiv2_S(0) <= not testclockDiv2_S(0);
+ end if;
+end process;\r
+process(clock_ADCref_S)
+begin
+ if (rising_edge(clock_ADCref_S)) then
+ testclockDiv2_S(1) <= not testclockDiv2_S(1);
+ end if;
+end process;\r
+process(clock_ADCrefdiv2_S)
+begin
+ if (rising_edge(clock_ADCrefdiv2_S)) then
+ testclockDiv2_S(2) <= not testclockDiv2_S(2);
+ end if;
+end process;\r
+process(RCV_CLK_S)
+begin
+ if (rising_edge(RCV_CLK_S)) then
+ testclockDiv2_S(3) <= not testclockDiv2_S(3);
+ end if;
+end process;
+process(GCLK_S)
+begin
+ if (rising_edge(GCLK_S)) then
+ testclockDiv2_S(4) <= not testclockDiv2_S(4);
+ end if;
+end process;\r
+process(rxSodaClk_S)
+begin
+ if (rising_edge(rxSodaClk_S)) then
+ testclockDiv2_S(5) <= not testclockDiv2_S(5);
+ end if;
+end process;
+process(txUsrClk_S)
+begin
+ if (rising_edge(txUsrClk_S)) then
+ testclockDiv2_S(6) <= not testclockDiv2_S(6);
+ end if;
+end process;\r
+process(ADC_clk_S)
+begin
+ if (rising_edge(ADC_clk_S)) then
+ testclockDiv2_S(7) <= not testclockDiv2_S(7);
+ end if;
+end process;\r
+
+
+SM1_P <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
+SM1_N <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));\r
+
+--SM3_P <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
+--SM3_N <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));\r
+\r
+\r
+end Behavioral;
+
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 FEE_clockbuf80MHz
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_clockbuf80MHz.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="FEE_clockbuf80MHz.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="FEE_clockbuf80MHz.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1411996303" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411996303">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2931233228134520341" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3005896570206739925" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9209316580054018149" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+# file: FEE_clockbuf80MHz.ucf\r
+# \r
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+# \r
+# This file contains confidential and proprietary information\r
+# of Xilinx, Inc. and is protected under U.S. and\r
+# international copyright and other intellectual property\r
+# laws.\r
+# \r
+# DISCLAIMER\r
+# This disclaimer is not a license and does not grant any\r
+# rights to the materials distributed herewith. Except as\r
+# otherwise provided in a valid license issued to you by\r
+# Xilinx, and to the maximum extent permitted by applicable\r
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+# (2) Xilinx shall not be liable (whether in contract or tort,\r
+# including negligence, or under any other theory of\r
+# liability) for any loss or damage of any kind or nature\r
+# related to, arising under or in connection with these\r
+# materials, including for any direct, or any indirect,\r
+# special, incidental, or consequential loss or damage\r
+# (including loss of data, profits, goodwill, or any type of\r
+# loss or damage suffered as a result of any action brought\r
+# by a third party) even if such damage or loss was\r
+# reasonably foreseeable or Xilinx had been advised of the\r
+# possibility of the same.\r
+# \r
+# CRITICAL APPLICATIONS\r
+# Xilinx products are not designed or intended to be fail-\r
+# safe, or for use in any application requiring fail-safe\r
+# performance, such as life-support or safety devices or\r
+# systems, Class III medical devices, nuclear facilities,\r
+# applications related to the deployment of airbags, or any\r
+# other applications that could lead to death, personal\r
+# injury, or severe property or environmental damage\r
+# (individually and collectively, "Critical\r
+# Applications"). Customer assumes the sole risk and\r
+# liability of any use of Xilinx products in Critical\r
+# Applications, subject only to applicable laws and\r
+# regulations governing limitations on product liability.\r
+# \r
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+# PART OF THIS FILE AT ALL TIMES.\r
+# \r
+\r
+# Input clock periods. These duplicate the values entered for the\r
+# input clocks. You can use these to time your system\r
+#----------------------------------------------------------------\r
+NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 12.500 ns HIGH 50% INPUT_JITTER 125.0ps;\r
+\r
+\r
+# FALSE PATH constraints \r
+\r
--- /dev/null
+-- file: FEE_clockbuf80MHz.vhd\r
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____80.000______0.000______50.0______147.966____103.963\r
+-- CLK_OUT2____80.000____180.000______50.0______147.966____103.963\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary______________80____________0.010\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.numeric_std.all;\r
+\r
+library unisim;\r
+use unisim.vcomponents.all;\r
+\r
+entity FEE_clockbuf80MHz is\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic\r
+ );\r
+end FEE_clockbuf80MHz;\r
+\r
+architecture xilinx of FEE_clockbuf80MHz is\r
+ attribute CORE_GENERATION_INFO : string;\r
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "FEE_clockbuf80MHz,clk_wiz_v3_6,{component_name=FEE_clockbuf80MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=12.500,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
+ -- Input clock buffering / unused connectors\r
+ signal clkin1 : std_logic;\r
+ -- Output clock buffering / unused connectors\r
+ signal clkfbout : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+ signal clkfboutb_unused : std_logic;\r
+ signal clkout0 : std_logic;\r
+ signal clkout0b_unused : std_logic;\r
+ signal clkout1 : std_logic;\r
+ signal clkout1b_unused : std_logic;\r
+ signal clkout2_unused : std_logic;\r
+ signal clkout2b_unused : std_logic;\r
+ signal clkout3_unused : std_logic;\r
+ signal clkout3b_unused : std_logic;\r
+ signal clkout4_unused : std_logic;\r
+ signal clkout5_unused : std_logic;\r
+ signal clkout6_unused : std_logic;\r
+ -- Dynamic programming unused signals\r
+ signal do_unused : std_logic_vector(15 downto 0);\r
+ signal drdy_unused : std_logic;\r
+ -- Dynamic phase shift unused signals\r
+ signal psdone_unused : std_logic;\r
+ -- Unused status signals\r
+ signal locked_unused : std_logic;\r
+ signal clkfbstopped_unused : std_logic;\r
+ signal clkinstopped_unused : std_logic;\r
+begin\r
+\r
+\r
+ -- Input buffering\r
+ --------------------------------------\r
+ clkin1 <= CLK_IN1;\r
+\r
+\r
+ -- Clocking primitive\r
+ --------------------------------------\r
+ -- Instantiation of the MMCM primitive\r
+ -- * Unused inputs are tied off\r
+ -- * Unused outputs are labeled unused\r
+ mmcm_adv_inst : MMCM_ADV\r
+ generic map\r
+ (BANDWIDTH => "OPTIMIZED",\r
+ CLKOUT4_CASCADE => FALSE,\r
+ CLOCK_HOLD => FALSE,\r
+ COMPENSATION => "ZHOLD",\r
+ STARTUP_WAIT => FALSE,\r
+ DIVCLK_DIVIDE => 1,\r
+ CLKFBOUT_MULT_F => 12.000,\r
+ CLKFBOUT_PHASE => 0.000,\r
+ CLKFBOUT_USE_FINE_PS => FALSE,\r
+ CLKOUT0_DIVIDE_F => 12.000,\r
+ CLKOUT0_PHASE => 0.000,\r
+ CLKOUT0_DUTY_CYCLE => 0.500,\r
+ CLKOUT0_USE_FINE_PS => FALSE,\r
+ CLKOUT1_DIVIDE => 12,\r
+ CLKOUT1_PHASE => 180.000,\r
+ CLKOUT1_DUTY_CYCLE => 0.500,\r
+ CLKOUT1_USE_FINE_PS => FALSE,\r
+ CLKIN1_PERIOD => 12.500,\r
+ REF_JITTER1 => 0.010)\r
+ port map\r
+ -- Output clocks\r
+ (CLKFBOUT => clkfbout,\r
+ CLKFBOUTB => clkfboutb_unused,\r
+ CLKOUT0 => clkout0,\r
+ CLKOUT0B => clkout0b_unused,\r
+ CLKOUT1 => clkout1,\r
+ CLKOUT1B => clkout1b_unused,\r
+ CLKOUT2 => clkout2_unused,\r
+ CLKOUT2B => clkout2b_unused,\r
+ CLKOUT3 => clkout3_unused,\r
+ CLKOUT3B => clkout3b_unused,\r
+ CLKOUT4 => clkout4_unused,\r
+ CLKOUT5 => clkout5_unused,\r
+ CLKOUT6 => clkout6_unused,\r
+ -- Input clock control\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKIN1 => clkin1,\r
+ CLKIN2 => '0',\r
+ -- Tied to always select the primary input clock\r
+ CLKINSEL => '1',\r
+ -- Ports for dynamic reconfiguration\r
+ DADDR => (others => '0'),\r
+ DCLK => '0',\r
+ DEN => '0',\r
+ DI => (others => '0'),\r
+ DO => do_unused,\r
+ DRDY => drdy_unused,\r
+ DWE => '0',\r
+ -- Ports for dynamic phase shift\r
+ PSCLK => '0',\r
+ PSEN => '0',\r
+ PSINCDEC => '0',\r
+ PSDONE => psdone_unused,\r
+ -- Other control and status signals\r
+ LOCKED => locked_unused,\r
+ CLKINSTOPPED => clkinstopped_unused,\r
+ CLKFBSTOPPED => clkfbstopped_unused,\r
+ PWRDWN => '0',\r
+ RST => '0');\r
+\r
+ -- Output buffering\r
+ -------------------------------------\r
+ clkf_buf : BUFG\r
+ port map\r
+ (O => clkfbout_buf,\r
+ I => clkfbout);\r
+\r
+\r
+ clkout1_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT1,\r
+ I => clkout0);\r
+\r
+\r
+\r
+ clkout2_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT2,\r
+ I => clkout1);\r
+\r
+end xilinx;\r
--- /dev/null
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____80.000______0.000______50.0______147.966____103.963\r
+-- CLK_OUT2____80.000____180.000______50.0______147.966____103.963\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary______________80____________0.010\r
+\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component FEE_clockbuf80MHz\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic\r
+ );\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : FEE_clockbuf80MHz\r
+ port map\r
+ (-- Clock in ports\r
+ CLK_IN1 => CLK_IN1,\r
+ -- Clock out ports\r
+ CLK_OUT1 => CLK_OUT1,\r
+ CLK_OUT2 => CLK_OUT2);\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Thu Sep 25 14:23:17 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
+# END Select\r
+# BEGIN Parameters\r
+CSET calc_done=DONE\r
+CSET clk_in_sel_port=CLK_IN_SEL\r
+CSET clk_out1_port=CLK_OUT1\r
+CSET clk_out1_use_fine_ps_gui=false\r
+CSET clk_out2_port=CLK_OUT2\r
+CSET clk_out2_use_fine_ps_gui=false\r
+CSET clk_out3_port=CLK_OUT3\r
+CSET clk_out3_use_fine_ps_gui=false\r
+CSET clk_out4_port=CLK_OUT4\r
+CSET clk_out4_use_fine_ps_gui=false\r
+CSET clk_out5_port=CLK_OUT5\r
+CSET clk_out5_use_fine_ps_gui=false\r
+CSET clk_out6_port=CLK_OUT6\r
+CSET clk_out6_use_fine_ps_gui=false\r
+CSET clk_out7_port=CLK_OUT7\r
+CSET clk_out7_use_fine_ps_gui=false\r
+CSET clk_valid_port=CLK_VALID\r
+CSET clkfb_in_n_port=CLKFB_IN_N\r
+CSET clkfb_in_p_port=CLKFB_IN_P\r
+CSET clkfb_in_port=CLKFB_IN\r
+CSET clkfb_in_signaling=SINGLE\r
+CSET clkfb_out_n_port=CLKFB_OUT_N\r
+CSET clkfb_out_p_port=CLKFB_OUT_P\r
+CSET clkfb_out_port=CLKFB_OUT\r
+CSET clkfb_stopped_port=CLKFB_STOPPED\r
+CSET clkin1_jitter_ps=125.0\r
+CSET clkin1_ui_jitter=0.010\r
+CSET clkin2_jitter_ps=100.0\r
+CSET clkin2_ui_jitter=0.010\r
+CSET clkout1_drives=BUFG\r
+CSET clkout1_requested_duty_cycle=50.000\r
+CSET clkout1_requested_out_freq=80\r
+CSET clkout1_requested_phase=0.000\r
+CSET clkout2_drives=BUFG\r
+CSET clkout2_requested_duty_cycle=50.000\r
+CSET clkout2_requested_out_freq=80\r
+CSET clkout2_requested_phase=180\r
+CSET clkout2_used=true\r
+CSET clkout3_drives=BUFG\r
+CSET clkout3_requested_duty_cycle=50.000\r
+CSET clkout3_requested_out_freq=80\r
+CSET clkout3_requested_phase=0.000\r
+CSET clkout3_used=false\r
+CSET clkout4_drives=BUFG\r
+CSET clkout4_requested_duty_cycle=50.000\r
+CSET clkout4_requested_out_freq=80\r
+CSET clkout4_requested_phase=0.000\r
+CSET clkout4_used=false\r
+CSET clkout5_drives=BUFG\r
+CSET clkout5_requested_duty_cycle=50.000\r
+CSET clkout5_requested_out_freq=80\r
+CSET clkout5_requested_phase=0.000\r
+CSET clkout5_used=false\r
+CSET clkout6_drives=BUFG\r
+CSET clkout6_requested_duty_cycle=50.000\r
+CSET clkout6_requested_out_freq=80\r
+CSET clkout6_requested_phase=0.000\r
+CSET clkout6_used=false\r
+CSET clkout7_drives=BUFG\r
+CSET clkout7_requested_duty_cycle=50.000\r
+CSET clkout7_requested_out_freq=80\r
+CSET clkout7_requested_phase=0.000\r
+CSET clkout7_used=false\r
+CSET clock_mgr_type=MANUAL\r
+CSET component_name=FEE_clockbuf80MHz\r
+CSET daddr_port=DADDR\r
+CSET dclk_port=DCLK\r
+CSET dcm_clk_feedback=1X\r
+CSET dcm_clk_out1_port=CLK0\r
+CSET dcm_clk_out2_port=CLK0\r
+CSET dcm_clk_out3_port=CLK0\r
+CSET dcm_clk_out4_port=CLK0\r
+CSET dcm_clk_out5_port=CLK0\r
+CSET dcm_clk_out6_port=CLK0\r
+CSET dcm_clkdv_divide=2.0\r
+CSET dcm_clkfx_divide=1\r
+CSET dcm_clkfx_multiply=4\r
+CSET dcm_clkgen_clk_out1_port=CLKFX\r
+CSET dcm_clkgen_clk_out2_port=CLKFX\r
+CSET dcm_clkgen_clk_out3_port=CLKFX\r
+CSET dcm_clkgen_clkfx_divide=1\r
+CSET dcm_clkgen_clkfx_md_max=0.000\r
+CSET dcm_clkgen_clkfx_multiply=4\r
+CSET dcm_clkgen_clkfxdv_divide=2\r
+CSET dcm_clkgen_clkin_period=10.000\r
+CSET dcm_clkgen_notes=None\r
+CSET dcm_clkgen_spread_spectrum=NONE\r
+CSET dcm_clkgen_startup_wait=false\r
+CSET dcm_clkin_divide_by_2=false\r
+CSET dcm_clkin_period=10.000\r
+CSET dcm_clkout_phase_shift=NONE\r
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
+CSET dcm_notes=None\r
+CSET dcm_phase_shift=0\r
+CSET dcm_pll_cascade=NONE\r
+CSET dcm_startup_wait=false\r
+CSET den_port=DEN\r
+CSET din_port=DIN\r
+CSET dout_port=DOUT\r
+CSET drdy_port=DRDY\r
+CSET dwe_port=DWE\r
+CSET feedback_source=FDBK_AUTO\r
+CSET in_freq_units=Units_MHz\r
+CSET in_jitter_units=Units_UI\r
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
+CSET jitter_options=UI\r
+CSET jitter_sel=No_Jitter\r
+CSET locked_port=LOCKED\r
+CSET mmcm_bandwidth=OPTIMIZED\r
+CSET mmcm_clkfbout_mult_f=12.000\r
+CSET mmcm_clkfbout_phase=0.000\r
+CSET mmcm_clkfbout_use_fine_ps=false\r
+CSET mmcm_clkin1_period=12.500\r
+CSET mmcm_clkin2_period=10.000\r
+CSET mmcm_clkout0_divide_f=12.000\r
+CSET mmcm_clkout0_duty_cycle=0.500\r
+CSET mmcm_clkout0_phase=0.000\r
+CSET mmcm_clkout0_use_fine_ps=false\r
+CSET mmcm_clkout1_divide=12\r
+CSET mmcm_clkout1_duty_cycle=0.500\r
+CSET mmcm_clkout1_phase=180.000\r
+CSET mmcm_clkout1_use_fine_ps=false\r
+CSET mmcm_clkout2_divide=1\r
+CSET mmcm_clkout2_duty_cycle=0.500\r
+CSET mmcm_clkout2_phase=0.000\r
+CSET mmcm_clkout2_use_fine_ps=false\r
+CSET mmcm_clkout3_divide=1\r
+CSET mmcm_clkout3_duty_cycle=0.500\r
+CSET mmcm_clkout3_phase=0.000\r
+CSET mmcm_clkout3_use_fine_ps=false\r
+CSET mmcm_clkout4_cascade=false\r
+CSET mmcm_clkout4_divide=1\r
+CSET mmcm_clkout4_duty_cycle=0.500\r
+CSET mmcm_clkout4_phase=0.000\r
+CSET mmcm_clkout4_use_fine_ps=false\r
+CSET mmcm_clkout5_divide=1\r
+CSET mmcm_clkout5_duty_cycle=0.500\r
+CSET mmcm_clkout5_phase=0.000\r
+CSET mmcm_clkout5_use_fine_ps=false\r
+CSET mmcm_clkout6_divide=1\r
+CSET mmcm_clkout6_duty_cycle=0.500\r
+CSET mmcm_clkout6_phase=0.000\r
+CSET mmcm_clkout6_use_fine_ps=false\r
+CSET mmcm_clock_hold=false\r
+CSET mmcm_compensation=ZHOLD\r
+CSET mmcm_divclk_divide=1\r
+CSET mmcm_notes=None\r
+CSET mmcm_ref_jitter1=0.010\r
+CSET mmcm_ref_jitter2=0.010\r
+CSET mmcm_startup_wait=false\r
+CSET num_out_clks=2\r
+CSET override_dcm=false\r
+CSET override_dcm_clkgen=false\r
+CSET override_mmcm=false\r
+CSET override_pll=false\r
+CSET platform=nt64\r
+CSET pll_bandwidth=OPTIMIZED\r
+CSET pll_clk_feedback=CLKFBOUT\r
+CSET pll_clkfbout_mult=4\r
+CSET pll_clkfbout_phase=0.000\r
+CSET pll_clkin_period=10.000\r
+CSET pll_clkout0_divide=1\r
+CSET pll_clkout0_duty_cycle=0.500\r
+CSET pll_clkout0_phase=0.000\r
+CSET pll_clkout1_divide=1\r
+CSET pll_clkout1_duty_cycle=0.500\r
+CSET pll_clkout1_phase=0.000\r
+CSET pll_clkout2_divide=1\r
+CSET pll_clkout2_duty_cycle=0.500\r
+CSET pll_clkout2_phase=0.000\r
+CSET pll_clkout3_divide=1\r
+CSET pll_clkout3_duty_cycle=0.500\r
+CSET pll_clkout3_phase=0.000\r
+CSET pll_clkout4_divide=1\r
+CSET pll_clkout4_duty_cycle=0.500\r
+CSET pll_clkout4_phase=0.000\r
+CSET pll_clkout5_divide=1\r
+CSET pll_clkout5_duty_cycle=0.500\r
+CSET pll_clkout5_phase=0.000\r
+CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
+CSET pll_divclk_divide=1\r
+CSET pll_notes=None\r
+CSET pll_ref_jitter=0.010\r
+CSET power_down_port=POWER_DOWN\r
+CSET prim_in_freq=80\r
+CSET prim_in_jitter=0.010\r
+CSET prim_source=No_buffer\r
+CSET primary_port=CLK_IN1\r
+CSET primitive=MMCM\r
+CSET primtype_sel=MMCM_ADV\r
+CSET psclk_port=PSCLK\r
+CSET psdone_port=PSDONE\r
+CSET psen_port=PSEN\r
+CSET psincdec_port=PSINCDEC\r
+CSET relative_inclk=REL_PRIMARY\r
+CSET reset_port=RESET\r
+CSET secondary_in_freq=100.000\r
+CSET secondary_in_jitter=0.010\r
+CSET secondary_port=CLK_IN2\r
+CSET secondary_source=Single_ended_clock_capable_pin\r
+CSET ss_mod_freq=250\r
+CSET ss_mode=CENTER_HIGH\r
+CSET status_port=STATUS\r
+CSET summary_strings=empty\r
+CSET use_clk_valid=false\r
+CSET use_clkfb_stopped=false\r
+CSET use_dyn_phase_shift=false\r
+CSET use_dyn_reconfig=false\r
+CSET use_freeze=false\r
+CSET use_freq_synth=false\r
+CSET use_inclk_stopped=false\r
+CSET use_inclk_switchover=false\r
+CSET use_locked=false\r
+CSET use_max_i_jitter=false\r
+CSET use_min_o_jitter=false\r
+CSET use_min_power=false\r
+CSET use_phase_alignment=true\r
+CSET use_power_down=false\r
+CSET use_reset=false\r
+CSET use_spread_spectrum=false\r
+CSET use_spread_spectrum_1=false\r
+CSET use_status=false\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-05-10T12:44:55Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: f339ac6c\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="FEE_clockbuf80MHz.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="FEE_clockbuf80MHz.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FEE_clockbuf80MHz|xilinx" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="FEE_clockbuf80MHz.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FEE_clockbuf80MHz" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="FEE_clockbuf80MHz" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-25T16:23:42" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A92535ED933448509FBB6E5ADC9D6C4B" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/FEE_clockbuf80MHz" xil_pn:name="FEE_clockbuf80MHz.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 SystemMonitorVirtex
+RECTANGLE Normal 32 32 640 1504
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName di_in[15:0]
+PINATTR Polarity IN
+LINE Wide 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName daddr_in[6:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName den_in
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName dwe_in
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName dclk_in
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName reset_in
+PINATTR Polarity IN
+LINE Normal 0 400 32 400
+PIN 0 400 LEFT 36
+PINATTR PinName vp_in
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName vn_in
+PINATTR Polarity IN
+LINE Wide 672 80 640 80
+PIN 672 80 RIGHT 36
+PINATTR PinName do_out[15:0]
+PINATTR Polarity OUT
+LINE Normal 672 112 640 112
+PIN 672 112 RIGHT 36
+PINATTR PinName drdy_out
+PINATTR Polarity OUT
+LINE Normal 672 176 640 176
+PIN 672 176 RIGHT 36
+PINATTR PinName user_temp_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 208 640 208
+PIN 672 208 RIGHT 36
+PINATTR PinName vccint_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 240 640 240
+PIN 672 240 RIGHT 36
+PINATTR PinName vccaux_alarm_out
+PINATTR Polarity OUT
+LINE Normal 672 272 640 272
+PIN 672 272 RIGHT 36
+PINATTR PinName ot_out
+PINATTR Polarity OUT
+LINE Wide 672 336 640 336
+PIN 672 336 RIGHT 36
+PINATTR PinName channel_out[4:0]
+PINATTR Polarity OUT
+LINE Normal 672 368 640 368
+PIN 672 368 RIGHT 36
+PINATTR PinName eoc_out
+PINATTR Polarity OUT
+LINE Normal 672 400 640 400
+PIN 672 400 RIGHT 36
+PINATTR PinName eos_out
+PINATTR Polarity OUT
+LINE Normal 672 432 640 432
+PIN 672 432 RIGHT 36
+PINATTR PinName busy_out
+PINATTR Polarity OUT
+LINE Normal 672 464 640 464
+PIN 672 464 RIGHT 36
+PINATTR PinName jtaglocked_out
+PINATTR Polarity OUT
+LINE Normal 672 496 640 496
+PIN 672 496 RIGHT 36
+PINATTR PinName jtagmodified_out
+PINATTR Polarity OUT
+LINE Normal 672 528 640 528
+PIN 672 528 RIGHT 36
+PINATTR PinName jtagbusy_out
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="SystemMonitorVirtex.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="SystemMonitorVirtex.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="SystemMonitorVirtex.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="SystemMonitorVirtex.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1381060267" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381060267">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3728760624764540981" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="851620736073740107" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3180520481145995643" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+-- file: SystemMonitorVirtex.vhd\r
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+Library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity SystemMonitorVirtex is\r
+ port (\r
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
+ VN_IN : in STD_LOGIC\r
+);\r
+end SystemMonitorVirtex;\r
+\r
+architecture xilinx of SystemMonitorVirtex is\r
+\r
+ attribute X_CORE_INFO : string;\r
+ attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";\r
+\r
+ signal aux_channel_p : std_logic_vector (15 downto 0);\r
+ signal aux_channel_n : std_logic_vector (15 downto 0);\r
+\r
+begin\r
+\r
+ aux_channel_p(0) <= '0';\r
+ aux_channel_n(0) <= '0';\r
+\r
+ aux_channel_p(1) <= '0';\r
+ aux_channel_n(1) <= '0';\r
+\r
+ aux_channel_p(2) <= '0';\r
+ aux_channel_n(2) <= '0';\r
+\r
+ aux_channel_p(3) <= '0';\r
+ aux_channel_n(3) <= '0';\r
+\r
+ aux_channel_p(4) <= '0';\r
+ aux_channel_n(4) <= '0';\r
+\r
+ aux_channel_p(5) <= '0';\r
+ aux_channel_n(5) <= '0';\r
+\r
+ aux_channel_p(6) <= '0';\r
+ aux_channel_n(6) <= '0';\r
+\r
+ aux_channel_p(7) <= '0';\r
+ aux_channel_n(7) <= '0';\r
+\r
+ aux_channel_p(8) <= '0';\r
+ aux_channel_n(8) <= '0';\r
+\r
+ aux_channel_p(9) <= '0';\r
+ aux_channel_n(9) <= '0';\r
+\r
+ aux_channel_p(10) <= '0';\r
+ aux_channel_n(10) <= '0';\r
+\r
+ aux_channel_p(11) <= '0';\r
+ aux_channel_n(11) <= '0';\r
+\r
+ aux_channel_p(12) <= '0';\r
+ aux_channel_n(12) <= '0';\r
+\r
+ aux_channel_p(13) <= '0';\r
+ aux_channel_n(13) <= '0';\r
+\r
+ aux_channel_p(14) <= '0';\r
+ aux_channel_n(14) <= '0';\r
+\r
+ aux_channel_p(15) <= '0';\r
+ aux_channel_n(15) <= '0';\r
+\r
+\r
+ SYSMON_INST : SYSMON\r
+ generic map(\r
+ INIT_40 => X"0000", -- config reg 0\r
+ INIT_41 => X"3000", -- config reg 1\r
+ INIT_42 => X"1900", -- config reg 2\r
+ INIT_48 => X"0100", -- Sequencer channel selection\r
+ INIT_49 => X"0000", -- Sequencer channel selection\r
+ INIT_4A => X"0000", -- Sequencer Average selection\r
+ INIT_4B => X"0000", -- Sequencer Average selection\r
+ INIT_4C => X"0000", -- Sequencer Bipolar selection\r
+ INIT_4D => X"0000", -- Sequencer Bipolar selection\r
+ INIT_4E => X"0000", -- Sequencer Acq time selection\r
+ INIT_4F => X"0000", -- Sequencer Acq time selection\r
+ INIT_50 => X"b5ed", -- Temp alarm trigger\r
+ INIT_51 => X"5999", -- Vccint upper alarm limit\r
+ INIT_52 => X"e000", -- Vccaux upper alarm limit\r
+ INIT_53 => X"ca33", -- Temp alarm OT upper\r
+ INIT_54 => X"a93a", -- Temp alarm reset\r
+ INIT_55 => X"5111", -- Vccint lower alarm limit\r
+ INIT_56 => X"caaa", -- Vccaux lower alarm limit\r
+ INIT_57 => X"ae4e", -- Temp alarm OT reset\r
+ SIM_DEVICE => "VIRTEX6",\r
+ SIM_MONITOR_FILE => "design.txt"\r
+ )\r
+\r
+port map (\r
+ CONVST => '0',\r
+ CONVSTCLK => '0',\r
+ DADDR(6 downto 0) => DADDR_IN(6 downto 0),\r
+ DCLK => DCLK_IN,\r
+ DEN => DEN_IN,\r
+ DI(15 downto 0) => DI_IN(15 downto 0),\r
+ DWE => DWE_IN,\r
+ RESET => RESET_IN,\r
+ VAUXN(15 downto 0) => aux_channel_n(15 downto 0),\r
+ VAUXP(15 downto 0) => aux_channel_p(15 downto 0),\r
+ ALM(2) => VCCAUX_ALARM_OUT,\r
+ ALM(1) => VCCINT_ALARM_OUT,\r
+ ALM(0) => USER_TEMP_ALARM_OUT,\r
+ BUSY => BUSY_OUT,\r
+ CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),\r
+ DO(15 downto 0) => DO_OUT(15 downto 0),\r
+ DRDY => DRDY_OUT,\r
+ EOC => EOC_OUT,\r
+ EOS => EOS_OUT,\r
+ JTAGBUSY => JTAGBUSY_OUT,\r
+ JTAGLOCKED => JTAGLOCKED_OUT,\r
+ JTAGMODIFIED => JTAGMODIFIED_OUT,\r
+ OT => OT_OUT,\r
+ VN => VN_IN,\r
+ VP => VP_IN\r
+ );\r
+end xilinx;\r
+\r
--- /dev/null
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+--\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component SystemMonitorVirtex\r
+ port (\r
+ DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port\r
+ DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port\r
+ DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port\r
+ DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port\r
+ DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port\r
+ RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic\r
+ BUSY_OUT : out STD_LOGIC; -- ADC Busy signal\r
+ CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs\r
+ DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port\r
+ DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port\r
+ EOC_OUT : out STD_LOGIC; -- End of Conversion Signal\r
+ EOS_OUT : out STD_LOGIC; -- End of Sequence Signal\r
+ JTAGBUSY_OUT : out STD_LOGIC; -- JTAG DRP transaction is in progress signal\r
+ JTAGLOCKED_OUT : out STD_LOGIC; -- DRP port lock request has been made by JTAG\r
+ JTAGMODIFIED_OUT : out STD_LOGIC; -- Indicates JTAG Write to the DRP has occurred\r
+ OT_OUT : out STD_LOGIC; -- Over-Temperature alarm output\r
+ VCCAUX_ALARM_OUT : out STD_LOGIC; -- VCCAUX-sensor alarm output\r
+ VCCINT_ALARM_OUT : out STD_LOGIC; -- VCCINT-sensor alarm output\r
+ USER_TEMP_ALARM_OUT : out STD_LOGIC; -- Temperature-sensor alarm output\r
+ VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair\r
+ VN_IN : in STD_LOGIC\r
+);\r
+end component;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : SystemMonitorVirtex\r
+ port map ( \r
+ DADDR_IN => DADDR_IN, \r
+ DCLK_IN => DCLK_IN, \r
+ DEN_IN => DEN_IN, \r
+ DI_IN => DI_IN,\r
+ DWE_IN => DWE_IN, \r
+ RESET_IN => RESET_IN, \r
+ BUSY_OUT => BUSY_OUT,\r
+ CHANNEL_OUT => CHANNEL_OUT,\r
+ DO_OUT => DO_OUT,\r
+ DRDY_OUT => DRDY_OUT,\r
+ EOC_OUT => EOC_OUT,\r
+ EOS_OUT => EOS_OUT,\r
+ JTAGBUSY_OUT => JTAGBUSY_OUT,\r
+ JTAGLOCKED_OUT => JTAGLOCKED_OUT,\r
+ JTAGMODIFIED_OUT => JTAGMODIFIED_OUT,\r
+ OT_OUT => OT_OUT,\r
+ VCCAUX_ALARM_OUT => VCCAUX_ALARM_OUT,\r
+ VCCINT_ALARM_OUT => VCCINT_ALARM_OUT,\r
+ USER_TEMP_ALARM_OUT => USER_TEMP_ALARM_OUT,\r
+ VP_IN => VP_IN, \r
+ VN_IN => VN_IN\r
+ );\r
+\r
+-- INST_TAG_END ------ End INSTANTIATION Template ---------\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 13.3\r
+# Date: Wed Oct 17 13:30:12 2012\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:sysmon_wiz:2.1\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT System_Monitor_Wizard family Xilinx,_Inc. 2.1\r
+# END Select\r
+# BEGIN Parameters\r
+CSET acquisition_time_vauxp0_vauxn0=false\r
+CSET acquisition_time_vauxp10_vauxn10=false\r
+CSET acquisition_time_vauxp11_vauxn11=false\r
+CSET acquisition_time_vauxp12_vauxn12=false\r
+CSET acquisition_time_vauxp13_vauxn13=false\r
+CSET acquisition_time_vauxp14_vauxn14=false\r
+CSET acquisition_time_vauxp15_vauxn15=false\r
+CSET acquisition_time_vauxp1_vauxn1=false\r
+CSET acquisition_time_vauxp2_vauxn2=false\r
+CSET acquisition_time_vauxp3_vauxn3=false\r
+CSET acquisition_time_vauxp4_vauxn4=false\r
+CSET acquisition_time_vauxp5_vauxn5=false\r
+CSET acquisition_time_vauxp6_vauxn6=false\r
+CSET acquisition_time_vauxp7_vauxn7=false\r
+CSET acquisition_time_vauxp8_vauxn8=false\r
+CSET acquisition_time_vauxp9_vauxn9=false\r
+CSET acquisition_time_vp_vn=false\r
+CSET adc_conversion_rate=100.0\r
+CSET adc_offset_and_gain_calibration=false\r
+CSET adc_offset_calibration=false\r
+CSET average_enable_temperature=false\r
+CSET average_enable_vauxp0_vauxn0=false\r
+CSET average_enable_vauxp10_vauxn10=false\r
+CSET average_enable_vauxp11_vauxn11=false\r
+CSET average_enable_vauxp12_vauxn12=false\r
+CSET average_enable_vauxp13_vauxn13=false\r
+CSET average_enable_vauxp14_vauxn14=false\r
+CSET average_enable_vauxp15_vauxn15=false\r
+CSET average_enable_vauxp1_vauxn1=false\r
+CSET average_enable_vauxp2_vauxn2=false\r
+CSET average_enable_vauxp3_vauxn3=false\r
+CSET average_enable_vauxp4_vauxn4=false\r
+CSET average_enable_vauxp5_vauxn5=false\r
+CSET average_enable_vauxp6_vauxn6=false\r
+CSET average_enable_vauxp7_vauxn7=false\r
+CSET average_enable_vauxp8_vauxn8=false\r
+CSET average_enable_vauxp9_vauxn9=false\r
+CSET average_enable_vccaux=false\r
+CSET average_enable_vccint=false\r
+CSET average_enable_vp_vn=false\r
+CSET bipolar_operation=false\r
+CSET bipolar_vauxp0_vauxn0=false\r
+CSET bipolar_vauxp10_vauxn10=false\r
+CSET bipolar_vauxp11_vauxn11=false\r
+CSET bipolar_vauxp12_vauxn12=false\r
+CSET bipolar_vauxp13_vauxn13=false\r
+CSET bipolar_vauxp14_vauxn14=false\r
+CSET bipolar_vauxp15_vauxn15=false\r
+CSET bipolar_vauxp1_vauxn1=false\r
+CSET bipolar_vauxp2_vauxn2=false\r
+CSET bipolar_vauxp3_vauxn3=false\r
+CSET bipolar_vauxp4_vauxn4=false\r
+CSET bipolar_vauxp5_vauxn5=false\r
+CSET bipolar_vauxp6_vauxn6=false\r
+CSET bipolar_vauxp7_vauxn7=false\r
+CSET bipolar_vauxp8_vauxn8=false\r
+CSET bipolar_vauxp9_vauxn9=false\r
+CSET bipolar_vp_vn=false\r
+CSET channel_averaging=None\r
+CSET channel_enable_calibration=false\r
+CSET channel_enable_temperature=false\r
+CSET channel_enable_vauxp0_vauxn0=false\r
+CSET channel_enable_vauxp10_vauxn10=false\r
+CSET channel_enable_vauxp11_vauxn11=false\r
+CSET channel_enable_vauxp12_vauxn12=false\r
+CSET channel_enable_vauxp13_vauxn13=false\r
+CSET channel_enable_vauxp14_vauxn14=false\r
+CSET channel_enable_vauxp15_vauxn15=false\r
+CSET channel_enable_vauxp1_vauxn1=false\r
+CSET channel_enable_vauxp2_vauxn2=false\r
+CSET channel_enable_vauxp3_vauxn3=false\r
+CSET channel_enable_vauxp4_vauxn4=false\r
+CSET channel_enable_vauxp5_vauxn5=false\r
+CSET channel_enable_vauxp6_vauxn6=false\r
+CSET channel_enable_vauxp7_vauxn7=false\r
+CSET channel_enable_vauxp8_vauxn8=false\r
+CSET channel_enable_vauxp9_vauxn9=false\r
+CSET channel_enable_vccaux=false\r
+CSET channel_enable_vccint=false\r
+CSET channel_enable_vp_vn=false\r
+CSET channel_enable_vrefn=false\r
+CSET channel_enable_vrefp=false\r
+CSET component_name=SystemMonitorVirtex\r
+CSET dclk_frequency=62.5\r
+CSET enable_busy=true\r
+CSET enable_calibration_averaging=true\r
+CSET enable_channel=true\r
+CSET enable_convst=false\r
+CSET enable_convstclk=false\r
+CSET enable_dclk=true\r
+CSET enable_drp=true\r
+CSET enable_eoc=true\r
+CSET enable_eos=true\r
+CSET enable_jtagbusy=true\r
+CSET enable_jtaglocked=true\r
+CSET enable_jtagmodified=true\r
+CSET enable_reset=true\r
+CSET increase_acquisition_time=false\r
+CSET ot_alarm=true\r
+CSET sensor_offset_and_gain_calibration=false\r
+CSET sensor_offset_calibration=false\r
+CSET sequencer_mode=Off\r
+CSET sim_file_name=design\r
+CSET single_channel_acquisition_time=false\r
+CSET single_channel_enable_calibration=true\r
+CSET single_channel_selection=Temperature\r
+CSET startup_channel_selection=single_channel\r
+CSET temperature_alarm_ot_reset=70.0\r
+CSET temperature_alarm_ot_trigger=125.0\r
+CSET temperature_alarm_reset=60.0\r
+CSET temperature_alarm_trigger=85.0\r
+CSET timing_mode=Continuous\r
+CSET user_temp_alarm=true\r
+CSET vccaux_alarm=true\r
+CSET vccaux_alarm_lower=2.375\r
+CSET vccaux_alarm_upper=2.625\r
+CSET vccint_alarm=true\r
+CSET vccint_alarm_lower=0.95\r
+CSET vccint_alarm_upper=1.05\r
+# END Parameters\r
+GENERATE\r
+# CRC: f7c86d59\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="SystemMonitorVirtex.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SystemMonitorVirtex|xilinx" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="SystemMonitorVirtex.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SystemMonitorVirtex" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="SystemMonitorVirtex" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-10-17T15:30:23" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="57CB37DF213B424C978A20B38A2AF937" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<!-- IMPORTANT: This is an internal file that has been generated -->\r
+<!-- by the Xilinx ISE software. Any direct editing or -->\r
+<!-- changes made to this file may result in unpredictable -->\r
+<!-- behavior or data corruption. It is strongly advised that -->\r
+<!-- users do not edit the contents of this file. -->\r
+<!-- -->\r
+<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+<messages>\r
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "D:/Project/Panda/GIT/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd" into library work</arg>\r
+</msg>\r
+\r
+</messages>\r
+\r
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 async_fifo_16x9
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[8:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[8:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="async_fifo_16x9.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="async_fifo_16x9.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="async_fifo_16x9.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="async_fifo_16x9.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8196757456903485200" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8922373193325759184" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6619080276402113216" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
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\7fM4192we?4650;3xL7063td::>4?:0yK637<utwvLMMt40;9f0`e:=98qMNM{1
\7fCDU}zHI
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file async_fifo_16x9.vhd when simulating\r
+-- the core, async_fifo_16x9. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY async_fifo_16x9 IS\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END async_fifo_16x9;\r
+\r
+ARCHITECTURE async_fifo_16x9_a OF async_fifo_16x9 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_async_fifo_16x9\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_async_fifo_16x9 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 0,\r
+ c_count_type => 0,\r
+ c_data_count_width => 4,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 9,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 9,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 2,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 1,\r
+ c_preload_regs => 0,\r
+ c_prim_fifo_type => "512x36",\r
+ c_prog_empty_thresh_assert_val => 2,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 3,\r
+ c_prog_empty_type => 0,\r
+ c_prog_empty_type_axis => 0,\r
+ c_prog_empty_type_rach => 0,\r
+ c_prog_empty_type_rdch => 0,\r
+ c_prog_empty_type_wach => 0,\r
+ c_prog_empty_type_wdch => 0,\r
+ c_prog_empty_type_wrch => 0,\r
+ c_prog_full_thresh_assert_val => 13,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 12,\r
+ c_prog_full_type => 0,\r
+ c_prog_full_type_axis => 0,\r
+ c_prog_full_type_rach => 0,\r
+ c_prog_full_type_rdch => 0,\r
+ c_prog_full_type_wach => 0,\r
+ c_prog_full_type_wdch => 0,\r
+ c_prog_full_type_wrch => 0,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 4,\r
+ c_rd_depth => 16,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 4,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_synchronizer_stage => 2,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 0,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 4,\r
+ c_wr_depth => 16,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 4,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_async_fifo_16x9\r
+ PORT MAP (\r
+ rst => rst,\r
+ wr_clk => wr_clk,\r
+ rd_clk => rd_clk,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END async_fifo_16x9_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
+-- --\r
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
+-- memory queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+-- master_aclk\r
+-- slave_aclk\r
+-- slave_aresetn\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT async_fifo_16x9\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : async_fifo_16x9\r
+ PORT MAP (\r
+ rst => rst,\r
+ wr_clk => wr_clk,\r
+ rd_clk => rd_clk,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file async_fifo_16x9.vhd when simulating\r
+-- the core, async_fifo_16x9. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Thu Nov 27 10:27:02 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=async_fifo_16x9\r
+CSET data_count=false\r
+CSET data_count_width=4\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=2\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=3\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Independent_Clocks_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=13\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=12\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=9\r
+CSET input_depth=16\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=9\r
+CSET output_depth=16\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=Standard_FIFO\r
+CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
+CSET programmable_full_type=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=4\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET synchronization_stages=2\r
+CSET synchronization_stages_axi=2\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=false\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=4\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-11-19T12:39:56Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: e70f47ef\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="async_fifo_16x9.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="async_fifo_16x9.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|async_fifo_16x9|async_fifo_16x9_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="async_fifo_16x9.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/async_fifo_16x9" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="async_fifo_16x9" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-27T11:28:50" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5E9AED9EED564544B04AED8AD2D6A268" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 async_fifo_512x32
+RECTANGLE Normal 32 32 800 3680
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Normal 0 208 32 208
+PIN 0 208 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[31:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 832 240 800 240
+PIN 832 240 RIGHT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[31:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="async_fifo_512x32.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="async_fifo_512x32.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="async_fifo_512x32.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="async_fifo_512x32.vho" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_v8_3_readme.txt" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1343823802" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343823802">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6081577449302675146" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6587804894567336138" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3493164220429793914" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2012 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file async_fifo_512x32.vhd when simulating\r
+-- the core, async_fifo_512x32. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY async_fifo_512x32 IS\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END async_fifo_512x32;\r
+\r
+ARCHITECTURE async_fifo_512x32_a OF async_fifo_512x32 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_async_fifo_512x32\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_async_fifo_512x32 USE ENTITY XilinxCoreLib.fifo_generator_v8_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 0,\r
+ c_count_type => 0,\r
+ c_data_count_width => 9,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 32,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 32,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 2,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 1,\r
+ c_preload_regs => 0,\r
+ c_prim_fifo_type => "512x36",\r
+ c_prog_empty_thresh_assert_val => 2,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 3,\r
+ c_prog_empty_type => 0,\r
+ c_prog_empty_type_axis => 5,\r
+ c_prog_empty_type_rach => 5,\r
+ c_prog_empty_type_rdch => 5,\r
+ c_prog_empty_type_wach => 5,\r
+ c_prog_empty_type_wdch => 5,\r
+ c_prog_empty_type_wrch => 5,\r
+ c_prog_full_thresh_assert_val => 509,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 508,\r
+ c_prog_full_type => 0,\r
+ c_prog_full_type_axis => 5,\r
+ c_prog_full_type_rach => 5,\r
+ c_prog_full_type_rdch => 5,\r
+ c_prog_full_type_wach => 5,\r
+ c_prog_full_type_wdch => 5,\r
+ c_prog_full_type_wrch => 5,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 9,\r
+ c_rd_depth => 512,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 9,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 0,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 9,\r
+ c_wr_depth => 512,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 9,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_async_fifo_512x32\r
+ PORT MAP (\r
+ rst => rst,\r
+ wr_clk => wr_clk,\r
+ rd_clk => rd_clk,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END async_fifo_512x32_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2012 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:8.3 --\r
+-- --\r
+-- The FIFO Generator is a parameterizable first-in/first-out memory --\r
+-- queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT async_fifo_512x32\r
+ PORT (\r
+ rst : IN STD_LOGIC;\r
+ wr_clk : IN STD_LOGIC;\r
+ rd_clk : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : async_fifo_512x32\r
+ PORT MAP (\r
+ rst => rst,\r
+ wr_clk => wr_clk,\r
+ rd_clk => rd_clk,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file async_fifo_512x32.vhd when simulating\r
+-- the core, async_fifo_512x32. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 13.3\r
+# Date: Thu Jul 26 14:36:50 2012\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:8.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=async_fifo_512x32\r
+CSET data_count=false\r
+CSET data_count_width=9\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=2\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=3\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_handshake_flag_options_axis=false\r
+CSET enable_handshake_flag_options_rach=false\r
+CSET enable_handshake_flag_options_rdch=false\r
+CSET enable_handshake_flag_options_wach=false\r
+CSET enable_handshake_flag_options_wdch=false\r
+CSET enable_handshake_flag_options_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Independent_Clocks_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=509\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=508\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=32\r
+CSET input_depth=512\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=32\r
+CSET output_depth=512\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=Standard_FIFO\r
+CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_axis=Empty\r
+CSET programmable_empty_type_rach=Empty\r
+CSET programmable_empty_type_rdch=Empty\r
+CSET programmable_empty_type_wach=Empty\r
+CSET programmable_empty_type_wdch=Empty\r
+CSET programmable_empty_type_wrch=Empty\r
+CSET programmable_full_type=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_axis=Full\r
+CSET programmable_full_type_rach=Full\r
+CSET programmable_full_type_rdch=Full\r
+CSET programmable_full_type_wach=Full\r
+CSET programmable_full_type_wdch=Full\r
+CSET programmable_full_type_wrch=Full\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=9\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=false\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=9\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2011-03-14T07:12:32.000Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: 5b1bf9c4\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="async_fifo_512x32.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="async_fifo_512x32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|async_fifo_512x32|async_fifo_512x32_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="async_fifo_512x32.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/async_fifo_512x32" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="async_fifo_512x32" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-26T16:38:38" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CECC96E91D3845338B0F194B6C73657D" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 clockmodule40switch
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName clk_in2
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName clk_in_sel
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName reset
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule40switch.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule40switch.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule40switch.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-798096215140453084" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6740456813635759876" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6111184890770083540" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+# file: clockmodule40switch.ucf\r
+# \r
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+# \r
+# This file contains confidential and proprietary information\r
+# of Xilinx, Inc. and is protected under U.S. and\r
+# international copyright and other intellectual property\r
+# laws.\r
+# \r
+# DISCLAIMER\r
+# This disclaimer is not a license and does not grant any\r
+# rights to the materials distributed herewith. Except as\r
+# otherwise provided in a valid license issued to you by\r
+# Xilinx, and to the maximum extent permitted by applicable\r
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+# (2) Xilinx shall not be liable (whether in contract or tort,\r
+# including negligence, or under any other theory of\r
+# liability) for any loss or damage of any kind or nature\r
+# related to, arising under or in connection with these\r
+# materials, including for any direct, or any indirect,\r
+# special, incidental, or consequential loss or damage\r
+# (including loss of data, profits, goodwill, or any type of\r
+# loss or damage suffered as a result of any action brought\r
+# by a third party) even if such damage or loss was\r
+# reasonably foreseeable or Xilinx had been advised of the\r
+# possibility of the same.\r
+# \r
+# CRITICAL APPLICATIONS\r
+# Xilinx products are not designed or intended to be fail-\r
+# safe, or for use in any application requiring fail-safe\r
+# performance, such as life-support or safety devices or\r
+# systems, Class III medical devices, nuclear facilities,\r
+# applications related to the deployment of airbags, or any\r
+# other applications that could lead to death, personal\r
+# injury, or severe property or environmental damage\r
+# (individually and collectively, "Critical\r
+# Applications"). Customer assumes the sole risk and\r
+# liability of any use of Xilinx products in Critical\r
+# Applications, subject only to applicable laws and\r
+# regulations governing limitations on product liability.\r
+# \r
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+# PART OF THIS FILE AT ALL TIMES.\r
+# \r
+\r
+# Input clock periods. These duplicate the values entered for the\r
+# input clocks. You can use these to time your system\r
+#----------------------------------------------------------------\r
+NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;\r
+NET "CLK_IN2" TNM_NET = "CLK_IN2";\r
+TIMESPEC "TS_CLK_IN2" = PERIOD "CLK_IN2" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;\r
+\r
+\r
+# FALSE PATH constraints \r
+PIN "RESET" TIG;\r
+\r
--- /dev/null
+-- file: clockmodule40switch.vhd\r
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____40.000______0.000______50.0______247.096____196.976\r
+-- CLK_OUT2____80.000______0.000______50.0______200.412____196.976\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary______________40____________0.010\r
+-- _secondary____________40____________0.010\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.numeric_std.all;\r
+\r
+library unisim;\r
+use unisim.vcomponents.all;\r
+\r
+entity clockmodule40switch is\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ CLK_IN2 : in std_logic;\r
+ CLK_IN_SEL : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ -- Status and control signals\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end clockmodule40switch;\r
+\r
+architecture xilinx of clockmodule40switch is\r
+ attribute CORE_GENERATION_INFO : string;\r
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule40switch,clk_wiz_v3_6,{component_name=clockmodule40switch,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=true,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
+ -- Input clock buffering / unused connectors\r
+ signal clkin1 : std_logic;\r
+ signal clkin2 : std_logic;\r
+ -- Output clock buffering / unused connectors\r
+ signal clkfbout : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+ signal clkfboutb_unused : std_logic;\r
+ signal clkout0 : std_logic;\r
+ signal clkout0b_unused : std_logic;\r
+ signal clkout1 : std_logic;\r
+ signal clkout1b_unused : std_logic;\r
+ signal clkout2_unused : std_logic;\r
+ signal clkout2b_unused : std_logic;\r
+ signal clkout3_unused : std_logic;\r
+ signal clkout3b_unused : std_logic;\r
+ signal clkout4_unused : std_logic;\r
+ signal clkout5_unused : std_logic;\r
+ signal clkout6_unused : std_logic;\r
+ -- Dynamic programming unused signals\r
+ signal do_unused : std_logic_vector(15 downto 0);\r
+ signal drdy_unused : std_logic;\r
+ -- Dynamic phase shift unused signals\r
+ signal psdone_unused : std_logic;\r
+ -- Unused status signals\r
+ signal clkfbstopped_unused : std_logic;\r
+ signal clkinstopped_unused : std_logic;\r
+begin\r
+\r
+\r
+ -- Input buffering\r
+ --------------------------------------\r
+ clkin1_buf : BUFG\r
+ port map\r
+ (O => clkin1,\r
+ I => CLK_IN1);\r
+\r
+ clkin2_buf : BUFG\r
+ port map\r
+ (O => clkin2,\r
+ I => CLK_IN2);\r
+\r
+ -- Clocking primitive\r
+ --------------------------------------\r
+ -- Instantiation of the MMCM primitive\r
+ -- * Unused inputs are tied off\r
+ -- * Unused outputs are labeled unused\r
+ mmcm_adv_inst : MMCM_ADV\r
+ generic map\r
+ (BANDWIDTH => "OPTIMIZED",\r
+ CLKOUT4_CASCADE => FALSE,\r
+ CLOCK_HOLD => FALSE,\r
+ COMPENSATION => "ZHOLD",\r
+ STARTUP_WAIT => FALSE,\r
+ DIVCLK_DIVIDE => 1,\r
+ CLKFBOUT_MULT_F => 24.000,\r
+ CLKFBOUT_PHASE => 0.000,\r
+ CLKFBOUT_USE_FINE_PS => FALSE,\r
+ CLKOUT0_DIVIDE_F => 24.000,\r
+ CLKOUT0_PHASE => 0.000,\r
+ CLKOUT0_DUTY_CYCLE => 0.500,\r
+ CLKOUT0_USE_FINE_PS => FALSE,\r
+ CLKOUT1_DIVIDE => 12,\r
+ CLKOUT1_PHASE => 0.000,\r
+ CLKOUT1_DUTY_CYCLE => 0.500,\r
+ CLKOUT1_USE_FINE_PS => FALSE,\r
+ CLKIN1_PERIOD => 25.000,\r
+ REF_JITTER1 => 0.010,\r
+ CLKIN2_PERIOD => 25.000,\r
+ REF_JITTER2 => 0.010)\r
+ port map\r
+ -- Output clocks\r
+ (CLKFBOUT => clkfbout,\r
+ CLKFBOUTB => clkfboutb_unused,\r
+ CLKOUT0 => clkout0,\r
+ CLKOUT0B => clkout0b_unused,\r
+ CLKOUT1 => clkout1,\r
+ CLKOUT1B => clkout1b_unused,\r
+ CLKOUT2 => clkout2_unused,\r
+ CLKOUT2B => clkout2b_unused,\r
+ CLKOUT3 => clkout3_unused,\r
+ CLKOUT3B => clkout3b_unused,\r
+ CLKOUT4 => clkout4_unused,\r
+ CLKOUT5 => clkout5_unused,\r
+ CLKOUT6 => clkout6_unused,\r
+ -- Input clock control\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKIN1 => clkin1,\r
+ CLKIN2 => clkin2,\r
+ CLKINSEL => CLK_IN_SEL,\r
+ -- Ports for dynamic reconfiguration\r
+ DADDR => (others => '0'),\r
+ DCLK => '0',\r
+ DEN => '0',\r
+ DI => (others => '0'),\r
+ DO => do_unused,\r
+ DRDY => drdy_unused,\r
+ DWE => '0',\r
+ -- Ports for dynamic phase shift\r
+ PSCLK => '0',\r
+ PSEN => '0',\r
+ PSINCDEC => '0',\r
+ PSDONE => psdone_unused,\r
+ -- Other control and status signals\r
+ LOCKED => LOCKED,\r
+ CLKINSTOPPED => clkinstopped_unused,\r
+ CLKFBSTOPPED => clkfbstopped_unused,\r
+ PWRDWN => '0',\r
+ RST => RESET);\r
+\r
+ -- Output buffering\r
+ -------------------------------------\r
+ clkf_buf : BUFG\r
+ port map\r
+ (O => clkfbout_buf,\r
+ I => clkfbout);\r
+\r
+\r
+ clkout1_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT1,\r
+ I => clkout0);\r
+\r
+\r
+\r
+ clkout2_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT2,\r
+ I => clkout1);\r
+\r
+end xilinx;\r
--- /dev/null
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____40.000______0.000______50.0______247.096____196.976\r
+-- CLK_OUT2____80.000______0.000______50.0______200.412____196.976\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary______________40____________0.010\r
+-- _secondary____________40____________0.010\r
+\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component clockmodule40switch\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ CLK_IN2 : in std_logic;\r
+ CLK_IN_SEL : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ -- Status and control signals\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : clockmodule40switch\r
+ port map\r
+ (-- Clock in ports\r
+ CLK_IN1 => CLK_IN1,\r
+ CLK_IN2 => CLK_IN2,\r
+ CLK_IN_SEL => CLK_IN_SEL,\r
+ -- Clock out ports\r
+ CLK_OUT1 => CLK_OUT1,\r
+ CLK_OUT2 => CLK_OUT2,\r
+ -- Status and control signals\r
+ RESET => RESET,\r
+ LOCKED => LOCKED);\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Wed Nov 26 08:54:36 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
+# END Select\r
+# BEGIN Parameters\r
+CSET calc_done=DONE\r
+CSET clk_in_sel_port=CLK_IN_SEL\r
+CSET clk_out1_port=CLK_OUT1\r
+CSET clk_out1_use_fine_ps_gui=false\r
+CSET clk_out2_port=CLK_OUT2\r
+CSET clk_out2_use_fine_ps_gui=false\r
+CSET clk_out3_port=CLK_OUT3\r
+CSET clk_out3_use_fine_ps_gui=false\r
+CSET clk_out4_port=CLK_OUT4\r
+CSET clk_out4_use_fine_ps_gui=false\r
+CSET clk_out5_port=CLK_OUT5\r
+CSET clk_out5_use_fine_ps_gui=false\r
+CSET clk_out6_port=CLK_OUT6\r
+CSET clk_out6_use_fine_ps_gui=false\r
+CSET clk_out7_port=CLK_OUT7\r
+CSET clk_out7_use_fine_ps_gui=false\r
+CSET clk_valid_port=CLK_VALID\r
+CSET clkfb_in_n_port=CLKFB_IN_N\r
+CSET clkfb_in_p_port=CLKFB_IN_P\r
+CSET clkfb_in_port=CLKFB_IN\r
+CSET clkfb_in_signaling=SINGLE\r
+CSET clkfb_out_n_port=CLKFB_OUT_N\r
+CSET clkfb_out_p_port=CLKFB_OUT_P\r
+CSET clkfb_out_port=CLKFB_OUT\r
+CSET clkfb_stopped_port=CLKFB_STOPPED\r
+CSET clkin1_jitter_ps=250.0\r
+CSET clkin1_ui_jitter=0.010\r
+CSET clkin2_jitter_ps=250.0\r
+CSET clkin2_ui_jitter=0.010\r
+CSET clkout1_drives=BUFG\r
+CSET clkout1_requested_duty_cycle=50.000\r
+CSET clkout1_requested_out_freq=40\r
+CSET clkout1_requested_phase=0.000\r
+CSET clkout2_drives=BUFG\r
+CSET clkout2_requested_duty_cycle=50.000\r
+CSET clkout2_requested_out_freq=80\r
+CSET clkout2_requested_phase=0.000\r
+CSET clkout2_used=true\r
+CSET clkout3_drives=BUFG\r
+CSET clkout3_requested_duty_cycle=50.000\r
+CSET clkout3_requested_out_freq=100.000\r
+CSET clkout3_requested_phase=0.000\r
+CSET clkout3_used=false\r
+CSET clkout4_drives=BUFG\r
+CSET clkout4_requested_duty_cycle=50.000\r
+CSET clkout4_requested_out_freq=100.000\r
+CSET clkout4_requested_phase=0.000\r
+CSET clkout4_used=false\r
+CSET clkout5_drives=BUFG\r
+CSET clkout5_requested_duty_cycle=50.000\r
+CSET clkout5_requested_out_freq=100.000\r
+CSET clkout5_requested_phase=0.000\r
+CSET clkout5_used=false\r
+CSET clkout6_drives=BUFG\r
+CSET clkout6_requested_duty_cycle=50.000\r
+CSET clkout6_requested_out_freq=100.000\r
+CSET clkout6_requested_phase=0.000\r
+CSET clkout6_used=false\r
+CSET clkout7_drives=BUFG\r
+CSET clkout7_requested_duty_cycle=50.000\r
+CSET clkout7_requested_out_freq=100.000\r
+CSET clkout7_requested_phase=0.000\r
+CSET clkout7_used=false\r
+CSET clock_mgr_type=MANUAL\r
+CSET component_name=clockmodule40switch\r
+CSET daddr_port=DADDR\r
+CSET dclk_port=DCLK\r
+CSET dcm_clk_feedback=1X\r
+CSET dcm_clk_out1_port=CLK0\r
+CSET dcm_clk_out2_port=CLK0\r
+CSET dcm_clk_out3_port=CLK0\r
+CSET dcm_clk_out4_port=CLK0\r
+CSET dcm_clk_out5_port=CLK0\r
+CSET dcm_clk_out6_port=CLK0\r
+CSET dcm_clkdv_divide=2.0\r
+CSET dcm_clkfx_divide=1\r
+CSET dcm_clkfx_multiply=4\r
+CSET dcm_clkgen_clk_out1_port=CLKFX\r
+CSET dcm_clkgen_clk_out2_port=CLKFX\r
+CSET dcm_clkgen_clk_out3_port=CLKFX\r
+CSET dcm_clkgen_clkfx_divide=1\r
+CSET dcm_clkgen_clkfx_md_max=0.000\r
+CSET dcm_clkgen_clkfx_multiply=4\r
+CSET dcm_clkgen_clkfxdv_divide=2\r
+CSET dcm_clkgen_clkin_period=10.000\r
+CSET dcm_clkgen_notes=None\r
+CSET dcm_clkgen_spread_spectrum=NONE\r
+CSET dcm_clkgen_startup_wait=false\r
+CSET dcm_clkin_divide_by_2=false\r
+CSET dcm_clkin_period=10.000\r
+CSET dcm_clkout_phase_shift=NONE\r
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
+CSET dcm_notes=None\r
+CSET dcm_phase_shift=0\r
+CSET dcm_pll_cascade=NONE\r
+CSET dcm_startup_wait=false\r
+CSET den_port=DEN\r
+CSET din_port=DIN\r
+CSET dout_port=DOUT\r
+CSET drdy_port=DRDY\r
+CSET dwe_port=DWE\r
+CSET feedback_source=FDBK_AUTO\r
+CSET in_freq_units=Units_MHz\r
+CSET in_jitter_units=Units_UI\r
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
+CSET jitter_options=UI\r
+CSET jitter_sel=No_Jitter\r
+CSET locked_port=LOCKED\r
+CSET mmcm_bandwidth=OPTIMIZED\r
+CSET mmcm_clkfbout_mult_f=24.000\r
+CSET mmcm_clkfbout_phase=0.000\r
+CSET mmcm_clkfbout_use_fine_ps=false\r
+CSET mmcm_clkin1_period=25.000\r
+CSET mmcm_clkin2_period=25.000\r
+CSET mmcm_clkout0_divide_f=24.000\r
+CSET mmcm_clkout0_duty_cycle=0.500\r
+CSET mmcm_clkout0_phase=0.000\r
+CSET mmcm_clkout0_use_fine_ps=false\r
+CSET mmcm_clkout1_divide=12\r
+CSET mmcm_clkout1_duty_cycle=0.500\r
+CSET mmcm_clkout1_phase=0.000\r
+CSET mmcm_clkout1_use_fine_ps=false\r
+CSET mmcm_clkout2_divide=1\r
+CSET mmcm_clkout2_duty_cycle=0.500\r
+CSET mmcm_clkout2_phase=0.000\r
+CSET mmcm_clkout2_use_fine_ps=false\r
+CSET mmcm_clkout3_divide=1\r
+CSET mmcm_clkout3_duty_cycle=0.500\r
+CSET mmcm_clkout3_phase=0.000\r
+CSET mmcm_clkout3_use_fine_ps=false\r
+CSET mmcm_clkout4_cascade=false\r
+CSET mmcm_clkout4_divide=1\r
+CSET mmcm_clkout4_duty_cycle=0.500\r
+CSET mmcm_clkout4_phase=0.000\r
+CSET mmcm_clkout4_use_fine_ps=false\r
+CSET mmcm_clkout5_divide=1\r
+CSET mmcm_clkout5_duty_cycle=0.500\r
+CSET mmcm_clkout5_phase=0.000\r
+CSET mmcm_clkout5_use_fine_ps=false\r
+CSET mmcm_clkout6_divide=1\r
+CSET mmcm_clkout6_duty_cycle=0.500\r
+CSET mmcm_clkout6_phase=0.000\r
+CSET mmcm_clkout6_use_fine_ps=false\r
+CSET mmcm_clock_hold=false\r
+CSET mmcm_compensation=ZHOLD\r
+CSET mmcm_divclk_divide=1\r
+CSET mmcm_notes=None\r
+CSET mmcm_ref_jitter1=0.010\r
+CSET mmcm_ref_jitter2=0.010\r
+CSET mmcm_startup_wait=false\r
+CSET num_out_clks=2\r
+CSET override_dcm=false\r
+CSET override_dcm_clkgen=false\r
+CSET override_mmcm=false\r
+CSET override_pll=false\r
+CSET platform=nt64\r
+CSET pll_bandwidth=OPTIMIZED\r
+CSET pll_clk_feedback=CLKFBOUT\r
+CSET pll_clkfbout_mult=4\r
+CSET pll_clkfbout_phase=0.000\r
+CSET pll_clkin_period=10.000\r
+CSET pll_clkout0_divide=1\r
+CSET pll_clkout0_duty_cycle=0.500\r
+CSET pll_clkout0_phase=0.000\r
+CSET pll_clkout1_divide=1\r
+CSET pll_clkout1_duty_cycle=0.500\r
+CSET pll_clkout1_phase=0.000\r
+CSET pll_clkout2_divide=1\r
+CSET pll_clkout2_duty_cycle=0.500\r
+CSET pll_clkout2_phase=0.000\r
+CSET pll_clkout3_divide=1\r
+CSET pll_clkout3_duty_cycle=0.500\r
+CSET pll_clkout3_phase=0.000\r
+CSET pll_clkout4_divide=1\r
+CSET pll_clkout4_duty_cycle=0.500\r
+CSET pll_clkout4_phase=0.000\r
+CSET pll_clkout5_divide=1\r
+CSET pll_clkout5_duty_cycle=0.500\r
+CSET pll_clkout5_phase=0.000\r
+CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
+CSET pll_divclk_divide=1\r
+CSET pll_notes=None\r
+CSET pll_ref_jitter=0.010\r
+CSET power_down_port=POWER_DOWN\r
+CSET prim_in_freq=40\r
+CSET prim_in_jitter=0.010\r
+CSET prim_source=Global_buffer\r
+CSET primary_port=CLK_IN1\r
+CSET primitive=MMCM\r
+CSET primtype_sel=MMCM_ADV\r
+CSET psclk_port=PSCLK\r
+CSET psdone_port=PSDONE\r
+CSET psen_port=PSEN\r
+CSET psincdec_port=PSINCDEC\r
+CSET relative_inclk=REL_PRIMARY\r
+CSET reset_port=RESET\r
+CSET secondary_in_freq=40\r
+CSET secondary_in_jitter=0.010\r
+CSET secondary_port=CLK_IN2\r
+CSET secondary_source=Global_buffer\r
+CSET ss_mod_freq=250\r
+CSET ss_mode=CENTER_HIGH\r
+CSET status_port=STATUS\r
+CSET summary_strings=empty\r
+CSET use_clk_valid=false\r
+CSET use_clkfb_stopped=false\r
+CSET use_dyn_phase_shift=false\r
+CSET use_dyn_reconfig=false\r
+CSET use_freeze=false\r
+CSET use_freq_synth=true\r
+CSET use_inclk_stopped=false\r
+CSET use_inclk_switchover=true\r
+CSET use_locked=true\r
+CSET use_max_i_jitter=false\r
+CSET use_min_o_jitter=false\r
+CSET use_min_power=false\r
+CSET use_phase_alignment=true\r
+CSET use_power_down=false\r
+CSET use_reset=true\r
+CSET use_spread_spectrum=false\r
+CSET use_spread_spectrum_1=false\r
+CSET use_status=false\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-05-10T12:44:55Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: 41fd2223\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="clockmodule40switch.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="clockmodule40switch.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule40switch|xilinx" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule40switch.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule40switch" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule40switch" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:55:02" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1222C6006EB742BD9905A04365D9D9E4" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/clockmodule40switch" xil_pn:name="clockmodule40switch.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 clockmodule80M
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80M.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80M.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80M.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4328670307819663427" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5868735601060516189" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="136310429885004787" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+# file: clockmodule80M.ucf\r
+# \r
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+# \r
+# This file contains confidential and proprietary information\r
+# of Xilinx, Inc. and is protected under U.S. and\r
+# international copyright and other intellectual property\r
+# laws.\r
+# \r
+# DISCLAIMER\r
+# This disclaimer is not a license and does not grant any\r
+# rights to the materials distributed herewith. Except as\r
+# otherwise provided in a valid license issued to you by\r
+# Xilinx, and to the maximum extent permitted by applicable\r
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+# (2) Xilinx shall not be liable (whether in contract or tort,\r
+# including negligence, or under any other theory of\r
+# liability) for any loss or damage of any kind or nature\r
+# related to, arising under or in connection with these\r
+# materials, including for any direct, or any indirect,\r
+# special, incidental, or consequential loss or damage\r
+# (including loss of data, profits, goodwill, or any type of\r
+# loss or damage suffered as a result of any action brought\r
+# by a third party) even if such damage or loss was\r
+# reasonably foreseeable or Xilinx had been advised of the\r
+# possibility of the same.\r
+# \r
+# CRITICAL APPLICATIONS\r
+# Xilinx products are not designed or intended to be fail-\r
+# safe, or for use in any application requiring fail-safe\r
+# performance, such as life-support or safety devices or\r
+# systems, Class III medical devices, nuclear facilities,\r
+# applications related to the deployment of airbags, or any\r
+# other applications that could lead to death, personal\r
+# injury, or severe property or environmental damage\r
+# (individually and collectively, "Critical\r
+# Applications"). Customer assumes the sole risk and\r
+# liability of any use of Xilinx products in Critical\r
+# Applications, subject only to applicable laws and\r
+# regulations governing limitations on product liability.\r
+# \r
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+# PART OF THIS FILE AT ALL TIMES.\r
+# \r
+\r
+# Input clock periods. These duplicate the values entered for the\r
+# input clocks. You can use these to time your system\r
+#----------------------------------------------------------------\r
+NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 6.430 ns HIGH 50% INPUT_JITTER 64.3ps;\r
+\r
+\r
+# FALSE PATH constraints \r
+\r
--- /dev/null
+-- file: clockmodule80M.vhd\r
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____99.999______0.000______50.0______144.151____174.045\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary__________155.52____________0.010\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.numeric_std.all;\r
+\r
+library unisim;\r
+use unisim.vcomponents.all;\r
+\r
+entity clockmodule80M is\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ -- Status and control signals\r
+ LOCKED : out std_logic\r
+ );\r
+end clockmodule80M;\r
+\r
+architecture xilinx of clockmodule80M is\r
+ attribute CORE_GENERATION_INFO : string;\r
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80M,clk_wiz_v3_6,{component_name=clockmodule80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=6.430,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
+ -- Input clock buffering / unused connectors\r
+ signal clkin1 : std_logic;\r
+ -- Output clock buffering / unused connectors\r
+ signal clkfbout : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+ signal clkfboutb_unused : std_logic;\r
+ signal clkout0 : std_logic;\r
+ signal clkout0b_unused : std_logic;\r
+ signal clkout1_unused : std_logic;\r
+ signal clkout1b_unused : std_logic;\r
+ signal clkout2_unused : std_logic;\r
+ signal clkout2b_unused : std_logic;\r
+ signal clkout3_unused : std_logic;\r
+ signal clkout3b_unused : std_logic;\r
+ signal clkout4_unused : std_logic;\r
+ signal clkout5_unused : std_logic;\r
+ signal clkout6_unused : std_logic;\r
+ -- Dynamic programming unused signals\r
+ signal do_unused : std_logic_vector(15 downto 0);\r
+ signal drdy_unused : std_logic;\r
+ -- Dynamic phase shift unused signals\r
+ signal psdone_unused : std_logic;\r
+ -- Unused status signals\r
+ signal clkfbstopped_unused : std_logic;\r
+ signal clkinstopped_unused : std_logic;\r
+begin\r
+\r
+\r
+ -- Input buffering\r
+ --------------------------------------\r
+ clkin1 <= CLK_IN1;\r
+\r
+\r
+ -- Clocking primitive\r
+ --------------------------------------\r
+ -- Instantiation of the MMCM primitive\r
+ -- * Unused inputs are tied off\r
+ -- * Unused outputs are labeled unused\r
+ mmcm_adv_inst : MMCM_ADV\r
+ generic map\r
+ (BANDWIDTH => "OPTIMIZED",\r
+ CLKOUT4_CASCADE => FALSE,\r
+ CLOCK_HOLD => FALSE,\r
+ COMPENSATION => "ZHOLD",\r
+ STARTUP_WAIT => FALSE,\r
+ DIVCLK_DIVIDE => 5,\r
+ CLKFBOUT_MULT_F => 43.000,\r
+ CLKFBOUT_PHASE => 0.000,\r
+ CLKFBOUT_USE_FINE_PS => FALSE,\r
+ CLKOUT0_DIVIDE_F => 13.375,\r
+ CLKOUT0_PHASE => 0.000,\r
+ CLKOUT0_DUTY_CYCLE => 0.500,\r
+ CLKOUT0_USE_FINE_PS => FALSE,\r
+ CLKIN1_PERIOD => 6.430,\r
+ REF_JITTER1 => 0.010)\r
+ port map\r
+ -- Output clocks\r
+ (CLKFBOUT => clkfbout,\r
+ CLKFBOUTB => clkfboutb_unused,\r
+ CLKOUT0 => clkout0,\r
+ CLKOUT0B => clkout0b_unused,\r
+ CLKOUT1 => clkout1_unused,\r
+ CLKOUT1B => clkout1b_unused,\r
+ CLKOUT2 => clkout2_unused,\r
+ CLKOUT2B => clkout2b_unused,\r
+ CLKOUT3 => clkout3_unused,\r
+ CLKOUT3B => clkout3b_unused,\r
+ CLKOUT4 => clkout4_unused,\r
+ CLKOUT5 => clkout5_unused,\r
+ CLKOUT6 => clkout6_unused,\r
+ -- Input clock control\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKIN1 => clkin1,\r
+ CLKIN2 => '0',\r
+ -- Tied to always select the primary input clock\r
+ CLKINSEL => '1',\r
+ -- Ports for dynamic reconfiguration\r
+ DADDR => (others => '0'),\r
+ DCLK => '0',\r
+ DEN => '0',\r
+ DI => (others => '0'),\r
+ DO => do_unused,\r
+ DRDY => drdy_unused,\r
+ DWE => '0',\r
+ -- Ports for dynamic phase shift\r
+ PSCLK => '0',\r
+ PSEN => '0',\r
+ PSINCDEC => '0',\r
+ PSDONE => psdone_unused,\r
+ -- Other control and status signals\r
+ LOCKED => LOCKED,\r
+ CLKINSTOPPED => clkinstopped_unused,\r
+ CLKFBSTOPPED => clkfbstopped_unused,\r
+ PWRDWN => '0',\r
+ RST => '0');\r
+\r
+ -- Output buffering\r
+ -------------------------------------\r
+ clkf_buf : BUFG\r
+ port map\r
+ (O => clkfbout_buf,\r
+ I => clkfbout);\r
+\r
+\r
+ clkout1_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT1,\r
+ I => clkout0);\r
+\r
+\r
+\r
+end xilinx;\r
--- /dev/null
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____99.999______0.000______50.0______144.151____174.045\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary__________155.52____________0.010\r
+\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component clockmodule80M\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ -- Status and control signals\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : clockmodule80M\r
+ port map\r
+ (-- Clock in ports\r
+ CLK_IN1 => CLK_IN1,\r
+ -- Clock out ports\r
+ CLK_OUT1 => CLK_OUT1,\r
+ -- Status and control signals\r
+ LOCKED => LOCKED);\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Wed Nov 26 08:35:23 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
+# END Select\r
+# BEGIN Parameters\r
+CSET calc_done=DONE\r
+CSET clk_in_sel_port=CLK_IN_SEL\r
+CSET clk_out1_port=CLK_OUT1\r
+CSET clk_out1_use_fine_ps_gui=false\r
+CSET clk_out2_port=CLK_OUT2\r
+CSET clk_out2_use_fine_ps_gui=false\r
+CSET clk_out3_port=CLK_OUT3\r
+CSET clk_out3_use_fine_ps_gui=false\r
+CSET clk_out4_port=CLK_OUT4\r
+CSET clk_out4_use_fine_ps_gui=false\r
+CSET clk_out5_port=CLK_OUT5\r
+CSET clk_out5_use_fine_ps_gui=false\r
+CSET clk_out6_port=CLK_OUT6\r
+CSET clk_out6_use_fine_ps_gui=false\r
+CSET clk_out7_port=CLK_OUT7\r
+CSET clk_out7_use_fine_ps_gui=false\r
+CSET clk_valid_port=CLK_VALID\r
+CSET clkfb_in_n_port=CLKFB_IN_N\r
+CSET clkfb_in_p_port=CLKFB_IN_P\r
+CSET clkfb_in_port=CLKFB_IN\r
+CSET clkfb_in_signaling=SINGLE\r
+CSET clkfb_out_n_port=CLKFB_OUT_N\r
+CSET clkfb_out_p_port=CLKFB_OUT_P\r
+CSET clkfb_out_port=CLKFB_OUT\r
+CSET clkfb_stopped_port=CLKFB_STOPPED\r
+CSET clkin1_jitter_ps=64.3\r
+CSET clkin1_ui_jitter=0.010\r
+CSET clkin2_jitter_ps=100.0\r
+CSET clkin2_ui_jitter=0.010\r
+CSET clkout1_drives=BUFG\r
+CSET clkout1_requested_duty_cycle=50.000\r
+CSET clkout1_requested_out_freq=100\r
+CSET clkout1_requested_phase=0.000\r
+CSET clkout2_drives=BUFG\r
+CSET clkout2_requested_duty_cycle=50.000\r
+CSET clkout2_requested_out_freq=100.000\r
+CSET clkout2_requested_phase=0.000\r
+CSET clkout2_used=false\r
+CSET clkout3_drives=BUFG\r
+CSET clkout3_requested_duty_cycle=50.000\r
+CSET clkout3_requested_out_freq=100.000\r
+CSET clkout3_requested_phase=0.000\r
+CSET clkout3_used=false\r
+CSET clkout4_drives=BUFG\r
+CSET clkout4_requested_duty_cycle=50.000\r
+CSET clkout4_requested_out_freq=100.000\r
+CSET clkout4_requested_phase=0.000\r
+CSET clkout4_used=false\r
+CSET clkout5_drives=BUFG\r
+CSET clkout5_requested_duty_cycle=50.000\r
+CSET clkout5_requested_out_freq=100.000\r
+CSET clkout5_requested_phase=0.000\r
+CSET clkout5_used=false\r
+CSET clkout6_drives=BUFG\r
+CSET clkout6_requested_duty_cycle=50.000\r
+CSET clkout6_requested_out_freq=100.000\r
+CSET clkout6_requested_phase=0.000\r
+CSET clkout6_used=false\r
+CSET clkout7_drives=BUFG\r
+CSET clkout7_requested_duty_cycle=50.000\r
+CSET clkout7_requested_out_freq=100.000\r
+CSET clkout7_requested_phase=0.000\r
+CSET clkout7_used=false\r
+CSET clock_mgr_type=MANUAL\r
+CSET component_name=clockmodule80M\r
+CSET daddr_port=DADDR\r
+CSET dclk_port=DCLK\r
+CSET dcm_clk_feedback=1X\r
+CSET dcm_clk_out1_port=CLK0\r
+CSET dcm_clk_out2_port=CLK0\r
+CSET dcm_clk_out3_port=CLK0\r
+CSET dcm_clk_out4_port=CLK0\r
+CSET dcm_clk_out5_port=CLK0\r
+CSET dcm_clk_out6_port=CLK0\r
+CSET dcm_clkdv_divide=2.0\r
+CSET dcm_clkfx_divide=1\r
+CSET dcm_clkfx_multiply=4\r
+CSET dcm_clkgen_clk_out1_port=CLKFX\r
+CSET dcm_clkgen_clk_out2_port=CLKFX\r
+CSET dcm_clkgen_clk_out3_port=CLKFX\r
+CSET dcm_clkgen_clkfx_divide=1\r
+CSET dcm_clkgen_clkfx_md_max=0.000\r
+CSET dcm_clkgen_clkfx_multiply=4\r
+CSET dcm_clkgen_clkfxdv_divide=2\r
+CSET dcm_clkgen_clkin_period=10.000\r
+CSET dcm_clkgen_notes=None\r
+CSET dcm_clkgen_spread_spectrum=NONE\r
+CSET dcm_clkgen_startup_wait=false\r
+CSET dcm_clkin_divide_by_2=false\r
+CSET dcm_clkin_period=10.000\r
+CSET dcm_clkout_phase_shift=NONE\r
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
+CSET dcm_notes=None\r
+CSET dcm_phase_shift=0\r
+CSET dcm_pll_cascade=NONE\r
+CSET dcm_startup_wait=false\r
+CSET den_port=DEN\r
+CSET din_port=DIN\r
+CSET dout_port=DOUT\r
+CSET drdy_port=DRDY\r
+CSET dwe_port=DWE\r
+CSET feedback_source=FDBK_AUTO\r
+CSET in_freq_units=Units_MHz\r
+CSET in_jitter_units=Units_UI\r
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
+CSET jitter_options=UI\r
+CSET jitter_sel=No_Jitter\r
+CSET locked_port=LOCKED\r
+CSET mmcm_bandwidth=OPTIMIZED\r
+CSET mmcm_clkfbout_mult_f=43.000\r
+CSET mmcm_clkfbout_phase=0.000\r
+CSET mmcm_clkfbout_use_fine_ps=false\r
+CSET mmcm_clkin1_period=6.430\r
+CSET mmcm_clkin2_period=10.000\r
+CSET mmcm_clkout0_divide_f=13.375\r
+CSET mmcm_clkout0_duty_cycle=0.500\r
+CSET mmcm_clkout0_phase=0.000\r
+CSET mmcm_clkout0_use_fine_ps=false\r
+CSET mmcm_clkout1_divide=1\r
+CSET mmcm_clkout1_duty_cycle=0.500\r
+CSET mmcm_clkout1_phase=0.000\r
+CSET mmcm_clkout1_use_fine_ps=false\r
+CSET mmcm_clkout2_divide=1\r
+CSET mmcm_clkout2_duty_cycle=0.500\r
+CSET mmcm_clkout2_phase=0.000\r
+CSET mmcm_clkout2_use_fine_ps=false\r
+CSET mmcm_clkout3_divide=1\r
+CSET mmcm_clkout3_duty_cycle=0.500\r
+CSET mmcm_clkout3_phase=0.000\r
+CSET mmcm_clkout3_use_fine_ps=false\r
+CSET mmcm_clkout4_cascade=false\r
+CSET mmcm_clkout4_divide=1\r
+CSET mmcm_clkout4_duty_cycle=0.500\r
+CSET mmcm_clkout4_phase=0.000\r
+CSET mmcm_clkout4_use_fine_ps=false\r
+CSET mmcm_clkout5_divide=1\r
+CSET mmcm_clkout5_duty_cycle=0.500\r
+CSET mmcm_clkout5_phase=0.000\r
+CSET mmcm_clkout5_use_fine_ps=false\r
+CSET mmcm_clkout6_divide=1\r
+CSET mmcm_clkout6_duty_cycle=0.500\r
+CSET mmcm_clkout6_phase=0.000\r
+CSET mmcm_clkout6_use_fine_ps=false\r
+CSET mmcm_clock_hold=false\r
+CSET mmcm_compensation=ZHOLD\r
+CSET mmcm_divclk_divide=5\r
+CSET mmcm_notes=None\r
+CSET mmcm_ref_jitter1=0.010\r
+CSET mmcm_ref_jitter2=0.010\r
+CSET mmcm_startup_wait=false\r
+CSET num_out_clks=1\r
+CSET override_dcm=false\r
+CSET override_dcm_clkgen=false\r
+CSET override_mmcm=false\r
+CSET override_pll=false\r
+CSET platform=nt64\r
+CSET pll_bandwidth=OPTIMIZED\r
+CSET pll_clk_feedback=CLKFBOUT\r
+CSET pll_clkfbout_mult=4\r
+CSET pll_clkfbout_phase=0.000\r
+CSET pll_clkin_period=10.000\r
+CSET pll_clkout0_divide=1\r
+CSET pll_clkout0_duty_cycle=0.500\r
+CSET pll_clkout0_phase=0.000\r
+CSET pll_clkout1_divide=1\r
+CSET pll_clkout1_duty_cycle=0.500\r
+CSET pll_clkout1_phase=0.000\r
+CSET pll_clkout2_divide=1\r
+CSET pll_clkout2_duty_cycle=0.500\r
+CSET pll_clkout2_phase=0.000\r
+CSET pll_clkout3_divide=1\r
+CSET pll_clkout3_duty_cycle=0.500\r
+CSET pll_clkout3_phase=0.000\r
+CSET pll_clkout4_divide=1\r
+CSET pll_clkout4_duty_cycle=0.500\r
+CSET pll_clkout4_phase=0.000\r
+CSET pll_clkout5_divide=1\r
+CSET pll_clkout5_duty_cycle=0.500\r
+CSET pll_clkout5_phase=0.000\r
+CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
+CSET pll_divclk_divide=1\r
+CSET pll_notes=None\r
+CSET pll_ref_jitter=0.010\r
+CSET power_down_port=POWER_DOWN\r
+CSET prim_in_freq=155.52\r
+CSET prim_in_jitter=0.010\r
+CSET prim_source=No_buffer\r
+CSET primary_port=CLK_IN1\r
+CSET primitive=MMCM\r
+CSET primtype_sel=MMCM_ADV\r
+CSET psclk_port=PSCLK\r
+CSET psdone_port=PSDONE\r
+CSET psen_port=PSEN\r
+CSET psincdec_port=PSINCDEC\r
+CSET relative_inclk=REL_PRIMARY\r
+CSET reset_port=RESET\r
+CSET secondary_in_freq=100.000\r
+CSET secondary_in_jitter=0.010\r
+CSET secondary_port=CLK_IN2\r
+CSET secondary_source=Single_ended_clock_capable_pin\r
+CSET ss_mod_freq=250\r
+CSET ss_mode=CENTER_HIGH\r
+CSET status_port=STATUS\r
+CSET summary_strings=empty\r
+CSET use_clk_valid=false\r
+CSET use_clkfb_stopped=false\r
+CSET use_dyn_phase_shift=false\r
+CSET use_dyn_reconfig=false\r
+CSET use_freeze=false\r
+CSET use_freq_synth=true\r
+CSET use_inclk_stopped=false\r
+CSET use_inclk_switchover=false\r
+CSET use_locked=true\r
+CSET use_max_i_jitter=false\r
+CSET use_min_o_jitter=false\r
+CSET use_min_power=false\r
+CSET use_phase_alignment=true\r
+CSET use_power_down=false\r
+CSET use_reset=false\r
+CSET use_spread_spectrum=false\r
+CSET use_spread_spectrum_1=false\r
+CSET use_status=false\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-05-10T12:44:55Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: c8df1962\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="clockmodule80M.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="clockmodule80M.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80M|xilinx" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80M.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80M" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80M" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:35:49" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A77989C9A5740C8BC9FB6A41BD011E7" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/clockmodule80M" xil_pn:name="clockmodule80M.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 clockmodule80to80M
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 0 432 32 432
+PIN 0 432 LEFT 36
+PINATTR PinName reset
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 272 576 272
+PIN 608 272 RIGHT 36
+PINATTR PinName clk_out3
+PINATTR Polarity OUT
+LINE Normal 608 368 576 368
+PIN 608 368 RIGHT 36
+PINATTR PinName clk_out4
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80to80M.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80to80M.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80to80M.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5501743936565268942" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6677609659508388402" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1239178134026909054" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+# file: clockmodule80to80M.ucf\r
+# \r
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+# \r
+# This file contains confidential and proprietary information\r
+# of Xilinx, Inc. and is protected under U.S. and\r
+# international copyright and other intellectual property\r
+# laws.\r
+# \r
+# DISCLAIMER\r
+# This disclaimer is not a license and does not grant any\r
+# rights to the materials distributed herewith. Except as\r
+# otherwise provided in a valid license issued to you by\r
+# Xilinx, and to the maximum extent permitted by applicable\r
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+# (2) Xilinx shall not be liable (whether in contract or tort,\r
+# including negligence, or under any other theory of\r
+# liability) for any loss or damage of any kind or nature\r
+# related to, arising under or in connection with these\r
+# materials, including for any direct, or any indirect,\r
+# special, incidental, or consequential loss or damage\r
+# (including loss of data, profits, goodwill, or any type of\r
+# loss or damage suffered as a result of any action brought\r
+# by a third party) even if such damage or loss was\r
+# reasonably foreseeable or Xilinx had been advised of the\r
+# possibility of the same.\r
+# \r
+# CRITICAL APPLICATIONS\r
+# Xilinx products are not designed or intended to be fail-\r
+# safe, or for use in any application requiring fail-safe\r
+# performance, such as life-support or safety devices or\r
+# systems, Class III medical devices, nuclear facilities,\r
+# applications related to the deployment of airbags, or any\r
+# other applications that could lead to death, personal\r
+# injury, or severe property or environmental damage\r
+# (individually and collectively, "Critical\r
+# Applications"). Customer assumes the sole risk and\r
+# liability of any use of Xilinx products in Critical\r
+# Applications, subject only to applicable laws and\r
+# regulations governing limitations on product liability.\r
+# \r
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+# PART OF THIS FILE AT ALL TIMES.\r
+# \r
+\r
+# Input clock periods. These duplicate the values entered for the\r
+# input clocks. You can use these to time your system\r
+#----------------------------------------------------------------\r
+NET "CLK_IN1" TNM_NET = "CLK_IN1";\r
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 10.000 ns HIGH 50% INPUT_JITTER 100.0ps;\r
+\r
+\r
+# FALSE PATH constraints \r
+PIN "RESET" TIG;\r
+\r
--- /dev/null
+-- file: clockmodule80to80M.vhd\r
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____40.000______0.000______50.0______174.629____114.212\r
+-- CLK_OUT2____80.000______0.000______50.0______151.652____114.212\r
+-- CLK_OUT3___100.000______0.000______50.0______144.719____114.212\r
+-- CLK_OUT4___200.000______0.000______50.0______126.455____114.212\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary_____________100____________0.010\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.std_logic_arith.all;\r
+use ieee.numeric_std.all;\r
+\r
+library unisim;\r
+use unisim.vcomponents.all;\r
+\r
+entity clockmodule80to80M is\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ CLK_OUT3 : out std_logic;\r
+ CLK_OUT4 : out std_logic;\r
+ -- Status and control signals\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end clockmodule80to80M;\r
+\r
+architecture xilinx of clockmodule80to80M is\r
+ attribute CORE_GENERATION_INFO : string;\r
+ attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80to80M,clk_wiz_v3_6,{component_name=clockmodule80to80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";\r
+ -- Input clock buffering / unused connectors\r
+ signal clkin1 : std_logic;\r
+ -- Output clock buffering / unused connectors\r
+ signal clkfbout : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+ signal clkfboutb_unused : std_logic;\r
+ signal clkout0 : std_logic;\r
+ signal clkout0b_unused : std_logic;\r
+ signal clkout1 : std_logic;\r
+ signal clkout1b_unused : std_logic;\r
+ signal clkout2 : std_logic;\r
+ signal clkout2b_unused : std_logic;\r
+ signal clkout3 : std_logic;\r
+ signal clkout3b_unused : std_logic;\r
+ signal clkout4_unused : std_logic;\r
+ signal clkout5_unused : std_logic;\r
+ signal clkout6_unused : std_logic;\r
+ -- Dynamic programming unused signals\r
+ signal do_unused : std_logic_vector(15 downto 0);\r
+ signal drdy_unused : std_logic;\r
+ -- Dynamic phase shift unused signals\r
+ signal psdone_unused : std_logic;\r
+ -- Unused status signals\r
+ signal clkfbstopped_unused : std_logic;\r
+ signal clkinstopped_unused : std_logic;\r
+begin\r
+\r
+\r
+ -- Input buffering\r
+ --------------------------------------\r
+ clkin1 <= CLK_IN1;\r
+\r
+\r
+ -- Clocking primitive\r
+ --------------------------------------\r
+ -- Instantiation of the MMCM primitive\r
+ -- * Unused inputs are tied off\r
+ -- * Unused outputs are labeled unused\r
+ mmcm_adv_inst : MMCM_ADV\r
+ generic map\r
+ (BANDWIDTH => "OPTIMIZED",\r
+ CLKOUT4_CASCADE => FALSE,\r
+ CLOCK_HOLD => FALSE,\r
+ COMPENSATION => "ZHOLD",\r
+ STARTUP_WAIT => FALSE,\r
+ DIVCLK_DIVIDE => 1,\r
+ CLKFBOUT_MULT_F => 8.000,\r
+ CLKFBOUT_PHASE => 0.000,\r
+ CLKFBOUT_USE_FINE_PS => FALSE,\r
+ CLKOUT0_DIVIDE_F => 20.000,\r
+ CLKOUT0_PHASE => 0.000,\r
+ CLKOUT0_DUTY_CYCLE => 0.500,\r
+ CLKOUT0_USE_FINE_PS => FALSE,\r
+ CLKOUT1_DIVIDE => 10,\r
+ CLKOUT1_PHASE => 0.000,\r
+ CLKOUT1_DUTY_CYCLE => 0.500,\r
+ CLKOUT1_USE_FINE_PS => FALSE,\r
+ CLKOUT2_DIVIDE => 8,\r
+ CLKOUT2_PHASE => 0.000,\r
+ CLKOUT2_DUTY_CYCLE => 0.500,\r
+ CLKOUT2_USE_FINE_PS => FALSE,\r
+ CLKOUT3_DIVIDE => 4,\r
+ CLKOUT3_PHASE => 0.000,\r
+ CLKOUT3_DUTY_CYCLE => 0.500,\r
+ CLKOUT3_USE_FINE_PS => FALSE,\r
+ CLKIN1_PERIOD => 10.000,\r
+ REF_JITTER1 => 0.010)\r
+ port map\r
+ -- Output clocks\r
+ (CLKFBOUT => clkfbout,\r
+ CLKFBOUTB => clkfboutb_unused,\r
+ CLKOUT0 => clkout0,\r
+ CLKOUT0B => clkout0b_unused,\r
+ CLKOUT1 => clkout1,\r
+ CLKOUT1B => clkout1b_unused,\r
+ CLKOUT2 => clkout2,\r
+ CLKOUT2B => clkout2b_unused,\r
+ CLKOUT3 => clkout3,\r
+ CLKOUT3B => clkout3b_unused,\r
+ CLKOUT4 => clkout4_unused,\r
+ CLKOUT5 => clkout5_unused,\r
+ CLKOUT6 => clkout6_unused,\r
+ -- Input clock control\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKIN1 => clkin1,\r
+ CLKIN2 => '0',\r
+ -- Tied to always select the primary input clock\r
+ CLKINSEL => '1',\r
+ -- Ports for dynamic reconfiguration\r
+ DADDR => (others => '0'),\r
+ DCLK => '0',\r
+ DEN => '0',\r
+ DI => (others => '0'),\r
+ DO => do_unused,\r
+ DRDY => drdy_unused,\r
+ DWE => '0',\r
+ -- Ports for dynamic phase shift\r
+ PSCLK => '0',\r
+ PSEN => '0',\r
+ PSINCDEC => '0',\r
+ PSDONE => psdone_unused,\r
+ -- Other control and status signals\r
+ LOCKED => LOCKED,\r
+ CLKINSTOPPED => clkinstopped_unused,\r
+ CLKFBSTOPPED => clkfbstopped_unused,\r
+ PWRDWN => '0',\r
+ RST => RESET);\r
+\r
+ -- Output buffering\r
+ -------------------------------------\r
+ clkf_buf : BUFG\r
+ port map\r
+ (O => clkfbout_buf,\r
+ I => clkfbout);\r
+\r
+\r
+ clkout1_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT1,\r
+ I => clkout0);\r
+\r
+\r
+\r
+ clkout2_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT2,\r
+ I => clkout1);\r
+\r
+ clkout3_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT3,\r
+ I => clkout2);\r
+\r
+ clkout4_buf : BUFG\r
+ port map\r
+ (O => CLK_OUT4,\r
+ I => clkout3);\r
+\r
+end xilinx;\r
--- /dev/null
+-- \r
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.\r
+-- \r
+-- This file contains confidential and proprietary information\r
+-- of Xilinx, Inc. and is protected under U.S. and\r
+-- international copyright and other intellectual property\r
+-- laws.\r
+-- \r
+-- DISCLAIMER\r
+-- This disclaimer is not a license and does not grant any\r
+-- rights to the materials distributed herewith. Except as\r
+-- otherwise provided in a valid license issued to you by\r
+-- Xilinx, and to the maximum extent permitted by applicable\r
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+-- (2) Xilinx shall not be liable (whether in contract or tort,\r
+-- including negligence, or under any other theory of\r
+-- liability) for any loss or damage of any kind or nature\r
+-- related to, arising under or in connection with these\r
+-- materials, including for any direct, or any indirect,\r
+-- special, incidental, or consequential loss or damage\r
+-- (including loss of data, profits, goodwill, or any type of\r
+-- loss or damage suffered as a result of any action brought\r
+-- by a third party) even if such damage or loss was\r
+-- reasonably foreseeable or Xilinx had been advised of the\r
+-- possibility of the same.\r
+-- \r
+-- CRITICAL APPLICATIONS\r
+-- Xilinx products are not designed or intended to be fail-\r
+-- safe, or for use in any application requiring fail-safe\r
+-- performance, such as life-support or safety devices or\r
+-- systems, Class III medical devices, nuclear facilities,\r
+-- applications related to the deployment of airbags, or any\r
+-- other applications that could lead to death, personal\r
+-- injury, or severe property or environmental damage\r
+-- (individually and collectively, "Critical\r
+-- Applications"). Customer assumes the sole risk and\r
+-- liability of any use of Xilinx products in Critical\r
+-- Applications, subject only to applicable laws and\r
+-- regulations governing limitations on product liability.\r
+-- \r
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+-- PART OF THIS FILE AT ALL TIMES.\r
+-- \r
+------------------------------------------------------------------------------\r
+-- User entered comments\r
+------------------------------------------------------------------------------\r
+-- None\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Output Output Phase Duty Pk-to-Pk Phase"\r
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"\r
+------------------------------------------------------------------------------\r
+-- CLK_OUT1____40.000______0.000______50.0______174.629____114.212\r
+-- CLK_OUT2____80.000______0.000______50.0______151.652____114.212\r
+-- CLK_OUT3___100.000______0.000______50.0______144.719____114.212\r
+-- CLK_OUT4___200.000______0.000______50.0______126.455____114.212\r
+--\r
+------------------------------------------------------------------------------\r
+-- "Input Clock Freq (MHz) Input Jitter (UI)"\r
+------------------------------------------------------------------------------\r
+-- __primary_____________100____________0.010\r
+\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component clockmodule80to80M\r
+port\r
+ (-- Clock in ports\r
+ CLK_IN1 : in std_logic;\r
+ -- Clock out ports\r
+ CLK_OUT1 : out std_logic;\r
+ CLK_OUT2 : out std_logic;\r
+ CLK_OUT3 : out std_logic;\r
+ CLK_OUT4 : out std_logic;\r
+ -- Status and control signals\r
+ RESET : in std_logic;\r
+ LOCKED : out std_logic\r
+ );\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : clockmodule80to80M\r
+ port map\r
+ (-- Clock in ports\r
+ CLK_IN1 => CLK_IN1,\r
+ -- Clock out ports\r
+ CLK_OUT1 => CLK_OUT1,\r
+ CLK_OUT2 => CLK_OUT2,\r
+ CLK_OUT3 => CLK_OUT3,\r
+ CLK_OUT4 => CLK_OUT4,\r
+ -- Status and control signals\r
+ RESET => RESET,\r
+ LOCKED => LOCKED);\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Wed Nov 26 08:36:53 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:clk_wiz:3.6\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6\r
+# END Select\r
+# BEGIN Parameters\r
+CSET calc_done=DONE\r
+CSET clk_in_sel_port=CLK_IN_SEL\r
+CSET clk_out1_port=CLK_OUT1\r
+CSET clk_out1_use_fine_ps_gui=false\r
+CSET clk_out2_port=CLK_OUT2\r
+CSET clk_out2_use_fine_ps_gui=false\r
+CSET clk_out3_port=CLK_OUT3\r
+CSET clk_out3_use_fine_ps_gui=false\r
+CSET clk_out4_port=CLK_OUT4\r
+CSET clk_out4_use_fine_ps_gui=false\r
+CSET clk_out5_port=CLK_OUT5\r
+CSET clk_out5_use_fine_ps_gui=false\r
+CSET clk_out6_port=CLK_OUT6\r
+CSET clk_out6_use_fine_ps_gui=false\r
+CSET clk_out7_port=CLK_OUT7\r
+CSET clk_out7_use_fine_ps_gui=false\r
+CSET clk_valid_port=CLK_VALID\r
+CSET clkfb_in_n_port=CLKFB_IN_N\r
+CSET clkfb_in_p_port=CLKFB_IN_P\r
+CSET clkfb_in_port=CLKFB_IN\r
+CSET clkfb_in_signaling=SINGLE\r
+CSET clkfb_out_n_port=CLKFB_OUT_N\r
+CSET clkfb_out_p_port=CLKFB_OUT_P\r
+CSET clkfb_out_port=CLKFB_OUT\r
+CSET clkfb_stopped_port=CLKFB_STOPPED\r
+CSET clkin1_jitter_ps=100.0\r
+CSET clkin1_ui_jitter=0.010\r
+CSET clkin2_jitter_ps=100.0\r
+CSET clkin2_ui_jitter=0.010\r
+CSET clkout1_drives=BUFG\r
+CSET clkout1_requested_duty_cycle=50.000\r
+CSET clkout1_requested_out_freq=40.000\r
+CSET clkout1_requested_phase=0.000\r
+CSET clkout2_drives=BUFG\r
+CSET clkout2_requested_duty_cycle=50.000\r
+CSET clkout2_requested_out_freq=80.000\r
+CSET clkout2_requested_phase=0.000\r
+CSET clkout2_used=true\r
+CSET clkout3_drives=BUFG\r
+CSET clkout3_requested_duty_cycle=50.000\r
+CSET clkout3_requested_out_freq=100.000\r
+CSET clkout3_requested_phase=0.000\r
+CSET clkout3_used=true\r
+CSET clkout4_drives=BUFG\r
+CSET clkout4_requested_duty_cycle=50.000\r
+CSET clkout4_requested_out_freq=200\r
+CSET clkout4_requested_phase=0.000\r
+CSET clkout4_used=true\r
+CSET clkout5_drives=BUFG\r
+CSET clkout5_requested_duty_cycle=50.000\r
+CSET clkout5_requested_out_freq=200.000\r
+CSET clkout5_requested_phase=0.000\r
+CSET clkout5_used=false\r
+CSET clkout6_drives=BUFG\r
+CSET clkout6_requested_duty_cycle=50.000\r
+CSET clkout6_requested_out_freq=100.000\r
+CSET clkout6_requested_phase=0.000\r
+CSET clkout6_used=false\r
+CSET clkout7_drives=BUFG\r
+CSET clkout7_requested_duty_cycle=50.000\r
+CSET clkout7_requested_out_freq=100.000\r
+CSET clkout7_requested_phase=0.000\r
+CSET clkout7_used=false\r
+CSET clock_mgr_type=MANUAL\r
+CSET component_name=clockmodule80to80M\r
+CSET daddr_port=DADDR\r
+CSET dclk_port=DCLK\r
+CSET dcm_clk_feedback=1X\r
+CSET dcm_clk_out1_port=CLK0\r
+CSET dcm_clk_out2_port=CLK0\r
+CSET dcm_clk_out3_port=CLK0\r
+CSET dcm_clk_out4_port=CLK0\r
+CSET dcm_clk_out5_port=CLK0\r
+CSET dcm_clk_out6_port=CLK0\r
+CSET dcm_clkdv_divide=2.0\r
+CSET dcm_clkfx_divide=1\r
+CSET dcm_clkfx_multiply=4\r
+CSET dcm_clkgen_clk_out1_port=CLKFX\r
+CSET dcm_clkgen_clk_out2_port=CLKFX\r
+CSET dcm_clkgen_clk_out3_port=CLKFX\r
+CSET dcm_clkgen_clkfx_divide=1\r
+CSET dcm_clkgen_clkfx_md_max=0.000\r
+CSET dcm_clkgen_clkfx_multiply=4\r
+CSET dcm_clkgen_clkfxdv_divide=2\r
+CSET dcm_clkgen_clkin_period=10.000\r
+CSET dcm_clkgen_notes=None\r
+CSET dcm_clkgen_spread_spectrum=NONE\r
+CSET dcm_clkgen_startup_wait=false\r
+CSET dcm_clkin_divide_by_2=false\r
+CSET dcm_clkin_period=10.000\r
+CSET dcm_clkout_phase_shift=NONE\r
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS\r
+CSET dcm_notes=None\r
+CSET dcm_phase_shift=0\r
+CSET dcm_pll_cascade=NONE\r
+CSET dcm_startup_wait=false\r
+CSET den_port=DEN\r
+CSET din_port=DIN\r
+CSET dout_port=DOUT\r
+CSET drdy_port=DRDY\r
+CSET dwe_port=DWE\r
+CSET feedback_source=FDBK_AUTO\r
+CSET in_freq_units=Units_MHz\r
+CSET in_jitter_units=Units_UI\r
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED\r
+CSET jitter_options=UI\r
+CSET jitter_sel=No_Jitter\r
+CSET locked_port=LOCKED\r
+CSET mmcm_bandwidth=OPTIMIZED\r
+CSET mmcm_clkfbout_mult_f=8.000\r
+CSET mmcm_clkfbout_phase=0.000\r
+CSET mmcm_clkfbout_use_fine_ps=false\r
+CSET mmcm_clkin1_period=10.000\r
+CSET mmcm_clkin2_period=10.000\r
+CSET mmcm_clkout0_divide_f=20.000\r
+CSET mmcm_clkout0_duty_cycle=0.500\r
+CSET mmcm_clkout0_phase=0.000\r
+CSET mmcm_clkout0_use_fine_ps=false\r
+CSET mmcm_clkout1_divide=10\r
+CSET mmcm_clkout1_duty_cycle=0.500\r
+CSET mmcm_clkout1_phase=0.000\r
+CSET mmcm_clkout1_use_fine_ps=false\r
+CSET mmcm_clkout2_divide=8\r
+CSET mmcm_clkout2_duty_cycle=0.500\r
+CSET mmcm_clkout2_phase=0.000\r
+CSET mmcm_clkout2_use_fine_ps=false\r
+CSET mmcm_clkout3_divide=4\r
+CSET mmcm_clkout3_duty_cycle=0.500\r
+CSET mmcm_clkout3_phase=0.000\r
+CSET mmcm_clkout3_use_fine_ps=false\r
+CSET mmcm_clkout4_cascade=false\r
+CSET mmcm_clkout4_divide=4\r
+CSET mmcm_clkout4_duty_cycle=0.500\r
+CSET mmcm_clkout4_phase=0.000\r
+CSET mmcm_clkout4_use_fine_ps=false\r
+CSET mmcm_clkout5_divide=1\r
+CSET mmcm_clkout5_duty_cycle=0.500\r
+CSET mmcm_clkout5_phase=0.000\r
+CSET mmcm_clkout5_use_fine_ps=false\r
+CSET mmcm_clkout6_divide=1\r
+CSET mmcm_clkout6_duty_cycle=0.500\r
+CSET mmcm_clkout6_phase=0.000\r
+CSET mmcm_clkout6_use_fine_ps=false\r
+CSET mmcm_clock_hold=false\r
+CSET mmcm_compensation=ZHOLD\r
+CSET mmcm_divclk_divide=1\r
+CSET mmcm_notes=None\r
+CSET mmcm_ref_jitter1=0.010\r
+CSET mmcm_ref_jitter2=0.010\r
+CSET mmcm_startup_wait=false\r
+CSET num_out_clks=4\r
+CSET override_dcm=false\r
+CSET override_dcm_clkgen=false\r
+CSET override_mmcm=false\r
+CSET override_pll=false\r
+CSET platform=nt64\r
+CSET pll_bandwidth=OPTIMIZED\r
+CSET pll_clk_feedback=CLKFBOUT\r
+CSET pll_clkfbout_mult=4\r
+CSET pll_clkfbout_phase=0.000\r
+CSET pll_clkin_period=10.000\r
+CSET pll_clkout0_divide=1\r
+CSET pll_clkout0_duty_cycle=0.500\r
+CSET pll_clkout0_phase=0.000\r
+CSET pll_clkout1_divide=1\r
+CSET pll_clkout1_duty_cycle=0.500\r
+CSET pll_clkout1_phase=0.000\r
+CSET pll_clkout2_divide=1\r
+CSET pll_clkout2_duty_cycle=0.500\r
+CSET pll_clkout2_phase=0.000\r
+CSET pll_clkout3_divide=1\r
+CSET pll_clkout3_duty_cycle=0.500\r
+CSET pll_clkout3_phase=0.000\r
+CSET pll_clkout4_divide=1\r
+CSET pll_clkout4_duty_cycle=0.500\r
+CSET pll_clkout4_phase=0.000\r
+CSET pll_clkout5_divide=1\r
+CSET pll_clkout5_duty_cycle=0.500\r
+CSET pll_clkout5_phase=0.000\r
+CSET pll_compensation=SYSTEM_SYNCHRONOUS\r
+CSET pll_divclk_divide=1\r
+CSET pll_notes=None\r
+CSET pll_ref_jitter=0.010\r
+CSET power_down_port=POWER_DOWN\r
+CSET prim_in_freq=100\r
+CSET prim_in_jitter=0.010\r
+CSET prim_source=No_buffer\r
+CSET primary_port=CLK_IN1\r
+CSET primitive=MMCM\r
+CSET primtype_sel=MMCM_ADV\r
+CSET psclk_port=PSCLK\r
+CSET psdone_port=PSDONE\r
+CSET psen_port=PSEN\r
+CSET psincdec_port=PSINCDEC\r
+CSET relative_inclk=REL_PRIMARY\r
+CSET reset_port=RESET\r
+CSET secondary_in_freq=100.000\r
+CSET secondary_in_jitter=0.010\r
+CSET secondary_port=CLK_IN2\r
+CSET secondary_source=Single_ended_clock_capable_pin\r
+CSET ss_mod_freq=250\r
+CSET ss_mode=CENTER_HIGH\r
+CSET status_port=STATUS\r
+CSET summary_strings=empty\r
+CSET use_clk_valid=false\r
+CSET use_clkfb_stopped=false\r
+CSET use_dyn_phase_shift=false\r
+CSET use_dyn_reconfig=false\r
+CSET use_freeze=false\r
+CSET use_freq_synth=true\r
+CSET use_inclk_stopped=false\r
+CSET use_inclk_switchover=false\r
+CSET use_locked=true\r
+CSET use_max_i_jitter=false\r
+CSET use_min_o_jitter=false\r
+CSET use_min_power=false\r
+CSET use_phase_alignment=true\r
+CSET use_power_down=false\r
+CSET use_reset=true\r
+CSET use_spread_spectrum=false\r
+CSET use_spread_spectrum_1=false\r
+CSET use_status=false\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-05-10T12:44:55Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: f0b0ba04\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="clockmodule80to80M.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="clockmodule80to80M.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80to80M|xilinx" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80to80M.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80to80M" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80to80M" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:37:18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5931B5D0516D4A0896A5522B5D44137B" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/clockmodule80to80M" xil_pn:name="clockmodule80to80M.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET package = ff484\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
+$b25
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0;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::50;3xLg`33td9>:;50;3xLg`33td9>:850;3xLg`33td9>:950;3xLg`33td9>:650;3xLg`33td9>:750;3xLg`33td9>:o50;3xLg`33td9>:l50;3xLg`33td9>:m50;3xLg`33td9>:j50;3xLg`33td9>:k50;3xLg`33td9>:h50;3xLg`33td9>5>50;3xLg`33td9>5?50;3xLg`33td9>5<50;3xLg`33td9>5=50;3xLg`33td9>5:50;3xLg`33td9>5;50;3xLg`33td9>5850;3xLg`33td9>5950;3xLg`33td9>5650;3xLg`33td9>5750;3xLg`33td9>5o50;3xLg`33td9>5l50;3xLg`33td9>5m50;3xLg`33td9>5j50;3xLg`33td9>5k50;3xLg`33td9>5h50;3xLg`33td9>4>50;3xLg`33td9>4?50;3xLg`33td9>4<50;3xLg`33td9>4=50;3xLg`33td9>4:50;3xLg`33td9>4;50;3xLg`33td9>4850;3xLg`33td9>4950;3xLg`33td9>4650;3xLg`33td9>4750;3xLg`33td9>4o50;3xLg`33td9>4l50;3xLg`33td9>4m50;3xLg`33td9>4j50;3xLg`33td9>4k50;3xLg`33td9>4h50;3xLg`33td9>l>50;3xLg`33td9>l?50;3xLg`33td9>l<50;3xLg`33td9>l=50;3xLg`33td9>l:50;3xLg`33td9>l;50;3xLg`33td9>l850;3xLg`33td9>l950;3xLg`33td9>l650;3xLg`33td9>l750;3xLg`33td9>lo50;3xLg`33td9>ll50;3xLg`33td9>lm50;3xLg`33td9>lj50;3xLg`33td9>lk50;3xLg`33td9>lh50;3xLg`33td9>o>50;3xLg`33td9>o?50;3xLg`33td9>o<50;3xLg`33td9>o=50;3xLg`33td9>o:50;3xLg`33td9>o;50;3xLg`33td9>o850;3xLg`33td9>o950;3xLg`33td9>o650;3xLg`33td9>o750;3xLg`33td9>oo50;3xLg`33td9>ol50;3xLg`33td9>om50;3xLg`33td9>oj50;3xLg`33td9>ok50;3xLg`33td9>oh50;3xLg`33td9>n>50;3xLg`33td9>n?50;3xLg`33td9>n<50;3xLg`33td9>n=50;3xLg`33td9>n:50;3xLg`33td9>n;50;3xLg`33td9>n850;3xLg`33td9>n950;3xLg`33td9>n650;3xLg`33td9>n750;3xLg`33td9>no50;3xLg`33td9>nl50;3xLg`33td9>nm50;3xLg`33td9>nj50;3xLg`33td9>nk50;3xLg`33td9>nh50;3xLg`33td9>i>50;3xLg`33td9>i?50;3xLg`33td9>i<50;3xLg`33td9>i=50;3xLg`33td9>i:50;3xLg`33td9>i;50;3xLg`33td9>i850;3xLg`33td9>i950;3xLg`33td9>i650;3xLg`33td9>i750;3xLg`33td9>io50;3xLg`33td9>il50;3xLg`33td9>im50;3xLg`33td9>ij50;3xLg`33td9>ik50;3xLg`33td9>ih50;3xLg`33td9>h>50;3xLg`33td9>h?50;3xLg`33td9>h<50;3xLg`33td9>h=50;3xLg`33td9>h:50;3xLg`33td9>h;50;3xLg`33td9>h850;3xLg`33td9>h950;3xLg`33td9>h650;3xLg`33td9>h750;3xLg`33td9>ho50;3xLg`33td9>hl50;3xLg`33td9>hm50;3xLg`33td9>hj50;3xLg`33td9>hk50;3xLg`33td9>hh50;3xLg`33td9>k>50;3xLg`33td9>k?50;3xLg`33td9>k<50;3xLg`33td9>k=50;3xLg`33td9>k:50;3xLg`33td9>k;50;3xLg`33td9>k850;3xLg`33td9>k950;3xLg`33td9>k650;3xLg`33td9>k750;3xLg`33td9>ko50;3xLg`33td9>kl50;3xLg`33td9>km50;3xLg`33td9>kj50;3xLg`33td9>kk50;3xLg`33td9>kh50;3xLg`33td9?=>50;3xLg`33td9?=?50;3xLg`33td9?=<50;3xLg`33td9?==50;3xLg`33td9?=:50;3xLg`33td9?=;50;3xLg`33td9?=850;3xLg`33td9?=950;3xLg`33td9?=650;3xLg`33td9?=750;3xLg`33td9?=o50;3xLg`33td9?=l50;3xLg`33td9?=m50;3xLg`33td9?=j50;3xLg`33td9?=k50;3xLg`33td9?=h50;3xLg`33td9?<>50;3xLg`33td9?<?50;3xLg`33td9?<<50;3xLg`33td9?<=50;3xLg`33td9?<:50;3xLg`33td9?<;50;3xLg`33td9?<850;3xLg`33td9?<950;3xLg`33td9?<650;3xLg`33td9?<750;3xLg`33td9?<o50;3xLg`33td9?<l50;3xLg`33td9?<m50;3xLg`33td9?<j50;3xLg`33td9?<k50;3xLg`33td9?<h50;3xLg`33td9??>50;3xLg`33td9???50;3xLg`33td9??<50;3xLg`33td9??=50;3xLg`33td9??:50;3xLg`33td9??;50;3xLg`33td9??850;3xLg`33td9??950;3xLg`33td9??650;3xLg`33td9??750;3xLg`33td9??o50;3xLg`33td9??l50;3xLg`33td9??m50;3xLg`33td9??j50;3xLg`33td9??k50;3xLg`33td9??h50;3xLg`33td9?>>50;3xLg`33td9?>?50;3xLg`33td9?><50;3xLg`33td9?>=50;3xLg`33td9?>:50;3xLg`33td9?>;50;3xLg`33td9?>850;3xLg`33td9?>950;3xLg`33td9?>650;3xLg`33td9?>750;3xLg`33td9?>o50;3xLg`33td9?>l50;3xLg`33td9?>m50;3xLg`33td9?>j50;3xLg`33td9?>k50;3xLg`33td9?>h50;3xLg`33td9?9>50;3xLg`33td9?9?50;3xLg`33td9?9<50;3xLg`33td9?9=50;3xLg`33td9?9:50;3xLg`33td9?9;50;3xLg`33td9?9850;3xLg`33td9?9950;3xLg`33td9?9650;3xLg`33td9?9750;3xLg`33td9?9o50;3xLg`33td9?9l50;3xLg`33td9?9m50;3xLg`33td9?9j50;3xLg`33td9?9k50;3xLg`33td9?9h50;3xLg`33td9?8>50;3xLg`33td9?8?50;3xLg`33td9?8<50;3xLg`33td9?8=50;3xLg`33td9?8:50;3xLg`33td9?8;50;3xLg`33td9?8850;3xLg`33td9?8950;3xLg`33td9?8650;3xLg`33td9?8750;3xLg`33td9?8o50;3xLg`33td9?8l50;3xLg`33td9?8m50;3xLg`33td9?8j50;3xLg`33td9?8k50;3xLg`33td9?8h50;3xLg`33td9?;>50;3xLg`33td9?;?50;3xLg`33td9?;<50;3xLg`33td9?;=50;3xLg`33td9?;:50;3xLg`33td9?;;50;3xLg`33td9?;850;3xLg`33td9?;950;3xLg`33td9?;650;3xLg`33td9?;750;3xLg`33td9?;o50;3xLg`33td9?;l50;3xLg`33td9?;m50;3xLg`33td9?;j50;3xLg`33td9?;k50;3xLg`33td9?;h50;3xLg`33td9?:>50;3xLg`33td9?:?50;3xLg`33td9?:<50;3xLg`33td9?:=50;3xLg`33td9?::50;3xLg`33td9?:;50;3xLg`33td9?:850;3xLg`33td9?:950;3xLg`33td9?:650;3xLg`33td9?:750;3xLg`33td9?:o50;3xLg`33td9?:l50;3xLg`33td9?:m50;3xLg`33td9?:j50;3xLg`33td9?:k50;3xLg`33td9?:h50;3xLg`33td9?5>50;3xLg`33td9?5?50;3xLg`33td9?5<50;3xLg`33td9?5=50;3xLg`33td9?5:50;3xLg`33td9?5;50;3xLg`33td9?5850;3xLg`33td9?5950;3xLg`33td9?5650;3xLg`33td9?5750;3xLg`33td9?5o50;3xLg`33td9?5l50;3xLg`33td9?5m50;3xLg`33td9?5j50;3xLg`33td9?5k50;3xLg`33td9?5h50;3xLg`33td9?4>50;3xLg`33td9?4?50;3xLg`33td9?4<50;3xLg`33td9?4=50;3xLg`33td9?4:50;3xLg`33td9?4;50;3xLg`33td9?4850;3xLg`33td9?4950;3xLg`33td9?4650;3xLg`33td9?4750;3xLg`33td9?4o50;3xLg`33td9?4l50;3xLg`33td9?4m50;3xLg`33td9?4j50;3xLg`33td9?4k50;3xLg`33td9?4h50;3xLg`33td9?l>50;3xLg`33td9?l?50;3xLg`33td9?l<50;3xLg`33td9?l=50;3xLg`33td9?l:50;3xLg`33td9?l;50;3xLg`33td9?l850;3xLg`33td9?l950;3xLg`33td9?l650;3xLg`33td9?l750;3xLg`33td9?lo50;3xLg`33td9?ll50;3xLg`33td9?lm50;3xLg`33td9?lj50;3xLg`33td9?lk50;3xLg`33twvqMNL{3;`3?7f>123:isO@Cy3yEFWstJK
\ No newline at end of file
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : double_reset.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module DOUBLE_RESET\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity DOUBLE_RESET is\r
+port\r
+(\r
+ CLK : in std_logic;\r
+ PLLLKDET : in std_logic;\r
+ GTXTEST_DONE : out std_logic;\r
+ GTXTEST_BIT1 : out std_logic\r
+);\r
+\r
+end DOUBLE_RESET;\r
+\r
+architecture RTL of DOUBLE_RESET is\r
+--***********************************Parameter Declarations********************\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+ signal plllkdet_sync : std_logic;\r
+ signal plllkdet_r : std_logic;\r
+ signal reset_dly_ctr : unsigned(10 downto 0);\r
+ signal reset_dly_done : std_logic;\r
+ signal testdone_f : std_logic_vector(3 downto 0);\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ plllkdet_r <= PLLLKDET after DLY;\r
+ plllkdet_sync <= plllkdet_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ GTXTEST_BIT1 <= reset_dly_done; \r
+ GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if (plllkdet_sync = '0') then\r
+ reset_dly_ctr <= b"11111111111" after DLY;\r
+ elsif (reset_dly_ctr /= b"00000000000") then\r
+ reset_dly_ctr <= reset_dly_ctr - 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if (plllkdet_sync = '0') then\r
+ reset_dly_done <= '0' after DLY;\r
+ elsif (reset_dly_ctr(10) = '0') then\r
+ reset_dly_done <= reset_dly_ctr(8) after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if(reset_dly_ctr /= b"00000000000") then\r
+ testdone_f <= b"1111" after DLY;\r
+ else\r
+ testdone_f <= '0' & testdone_f(3 downto 1) after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+\r
+end RTL;\r
--- /dev/null
+ Core Name: Xilinx LogiCORE FIFO Generator
+ Version: 8.3
+ Release Date: October 19, 2011
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+
+2. NEW FEATURES
+
+ - ISE 13.3 software support
+ - QVirtex-6L device support
+
+3. SUPPORTED DEVICES
+
+ The following device families are supported by the core for this release.
+
+ - Zynq-7000*
+
+ - Virtex-7
+ - Virtex-7 XT (7vx485t)
+ - Virtex-7 -2L
+
+ - Kintex-7
+ - Kintex-7 -2L
+
+ - Artix-7*
+
+ - Virtex-6 XC CXT/LXT/SXT/HXT
+ - Virtex-6 XQ LXT/SXT
+ - Virtex-6 -1L XC LXT/SXT
+
+ - Spartan-6 XC LX/LXT
+ - Spartan-6 XA
+ - Spartan-6 XQ LX/LXT
+ - Spartan-6 -1L XC LX
+
+ - Virtex-5 XC LX/LXT/SXT/TXT/FXT
+ - Virtex-5 XQ LX/ LXT/SXT/FXT
+
+ - Virtex-4 XC LX/SX/FX
+ - Virtex-4 XQ LX/SX/FX
+ - Virtex-4 XQR LX/SX/FX
+
+ - Spartan-3 XC
+ - Spartan-3 XA
+ - Spartan-3A XC 3A / 3A DSP / 3AN DSP
+ - Spartan-3A XA 3A / 3A DSP
+ - Spartan-3E XC
+ - Spartan-3E XA
+
+*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
+
+4. RESOLVED ISSUES
+
+
+5. KNOWN ISSUES
+
+ The following are known issues for v8.2 of this core at time of release:
+
+ - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+ into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
+ page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+ - CR 467240
+ - AR 31379
+
+ - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+ correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+
+ Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+ For more information and additional workaround see Answer Record 41099.
+
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes User Guide
+ located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT
+
+ To obtain technical support, create a WebCase at www.xilinx.com/support.
+ Questions are routed to a team with expertise using this product.
+
+ Xilinx provides technical support for use of this product when used
+ according to the guidelines described in the core documentation, and
+ cannot guarantee timing, functionality, or support of this product for
+ designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+
+Date By Version Description
+================================================================================
+09/28/2011 Xilinx, Inc. 8.3 ISE 13.3 support and QVirtex-6L and QSpartan-6 device support
+06/22/2011 Xilinx, Inc. 8.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
+03/01/2011 Xilinx, Inc. 8.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010 Xilinx, Inc. 7.3 ISE 13.0.2 support
+09/21/2010 Xilinx, Inc. 7.2 ISE 12.3 support; AXI4 Support
+07/30/2010 Xilinx, Inc. 7.1 ISE 13.0.1 support
+06/18/2010 Xilinx, Inc. 6.2 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
+08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
+05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
+04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : frame_check.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module FRAME_CHECK\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
+use std.textio.all;\r
+use ieee.std_logic_textio.all;\r
+use ieee.std_logic_misc.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity FRAME_CHECK is\r
+generic\r
+(\r
+ RX_DATA_WIDTH : integer := 16;\r
+ RXCTRL_WIDTH : integer := 2;\r
+ USE_COMMA : integer := 1;\r
+ NONE_MSB_FIRST_DEC : integer := 0;\r
+ COMMA_DOUBLE_DEC : integer := 0;\r
+ CHANBOND_SEQ_LEN : integer := 1;\r
+ WORDS_IN_BRAM : integer := 256;\r
+ CONFIG_INDEPENDENT_LANES : integer := 0;\r
+ START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
+ COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
+);\r
+port\r
+(\r
+ -- User Interface\r
+ RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0); \r
+ RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
+ \r
+ RX_ENMCOMMA_ALIGN : out std_logic;\r
+ RX_ENPCOMMA_ALIGN : out std_logic;\r
+ RX_ENCHAN_SYNC : out std_logic; \r
+ RX_CHANBOND_SEQ : in std_logic; \r
+\r
+ -- Control Interface\r
+ INC_IN : in std_logic; \r
+ INC_OUT : out std_logic; \r
+ PATTERN_MATCH_N : out std_logic;\r
+ RESET_ON_ERROR : in std_logic; \r
+ \r
+ -- Error Monitoring\r
+ ERROR_COUNT : out std_logic_vector(7 downto 0);\r
+ \r
+ -- Track Data\r
+ TRACK_DATA : out std_logic;\r
+ \r
+ -- System Interface\r
+ USER_CLK : in std_logic; \r
+ SYSTEM_RESET : in std_logic\r
+ \r
+);\r
+\r
+\r
+end FRAME_CHECK;\r
+\r
+\r
+architecture RTL of FRAME_CHECK is\r
+\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--***************************Internal Register Declarations********************\r
+\r
+ signal begin_r : std_logic;\r
+ signal data_error_detected_r : std_logic;\r
+ signal error_count_r : unsigned(8 downto 0);\r
+ signal error_detected_r : std_logic;\r
+ signal read_counter_i : unsigned(8 downto 0); \r
+ signal rx_chanbond_seq_r : std_logic;\r
+ signal rx_chanbond_seq_r2 : std_logic;\r
+ signal rx_chanbond_seq_r3 : std_logic;\r
+ signal rx_data_r : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r2 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r3 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r4 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r5 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r6 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r7 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r_track : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rxctrl_r : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_r2 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_r3 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_or : std_logic;\r
+ signal start_of_packet_detected_r : std_logic; \r
+ signal track_data_r : std_logic;\r
+ signal track_data_r2 : std_logic;\r
+ signal track_data_r3 : std_logic;\r
+ signal track_data_r4 : std_logic;\r
+ signal sel : std_logic_vector(1 downto 0);\r
+ signal bram_data_r : std_logic_vector(31 downto 0);\r
+ \r
+ \r
+--*********************************Wire Declarations***************************\r
+ \r
+ signal bram_data_i : std_logic_vector(31 downto 0);\r
+\r
+ signal chanbondseq_in_data : std_logic;\r
+ signal error_detected_c : std_logic;\r
+ signal input_to_chanbond_data_i : std_logic;\r
+ signal input_to_chanbond_reg_i : std_logic;\r
+ signal next_begin_c : std_logic;\r
+ signal next_data_error_detected_c : std_logic;\r
+ signal next_track_data_c : std_logic;\r
+ signal start_of_packet_detected_c : std_logic;\r
+ signal rx_chanbond_reg : std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);\r
+ signal rx_chanbond_reg_bitwise_or_i: std_logic;\r
+ signal rx_data_aligned : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_has_start_char_c : std_logic;\r
+ signal rx_data_matches_bram_c : std_logic;\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+\r
+\r
+--*********************************Main Body of Code***************************\r
+begin\r
+\r
+ --_______________________ Static signal Assigments _______________________ \r
+\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_vcc_i <= '1';\r
+\r
+ --______________________ Register RXDATA once to ease timing ______________ \r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rx_data_r <= RX_DATA after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rxctrl_r <= RXCTRL_IN after DLY;\r
+ end if;\r
+ end process;\r
+ --________________________________ State machine __________________________ \r
+ \r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then\r
+ begin_r <= '1' after DLY;\r
+ track_data_r <= '0' after DLY;\r
+ data_error_detected_r <= '0' after DLY;\r
+ else\r
+ begin_r <= next_begin_c after DLY;\r
+ track_data_r <= next_track_data_c after DLY;\r
+ data_error_detected_r <= next_data_error_detected_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_begin_c <= (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;\r
+\r
+ next_track_data_c <= (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);\r
+ \r
+ next_data_error_detected_c <= (track_data_r and error_detected_r); \r
+ \r
+ start_of_packet_detected_c <= INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ start_of_packet_detected_r <= start_of_packet_detected_c after DLY;\r
+ end if; \r
+ end process;\r
+ \r
+ -- Registering for timing\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r2 <= track_data_r after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r3 <= track_data_r2 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r4 <= track_data_r3 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ --______________________________ Capture incoming data ____________________ \r
+\r
+\r
+\r
+datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ rx_data_r2 <= (others => '0') after DLY;\r
+ rx_data_r4 <= (others => '0') after DLY;\r
+ rx_data_r5 <= (others => '0') after DLY;\r
+ rx_data_r6 <= (others => '0') after DLY;\r
+ rx_data_r7 <= (others => '0') after DLY;\r
+ rx_data_r_track <= (others => '0') after DLY;\r
+ else\r
+ rx_data_r2 <= rx_data_r after DLY;\r
+ rx_data_r4 <= rx_data_r3 after DLY;\r
+ rx_data_r5 <= rx_data_r4 after DLY;\r
+ rx_data_r6 <= rx_data_r5 after DLY;\r
+ rx_data_r7 <= rx_data_r6 after DLY;\r
+ rx_data_r_track <= rx_data_r7 after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ rx_data_aligned <= rx_data_r3;\r
+\r
+ --___________________________ Code for Channel bonding ____________________ \r
+ -- code to prevent checking of clock correction sequences for the start of packet char\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rx_chanbond_seq_r <= RX_CHANBOND_SEQ after DLY;\r
+ rx_chanbond_seq_r2 <= rx_chanbond_seq_r after DLY;\r
+ rx_chanbond_seq_r3 <= rx_chanbond_seq_r2 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ input_to_chanbond_reg_i <= rx_chanbond_seq_r2;\r
+ input_to_chanbond_data_i <= tied_to_ground_i;\r
+end generate datapath_width_32_40_16_or_20;\r
+\r
+datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ rx_data_r2 <= (others => '0') after DLY;\r
+ rx_data_r3 <= (others => '0') after DLY;\r
+ rx_data_r4 <= (others => '0') after DLY;\r
+ rx_data_r5 <= (others => '0') after DLY;\r
+ rx_data_r_track <= (others => '0') after DLY;\r
+ else\r
+ rx_data_r2 <= rx_data_r after DLY;\r
+ rx_data_r3 <= rx_data_r2 after DLY;\r
+ rx_data_r4 <= rx_data_r3 after DLY;\r
+ rx_data_r5 <= rx_data_r4 after DLY;\r
+ rx_data_r_track <= rx_data_r5 after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+ \r
+ rx_data_aligned <= RX_DATA;\r
+ input_to_chanbond_reg_i <= RX_CHANBOND_SEQ;\r
+ input_to_chanbond_data_i <= RX_CHANBOND_SEQ;\r
+end generate datapath_width_8_or_10;\r
+\r
+\r
+\r
+ \r
+\r
+\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then\r
+ rxctrl_r2 <= (others => '0') after DLY;\r
+ rxctrl_r3 <= (others => '0') after DLY;\r
+ else\r
+ rxctrl_r2 <= rxctrl_r after DLY;\r
+ rxctrl_r3 <= rxctrl_r2 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ --___________________________ Code for Channel bonding ____________________ \r
+ -- code to prevent checking of clock correction sequences for the start of packet char\r
+ register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate\r
+ case_i_equal_to_0: if (i=0) generate \r
+ rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);\r
+ end generate case_i_equal_to_0;\r
+ case_i_greater_than_0: if (i>0) generate \r
+ rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);\r
+ end generate case_i_greater_than_0;\r
+ end generate register_chan_seq;\r
+ \r
+ chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;\r
+\r
+ process(rx_chanbond_reg)\r
+ variable rx_chanbond_var : std_logic;\r
+ variable i : std_logic;\r
+ begin\r
+ rx_chanbond_var := '0';\r
+ bit_wise_or : for i in 0 to (CHANBOND_SEQ_LEN-1) loop\r
+ rx_chanbond_var := rx_chanbond_var or rx_chanbond_reg(i);\r
+ end loop;\r
+ rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;\r
+ end process;\r
+\r
+ process(RXCTRL_IN)\r
+ variable or_rxctrl_var : std_logic;\r
+ variable i : std_logic;\r
+ begin\r
+ or_rxctrl_var := '0';\r
+ bit_wise_rxctrl_or : for i in 0 to (RXCTRL_WIDTH-1) loop\r
+ or_rxctrl_var := or_rxctrl_var or RXCTRL_IN(i);\r
+ end loop;\r
+ rxctrl_or <= or_rxctrl_var;\r
+ end process;\r
+\r
+\r
+\r
+ rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';\r
+\r
+ --_____________________________ Assign output ports _______________________ \r
+\r
+ TRACK_DATA <= track_data_r; \r
+\r
+\r
+ -- Drive the enamcommaalign port of the mgt for alignment\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENMCOMMA_ALIGN <= '0' after DLY;\r
+ else \r
+ RX_ENMCOMMA_ALIGN <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ -- Drive the enapcommaalign port of the mgt for alignment\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENPCOMMA_ALIGN <= '0' after DLY;\r
+ else \r
+ RX_ENPCOMMA_ALIGN <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ INC_OUT <= start_of_packet_detected_c; \r
+\r
+ PATTERN_MATCH_N <= data_error_detected_r;\r
+\r
+ -- Drive the enchansync port of the mgt for channel bonding\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENCHAN_SYNC <= '0' after DLY;\r
+ else \r
+ RX_ENCHAN_SYNC <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+ \r
+ --___________________________ Check incoming data for errors ______________\r
+ \r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ bram_data_r <= bram_data_i after DLY;\r
+ end if; \r
+ end process;\r
+ \r
+ --An error is detected when data read for the BRAM does not match the incoming data\r
+use_40bit : if RX_DATA_WIDTH = 40 generate\r
+ rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';\r
+end generate use_40bit;\r
+\r
+not_40bit : if RX_DATA_WIDTH /= 40 generate\r
+ rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';\r
+end generate not_40bit;\r
+\r
+ error_detected_c <= track_data_r4 and not rx_data_matches_bram_c; \r
+ \r
+ \r
+enable_error_check : if USE_COMMA = 1 generate\r
+ --We register the error_detected signal for use with the error counter logic\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(not(track_data_r = '1')) then \r
+ error_detected_r <= '0' after DLY;\r
+ else\r
+ error_detected_r <= error_detected_c after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+end generate enable_error_check;\r
+\r
+disable_error_check : if USE_COMMA = 0 generate\r
+ -- Since the comma detect logic has not been enabled, the error counter has been disabled since\r
+ -- it doesnt make sense to be searching for an align character in the data. To enable the error \r
+ -- count again, please see the code above\r
+ \r
+ error_detected_r <= '0';\r
+\r
+end generate disable_error_check;\r
+\r
+ \r
+ --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss\r
+ --errors we did not directly observe. This counter must be reset when it reaches its max value\r
+ process ( USER_CLK )\r
+ begin\r
+ if( USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ error_count_r <= (others => '0') after DLY;\r
+ elsif(error_detected_r = '1') then\r
+ error_count_r <= error_count_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+ \r
+ --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches\r
+ --max value) to the module output\r
+ ERROR_COUNT <= std_logic_vector(error_count_r(7 downto 0));\r
+\r
+ --____________________________ Counter to read from BRAM __________________________ \r
+four_byte : if RX_DATA_WIDTH > 20 generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))) then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ elsif(((start_of_packet_detected_r and not track_data_r)='1')) then\r
+ read_counter_i <= "000000001" after DLY;\r
+ else read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+end generate four_byte;\r
+\r
+one_or_two_byte : if RX_DATA_WIDTH <= 20 generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))\r
+ or ((start_of_packet_detected_r and not track_data_r)='1')) then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ else read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+end generate one_or_two_byte;\r
+\r
+ --________________________________ BRAM Instantiation _____________________________ \r
+\r
+ dual_port_block_ram_i : RAMB16_S36_S36 \r
+ generic map\r
+ (\r
+ INIT_00 => MEM_00,\r
+ INIT_01 => MEM_01,\r
+ INIT_02 => MEM_02,\r
+ INIT_03 => MEM_03,\r
+ INIT_04 => MEM_04,\r
+ INIT_05 => MEM_05,\r
+ INIT_06 => MEM_06,\r
+ INIT_07 => MEM_07,\r
+ INIT_08 => MEM_08,\r
+ INIT_09 => MEM_09,\r
+ INIT_0A => MEM_0A,\r
+ INIT_0B => MEM_0B,\r
+ INIT_0C => MEM_0C,\r
+ INIT_0D => MEM_0D,\r
+ INIT_0E => MEM_0E,\r
+ INIT_0F => MEM_0F,\r
+ INIT_10 => MEM_10,\r
+ INIT_11 => MEM_11,\r
+ INIT_12 => MEM_12,\r
+ INIT_13 => MEM_13,\r
+ INIT_14 => MEM_14,\r
+ INIT_15 => MEM_15,\r
+ INIT_16 => MEM_16,\r
+ INIT_17 => MEM_17,\r
+ INIT_18 => MEM_18,\r
+ INIT_19 => MEM_19,\r
+ INIT_1A => MEM_1A,\r
+ INIT_1B => MEM_1B,\r
+ INIT_1C => MEM_1C,\r
+ INIT_1D => MEM_1D,\r
+ INIT_1E => MEM_1E,\r
+ INIT_1F => MEM_1F,\r
+ INIT_20 => MEM_20,\r
+ INIT_21 => MEM_21,\r
+ INIT_22 => MEM_22,\r
+ INIT_23 => MEM_23,\r
+ INIT_24 => MEM_24,\r
+ INIT_25 => MEM_25,\r
+ INIT_26 => MEM_26,\r
+ INIT_27 => MEM_27,\r
+ INIT_28 => MEM_28,\r
+ INIT_29 => MEM_29,\r
+ INIT_2A => MEM_2A,\r
+ INIT_2B => MEM_2B,\r
+ INIT_2C => MEM_2C,\r
+ INIT_2D => MEM_2D,\r
+ INIT_2E => MEM_2E,\r
+ INIT_2F => MEM_2F,\r
+ INIT_30 => MEM_30,\r
+ INIT_31 => MEM_31,\r
+ INIT_32 => MEM_32,\r
+ INIT_33 => MEM_33,\r
+ INIT_34 => MEM_34,\r
+ INIT_35 => MEM_35,\r
+ INIT_36 => MEM_36,\r
+ INIT_37 => MEM_37,\r
+ INIT_38 => MEM_38,\r
+ INIT_39 => MEM_39,\r
+ INIT_3A => MEM_3A,\r
+ INIT_3B => MEM_3B,\r
+ INIT_3C => MEM_3C,\r
+ INIT_3D => MEM_3D,\r
+ INIT_3E => MEM_3E,\r
+ INIT_3F => MEM_3F,\r
+ INITP_00 => MEMP_00,\r
+ INITP_01 => MEMP_01,\r
+ INITP_02 => MEMP_02,\r
+ INITP_03 => MEMP_03,\r
+ INITP_04 => MEMP_04,\r
+ INITP_05 => MEMP_05,\r
+ INITP_06 => MEMP_06,\r
+ INITP_07 => MEMP_07\r
+\r
+ )\r
+ port map \r
+ (\r
+ ADDRA => std_logic_vector(read_counter_i),\r
+ DIA => tied_to_ground_vec_i(31 downto 0),\r
+ DIPA => tied_to_ground_vec_i(3 downto 0),\r
+ DOA => bram_data_i,\r
+ DOPA => open, \r
+ WEA => tied_to_ground_i,\r
+ ENA => tied_to_vcc_i,\r
+ SSRA => tied_to_ground_i, \r
+ CLKA => USER_CLK,\r
+ \r
+ ADDRB => tied_to_ground_vec_i(8 downto 0),\r
+ DIB => tied_to_ground_vec_i(31 downto 0),\r
+ DIPB => tied_to_ground_vec_i(3 downto 0),\r
+ DOB => open, \r
+ DOPB => open, \r
+ WEB => tied_to_ground_i,\r
+ ENB => tied_to_ground_i,\r
+ SSRB => tied_to_ground_i,\r
+ CLKB => tied_to_ground_i \r
+ ); \r
+ \r
+ \r
+end RTL; \r
+\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : frame_gen.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module FRAME_GEN\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity FRAME_GEN is\r
+generic\r
+(\r
+ WORDS_IN_BRAM : integer := 256;\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
+); \r
+port\r
+(\r
+ -- User Interface\r
+ TX_DATA : out std_logic_vector(39 downto 0);\r
+ TX_CHARISK : out std_logic_vector(3 downto 0); \r
+\r
+ -- System Interface\r
+ USER_CLK : in std_logic; \r
+ SYSTEM_RESET : in std_logic\r
+); \r
+\r
+\r
+end FRAME_GEN;\r
+\r
+architecture RTL of FRAME_GEN is\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--********************************* Wire Declarations************************** \r
+\r
+ signal tx_charisk_i : std_logic_vector(3 downto 0);\r
+ signal tx_data_bram_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal tied_to_vcc_vec_i : std_logic_vector(15 downto 0);\r
+\r
+--***************************Internal signalister Declarations******************** \r
+\r
+ signal read_counter_i : unsigned(8 downto 0); \r
+\r
+\r
+--*********************************Main Body of Code***************************\r
+begin\r
+\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_ground_i <= '0';\r
+ tied_to_vcc_i <= '1';\r
+ \r
+ --__________________________ Counter to read from BRAM ____________________ \r
+ \r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ else\r
+ read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Assign TX_DATA to BRAM output\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ TX_DATA <= (others => '0') after DLY;\r
+ else\r
+ TX_DATA <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Assign TX_CHARISK to BRAM output\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ TX_CHARISK <= (others => '0') after DLY;\r
+ else\r
+ TX_CHARISK <= tx_charisk_i after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ --______________________________ BRAM Instantiation _______________________ \r
+\r
+ dual_port_block_ram_i : RAMB16_S36_S36 \r
+ generic map\r
+ (\r
+ INIT_00 => MEM_00,\r
+ INIT_01 => MEM_01,\r
+ INIT_02 => MEM_02,\r
+ INIT_03 => MEM_03,\r
+ INIT_04 => MEM_04,\r
+ INIT_05 => MEM_05,\r
+ INIT_06 => MEM_06,\r
+ INIT_07 => MEM_07,\r
+ INIT_08 => MEM_08,\r
+ INIT_09 => MEM_09,\r
+ INIT_0A => MEM_0A,\r
+ INIT_0B => MEM_0B,\r
+ INIT_0C => MEM_0C,\r
+ INIT_0D => MEM_0D,\r
+ INIT_0E => MEM_0E,\r
+ INIT_0F => MEM_0F,\r
+ INIT_10 => MEM_10,\r
+ INIT_11 => MEM_11,\r
+ INIT_12 => MEM_12,\r
+ INIT_13 => MEM_13,\r
+ INIT_14 => MEM_14,\r
+ INIT_15 => MEM_15,\r
+ INIT_16 => MEM_16,\r
+ INIT_17 => MEM_17,\r
+ INIT_18 => MEM_18,\r
+ INIT_19 => MEM_19,\r
+ INIT_1A => MEM_1A,\r
+ INIT_1B => MEM_1B,\r
+ INIT_1C => MEM_1C,\r
+ INIT_1D => MEM_1D,\r
+ INIT_1E => MEM_1E,\r
+ INIT_1F => MEM_1F,\r
+ INIT_20 => MEM_20,\r
+ INIT_21 => MEM_21,\r
+ INIT_22 => MEM_22,\r
+ INIT_23 => MEM_23,\r
+ INIT_24 => MEM_24,\r
+ INIT_25 => MEM_25,\r
+ INIT_26 => MEM_26,\r
+ INIT_27 => MEM_27,\r
+ INIT_28 => MEM_28,\r
+ INIT_29 => MEM_29,\r
+ INIT_2A => MEM_2A,\r
+ INIT_2B => MEM_2B,\r
+ INIT_2C => MEM_2C,\r
+ INIT_2D => MEM_2D,\r
+ INIT_2E => MEM_2E,\r
+ INIT_2F => MEM_2F,\r
+ INIT_30 => MEM_30,\r
+ INIT_31 => MEM_31,\r
+ INIT_32 => MEM_32,\r
+ INIT_33 => MEM_33,\r
+ INIT_34 => MEM_34,\r
+ INIT_35 => MEM_35,\r
+ INIT_36 => MEM_36,\r
+ INIT_37 => MEM_37,\r
+ INIT_38 => MEM_38,\r
+ INIT_39 => MEM_39,\r
+ INIT_3A => MEM_3A,\r
+ INIT_3B => MEM_3B,\r
+ INIT_3C => MEM_3C,\r
+ INIT_3D => MEM_3D,\r
+ INIT_3E => MEM_3E,\r
+ INIT_3F => MEM_3F,\r
+ INITP_00 => MEMP_00,\r
+ INITP_01 => MEMP_01,\r
+ INITP_02 => MEMP_02,\r
+ INITP_03 => MEMP_03,\r
+ INITP_04 => MEMP_04,\r
+ INITP_05 => MEMP_05,\r
+ INITP_06 => MEMP_06,\r
+ INITP_07 => MEMP_07\r
+ )\r
+ port map \r
+ (\r
+ ADDRA => std_logic_vector(read_counter_i),\r
+ DIA => tied_to_ground_vec_i(31 downto 0),\r
+ DIPA => tied_to_ground_vec_i(3 downto 0),\r
+ DOA => tx_data_bram_i,\r
+ DOPA => tx_charisk_i, \r
+ WEA => tied_to_ground_i,\r
+ ENA => tied_to_vcc_i,\r
+ SSRA => tied_to_ground_i, \r
+ CLKA => USER_CLK,\r
+ \r
+ ADDRB => tied_to_ground_vec_i(8 downto 0),\r
+ DIB => tied_to_ground_vec_i(31 downto 0),\r
+ DIPB => tied_to_ground_vec_i(3 downto 0),\r
+ DOB => open, \r
+ DOPB => open, \r
+ WEB => tied_to_ground_i,\r
+ ENB => tied_to_ground_i,\r
+ SSRB => tied_to_ground_i,\r
+ CLKB => tied_to_ground_i \r
+ ); \r
+\r
+end RTL;\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="gtxVirtex6FEE80.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="gtxvirtex6fee80.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2856154284446432025" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4212411167637456903" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6456468924679109783" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : gtxvirtex6fee80.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Instantiation Template\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+\r
+\r
+--**************************Component Declarations*****************************\r
+\r
+\r
+component gtxVirtex6FEE80 \r
+generic\r
+(\r
+ -- Simulation attributes\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+ \r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0_Y12)\r
+\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTX0_GTXTEST_IN : in std_logic_vector(12 downto 0);
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+\r
+\r
+);\r
+end component;\r
+\r
+\r
+\r
+component gtxvirtex6fee80_tx_sync \r
+port\r
+(\r
+ TXENPMAPHASEALIGN : out std_logic;\r
+ TXPMASETPHASE : out std_logic;\r
+ TXDLYALIGNDISABLE : out std_logic;\r
+ TXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+component gtxvirtex6fee80_rx_sync \r
+port\r
+(\r
+ RXENPMAPHASEALIGN : out std_logic;\r
+ RXPMASETPHASE : out std_logic;\r
+ RXDLYALIGNDISABLE : out std_logic;\r
+ RXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+\r
+\r
+\r
+\r
+\r
+ ----------------------------- The GTX Wrapper -----------------------------\r
+\r
+\r
+ gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
+ generic map\r
+ (\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP => 1\r
+ )\r
+ port map\r
+ (\r
+ --_____________________________________________________________________\r
+ --_____________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT => ,
+ GTX0_RXDISPERR_OUT => ,
+ GTX0_RXNOTINTABLE_OUT => ,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN => ,
+ GTX0_RXENPCOMMAALIGN_IN => ,
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT => ,
+ GTX0_RXRECCLK_OUT => ,
+ GTX0_RXRESET_IN => ,
+ GTX0_RXUSRCLK2_IN => ,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN => ,
+ GTX0_RXN_IN => ,
+ GTX0_RXP_IN => ,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN => ,
+ GTX0_RXDLYALIGNMONENB_IN => ,
+ GTX0_RXDLYALIGNMONITOR_OUT => ,
+ GTX0_RXDLYALIGNOVERRIDE_IN => ,
+ GTX0_RXDLYALIGNRESET_IN => ,
+ GTX0_RXENPMAPHASEALIGN_IN => ,
+ GTX0_RXPMASETPHASE_IN => ,
+ GTX0_RXSTATUS_OUT => ,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT => ,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN => ,
+ GTX0_MGTREFCLKRX_IN => ,
+ GTX0_PLLRXRESET_IN => ,
+ GTX0_RXPLLLKDET_OUT => ,
+ GTX0_RXRESETDONE_OUT => ,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT => ,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN => ,
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTX0_GTXTEST_IN => ,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN => ,
+ GTX0_TXOUTCLK_OUT => ,
+ GTX0_TXRESET_IN => ,
+ GTX0_TXUSRCLK2_IN => ,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT => ,
+ GTX0_TXP_OUT => ,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN => ,
+ GTX0_TXDLYALIGNMONENB_IN => ,
+ GTX0_TXDLYALIGNMONITOR_OUT => ,
+ GTX0_TXDLYALIGNRESET_IN => ,
+ GTX0_TXENPMAPHASEALIGN_IN => ,
+ GTX0_TXPMASETPHASE_IN => ,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN => ,
+ GTX0_TXRESETDONE_OUT =>
+\r
+\r
+ );\r
+\r
+\r
+\r
+ -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
+ -- Each dedicated refclk you are using in your design will need its own IBUFDS_GTXE1 instance\r
+ \r
+ q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
+ port map\r
+ (\r
+ O => ,\r
+ ODIV2 => ,\r
+ CEB => ,\r
+ I => , -- Connect to package pin L4\r
+ IB => -- Connect to package pin L3\r
+ );\r
+\r
+\r
+\r
+\r
+\r
+ ------------------------------ TXSYNC module ------------------------------\r
+ -- Since you are bypassing the TX Buffer in your wrapper, you will need to drive\r
+ -- the phase alignment ports to align the phase of the TX Datapath. Include\r
+ -- this module in your design to have phase alignment performed automatically as\r
+ -- it is done in the example design.\r
+\r
+ \r
+ gtx0_txsync_i : gtxvirtex6fee80_tx_sync\r
+ port map\r
+ (\r
+ TXENPMAPHASEALIGN => \r
+ TXPMASETPHASE => \r
+ TXDLYALIGNDISABLE => \r
+ TXDLYALIGNRESET => \r
+ SYNC_DONE => \r
+ USER_CLK => \r
+ RESET => ,\r
+ );\r
+\r
+\r
+ ---------------------------- RXSYNC modules -------------------------------\r
+ -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
+ -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
+ \r
+ -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
+ -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
+ -- a stable clock\r
+ \r
+ \r
+ \r
+ gtx0_rxsync_i : gtxvirtex6fee80_rx_sync\r
+ port map\r
+ (\r
+ RXENPMAPHASEALIGN => \r
+ RXPMASETPHASE => \r
+ RXDLYALIGNDISABLE => \r
+ RXDLYALIGNRESET => \r
+ SYNC_DONE => \r
+ USER_CLK => \r
+ RESET => ,\r
+ );\r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Mon Dec 01 12:54:17 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:v6_gtxwizard:1.12\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard xilinx.com:ip:v6_gtxwizard:1.12\r
+# END Select\r
+# BEGIN Parameters\r
+CSET advanced_clocking=false\r
+CSET bytes_to_reduce_error=8\r
+CSET cb_seq_1_1=00000000\r
+CSET cb_seq_1_1_disp=false\r
+CSET cb_seq_1_1_k=false\r
+CSET cb_seq_1_1_mask=true\r
+CSET cb_seq_1_2=00000000\r
+CSET cb_seq_1_2_disp=false\r
+CSET cb_seq_1_2_k=false\r
+CSET cb_seq_1_2_mask=true\r
+CSET cb_seq_1_3=00000000\r
+CSET cb_seq_1_3_disp=false\r
+CSET cb_seq_1_3_k=false\r
+CSET cb_seq_1_3_mask=true\r
+CSET cb_seq_1_4=00000000\r
+CSET cb_seq_1_4_disp=false\r
+CSET cb_seq_1_4_k=false\r
+CSET cb_seq_1_4_mask=true\r
+CSET cb_seq_2_1=00000000\r
+CSET cb_seq_2_1_disp=false\r
+CSET cb_seq_2_1_k=false\r
+CSET cb_seq_2_1_mask=true\r
+CSET cb_seq_2_2=00000000\r
+CSET cb_seq_2_2_disp=false\r
+CSET cb_seq_2_2_k=false\r
+CSET cb_seq_2_2_mask=true\r
+CSET cb_seq_2_3=00000000\r
+CSET cb_seq_2_3_disp=false\r
+CSET cb_seq_2_3_k=false\r
+CSET cb_seq_2_3_mask=true\r
+CSET cb_seq_2_4=00000000\r
+CSET cb_seq_2_4_disp=false\r
+CSET cb_seq_2_4_k=false\r
+CSET cb_seq_2_4_mask=true\r
+CSET cb_sequence_1_max_skew=1\r
+CSET cb_sequence_2_max_skew=1\r
+CSET cb_sequence_length=1\r
+CSET cc_keep_one_idle=false\r
+CSET cc_seq_1_1=00000000\r
+CSET cc_seq_1_1_disp=false\r
+CSET cc_seq_1_1_k=true\r
+CSET cc_seq_1_1_mask=true\r
+CSET cc_seq_1_2=00000000\r
+CSET cc_seq_1_2_disp=false\r
+CSET cc_seq_1_2_k=true\r
+CSET cc_seq_1_2_mask=true\r
+CSET cc_seq_1_3=00000000\r
+CSET cc_seq_1_3_disp=false\r
+CSET cc_seq_1_3_k=true\r
+CSET cc_seq_1_3_mask=true\r
+CSET cc_seq_1_4=00000000\r
+CSET cc_seq_1_4_disp=false\r
+CSET cc_seq_1_4_k=true\r
+CSET cc_seq_1_4_mask=true\r
+CSET cc_seq_2_1=00000000\r
+CSET cc_seq_2_1_disp=false\r
+CSET cc_seq_2_1_k=true\r
+CSET cc_seq_2_1_mask=true\r
+CSET cc_seq_2_2=00000000\r
+CSET cc_seq_2_2_disp=false\r
+CSET cc_seq_2_2_k=true\r
+CSET cc_seq_2_2_mask=true\r
+CSET cc_seq_2_3=00000000\r
+CSET cc_seq_2_3_disp=false\r
+CSET cc_seq_2_3_k=true\r
+CSET cc_seq_2_3_mask=true\r
+CSET cc_seq_2_4=00000000\r
+CSET cc_seq_2_4_disp=false\r
+CSET cc_seq_2_4_k=true\r
+CSET cc_seq_2_4_mask=true\r
+CSET cc_sequence_length=1\r
+CSET cdr_ph_adj_time=10100\r
+CSET chan_bond_keep_align=false\r
+CSET chan_bond_seq_2_cfg=00000\r
+CSET clk_cor_precedence=CC\r
+CSET clk_cor_repeat_wait=0\r
+CSET column=Left\r
+CSET com_burst_val=15\r
+CSET comma_alignment=Any_Byte_Boundary\r
+CSET comma_double=false\r
+CSET comma_mask=1111111100\r
+CSET comma_preset=K28.5\r
+CSET component_name=gtxVirtex6FEE80\r
+CSET dec_mcomma_detect=false\r
+CSET dec_pcomma_detect=false\r
+CSET dec_valid_comma_only=false\r
+CSET decoding=8B/10B\r
+CSET dfe_mode=Fixed_tap_mode\r
+CSET disable_ac_coupling=true\r
+CSET driver_swing=1000\r
+CSET en_idle_reset_buf=false\r
+CSET enable_dfe=false\r
+CSET encoding=8B/10B\r
+CSET errors_to_lose_sync=256\r
+CSET fifo_lower_bounds=14\r
+CSET fifo_upper_bounds=16\r
+CSET highpass_pole_location=Use_RXEQPOLE_Port\r
+CSET max_cb_level=7\r
+CSET mcomma_detect=true\r
+CSET minus_comma=1010000011\r
+CSET oob_clk_divider=0000000\r
+CSET pci_express_mode=false\r
+CSET pcomma_detect=true\r
+CSET pll_sata=false\r
+CSET plus_comma=0101111100\r
+CSET postemphasis_level=00000\r
+CSET ppm_offset=0_(Synchronous)\r
+CSET preemphasis_level=0000\r
+CSET protocol_file=Start_from_scratch\r
+CSET refclk_ac_coupling_x0_y0=false\r
+CSET refclk_ac_coupling_x0_y1=false\r
+CSET refclk_ac_coupling_x0_y10=false\r
+CSET refclk_ac_coupling_x0_y11=false\r
+CSET refclk_ac_coupling_x0_y12=false\r
+CSET refclk_ac_coupling_x0_y13=false\r
+CSET refclk_ac_coupling_x0_y14=false\r
+CSET refclk_ac_coupling_x0_y15=false\r
+CSET refclk_ac_coupling_x0_y16=false\r
+CSET refclk_ac_coupling_x0_y17=false\r
+CSET refclk_ac_coupling_x0_y18=false\r
+CSET refclk_ac_coupling_x0_y19=false\r
+CSET refclk_ac_coupling_x0_y2=false\r
+CSET refclk_ac_coupling_x0_y20=false\r
+CSET refclk_ac_coupling_x0_y21=false\r
+CSET refclk_ac_coupling_x0_y22=false\r
+CSET refclk_ac_coupling_x0_y23=false\r
+CSET refclk_ac_coupling_x0_y3=false\r
+CSET refclk_ac_coupling_x0_y4=false\r
+CSET refclk_ac_coupling_x0_y5=false\r
+CSET refclk_ac_coupling_x0_y6=false\r
+CSET refclk_ac_coupling_x0_y7=false\r
+CSET refclk_ac_coupling_x0_y8=false\r
+CSET refclk_ac_coupling_x0_y9=false\r
+CSET rx_datapath_width=8\r
+CSET rx_decode_seq_match=true\r
+CSET rx_divider=/2\r
+CSET rx_en_idle_hold_cdr=false\r
+CSET rx_en_idle_hold_dfe=true\r
+CSET rx_en_idle_reset_fr=false\r
+CSET rx_en_idle_reset_ph=false\r
+CSET rx_en_mode_reset_buf=true\r
+CSET rx_en_rate_reset_buf=true\r
+CSET rx_en_realign_reset_buf=false\r
+CSET rx_fifo_addr_mode=FULL\r
+CSET rx_idle_hi_cnt=1000\r
+CSET rx_idle_lo_cnt=0000\r
+CSET rx_line_rate=2\r
+CSET rx_oob_threshold=011\r
+CSET rx_refclk_x0_y0=REFCLK1_Q0\r
+CSET rx_refclk_x0_y1=REFCLK1_Q0\r
+CSET rx_refclk_x0_y10=REFCLK1_Q2\r
+CSET rx_refclk_x0_y11=REFCLK1_Q2\r
+CSET rx_refclk_x0_y12=REFCLK0_Q3\r
+CSET rx_refclk_x0_y13=REFCLK1_Q3\r
+CSET rx_refclk_x0_y14=REFCLK1_Q3\r
+CSET rx_refclk_x0_y15=REFCLK1_Q3\r
+CSET rx_refclk_x0_y16=REFCLK1_Q4\r
+CSET rx_refclk_x0_y17=REFCLK1_Q4\r
+CSET rx_refclk_x0_y18=REFCLK1_Q4\r
+CSET rx_refclk_x0_y19=REFCLK1_Q4\r
+CSET rx_refclk_x0_y2=REFCLK1_Q0\r
+CSET rx_refclk_x0_y20=REFCLK1_Q5\r
+CSET rx_refclk_x0_y21=REFCLK1_Q5\r
+CSET rx_refclk_x0_y22=REFCLK1_Q5\r
+CSET rx_refclk_x0_y23=REFCLK1_Q5\r
+CSET rx_refclk_x0_y24=REFCLK1_Q6\r
+CSET rx_refclk_x0_y25=REFCLK1_Q6\r
+CSET rx_refclk_x0_y26=REFCLK1_Q6\r
+CSET rx_refclk_x0_y27=REFCLK1_Q6\r
+CSET rx_refclk_x0_y28=REFCLK1_Q7\r
+CSET rx_refclk_x0_y29=REFCLK1_Q7\r
+CSET rx_refclk_x0_y3=REFCLK1_Q0\r
+CSET rx_refclk_x0_y30=REFCLK1_Q7\r
+CSET rx_refclk_x0_y31=REFCLK1_Q7\r
+CSET rx_refclk_x0_y32=REFCLK1_Q8\r
+CSET rx_refclk_x0_y33=REFCLK1_Q8\r
+CSET rx_refclk_x0_y34=REFCLK1_Q8\r
+CSET rx_refclk_x0_y35=REFCLK1_Q8\r
+CSET rx_refclk_x0_y4=REFCLK1_Q1\r
+CSET rx_refclk_x0_y5=REFCLK1_Q1\r
+CSET rx_refclk_x0_y6=REFCLK1_Q1\r
+CSET rx_refclk_x0_y7=REFCLK1_Q1\r
+CSET rx_refclk_x0_y8=REFCLK1_Q2\r
+CSET rx_refclk_x0_y9=REFCLK1_Q2\r
+CSET rx_reference_clock=80.00\r
+CSET rx_slide_mode=OFF\r
+CSET rx_termination_voltage=MGTAVTT\r
+CSET rxlossofsyncport=true\r
+CSET rxrecclk_source=AUTO\r
+CSET rxrundisp_indicates_cc=false\r
+CSET rxusrclk_source=RXRECCLK\r
+CSET sas_max_comsas=52\r
+CSET sas_min_comsas=40\r
+CSET sata_burst_val=4\r
+CSET sata_idle_val=4\r
+CSET second_order_cdr_loop=false\r
+CSET show_realign_comma=true\r
+CSET sync_app=true\r
+CSET termination_ctrl=00000\r
+CSET termination_imp=50\r
+CSET termination_ovrd=false\r
+CSET trans_time_from_p2=60\r
+CSET trans_time_non_p2=25\r
+CSET trans_time_rate=FF\r
+CSET trans_time_to_p2=100\r
+CSET tx_datapath_width=8\r
+CSET tx_divider=/2\r
+CSET tx_drive_mode=DIRECT\r
+CSET tx_en_rate_reset_buf=true\r
+CSET tx_idle_assert_delay=100\r
+CSET tx_idle_deassert_delay=010\r
+CSET tx_line_rate=2\r
+CSET tx_refclk_x0_y0=use_rx_pll\r
+CSET tx_refclk_x0_y1=use_rx_pll\r
+CSET tx_refclk_x0_y10=use_rx_pll\r
+CSET tx_refclk_x0_y11=use_rx_pll\r
+CSET tx_refclk_x0_y12=use_rx_pll\r
+CSET tx_refclk_x0_y13=use_rx_pll\r
+CSET tx_refclk_x0_y14=use_rx_pll\r
+CSET tx_refclk_x0_y15=use_rx_pll\r
+CSET tx_refclk_x0_y16=use_rx_pll\r
+CSET tx_refclk_x0_y17=use_rx_pll\r
+CSET tx_refclk_x0_y18=use_rx_pll\r
+CSET tx_refclk_x0_y19=use_rx_pll\r
+CSET tx_refclk_x0_y2=use_rx_pll\r
+CSET tx_refclk_x0_y20=use_rx_pll\r
+CSET tx_refclk_x0_y21=use_rx_pll\r
+CSET tx_refclk_x0_y22=use_rx_pll\r
+CSET tx_refclk_x0_y23=use_rx_pll\r
+CSET tx_refclk_x0_y24=use_rx_pll\r
+CSET tx_refclk_x0_y25=use_rx_pll\r
+CSET tx_refclk_x0_y26=use_rx_pll\r
+CSET tx_refclk_x0_y27=use_rx_pll\r
+CSET tx_refclk_x0_y28=use_rx_pll\r
+CSET tx_refclk_x0_y29=use_rx_pll\r
+CSET tx_refclk_x0_y3=use_rx_pll\r
+CSET tx_refclk_x0_y30=use_rx_pll\r
+CSET tx_refclk_x0_y31=use_rx_pll\r
+CSET tx_refclk_x0_y32=use_rx_pll\r
+CSET tx_refclk_x0_y33=use_rx_pll\r
+CSET tx_refclk_x0_y34=use_rx_pll\r
+CSET tx_refclk_x0_y35=use_rx_pll\r
+CSET tx_refclk_x0_y4=use_rx_pll\r
+CSET tx_refclk_x0_y5=use_rx_pll\r
+CSET tx_refclk_x0_y6=use_rx_pll\r
+CSET tx_refclk_x0_y7=use_rx_pll\r
+CSET tx_refclk_x0_y8=use_rx_pll\r
+CSET tx_refclk_x0_y9=use_rx_pll\r
+CSET tx_reference_clock=80.00\r
+CSET tx_tdcc_cfg=11\r
+CSET txoutclk_source=AUTO\r
+CSET txpll_sata=00\r
+CSET txrx_invert=00011\r
+CSET txusrclk_source=TXOUTCLK\r
+CSET use_cb=false\r
+CSET use_cc=false\r
+CSET use_comma_detect=true\r
+CSET use_external_rxusrclk=false\r
+CSET use_external_txusrclk=false\r
+CSET use_gtx_x0_y0=false\r
+CSET use_gtx_x0_y1=false\r
+CSET use_gtx_x0_y10=false\r
+CSET use_gtx_x0_y11=false\r
+CSET use_gtx_x0_y12=true\r
+CSET use_gtx_x0_y13=false\r
+CSET use_gtx_x0_y14=false\r
+CSET use_gtx_x0_y15=false\r
+CSET use_gtx_x0_y16=false\r
+CSET use_gtx_x0_y17=false\r
+CSET use_gtx_x0_y18=false\r
+CSET use_gtx_x0_y19=false\r
+CSET use_gtx_x0_y2=false\r
+CSET use_gtx_x0_y20=false\r
+CSET use_gtx_x0_y21=false\r
+CSET use_gtx_x0_y22=false\r
+CSET use_gtx_x0_y23=false\r
+CSET use_gtx_x0_y24=false\r
+CSET use_gtx_x0_y25=false\r
+CSET use_gtx_x0_y26=false\r
+CSET use_gtx_x0_y27=false\r
+CSET use_gtx_x0_y28=false\r
+CSET use_gtx_x0_y29=false\r
+CSET use_gtx_x0_y3=false\r
+CSET use_gtx_x0_y30=false\r
+CSET use_gtx_x0_y31=false\r
+CSET use_gtx_x0_y32=false\r
+CSET use_gtx_x0_y33=false\r
+CSET use_gtx_x0_y34=false\r
+CSET use_gtx_x0_y35=false\r
+CSET use_gtx_x0_y4=false\r
+CSET use_gtx_x0_y5=false\r
+CSET use_gtx_x0_y6=false\r
+CSET use_gtx_x0_y7=false\r
+CSET use_gtx_x0_y8=false\r
+CSET use_gtx_x0_y9=false\r
+CSET use_no_rx=false\r
+CSET use_no_tx=false\r
+CSET use_port_comfinish=false\r
+CSET use_port_cominitdet=false\r
+CSET use_port_comsasdet=false\r
+CSET use_port_comwakedet=false\r
+CSET use_port_drp=false\r
+CSET use_port_enmcommaalign=true\r
+CSET use_port_enpcommaalign=true\r
+CSET use_port_gtxtest=false\r
+CSET use_port_loopback=false\r
+CSET use_port_phystatus=true\r
+CSET use_port_plllkdet=true\r
+CSET use_port_plllkdeten=true\r
+CSET use_port_pllpowerdown=false\r
+CSET use_port_refclkpowerdown=false\r
+CSET use_port_rxbufreset=false\r
+CSET use_port_rxbufstatus=false\r
+CSET use_port_rxbyteisaligned=false\r
+CSET use_port_rxbyterealign=false\r
+CSET use_port_rxcdrreset=true\r
+CSET use_port_rxchariscomma=false\r
+CSET use_port_rxcharisk=true\r
+CSET use_port_rxcommadet=false\r
+CSET use_port_rxlossofsync=true\r
+CSET use_port_rxoversampleerr=false\r
+CSET use_port_rxpolarity=false\r
+CSET use_port_rxpowerdown=false\r
+CSET use_port_rxrate=false\r
+CSET use_port_rxrecclk=true\r
+CSET use_port_rxreset=true\r
+CSET use_port_rxrundisp=false\r
+CSET use_port_rxslide=false\r
+CSET use_port_rxstatus=true\r
+CSET use_port_rxvalid=false\r
+CSET use_port_txbufstatus=false\r
+CSET use_port_txbypass8b10b=false\r
+CSET use_port_txchardispmode=false\r
+CSET use_port_txchardispval=false\r
+CSET use_port_txcominit=false\r
+CSET use_port_txcomsas=false\r
+CSET use_port_txcomwake=false\r
+CSET use_port_txdetectrx=false\r
+CSET use_port_txelecidle=false\r
+CSET use_port_txenprbstst=false\r
+CSET use_port_txinhibit=false\r
+CSET use_port_txkerr=false\r
+CSET use_port_txoutclk=true\r
+CSET use_port_txpolarity=false\r
+CSET use_port_txpowerdown=false\r
+CSET use_port_txprbsforceerr=false\r
+CSET use_port_txrate=false\r
+CSET use_port_txreset=true\r
+CSET use_port_txrundisp=false\r
+CSET use_prbs_detector=false\r
+CSET use_resistor_cal_circuit=false\r
+CSET use_rx_eq=false\r
+CSET use_rx_oob=false\r
+CSET use_rx_oversampling=false\r
+CSET use_rxbuffer=false\r
+CSET use_rxpllrefclk=false\r
+CSET use_rxprbserr_loopback=false\r
+CSET use_turbo_mode=false\r
+CSET use_two_cb_sequences=false\r
+CSET use_two_cc_sequences=false\r
+CSET use_tx_oversampling=false\r
+CSET use_txbuffer=false\r
+CSET use_txpllrefclk=false\r
+CSET wideband_highpass_mix=000\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2011-04-08T05:24:23Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: dc79b500\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/double_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_check.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+ </file>
+ <file xil_pn:name="gtxvirtex6fee80_gtx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
+ </file>
+ <file xil_pn:name="gtxvirtex6fee80.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/gtx_attributes.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/implement/data_vio.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/implement/icon.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="gtxVirtex6FEE80/implement/ila.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gtxVirtex6FEE80_top|RTL" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gtxVirtex6FEE80_top" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="gtxVirtex6FEE80" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-12-01T13:54:54" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DB12E7AF65204F95AA56371BC098BFF3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : double_reset.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module DOUBLE_RESET\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity DOUBLE_RESET is\r
+port\r
+(\r
+ CLK : in std_logic;\r
+ PLLLKDET : in std_logic;\r
+ GTXTEST_DONE : out std_logic;\r
+ GTXTEST_BIT1 : out std_logic\r
+);\r
+\r
+end DOUBLE_RESET;\r
+\r
+architecture RTL of DOUBLE_RESET is\r
+--***********************************Parameter Declarations********************\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+ signal plllkdet_sync : std_logic;\r
+ signal plllkdet_r : std_logic;\r
+ signal reset_dly_ctr : unsigned(10 downto 0);\r
+ signal reset_dly_done : std_logic;\r
+ signal testdone_f : std_logic_vector(3 downto 0);\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ plllkdet_r <= PLLLKDET after DLY;\r
+ plllkdet_sync <= plllkdet_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ GTXTEST_BIT1 <= reset_dly_done; \r
+ GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if (plllkdet_sync = '0') then\r
+ reset_dly_ctr <= b"11111111111" after DLY;\r
+ elsif (reset_dly_ctr /= b"00000000000") then\r
+ reset_dly_ctr <= reset_dly_ctr - 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if (plllkdet_sync = '0') then\r
+ reset_dly_done <= '0' after DLY;\r
+ elsif (reset_dly_ctr(10) = '0') then\r
+ reset_dly_done <= reset_dly_ctr(8) after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ process(CLK )\r
+ begin\r
+ if(CLK'event and CLK = '1') then\r
+ if(reset_dly_ctr /= b"00000000000") then\r
+ testdone_f <= b"1111" after DLY;\r
+ else\r
+ testdone_f <= '0' & testdone_f(3 downto 1) after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+\r
+end RTL;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : frame_check.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module FRAME_CHECK\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+use ieee.numeric_std.all;\r
+use std.textio.all;\r
+use ieee.std_logic_textio.all;\r
+use ieee.std_logic_misc.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity FRAME_CHECK is\r
+generic\r
+(\r
+ RX_DATA_WIDTH : integer := 16;\r
+ RXCTRL_WIDTH : integer := 2;\r
+ USE_COMMA : integer := 1;\r
+ NONE_MSB_FIRST_DEC : integer := 0;\r
+ COMMA_DOUBLE_DEC : integer := 0;\r
+ CHANBOND_SEQ_LEN : integer := 1;\r
+ WORDS_IN_BRAM : integer := 256;\r
+ CONFIG_INDEPENDENT_LANES : integer := 0;\r
+ START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
+ COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
+);\r
+port\r
+(\r
+ -- User Interface\r
+ RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0); \r
+ RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
+ \r
+ RX_ENMCOMMA_ALIGN : out std_logic;\r
+ RX_ENPCOMMA_ALIGN : out std_logic;\r
+ RX_ENCHAN_SYNC : out std_logic; \r
+ RX_CHANBOND_SEQ : in std_logic; \r
+\r
+ -- Control Interface\r
+ INC_IN : in std_logic; \r
+ INC_OUT : out std_logic; \r
+ PATTERN_MATCH_N : out std_logic;\r
+ RESET_ON_ERROR : in std_logic; \r
+ \r
+ -- Error Monitoring\r
+ ERROR_COUNT : out std_logic_vector(7 downto 0);\r
+ \r
+ -- Track Data\r
+ TRACK_DATA : out std_logic;\r
+ \r
+ -- System Interface\r
+ USER_CLK : in std_logic; \r
+ SYSTEM_RESET : in std_logic\r
+ \r
+);\r
+\r
+\r
+end FRAME_CHECK;\r
+\r
+\r
+architecture RTL of FRAME_CHECK is\r
+\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--***************************Internal Register Declarations********************\r
+\r
+ signal begin_r : std_logic;\r
+ signal data_error_detected_r : std_logic;\r
+ signal error_count_r : unsigned(8 downto 0);\r
+ signal error_detected_r : std_logic;\r
+ signal read_counter_i : unsigned(8 downto 0); \r
+ signal rx_chanbond_seq_r : std_logic;\r
+ signal rx_chanbond_seq_r2 : std_logic;\r
+ signal rx_chanbond_seq_r3 : std_logic;\r
+ signal rx_data_r : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r2 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r3 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r4 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r5 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r6 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r7 : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_r_track : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rxctrl_r : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_r2 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_r3 : std_logic_vector((RXCTRL_WIDTH-1) downto 0);\r
+ signal rxctrl_or : std_logic;\r
+ signal start_of_packet_detected_r : std_logic; \r
+ signal track_data_r : std_logic;\r
+ signal track_data_r2 : std_logic;\r
+ signal track_data_r3 : std_logic;\r
+ signal track_data_r4 : std_logic;\r
+ signal sel : std_logic_vector(1 downto 0);\r
+ signal bram_data_r : std_logic_vector(31 downto 0);\r
+ \r
+ \r
+--*********************************Wire Declarations***************************\r
+ \r
+ signal bram_data_i : std_logic_vector(31 downto 0);\r
+\r
+ signal chanbondseq_in_data : std_logic;\r
+ signal error_detected_c : std_logic;\r
+ signal input_to_chanbond_data_i : std_logic;\r
+ signal input_to_chanbond_reg_i : std_logic;\r
+ signal next_begin_c : std_logic;\r
+ signal next_data_error_detected_c : std_logic;\r
+ signal next_track_data_c : std_logic;\r
+ signal start_of_packet_detected_c : std_logic;\r
+ signal rx_chanbond_reg : std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);\r
+ signal rx_chanbond_reg_bitwise_or_i: std_logic;\r
+ signal rx_data_aligned : std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ signal rx_data_has_start_char_c : std_logic;\r
+ signal rx_data_matches_bram_c : std_logic;\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+\r
+\r
+--*********************************Main Body of Code***************************\r
+begin\r
+\r
+ --_______________________ Static signal Assigments _______________________ \r
+\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_vcc_i <= '1';\r
+\r
+ --______________________ Register RXDATA once to ease timing ______________ \r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rx_data_r <= RX_DATA after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rxctrl_r <= RXCTRL_IN after DLY;\r
+ end if;\r
+ end process;\r
+ --________________________________ State machine __________________________ \r
+ \r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then\r
+ begin_r <= '1' after DLY;\r
+ track_data_r <= '0' after DLY;\r
+ data_error_detected_r <= '0' after DLY;\r
+ else\r
+ begin_r <= next_begin_c after DLY;\r
+ track_data_r <= next_track_data_c after DLY;\r
+ data_error_detected_r <= next_data_error_detected_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_begin_c <= (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;\r
+\r
+ next_track_data_c <= (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);\r
+ \r
+ next_data_error_detected_c <= (track_data_r and error_detected_r); \r
+ \r
+ start_of_packet_detected_c <= INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ start_of_packet_detected_r <= start_of_packet_detected_c after DLY;\r
+ end if; \r
+ end process;\r
+ \r
+ -- Registering for timing\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r2 <= track_data_r after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r3 <= track_data_r2 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ track_data_r4 <= track_data_r3 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ --______________________________ Capture incoming data ____________________ \r
+\r
+\r
+\r
+datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ rx_data_r2 <= (others => '0') after DLY;\r
+ rx_data_r4 <= (others => '0') after DLY;\r
+ rx_data_r5 <= (others => '0') after DLY;\r
+ rx_data_r6 <= (others => '0') after DLY;\r
+ rx_data_r7 <= (others => '0') after DLY;\r
+ rx_data_r_track <= (others => '0') after DLY;\r
+ else\r
+ rx_data_r2 <= rx_data_r after DLY;\r
+ rx_data_r4 <= rx_data_r3 after DLY;\r
+ rx_data_r5 <= rx_data_r4 after DLY;\r
+ rx_data_r6 <= rx_data_r5 after DLY;\r
+ rx_data_r7 <= rx_data_r6 after DLY;\r
+ rx_data_r_track <= rx_data_r7 after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ rx_data_aligned <= rx_data_r3;\r
+\r
+ --___________________________ Code for Channel bonding ____________________ \r
+ -- code to prevent checking of clock correction sequences for the start of packet char\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ rx_chanbond_seq_r <= RX_CHANBOND_SEQ after DLY;\r
+ rx_chanbond_seq_r2 <= rx_chanbond_seq_r after DLY;\r
+ rx_chanbond_seq_r3 <= rx_chanbond_seq_r2 after DLY;\r
+ end if; \r
+ end process;\r
+\r
+ input_to_chanbond_reg_i <= rx_chanbond_seq_r2;\r
+ input_to_chanbond_data_i <= tied_to_ground_i;\r
+end generate datapath_width_32_40_16_or_20;\r
+\r
+datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ rx_data_r2 <= (others => '0') after DLY;\r
+ rx_data_r3 <= (others => '0') after DLY;\r
+ rx_data_r4 <= (others => '0') after DLY;\r
+ rx_data_r5 <= (others => '0') after DLY;\r
+ rx_data_r_track <= (others => '0') after DLY;\r
+ else\r
+ rx_data_r2 <= rx_data_r after DLY;\r
+ rx_data_r3 <= rx_data_r2 after DLY;\r
+ rx_data_r4 <= rx_data_r3 after DLY;\r
+ rx_data_r5 <= rx_data_r4 after DLY;\r
+ rx_data_r_track <= rx_data_r5 after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+ \r
+ rx_data_aligned <= RX_DATA;\r
+ input_to_chanbond_reg_i <= RX_CHANBOND_SEQ;\r
+ input_to_chanbond_data_i <= RX_CHANBOND_SEQ;\r
+end generate datapath_width_8_or_10;\r
+\r
+\r
+\r
+ \r
+\r
+\r
+\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then\r
+ rxctrl_r2 <= (others => '0') after DLY;\r
+ rxctrl_r3 <= (others => '0') after DLY;\r
+ else\r
+ rxctrl_r2 <= rxctrl_r after DLY;\r
+ rxctrl_r3 <= rxctrl_r2 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ --___________________________ Code for Channel bonding ____________________ \r
+ -- code to prevent checking of clock correction sequences for the start of packet char\r
+ register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate\r
+ case_i_equal_to_0: if (i=0) generate \r
+ rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);\r
+ end generate case_i_equal_to_0;\r
+ case_i_greater_than_0: if (i>0) generate \r
+ rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);\r
+ end generate case_i_greater_than_0;\r
+ end generate register_chan_seq;\r
+ \r
+ chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;\r
+\r
+ process(rx_chanbond_reg)\r
+ variable rx_chanbond_var : std_logic;\r
+ variable i : std_logic;\r
+ begin\r
+ rx_chanbond_var := '0';\r
+ bit_wise_or : for i in 0 to (CHANBOND_SEQ_LEN-1) loop\r
+ rx_chanbond_var := rx_chanbond_var or rx_chanbond_reg(i);\r
+ end loop;\r
+ rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;\r
+ end process;\r
+\r
+ process(RXCTRL_IN)\r
+ variable or_rxctrl_var : std_logic;\r
+ variable i : std_logic;\r
+ begin\r
+ or_rxctrl_var := '0';\r
+ bit_wise_rxctrl_or : for i in 0 to (RXCTRL_WIDTH-1) loop\r
+ or_rxctrl_var := or_rxctrl_var or RXCTRL_IN(i);\r
+ end loop;\r
+ rxctrl_or <= or_rxctrl_var;\r
+ end process;\r
+\r
+\r
+\r
+ rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';\r
+\r
+ --_____________________________ Assign output ports _______________________ \r
+\r
+ TRACK_DATA <= track_data_r; \r
+\r
+\r
+ -- Drive the enamcommaalign port of the mgt for alignment\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENMCOMMA_ALIGN <= '0' after DLY;\r
+ else \r
+ RX_ENMCOMMA_ALIGN <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ -- Drive the enapcommaalign port of the mgt for alignment\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENPCOMMA_ALIGN <= '0' after DLY;\r
+ else \r
+ RX_ENPCOMMA_ALIGN <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+\r
+ INC_OUT <= start_of_packet_detected_c; \r
+\r
+ PATTERN_MATCH_N <= data_error_detected_r;\r
+\r
+ -- Drive the enchansync port of the mgt for channel bonding\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET = '1') then \r
+ RX_ENCHAN_SYNC <= '0' after DLY;\r
+ else \r
+ RX_ENCHAN_SYNC <= '1' after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+ \r
+ --___________________________ Check incoming data for errors ______________\r
+ \r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ bram_data_r <= bram_data_i after DLY;\r
+ end if; \r
+ end process;\r
+ \r
+ --An error is detected when data read for the BRAM does not match the incoming data\r
+use_40bit : if RX_DATA_WIDTH = 40 generate\r
+ rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';\r
+end generate use_40bit;\r
+\r
+not_40bit : if RX_DATA_WIDTH /= 40 generate\r
+ rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';\r
+end generate not_40bit;\r
+\r
+ error_detected_c <= track_data_r4 and not rx_data_matches_bram_c; \r
+ \r
+ \r
+enable_error_check : if USE_COMMA = 1 generate\r
+ --We register the error_detected signal for use with the error counter logic\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(not(track_data_r = '1')) then \r
+ error_detected_r <= '0' after DLY;\r
+ else\r
+ error_detected_r <= error_detected_c after DLY;\r
+ end if;\r
+ end if; \r
+ end process;\r
+end generate enable_error_check;\r
+\r
+disable_error_check : if USE_COMMA = 0 generate\r
+ -- Since the comma detect logic has not been enabled, the error counter has been disabled since\r
+ -- it doesnt make sense to be searching for an align character in the data. To enable the error \r
+ -- count again, please see the code above\r
+ \r
+ error_detected_r <= '0';\r
+\r
+end generate disable_error_check;\r
+\r
+ \r
+ --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss\r
+ --errors we did not directly observe. This counter must be reset when it reaches its max value\r
+ process ( USER_CLK )\r
+ begin\r
+ if( USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ error_count_r <= (others => '0') after DLY;\r
+ elsif(error_detected_r = '1') then\r
+ error_count_r <= error_count_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+ \r
+ --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches\r
+ --max value) to the module output\r
+ ERROR_COUNT <= std_logic_vector(error_count_r(7 downto 0));\r
+\r
+ --____________________________ Counter to read from BRAM __________________________ \r
+four_byte : if RX_DATA_WIDTH > 20 generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))) then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ elsif(((start_of_packet_detected_r and not track_data_r)='1')) then\r
+ read_counter_i <= "000000001" after DLY;\r
+ else read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+end generate four_byte;\r
+\r
+one_or_two_byte : if RX_DATA_WIDTH <= 20 generate\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))\r
+ or ((start_of_packet_detected_r and not track_data_r)='1')) then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ else read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+end generate one_or_two_byte;\r
+\r
+ --________________________________ BRAM Instantiation _____________________________ \r
+\r
+ dual_port_block_ram_i : RAMB16_S36_S36 \r
+ generic map\r
+ (\r
+ INIT_00 => MEM_00,\r
+ INIT_01 => MEM_01,\r
+ INIT_02 => MEM_02,\r
+ INIT_03 => MEM_03,\r
+ INIT_04 => MEM_04,\r
+ INIT_05 => MEM_05,\r
+ INIT_06 => MEM_06,\r
+ INIT_07 => MEM_07,\r
+ INIT_08 => MEM_08,\r
+ INIT_09 => MEM_09,\r
+ INIT_0A => MEM_0A,\r
+ INIT_0B => MEM_0B,\r
+ INIT_0C => MEM_0C,\r
+ INIT_0D => MEM_0D,\r
+ INIT_0E => MEM_0E,\r
+ INIT_0F => MEM_0F,\r
+ INIT_10 => MEM_10,\r
+ INIT_11 => MEM_11,\r
+ INIT_12 => MEM_12,\r
+ INIT_13 => MEM_13,\r
+ INIT_14 => MEM_14,\r
+ INIT_15 => MEM_15,\r
+ INIT_16 => MEM_16,\r
+ INIT_17 => MEM_17,\r
+ INIT_18 => MEM_18,\r
+ INIT_19 => MEM_19,\r
+ INIT_1A => MEM_1A,\r
+ INIT_1B => MEM_1B,\r
+ INIT_1C => MEM_1C,\r
+ INIT_1D => MEM_1D,\r
+ INIT_1E => MEM_1E,\r
+ INIT_1F => MEM_1F,\r
+ INIT_20 => MEM_20,\r
+ INIT_21 => MEM_21,\r
+ INIT_22 => MEM_22,\r
+ INIT_23 => MEM_23,\r
+ INIT_24 => MEM_24,\r
+ INIT_25 => MEM_25,\r
+ INIT_26 => MEM_26,\r
+ INIT_27 => MEM_27,\r
+ INIT_28 => MEM_28,\r
+ INIT_29 => MEM_29,\r
+ INIT_2A => MEM_2A,\r
+ INIT_2B => MEM_2B,\r
+ INIT_2C => MEM_2C,\r
+ INIT_2D => MEM_2D,\r
+ INIT_2E => MEM_2E,\r
+ INIT_2F => MEM_2F,\r
+ INIT_30 => MEM_30,\r
+ INIT_31 => MEM_31,\r
+ INIT_32 => MEM_32,\r
+ INIT_33 => MEM_33,\r
+ INIT_34 => MEM_34,\r
+ INIT_35 => MEM_35,\r
+ INIT_36 => MEM_36,\r
+ INIT_37 => MEM_37,\r
+ INIT_38 => MEM_38,\r
+ INIT_39 => MEM_39,\r
+ INIT_3A => MEM_3A,\r
+ INIT_3B => MEM_3B,\r
+ INIT_3C => MEM_3C,\r
+ INIT_3D => MEM_3D,\r
+ INIT_3E => MEM_3E,\r
+ INIT_3F => MEM_3F,\r
+ INITP_00 => MEMP_00,\r
+ INITP_01 => MEMP_01,\r
+ INITP_02 => MEMP_02,\r
+ INITP_03 => MEMP_03,\r
+ INITP_04 => MEMP_04,\r
+ INITP_05 => MEMP_05,\r
+ INITP_06 => MEMP_06,\r
+ INITP_07 => MEMP_07\r
+\r
+ )\r
+ port map \r
+ (\r
+ ADDRA => std_logic_vector(read_counter_i),\r
+ DIA => tied_to_ground_vec_i(31 downto 0),\r
+ DIPA => tied_to_ground_vec_i(3 downto 0),\r
+ DOA => bram_data_i,\r
+ DOPA => open, \r
+ WEA => tied_to_ground_i,\r
+ ENA => tied_to_vcc_i,\r
+ SSRA => tied_to_ground_i, \r
+ CLKA => USER_CLK,\r
+ \r
+ ADDRB => tied_to_ground_vec_i(8 downto 0),\r
+ DIB => tied_to_ground_vec_i(31 downto 0),\r
+ DIPB => tied_to_ground_vec_i(3 downto 0),\r
+ DOB => open, \r
+ DOPB => open, \r
+ WEB => tied_to_ground_i,\r
+ ENB => tied_to_ground_i,\r
+ SSRB => tied_to_ground_i,\r
+ CLKB => tied_to_ground_i \r
+ ); \r
+ \r
+ \r
+end RTL; \r
+\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : frame_gen.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module FRAME_GEN\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity FRAME_GEN is\r
+generic\r
+(\r
+ WORDS_IN_BRAM : integer := 256;\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
+); \r
+port\r
+(\r
+ -- User Interface\r
+ TX_DATA : out std_logic_vector(39 downto 0);\r
+ TX_CHARISK : out std_logic_vector(3 downto 0); \r
+\r
+ -- System Interface\r
+ USER_CLK : in std_logic; \r
+ SYSTEM_RESET : in std_logic\r
+); \r
+\r
+\r
+end FRAME_GEN;\r
+\r
+architecture RTL of FRAME_GEN is\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--********************************* Wire Declarations************************** \r
+\r
+ signal tx_charisk_i : std_logic_vector(3 downto 0);\r
+ signal tx_data_bram_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal tied_to_vcc_vec_i : std_logic_vector(15 downto 0);\r
+\r
+--***************************Internal signalister Declarations******************** \r
+\r
+ signal read_counter_i : unsigned(8 downto 0); \r
+\r
+\r
+--*********************************Main Body of Code***************************\r
+begin\r
+\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_ground_i <= '0';\r
+ tied_to_vcc_i <= '1';\r
+ \r
+ --__________________________ Counter to read from BRAM ____________________ \r
+ \r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then\r
+ read_counter_i <= (others => '0') after DLY;\r
+ else\r
+ read_counter_i <= read_counter_i + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Assign TX_DATA to BRAM output\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ TX_DATA <= (others => '0') after DLY;\r
+ else\r
+ TX_DATA <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Assign TX_CHARISK to BRAM output\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(SYSTEM_RESET='1') then\r
+ TX_CHARISK <= (others => '0') after DLY;\r
+ else\r
+ TX_CHARISK <= tx_charisk_i after DLY; \r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ --______________________________ BRAM Instantiation _______________________ \r
+\r
+ dual_port_block_ram_i : RAMB16_S36_S36 \r
+ generic map\r
+ (\r
+ INIT_00 => MEM_00,\r
+ INIT_01 => MEM_01,\r
+ INIT_02 => MEM_02,\r
+ INIT_03 => MEM_03,\r
+ INIT_04 => MEM_04,\r
+ INIT_05 => MEM_05,\r
+ INIT_06 => MEM_06,\r
+ INIT_07 => MEM_07,\r
+ INIT_08 => MEM_08,\r
+ INIT_09 => MEM_09,\r
+ INIT_0A => MEM_0A,\r
+ INIT_0B => MEM_0B,\r
+ INIT_0C => MEM_0C,\r
+ INIT_0D => MEM_0D,\r
+ INIT_0E => MEM_0E,\r
+ INIT_0F => MEM_0F,\r
+ INIT_10 => MEM_10,\r
+ INIT_11 => MEM_11,\r
+ INIT_12 => MEM_12,\r
+ INIT_13 => MEM_13,\r
+ INIT_14 => MEM_14,\r
+ INIT_15 => MEM_15,\r
+ INIT_16 => MEM_16,\r
+ INIT_17 => MEM_17,\r
+ INIT_18 => MEM_18,\r
+ INIT_19 => MEM_19,\r
+ INIT_1A => MEM_1A,\r
+ INIT_1B => MEM_1B,\r
+ INIT_1C => MEM_1C,\r
+ INIT_1D => MEM_1D,\r
+ INIT_1E => MEM_1E,\r
+ INIT_1F => MEM_1F,\r
+ INIT_20 => MEM_20,\r
+ INIT_21 => MEM_21,\r
+ INIT_22 => MEM_22,\r
+ INIT_23 => MEM_23,\r
+ INIT_24 => MEM_24,\r
+ INIT_25 => MEM_25,\r
+ INIT_26 => MEM_26,\r
+ INIT_27 => MEM_27,\r
+ INIT_28 => MEM_28,\r
+ INIT_29 => MEM_29,\r
+ INIT_2A => MEM_2A,\r
+ INIT_2B => MEM_2B,\r
+ INIT_2C => MEM_2C,\r
+ INIT_2D => MEM_2D,\r
+ INIT_2E => MEM_2E,\r
+ INIT_2F => MEM_2F,\r
+ INIT_30 => MEM_30,\r
+ INIT_31 => MEM_31,\r
+ INIT_32 => MEM_32,\r
+ INIT_33 => MEM_33,\r
+ INIT_34 => MEM_34,\r
+ INIT_35 => MEM_35,\r
+ INIT_36 => MEM_36,\r
+ INIT_37 => MEM_37,\r
+ INIT_38 => MEM_38,\r
+ INIT_39 => MEM_39,\r
+ INIT_3A => MEM_3A,\r
+ INIT_3B => MEM_3B,\r
+ INIT_3C => MEM_3C,\r
+ INIT_3D => MEM_3D,\r
+ INIT_3E => MEM_3E,\r
+ INIT_3F => MEM_3F,\r
+ INITP_00 => MEMP_00,\r
+ INITP_01 => MEMP_01,\r
+ INITP_02 => MEMP_02,\r
+ INITP_03 => MEMP_03,\r
+ INITP_04 => MEMP_04,\r
+ INITP_05 => MEMP_05,\r
+ INITP_06 => MEMP_06,\r
+ INITP_07 => MEMP_07\r
+ )\r
+ port map \r
+ (\r
+ ADDRA => std_logic_vector(read_counter_i),\r
+ DIA => tied_to_ground_vec_i(31 downto 0),\r
+ DIPA => tied_to_ground_vec_i(3 downto 0),\r
+ DOA => tx_data_bram_i,\r
+ DOPA => tx_charisk_i, \r
+ WEA => tied_to_ground_i,\r
+ ENA => tied_to_vcc_i,\r
+ SSRA => tied_to_ground_i, \r
+ CLKA => USER_CLK,\r
+ \r
+ ADDRB => tied_to_ground_vec_i(8 downto 0),\r
+ DIB => tied_to_ground_vec_i(31 downto 0),\r
+ DIPB => tied_to_ground_vec_i(3 downto 0),\r
+ DOB => open, \r
+ DOPB => open, \r
+ WEB => tied_to_ground_i,\r
+ ENB => tied_to_ground_i,\r
+ SSRB => tied_to_ground_i,\r
+ CLKB => tied_to_ground_i \r
+ ); \r
+\r
+end RTL;\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtxVirtex6FEE80_top.sdc\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## Device: xc6vlx130t\r
+## Package: ff484\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+################################################################################\r
+\r
+\r
+ \r
+# Buffer Constraints for synthesis\r
+define_attribute {n:gtx0_txoutclk_i} {syn_noclockbuf} {1};
+\r
+\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtxVirtex6FEE80_top.ucf\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## Device: xc6vlx130t\r
+## Package: ff484\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+################################## Clock Constraints ##########################\r
+\r
+NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";\r
+TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;\r
+\r
+\r
+\r
+# User Clock Constraints\r
+NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
+TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
+
+NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
+TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
+
+\r
+\r
+#################### locs for top level ports (ML623 Board) ###################\r
+\r
+\r
+\r
+####################### GTX reference clock constraints #######################\r
+NET Q3_CLK0_MGTREFCLK_PAD_N_IN LOC=L3;\r
+NET Q3_CLK0_MGTREFCLK_PAD_P_IN LOC=L4;\r
+\r
+\r
+################################# mgt wrapper constraints #####################\r
+\r
+##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------\r
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;\r
+\r
+\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtxVirtex6FEE80_top.xcf\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## Device: xc6vlx130t\r
+## Package: ff484\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+################################################################################\r
+\r
+\r
+ \r
+# Buffer Constraints for synthesis\r
+BEGIN MODEL "gtxVirtex6FEE80_top"\r
+NET "gtx0_txoutclk_i" BUFFER_TYPE = none;
+\r
+END;\r
+\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtx_attributes.ucf\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## GTX ATTRIBUTES \r
+## This file contains the attributes for the active GTX transceivers in the\r
+## design. If you would like to use this file in your design, please make\r
+## sure that the path to the GTX instance is correct.\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+############################## Active GTX Attributes #######################\r
+ \r
+##________________________ Attributes for GTX 0_____________________\r
+ \r
+
+##--------------------------TX PLL----------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE = "RXPLL";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG = 24'h21680a;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG = 8'h07;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT = 2;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG = 3'b111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER = 4;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE = 10'b0000110100;
+
+##-----------------------TX Interface-------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH = 10;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG = 6'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL = "TXPLLREFCLK_DIV1";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY = 10'b0000000000;
+
+##------------TX Buffering and Phase Alignment----------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT = 1'b1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG = 20'h80082;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG = 6'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL = "TXUSR";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC = 4'b0100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC = 4'b0110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING = 8'b10000000;
+
+##-----------------------TX Gearbox---------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE = "FALSE";
+
+##--------------TX Driver and OOB Signalling------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE = "DIRECT";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY = 3'b101;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY = 3'b011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD = "FALSE";
+
+##------------TX Pipe Control for PCI Express/SATA------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL = 4'b1111;
+
+##----------------TX Attributes for PCI Express---------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0 = 5'b11010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1 = 5'b10000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0 = 7'b1001110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1 = 7'b1001001;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2 = 7'b1000101;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3 = 7'b1000010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4 = 7'b1000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0 = 7'b1000110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1 = 7'b1000100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2 = 7'b1000010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3 = 7'b1000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4 = 7'b1000000;
+
+##--------------------------RX PLL----------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG = 24'h21680a;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG = 8'h07;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT = 2;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG = 3'b111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER = 4;
+
+##-----------------------RX Interface-------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH = 10;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL = "RXRECCLKPMA_DIV1";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY = 16'h0000;
+
+##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME = 5'b10100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD = 3'b011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN = 27'h640404C;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG = 25'h05ce008;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG = 14'h1832;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL = 5'b00000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM = 2'b01;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG = 7'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG = 76'h0040000040000000003;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG = 17'h00000;
+
+##------------RX Decision Feedback Equalizer(DFE)-------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME = 5'b01100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG = 8'b00011011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET = 8'h4C;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE = 2'b00;
+
+##-----------------------PRBS Detection-----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK = 1'b0;
+
+##----------------Comma Detection and Alignment---------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE = 10'b1111111100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE = 10'b1010000011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE = 10'b0101111100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE = "OFF";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA = "TRUE";
+
+##---------------RX Loss-of-sync State Machine----------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR = 8;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD = 256;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM = "TRUE";
+
+##-----------------------RX Gearbox---------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE = "FALSE";
+
+##-----------RX Elastic Buffer and Phase alignment------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2 = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE = "FAST";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT = 4'b1000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT = 4'b0000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL = "RXUSR";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC = 4'b1110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET = 5'b00010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC = 4'b1110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING = 8'b10000000;
+
+##----------------------Clock Correction----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT = 16;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT = 14;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT = 0;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE = "FALSE";
+
+##----------------------Channel Bonding----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG = 5'b00000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE = "FALSE";
+
+##-----------RX Attributes for PCI Express/SATA/SAS----------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS = 52;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS = 40;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL = 3'b100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL = 3'b100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST = 11;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT = 34;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE = 11;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST = 6;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT = 19;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE = 6;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2 = 12'h03c;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2 = 8'h19;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE = 8'hff;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2 = 10'h064;
+\r
+\r
+\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : gtxvirtex6fee80_rx_sync.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxvirtex6fee80_rx_sync\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity gtxvirtex6fee80_rx_sync is\r
+port\r
+(\r
+ RXENPMAPHASEALIGN : out std_logic;\r
+ RXPMASETPHASE : out std_logic;\r
+ RXDLYALIGNDISABLE : out std_logic;\r
+ RXDLYALIGNOVERRIDE : out std_logic;\r
+ RXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+\r
+\r
+end gtxvirtex6fee80_rx_sync;\r
+\r
+architecture RTL of gtxvirtex6fee80_rx_sync is\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+\r
+ signal begin_r : std_logic;\r
+ signal phase_align_r : std_logic;\r
+ signal ready_r : std_logic;\r
+ signal sync_counter_r : unsigned(5 downto 0);\r
+ signal sync_done_count_r : unsigned(5 downto 0);\r
+ signal align_reset_counter_r : unsigned(4 downto 0);\r
+ signal wait_after_sync_r : std_logic;\r
+ signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
+ signal wait_before_setphase_r : std_logic;\r
+ signal align_reset_r : std_logic;\r
+ \r
+--*******************************Wire Declarations****************************\r
+ \r
+ signal count_32_setphase_complete_r : std_logic;\r
+ signal count_32_wait_complete_r : std_logic;\r
+ signal count_align_reset_complete_r : std_logic;\r
+ signal next_phase_align_c : std_logic;\r
+ signal next_align_reset_c : std_logic;\r
+ signal next_ready_c : std_logic;\r
+ signal next_wait_after_sync_c : std_logic;\r
+ signal next_wait_before_setphase_c : std_logic;\r
+ signal sync_32_times_done_r : std_logic;\r
+ \r
+ attribute max_fanout:string; \r
+ attribute max_fanout of ready_r : signal is "2";\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ --________________________________ State machine __________________________ \r
+ -- This state machine manages the phase alingment procedure of the GTX on the\r
+ -- receive side. The module is held in reset till the usrclk source is stable\r
+ -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate \r
+ -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.\r
+ -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes \r
+ -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. \r
+ -- After this, it goes into the wait_before_setphase_r state for 32 cycles. \r
+ -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the \r
+ -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. \r
+ -- After the port is deasserted, the state machine goes into a wait state for\r
+ -- 32 cycles. This procedure is repeated 32 times.\r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET='1') then\r
+ begin_r <= '1' after DLY;\r
+ align_reset_r <= '0' after DLY;\r
+ wait_before_setphase_r <= '0' after DLY;\r
+ phase_align_r <= '0' after DLY;\r
+ wait_after_sync_r <= '0' after DLY;\r
+ ready_r <= '0' after DLY;\r
+ else\r
+ begin_r <= '0' after DLY;\r
+ align_reset_r <= next_align_reset_c after DLY;\r
+ wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
+ phase_align_r <= next_phase_align_c after DLY;\r
+ wait_after_sync_r <= next_wait_after_sync_c after DLY;\r
+ ready_r <= next_ready_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_align_reset_c <= begin_r or\r
+ (align_reset_r and not count_align_reset_complete_r);\r
+ \r
+ next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or\r
+ (wait_before_setphase_r and not count_32_wait_complete_r); \r
+ \r
+ next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or\r
+ (phase_align_r and not count_32_setphase_complete_r) or\r
+ (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);\r
+ \r
+ next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or\r
+ (wait_after_sync_r and not count_32_wait_complete_r);\r
+\r
+ next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or\r
+ ready_r;\r
+\r
+ --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (align_reset_r='0') then\r
+ align_reset_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
+ end if;\r
+ end if ;\r
+ end process;\r
+ \r
+ count_align_reset_complete_r <= align_reset_counter_r(4)\r
+ and align_reset_counter_r(2);\r
+ \r
+ --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then\r
+ wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_wait_complete_r <= wait_before_setphase_counter_r(5);\r
+ \r
+ --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (phase_align_r='0') then\r
+ sync_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ sync_counter_r <= sync_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_setphase_complete_r <= sync_counter_r(5);\r
+\r
+ --__________ Counter for counting number of times sync is done ____________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (RESET='1') then\r
+ sync_done_count_r <= (others=>'0') after DLY;\r
+ elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then\r
+ sync_done_count_r <= sync_done_count_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ sync_32_times_done_r <= sync_done_count_r(5);\r
+\r
+ --_______________ Assign the phase align ports into the GTX _______________\r
+\r
+ RXDLYALIGNRESET <= align_reset_r;\r
+ RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
+ RXPMASETPHASE <= phase_align_r;\r
+ RXDLYALIGNDISABLE <= '1';\r
+ RXDLYALIGNOVERRIDE <= '1';\r
+\r
+ --_______________________ Assign the sync_done port _______________________\r
+ \r
+ SYNC_DONE <= ready_r;\r
+ \r
+ \r
+end RTL;\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : gtxvirtex6fee80_top.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxVirtex6FEE80_top\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity gtxVirtex6FEE80_top is\r
+generic\r
+(\r
+ EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;\r
+ EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch\r
+ EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM\r
+ EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1; -- simulation setting for GTX SecureIP model\r
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets\r
+);\r
+port\r
+(\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
+ GTXTXRESET_IN : in std_logic;\r
+ GTXRXRESET_IN : in std_logic;\r
+ TRACK_DATA_OUT : out std_logic;\r
+ RXN_IN : in std_logic;\r
+ RXP_IN : in std_logic;\r
+ TXN_OUT : out std_logic;\r
+ TXP_OUT : out std_logic\r
+ \r
+);\r
+\r
+\r
+end gtxVirtex6FEE80_top;\r
+ \r
+architecture RTL of gtxVirtex6FEE80_top is\r
+\r
+--**************************Component Declarations*****************************\r
+\r
+\r
+component gtxVirtex6FEE80 \r
+generic\r
+(\r
+ -- Simulation attributes\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+\r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0_Y12)\r
+\r
+ GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+\r
+\r
+);\r
+end component;\r
+\r
+component MGT_USRCLK_SOURCE \r
+generic\r
+(\r
+ FREQUENCY_MODE : string := "LOW"; \r
+ PERFORMANCE_MODE : string := "MAX_SPEED" \r
+);\r
+port\r
+(\r
+ DIV1_OUT : out std_logic;\r
+ DIV2_OUT : out std_logic;\r
+ DCM_LOCKED_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ DCM_RESET_IN : in std_logic\r
+\r
+);\r
+end component;\r
+\r
+component FRAME_GEN \r
+generic\r
+(\r
+ WORDS_IN_BRAM : integer := 256;\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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+); \r
+port\r
+(\r
+ -- User Interface\r
+ TX_DATA : out std_logic_vector(39 downto 0);\r
+ TX_CHARISK : out std_logic_vector(3 downto 0); \r
+\r
+ -- System Interface\r
+ USER_CLK : in std_logic;\r
+ SYSTEM_RESET : in std_logic\r
+); \r
+end component;\r
+\r
+component FRAME_CHECK \r
+generic\r
+(\r
+ RX_DATA_WIDTH : integer := 16;\r
+ RXCTRL_WIDTH : integer := 2;\r
+ USE_COMMA : integer := 1;\r
+ NONE_MSB_FIRST_DEC : integer := 0;\r
+ COMMA_DOUBLE_DEC : integer := 0;\r
+ CHANBOND_SEQ_LEN : integer := 1;\r
+ WORDS_IN_BRAM : integer := 256;\r
+ CONFIG_INDEPENDENT_LANES : integer := 0;\r
+ START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
+ COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
+ MEM_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
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+);\r
+port\r
+(\r
+ -- User Interface\r
+ RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ \r
+ RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
+ RX_ENMCOMMA_ALIGN : out std_logic;\r
+ RX_ENPCOMMA_ALIGN : out std_logic;\r
+ \r
+ RX_ENCHAN_SYNC : out std_logic; \r
+ RX_CHANBOND_SEQ : in std_logic; \r
+\r
+ -- Control Interface\r
+ INC_IN : in std_logic; \r
+ INC_OUT : out std_logic; \r
+ PATTERN_MATCH_N : out std_logic;\r
+ RESET_ON_ERROR : in std_logic; \r
+ \r
+ -- Error Monitoring\r
+ ERROR_COUNT : out std_logic_vector(7 downto 0);\r
+ \r
+ -- Track Data\r
+ TRACK_DATA : out std_logic;\r
+ \r
+ -- System Interface\r
+ USER_CLK : in std_logic;\r
+ SYSTEM_RESET : in std_logic\r
+ \r
+);\r
+end component;\r
+\r
+component MGT_USRCLK_SOURCE_MMCM\r
+generic\r
+(\r
+ MULT : real := 2.0;\r
+ DIVIDE : integer := 2; \r
+ CLK_PERIOD : real := 6.4; \r
+ OUT0_DIVIDE : real := 2.0;\r
+ OUT1_DIVIDE : integer := 2;\r
+ OUT2_DIVIDE : integer := 2;\r
+ OUT3_DIVIDE : integer := 2\r
+);\r
+port\r
+(\r
+ CLKFBOUT : out std_logic; \r
+ CLK0_OUT : out std_logic;\r
+ CLK1_OUT : out std_logic;\r
+ CLK2_OUT : out std_logic;\r
+ CLK3_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ MMCM_LOCKED_OUT : out std_logic;\r
+ MMCM_RESET_IN : in std_logic\r
+);\r
+end component;\r
+\r
+component gtxVirtex6FEE80_tx_sync\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+ TXENPMAPHASEALIGN : out std_logic;\r
+ TXPMASETPHASE : out std_logic;\r
+ TXDLYALIGNDISABLE : out std_logic;\r
+ TXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+component gtxVirtex6FEE80_rx_sync\r
+port\r
+(\r
+ RXENPMAPHASEALIGN : out std_logic;\r
+ RXPMASETPHASE : out std_logic;\r
+ RXDLYALIGNDISABLE : out std_logic;\r
+ RXDLYALIGNOVERRIDE : out std_logic;\r
+ RXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+\r
+-- Chipscope modules\r
+attribute syn_black_box : boolean;\r
+attribute syn_noprune : boolean;\r
+\r
+\r
+component data_vio\r
+port\r
+(\r
+ control : inout std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ async_in : in std_logic_vector(31 downto 0);\r
+ async_out : out std_logic_vector(31 downto 0);\r
+ sync_in : in std_logic_vector(31 downto 0);\r
+ sync_out : out std_logic_vector(31 downto 0)\r
+);\r
+end component;\r
+attribute syn_black_box of data_vio : component is TRUE;\r
+attribute syn_noprune of data_vio : component is TRUE;\r
+\r
+\r
+component icon\r
+port\r
+(\r
+ control0 : inout std_logic_vector(35 downto 0);\r
+ control1 : inout std_logic_vector(35 downto 0);\r
+ control2 : inout std_logic_vector(35 downto 0);\r
+ control3 : inout std_logic_vector(35 downto 0)\r
+);\r
+end component;\r
+attribute syn_black_box of icon : component is TRUE;\r
+attribute syn_noprune of icon : component is TRUE;\r
+\r
+\r
+component ila\r
+port\r
+(\r
+ control : inout std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ trig0 : in std_logic_vector(84 downto 0)\r
+);\r
+end component;\r
+\r
+\r
+attribute syn_black_box of ila : component is TRUE;\r
+attribute syn_noprune of ila : component is TRUE;\r
+\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+ \r
+ attribute max_fanout : string; \r
+\r
+--************************** Register Declarations ****************************\r
+\r
+ signal gtx0_txresetdone_r : std_logic;\r
+ signal gtx0_txresetdone_r2 : std_logic;\r
+ signal gtx0_rxresetdone_i_r : std_logic;\r
+ signal gtx0_rxresetdone_r : std_logic;\r
+ signal gtx0_rxresetdone_r2 : std_logic;\r
+ signal gtx0_rxresetdone_r3 : std_logic;\r
+ attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";\r
+ signal gtx0_rxdata_r : std_logic_vector(7 downto 0);\r
+ signal gtx0_rxcharisk_r : std_logic_vector(0 downto 0); \r
+\r
+\r
+--**************************** Wire Declarations ******************************\r
+ -------------------------- MGT Wrapper Wires ------------------------------\r
+ --________________________________________________________________________\r
+ --________________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ signal gtx0_rxcharisk_i : std_logic;
+ signal gtx0_rxdisperr_i : std_logic;
+ signal gtx0_rxnotintable_i : std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ signal gtx0_rxenmcommaalign_i : std_logic;
+ signal gtx0_rxenpcommaalign_i : std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ signal gtx0_rxdata_i : std_logic_vector(7 downto 0);
+ signal gtx0_rxrecclk_i : std_logic;
+ signal gtx0_rxreset_i : std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ signal gtx0_rxcdrreset_i : std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ signal gtx0_rxdlyaligndisable_i : std_logic;
+ signal gtx0_rxdlyalignmonenb_i : std_logic;
+ signal gtx0_rxdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_rxdlyalignoverride_i : std_logic;
+ signal gtx0_rxdlyalignreset_i : std_logic;
+ signal gtx0_rxenpmaphasealign_i : std_logic;
+ signal gtx0_rxpmasetphase_i : std_logic;
+ signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ signal gtx0_rxlossofsync_i : std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ signal gtx0_gtxrxreset_i : std_logic;
+ signal gtx0_pllrxreset_i : std_logic;
+ signal gtx0_rxplllkdet_i : std_logic;
+ signal gtx0_rxresetdone_i : std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ signal gtx0_phystatus_i : std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ signal gtx0_txcharisk_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gtx0_txdata_i : std_logic_vector(7 downto 0);
+ signal gtx0_txoutclk_i : std_logic;
+ signal gtx0_txreset_i : std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ signal gtx0_txdlyaligndisable_i : std_logic;
+ signal gtx0_txdlyalignmonenb_i : std_logic;
+ signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_txdlyalignreset_i : std_logic;
+ signal gtx0_txenpmaphasealign_i : std_logic;
+ signal gtx0_txpmasetphase_i : std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ signal gtx0_gtxtxreset_i : std_logic;
+ signal gtx0_txresetdone_i : std_logic;
+\r
+\r
+\r
+\r
+ signal gtx0_tx_system_reset_c : std_logic;\r
+ signal gtx0_rx_system_reset_c : std_logic;\r
+ signal gtx0_double_reset_clk_i : std_logic;\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);\r
+ signal drp_clk_in_i : std_logic;\r
+ \r
+\r
+ ----------------------------- User Clocks ---------------------------------\r
+\r
+ signal gtx0_txusrclk2_i : std_logic;
+ signal gtx0_rxusrclk2_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gtx0_txoutclk_to_mmcm_i : std_logic;
+\r
+\r
+ ----------------------------- Reference Clocks ----------------------------\r
+ \r
+ signal q3_clk0_refclk_i : std_logic;\r
+ signal q3_clk0_refclk_i_bufg : std_logic;\r
+\r
+ ----------------------- Frame check/gen Module Signals --------------------\r
+ \r
+ signal gtx0_matchn_i : std_logic;\r
+ \r
+ signal gtx0_txcharisk_float_i : std_logic_vector(2 downto 0);\r
+ \r
+ signal gtx0_txdata_float_i : std_logic_vector(31 downto 0);\r
+ \r
+ signal gtx0_track_data_i : std_logic;\r
+ signal gtx0_block_sync_i : std_logic;\r
+ signal gtx0_error_count_i : std_logic_vector(7 downto 0);\r
+ signal gtx0_frame_check_reset_i : std_logic;\r
+ signal gtx0_inc_in_i : std_logic;\r
+ signal gtx0_inc_out_i : std_logic;\r
+ signal gtx0_unscrambled_data_i : std_logic_vector(7 downto 0);\r
+\r
+ signal reset_on_data_error_i : std_logic;\r
+ signal track_data_out_i : std_logic;\r
+ \r
+ \r
+ ------------------------- Sync Module Signals -----------------------------\r
+\r
+ signal gtx0_rx_sync_done_i : std_logic;\r
+ signal gtx0_reset_rxsync_c : std_logic;\r
+\r
+\r
+ signal gtx0_tx_sync_done_i : std_logic;\r
+ signal gtx0_reset_txsync_c : std_logic;\r
+\r
+ ----------------------- Chipscope Signals ---------------------------------\r
+\r
+ signal tx_data_vio_control_i : std_logic_vector(35 downto 0);
+ signal rx_data_vio_control_i : std_logic_vector(35 downto 0);
+ signal shared_vio_control_i : std_logic_vector(35 downto 0);
+ signal ila_control_i : std_logic_vector(35 downto 0);
+ signal tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal shared_vio_in_i : std_logic_vector(31 downto 0);
+ signal shared_vio_out_i : std_logic_vector(31 downto 0);
+ signal ila_in_i : std_logic_vector(84 downto 0);
+
+ signal gtx0_tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_ila_in_i : std_logic_vector(84 downto 0);
+
+\r
+ signal gtxtxreset_i : std_logic;\r
+ signal gtxrxreset_i : std_logic;\r
+\r
+ signal user_tx_reset_i : std_logic;\r
+ signal user_rx_reset_i : std_logic;\r
+ signal tx_vio_clk_i : std_logic;\r
+ signal tx_vio_clk_mux_out_i : std_logic;\r
+ signal rx_vio_ila_clk_i : std_logic;\r
+ signal rx_vio_ila_clk_mux_out_i : std_logic;\r
+\r
+ \r
+--**************************** Main Body of Code *******************************\r
+begin\r
+\r
+ -- Static signal Assigments\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= x"0000000000000000";\r
+ tied_to_vcc_i <= '1';\r
+ tied_to_vcc_vec_i <= x"ff";\r
+\r
+\r
+\r
+ \r
+ \r
+\r
+ -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
+ -- The dedicated reference clock inputs you selected in the GUI are implemented using\r
+ -- IBUFDS_GTXE1 instances.\r
+ --\r
+ -- In the UCF file for this example design, you will see that each of\r
+ -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these\r
+ -- locations, we tell the tools to use the dedicated input buffers to the GTX reference\r
+ -- clock network, rather than general purpose IOs. To select other pins, consult the \r
+ -- Implementation chapter of UG___, or rerun the wizard.\r
+ --\r
+ -- This network is the highest performace (lowest jitter) option for providing clocks\r
+ -- to the GTX transceivers.\r
+ \r
+ q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
+ port map\r
+ (\r
+ O => q3_clk0_refclk_i,\r
+ ODIV2 => open,\r
+ CEB => tied_to_ground_i,\r
+ I => Q3_CLK0_MGTREFCLK_PAD_P_IN,\r
+ IB => Q3_CLK0_MGTREFCLK_PAD_N_IN\r
+ );\r
+\r
+ \r
+\r
+ q3_clk0_refclk_bufg_i : BUFG\r
+ port map\r
+ (\r
+ I => q3_clk0_refclk_i,\r
+ O => q3_clk0_refclk_i_bufg\r
+ );\r
+\r
+ -----------------------Clock Input to Double Reset Module------------------\r
+ gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;\r
+\r
+\r
+ ----------------------------------- User Clocks ---------------------------\r
+ \r
+ -- The clock resources in this section were added based on userclk source selections on\r
+ -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:\r
+ -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to \r
+ -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits\r
+ -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency\r
+ -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when\r
+ -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all\r
+ -- the channels using the clock are receiving data from TX channels that share a reference clock \r
+ -- source with each other.\r
+\r
+ txoutclk_mmcm0_reset_i <= not gtx0_rxplllkdet_i;
+ txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
+ generic map
+ (
+ MULT => 15.0,
+ DIVIDE => 1,
+ CLK_PERIOD => 12.5,
+ OUT0_DIVIDE => 6.0,
+ OUT1_DIVIDE => 1,
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLKFBOUT => open,
+ CLK0_OUT => gtx0_txusrclk2_i,
+ CLK1_OUT => open,
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gtx0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxrecclk_bufr1_i : BUFR
+ generic map
+ (
+ BUFR_DIVIDE => "BYPASS"
+ )
+ port map
+ (
+ CE => '1',
+ CLR => '0',
+ I => gtx0_rxrecclk_i,
+ O => gtx0_rxusrclk2_i
+ );
+
+
+\r
+\r
+ ----------------------------- The GTX Wrapper -----------------------------\r
+ \r
+ -- Use the instantiation template in the example directory to add the GTX wrapper to your design.\r
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame \r
+ -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is \r
+ -- enabled, bonding should occur after alignment.\r
+\r
+\r
+ gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
+ generic map\r
+ (\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
+ )\r
+ port map\r
+ (\r
+ \r
+ \r
+ \r
+ \r
+\r
+ --_____________________________________________________________________\r
+ --_____________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+ GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT => gtx0_rxcharisk_i,
+ GTX0_RXDISPERR_OUT => gtx0_rxdisperr_i,
+ GTX0_RXNOTINTABLE_OUT => gtx0_rxnotintable_i,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN => gtx0_rxenmcommaalign_i,
+ GTX0_RXENPCOMMAALIGN_IN => gtx0_rxenpcommaalign_i,
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT => gtx0_rxdata_i,
+ GTX0_RXRECCLK_OUT => gtx0_rxrecclk_i,
+ GTX0_RXRESET_IN => gtx0_rxreset_i,
+ GTX0_RXUSRCLK2_IN => gtx0_rxusrclk2_i,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN => gtx0_rxcdrreset_i,
+ GTX0_RXN_IN => RXN_IN,
+ GTX0_RXP_IN => RXP_IN,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN => gtx0_rxdlyaligndisable_i,
+ GTX0_RXDLYALIGNMONENB_IN => gtx0_rxdlyalignmonenb_i,
+ GTX0_RXDLYALIGNMONITOR_OUT => gtx0_rxdlyalignmonitor_i,
+ GTX0_RXDLYALIGNOVERRIDE_IN => gtx0_rxdlyalignoverride_i,
+ GTX0_RXDLYALIGNRESET_IN => gtx0_rxdlyalignreset_i,
+ GTX0_RXENPMAPHASEALIGN_IN => gtx0_rxenpmaphasealign_i,
+ GTX0_RXPMASETPHASE_IN => gtx0_rxpmasetphase_i,
+ GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT => gtx0_rxlossofsync_i,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN => gtx0_gtxrxreset_i,
+ GTX0_MGTREFCLKRX_IN => q3_clk0_refclk_i,
+ GTX0_PLLRXRESET_IN => gtx0_pllrxreset_i,
+ GTX0_RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
+ GTX0_RXRESETDONE_OUT => gtx0_rxresetdone_i,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT => gtx0_phystatus_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN => gtx0_txcharisk_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN => gtx0_txdata_i,
+ GTX0_TXOUTCLK_OUT => gtx0_txoutclk_i,
+ GTX0_TXRESET_IN => gtx0_txreset_i,
+ GTX0_TXUSRCLK2_IN => gtx0_txusrclk2_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT => TXN_OUT,
+ GTX0_TXP_OUT => TXP_OUT,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
+ GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
+ GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
+ GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
+ GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
+ GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN => gtx0_gtxtxreset_i,
+ GTX0_TXRESETDONE_OUT => gtx0_txresetdone_i
+\r
+\r
+ );\r
+\r
+ -- Hold the TX in reset till the TX user clocks are stable\r
+ gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;\r
+\r
+ -- Hold the RX in reset till the RX user clocks are stable\r
+ \r
+ gtx0_rxreset_i <= not gtx0_rxplllkdet_i;\r
+\r
+\r
+\r
+ ------------------------------ TXSYNC module ------------------------------\r
+ -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It\r
+ -- waits for the user clocks to be stable, then drives the phase align signals on each\r
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
+ \r
+ -- Include the TX_SYNC module in your own design to perform phase synchronization if\r
+ -- your protocol bypasses the TX Buffers\r
+\r
+ \r
+ \r
+ gtx0_reset_txsync_c <= not gtx0_txresetdone_r2; \r
+\r
+ -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 \r
+ -- during implementation \r
+ gtx0_txsync_i : gtxVirtex6FEE80_tx_sync\r
+ generic map\r
+ (\r
+ SIM_TXPMASETPHASE_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
+ )\r
+ port map\r
+ (\r
+ TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,\r
+ TXPMASETPHASE => gtx0_txpmasetphase_i,\r
+ TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,\r
+ TXDLYALIGNRESET => gtx0_txdlyalignreset_i,\r
+ SYNC_DONE => gtx0_tx_sync_done_i,\r
+ USER_CLK => gtx0_txusrclk2_i,\r
+ RESET => gtx0_reset_txsync_c\r
+ );\r
+\r
+ ---------------------------- RXSYNC modules -------------------------------\r
+ -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
+ -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
+ \r
+ -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
+ -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
+ -- a stable clock\r
+ \r
+ \r
+ gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync\r
+ port map\r
+ (\r
+ RXENPMAPHASEALIGN => gtx0_rxenpmaphasealign_i,\r
+ RXPMASETPHASE => gtx0_rxpmasetphase_i,\r
+ RXDLYALIGNDISABLE => gtx0_rxdlyaligndisable_i,\r
+ RXDLYALIGNOVERRIDE => gtx0_rxdlyalignoverride_i,\r
+ RXDLYALIGNRESET => gtx0_rxdlyalignreset_i,\r
+ SYNC_DONE => gtx0_rx_sync_done_i,\r
+ USER_CLK => gtx0_rxusrclk2_i,\r
+ RESET => gtx0_reset_rxsync_c\r
+ );\r
+ \r
+ gtx0_reset_rxsync_c <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';\r
+ \r
+\r
+\r
+ -------------------------- User Module Resets -----------------------------\r
+ -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules\r
+ -- are held in reset till the RESETDONE goes high. \r
+ -- The RESETDONE is registered a couple of times on USRCLK2 and connected \r
+ -- to the reset of the modules\r
+ \r
+ process( gtx0_rxusrclk2_i)\r
+ begin\r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_i_r <= gtx0_rxresetdone_i after DLY;\r
+ end if; \r
+ end process; \r
+\r
+ process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)\r
+ begin\r
+ if(gtx0_rxresetdone_i_r = '0') then\r
+ gtx0_rxresetdone_r <= '0' after DLY;\r
+ gtx0_rxresetdone_r2 <= '0' after DLY;\r
+ elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_r <= gtx0_rxresetdone_i_r after DLY;\r
+ gtx0_rxresetdone_r2 <= gtx0_rxresetdone_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process( gtx0_rxusrclk2_i)\r
+ begin\r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_r3 <= gtx0_rxresetdone_r2 after DLY;\r
+ end if; \r
+ end process; \r
+\r
+ process( gtx0_txusrclk2_i,gtx0_txresetdone_i)\r
+ begin\r
+ if(gtx0_txresetdone_i = '0') then\r
+ gtx0_txresetdone_r <= '0' after DLY;\r
+ gtx0_txresetdone_r2 <= '0' after DLY;\r
+ elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then\r
+ gtx0_txresetdone_r <= gtx0_txresetdone_i after DLY;\r
+ gtx0_txresetdone_r2 <= gtx0_txresetdone_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ ------------------------------ Frame Generators ---------------------------\r
+ -- The example design uses Block RAM based frame generators to provide test\r
+ -- data to the GTXs for transmission. By default the frame generators are \r
+ -- loaded with an incrementing data sequence that includes commas/alignment\r
+ -- characters for alignment. If your protocol uses channel bonding, the \r
+ -- frame generator will also be preloaded with a channel bonding sequence.\r
+ \r
+ -- You can modify the data transmitted by changing the INIT values of the frame\r
+ -- generator in this file. Pay careful attention to bit order and the spacing\r
+ -- of your control and alignment characters.\r
+\r
+ gtx0_frame_gen : FRAME_GEN\r
+ generic map\r
+ (\r
+ WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
+ MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
+ )\r
+ port map\r
+ (\r
+ -- User Interface\r
+ TX_DATA(39 downto 8) => gtx0_txdata_float_i,\r
+ TX_DATA(7 downto 0) => gtx0_txdata_i,\r
+ \r
+ TX_CHARISK(3 downto 1) => gtx0_txcharisk_float_i,\r
+ TX_CHARISK(0) => gtx0_txcharisk_i,\r
+ -- System Interface\r
+ USER_CLK => gtx0_txusrclk2_i,\r
+ SYSTEM_RESET => gtx0_tx_system_reset_c\r
+ );\r
+ \r
+\r
+\r
+ ---------------------------------- Frame Checkers -------------------------\r
+ -- The example design uses Block RAM based frame checkers to verify incoming \r
+ -- data. By default the frame generators are loaded with a data sequence that \r
+ -- matches the outgoing sequence of the frame generators for the TX ports.\r
+ \r
+ -- You can modify the expected data sequence by changing the INIT values of the frame\r
+ -- checkers in this file. Pay careful attention to bit order and the spacing\r
+ -- of your control and alignment characters.\r
+ \r
+ -- When the frame checker receives data, it attempts to synchronise to the \r
+ -- incoming pattern by looking for the first sequence in the pattern. Once it \r
+ -- finds the first sequence, it increments through the sequence, and indicates an \r
+ -- error whenever the next value received does not match the expected value.\r
+\r
+ gtx0_frame_check_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;\r
+\r
+ -- gtx0_frame_check0 is always connected to the lane with the start of char\r
+ -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off\r
+ gtx0_inc_in_i <= '0';\r
+\r
+ process(gtx0_rxusrclk2_i)\r
+ begin \r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
+ gtx0_rxdata_r <= gtx0_rxdata_i after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process(gtx0_rxusrclk2_i)\r
+ begin \r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
+ gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i after DLY;\r
+ end if;\r
+ end process;\r
+ \r
+\r
+ \r
+ \r
+ gtx0_frame_check : FRAME_CHECK\r
+ generic map\r
+ (\r
+ RX_DATA_WIDTH => 8,\r
+ RXCTRL_WIDTH => 1,\r
+ USE_COMMA => 1,\r
+ WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
+ CONFIG_INDEPENDENT_LANES => 1,\r
+ START_OF_PACKET_CHAR => x"02bc",\r
+ MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
+ )\r
+ port map\r
+ (\r
+ -- MGT Interface\r
+ RX_DATA => gtx0_rxdata_r,\r
+ RXCTRL_IN => gtx0_rxcharisk_r,\r
+ RX_ENMCOMMA_ALIGN => gtx0_rxenmcommaalign_i,\r
+ RX_ENPCOMMA_ALIGN => gtx0_rxenpcommaalign_i,\r
+ RX_ENCHAN_SYNC => open,\r
+ RX_CHANBOND_SEQ => tied_to_ground_i,\r
+ -- Control Interface\r
+ INC_IN => gtx0_inc_in_i,\r
+ INC_OUT => gtx0_inc_out_i,\r
+ PATTERN_MATCH_N => gtx0_matchn_i,\r
+ RESET_ON_ERROR => gtx0_frame_check_reset_i,\r
+ -- System Interface\r
+ USER_CLK => gtx0_rxusrclk2_i,\r
+ SYSTEM_RESET => gtx0_rx_system_reset_c,\r
+ ERROR_COUNT => gtx0_error_count_i,\r
+ TRACK_DATA => gtx0_track_data_i\r
+ );\r
+ \r
+\r
+\r
+ TRACK_DATA_OUT <= track_data_out_i;\r
+\r
+ track_data_out_i <= \r
+ gtx0_track_data_i ;\r
+\r
+\r
+\r
+ ----------------------------- Chipscope Connections -----------------------\r
+ -- When the example design is run in hardware, it uses chipscope to allow the\r
+ -- example design and GTX wrapper to be controlled and monitored. The \r
+ -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.\r
+ \r
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate\r
+ \r
+ \r
+ -- Shared VIO for all transievers \r
+ shared_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => shared_vio_control_i,\r
+ clk => tied_to_ground_i,\r
+ async_in => shared_vio_in_i,\r
+ async_out => shared_vio_out_i,\r
+ sync_in => tied_to_ground_vec_i(31 downto 0),\r
+ sync_out => open\r
+ );\r
+ \r
+ -- ICON for all VIOs \r
+ i_icon : icon\r
+ port map\r
+ (\r
+ control0 => shared_vio_control_i,\r
+ control1 => tx_data_vio_control_i,\r
+ control2 => rx_data_vio_control_i,\r
+ control3 => ila_control_i\r
+ );\r
+\r
+ \r
+ -- TX VIO \r
+ tx_data_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => tx_data_vio_control_i,\r
+ clk => gtx0_txusrclk2_i,\r
+ async_in => tx_data_vio_async_in_i,\r
+ async_out => tx_data_vio_async_out_i,\r
+ sync_in => tx_data_vio_sync_in_i,\r
+ sync_out => tx_data_vio_sync_out_i\r
+ );\r
+ \r
+ -- RX VIO \r
+ rx_data_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => rx_data_vio_control_i,\r
+ clk => gtx0_rxusrclk2_i,\r
+ async_in => rx_data_vio_async_in_i,\r
+ async_out => rx_data_vio_async_out_i,\r
+ sync_in => rx_data_vio_sync_in_i,\r
+ sync_out => rx_data_vio_sync_out_i\r
+ );\r
+ \r
+ -- RX ILA\r
+ ila_i : ila\r
+ port map\r
+ (\r
+ control => ila_control_i,\r
+ clk => gtx0_rxusrclk2_i,\r
+ trig0 => ila_in_i\r
+ );\r
+\r
+\r
+\r
+ -- assign resets for frame_gen modules\r
+ gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i or user_tx_reset_i;\r
+ -- assign resets for frame_check modules\r
+ gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i or user_rx_reset_i;\r
+\r
+ gtx0_gtxtxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
+ gtx0_gtxrxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
+
+ -- Shared VIO Outputs
+ gtxtxreset_i <= shared_vio_out_i(31);
+ gtxrxreset_i <= shared_vio_out_i(30);
+ user_tx_reset_i <= shared_vio_out_i(29);
+ user_rx_reset_i <= shared_vio_out_i(28);
+
+ -- Shared VIO Inputs
+ shared_vio_in_i(31 downto 0) <= "00000000000000000000000000000000";
+
+ -- Chipscope connections on GTX 0
+ gtx0_tx_data_vio_async_in_i(31) <= '0';
+ gtx0_tx_data_vio_async_in_i(30) <= gtx0_txresetdone_i;
+ gtx0_tx_data_vio_async_in_i(29 downto 22) <= gtx0_txdlyalignmonitor_i;
+ gtx0_tx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
+ gtx0_tx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
+ gtx0_txdlyalignmonenb_i <= tx_data_vio_async_out_i(30);
+ gtx0_rx_data_vio_async_in_i(31) <= gtx0_rxplllkdet_i;
+ gtx0_rx_data_vio_async_in_i(30) <= gtx0_rxresetdone_i;
+ gtx0_rx_data_vio_async_in_i(29 downto 22) <= gtx0_rxdlyalignmonitor_i;
+ gtx0_rx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
+ gtx0_rx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
+ gtx0_pllrxreset_i <= rx_data_vio_async_out_i(31);
+ gtx0_rxcdrreset_i <= rx_data_vio_async_out_i(30);
+ gtx0_ila_in_i(84) <= gtx0_rxcharisk_i;
+ gtx0_ila_in_i(83) <= gtx0_rxdisperr_i;
+ gtx0_ila_in_i(82) <= gtx0_rxnotintable_i;
+ gtx0_ila_in_i(81 downto 74) <= gtx0_rxdata_i;
+ gtx0_ila_in_i(73 downto 71) <= gtx0_rxstatus_i;
+ gtx0_ila_in_i(70 downto 69) <= gtx0_rxlossofsync_i;
+ gtx0_ila_in_i(68) <= gtx0_phystatus_i;
+ gtx0_ila_in_i(67 downto 60) <= gtx0_error_count_i;
+ gtx0_ila_in_i(59 downto 0) <= "000000000000000000000000000000000000000000000000000000000000";
+\r
+\r
+\r
+ tx_data_vio_async_in_i <= gtx0_tx_data_vio_async_in_i;
+\r
+\r
+ tx_data_vio_sync_in_i <= gtx0_tx_data_vio_sync_in_i;
+\r
+ rx_data_vio_async_in_i <= gtx0_rx_data_vio_async_in_i;
+\r
+\r
+ rx_data_vio_sync_in_i <= gtx0_rx_data_vio_sync_in_i;
+\r
+\r
+ ila_in_i <= gtx0_ila_in_i;
+\r
+\r
+end generate chipscope;\r
+\r
+\r
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate\r
+\r
+ -- If Chipscope is not being used, drive GTX reset signal\r
+ -- from the top level ports\r
+ gtx0_gtxtxreset_i <= GTXTXRESET_IN;\r
+ gtx0_gtxrxreset_i <= GTXRXRESET_IN;\r
+\r
+ -- assign resets for frame_gen modules\r
+ gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i;\r
+ -- assign resets for frame_check modules\r
+ gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i;\r
+\r
+ gtxtxreset_i <= tied_to_ground_i;
+ gtxrxreset_i <= tied_to_ground_i;
+ user_tx_reset_i <= tied_to_ground_i;
+ user_rx_reset_i <= tied_to_ground_i;
+ gtx0_txdlyalignmonenb_i <= tied_to_ground_i;
+ gtx0_pllrxreset_i <= tied_to_ground_i;
+ gtx0_rxcdrreset_i <= tied_to_ground_i;
+\r
+\r
+\r
+end generate no_chipscope;\r
+\r
+\r
+end RTL;\r
+\r
+\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : gtxvirtex6fee80_tx_sync.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxvirtex6fee80_tx_sync\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity gtxvirtex6fee80_tx_sync is\r
+generic\r
+(\r
+ SIM_TXPMASETPHASE_SPEEDUP : integer:=0\r
+); \r
+port\r
+(\r
+ TXENPMAPHASEALIGN : out std_logic;\r
+ TXPMASETPHASE : out std_logic;\r
+ TXDLYALIGNDISABLE : out std_logic;\r
+ TXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+\r
+\r
+end gtxvirtex6fee80_tx_sync;\r
+\r
+architecture RTL of gtxvirtex6fee80_tx_sync is\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+\r
+ signal begin_r : std_logic;\r
+ signal phase_align_r : std_logic;\r
+ signal ready_r : std_logic;\r
+ signal sync_counter_r : unsigned(15 downto 0);\r
+ signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
+ signal align_reset_counter_r : unsigned(4 downto 0);\r
+ signal wait_before_setphase_r : std_logic;\r
+ signal align_reset_r : std_logic;\r
+ \r
+--*******************************Wire Declarations****************************\r
+ \r
+ signal count_setphase_complete_r : std_logic;\r
+ signal count_32_complete_r : std_logic;\r
+ signal count_align_reset_complete_r : std_logic;\r
+ signal next_phase_align_c : std_logic;\r
+ signal next_ready_c : std_logic;\r
+ signal next_wait_before_setphase_c : std_logic;\r
+ signal next_align_reset_c : std_logic;\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ --________________________________ State machine __________________________ \r
+ -- This state machine manages the TX phase alignment procedure of the GTX.\r
+ -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE \r
+ -- is asserted, the state machine goes into the align_reset_r state, asserting\r
+ -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the \r
+ -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and \r
+ -- waiting 32 cycles, it goes into the phase_align_r state where the last \r
+ -- part of the alignment procedure is completed. This involves asserting \r
+ -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), \r
+ -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase \r
+ -- alignment procedure, TXDLYALIGNDISABLE is deasserted.\r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET='1') then\r
+ begin_r <= '1' after DLY;\r
+ align_reset_r <= '0' after DLY;\r
+ wait_before_setphase_r <= '0' after DLY;\r
+ phase_align_r <= '0' after DLY;\r
+ ready_r <= '0' after DLY;\r
+ else\r
+ begin_r <= '0' after DLY;\r
+ align_reset_r <= next_align_reset_c after DLY;\r
+ wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
+ phase_align_r <= next_phase_align_c after DLY;\r
+ ready_r <= next_ready_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_align_reset_c <= begin_r or \r
+ (align_reset_r and not count_align_reset_complete_r);\r
+ \r
+ next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or \r
+ (wait_before_setphase_r and not count_32_complete_r);\r
+ \r
+ next_phase_align_c <= (wait_before_setphase_r and count_32_complete_r) or\r
+ (phase_align_r and not count_setphase_complete_r);\r
+ \r
+ next_ready_c <= (phase_align_r and count_setphase_complete_r) or\r
+ ready_r;\r
+\r
+ --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (align_reset_r='0') then\r
+ align_reset_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+ count_align_reset_complete_r <= align_reset_counter_r(4) \r
+ and align_reset_counter_r(2);\r
+\r
+ --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (wait_before_setphase_r='0') then\r
+ wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_complete_r <= wait_before_setphase_counter_r(5);\r
+\r
+ --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (phase_align_r='0') then\r
+ sync_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ sync_counter_r <= sync_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate\r
+ -- 64 cycles of setphase for simulation\r
+ count_setphase_complete_r <= sync_counter_r(6);\r
+end generate fast_simulation;\r
+\r
+no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate\r
+ -- 16384 cycles of setphase for output divider of 2\r
+ count_setphase_complete_r <= sync_counter_r(14);\r
+end generate no_fast_simulation;\r
+\r
+ --_______________ Assign the phase align ports into the GTX _______________\r
+\r
+ TXDLYALIGNRESET <= '0';\r
+ TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
+ TXPMASETPHASE <= phase_align_r;\r
+ TXDLYALIGNDISABLE <= '1';\r
+\r
+ --_______________________ Assign the sync_done port _______________________\r
+ \r
+ SYNC_DONE <= ready_r;\r
+ \r
+ \r
+end RTL;\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : mgt_usrclk_source_mmcm.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+use ieee.std_logic_unsigned.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration*******************************\r
+entity MGT_USRCLK_SOURCE_MMCM is\r
+generic\r
+(\r
+ MULT : real := 2.0;\r
+ DIVIDE : integer := 2; \r
+ CLK_PERIOD : real := 6.4; \r
+ OUT0_DIVIDE : real := 2.0;\r
+ OUT1_DIVIDE : integer := 2;\r
+ OUT2_DIVIDE : integer := 2;\r
+ OUT3_DIVIDE : integer := 2\r
+);\r
+port\r
+(\r
+ CLKFBOUT : out std_logic; \r
+ CLK0_OUT : out std_logic;\r
+ CLK1_OUT : out std_logic;\r
+ CLK2_OUT : out std_logic;\r
+ CLK3_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ MMCM_LOCKED_OUT : out std_logic;\r
+ MMCM_RESET_IN : in std_logic\r
+);\r
+\r
+\r
+end MGT_USRCLK_SOURCE_MMCM;\r
+\r
+architecture RTL of MGT_USRCLK_SOURCE_MMCM is\r
+--*********************************Wire Declarations**********************************\r
+\r
+ signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal clkout0_i : std_logic;\r
+ signal clkout1_i : std_logic;\r
+ signal clkout2_i : std_logic;\r
+ signal clkout3_i : std_logic;\r
+ signal clkfbout_i : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+\r
+begin\r
+\r
+--*********************************** Beginning of Code *******************************\r
+\r
+ -- Static signal Assigments \r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_vcc_i <= '1';\r
+\r
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback\r
+ -- for improved jitter performance, and to avoid consuming an additional BUFG\r
+ mmcm_adv_i : MMCM_ADV\r
+ generic map\r
+ (\r
+ COMPENSATION => "ZHOLD",\r
+ CLKFBOUT_MULT_F => MULT,\r
+ DIVCLK_DIVIDE => DIVIDE,\r
+ CLKFBOUT_PHASE => 0.0,\r
+ CLKIN1_PERIOD => CLK_PERIOD,\r
+ CLKIN2_PERIOD => 10.0, -- Not used\r
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,\r
+ CLKOUT0_PHASE => 0.0,\r
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,\r
+ CLKOUT1_PHASE => 0.0,\r
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,\r
+ CLKOUT2_PHASE => 0.0,\r
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,\r
+ CLKOUT3_PHASE => 0.0,\r
+ CLOCK_HOLD => TRUE \r
+ )\r
+ port map\r
+ (\r
+ CLKIN1 => CLK_IN,\r
+ CLKIN2 => tied_to_ground_i,\r
+ CLKINSEL => tied_to_vcc_i,\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKOUT0 => clkout0_i,\r
+ CLKOUT0B => open,\r
+ CLKOUT1 => clkout1_i,\r
+ CLKOUT1B => open,\r
+ CLKOUT2 => clkout2_i,\r
+ CLKOUT2B => open,\r
+ CLKOUT3 => clkout3_i,\r
+ CLKOUT3B => open,\r
+ CLKOUT4 => open,\r
+ CLKOUT5 => open,\r
+ CLKOUT6 => open,\r
+ CLKFBOUT => clkfbout_i,\r
+ CLKFBOUTB => open,\r
+ CLKFBSTOPPED => open,\r
+ CLKINSTOPPED => open,\r
+ DO => open,\r
+ DRDY => open,\r
+ DADDR => tied_to_ground_vec_i(6 downto 0),\r
+ DCLK => tied_to_ground_i,\r
+ DEN => tied_to_ground_i,\r
+ DI => tied_to_ground_vec_i(15 downto 0),\r
+ DWE => tied_to_ground_i,\r
+ LOCKED => MMCM_LOCKED_OUT,\r
+ PSCLK => tied_to_ground_i,\r
+ PSEN => tied_to_ground_i, \r
+ PSINCDEC => tied_to_ground_i, \r
+ PSDONE => open, \r
+ PWRDWN => tied_to_ground_i,\r
+ RST => MMCM_RESET_IN \r
+ );\r
+ \r
+ clkfb_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => clkfbout_buf, \r
+ I => clkfbout_i\r
+ ); \r
+ CLKFBOUT <= clkfbout_buf;\r
+ \r
+ clkout0_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK0_OUT, \r
+ I => clkout0_i\r
+ ); \r
+\r
+\r
+ clkout1_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK1_OUT,\r
+ I => clkout1_i\r
+ );\r
+ \r
+ \r
+ clkout2_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK2_OUT, \r
+ I => clkout2_i\r
+ ); \r
+\r
+\r
+ clkout3_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK3_OUT,\r
+ I => clkout3_i\r
+ ); \r
+ \r
+end RTL;\r
+ \r
--- /dev/null
+description=User generated protocol\r
+rx_line_rate=2\r
+use_rx_oversampling=false\r
+rx_divider=/2\r
+rx_datapath_width=10\r
+decoding=8B/10B\r
+rx_reference_clock=80.00\r
+tx_line_rate=2\r
+use_tx_oversampling=false\r
+tx_divider=/2\r
+tx_datapath_width=10\r
+encoding=8B/10B\r
+tx_reference_clock=80.00\r
+use_port_rxoversampleerr=false\r
+use_port_drp=false\r
+ppm_offset=0_(Synchronous)\r
+use_port_txbypass8b10b=false\r
+use_port_txchardispmode=false\r
+use_port_txchardispval=false\r
+use_port_txkerr=false\r
+use_port_txrundisp=false\r
+use_port_rxchariscomma=false\r
+use_port_rxcharisk=true\r
+use_port_rxrundisp=false\r
+use_txbuffer=false\r
+use_rxbuffer=false\r
+txusrclk_source=TXOUTCLK\r
+use_external_txusrclk=false\r
+rxusrclk_source=RXRECCLK\r
+use_external_rxusrclk=false\r
+use_port_txoutclk=true\r
+use_port_txreset=true\r
+use_port_txbufstatus=false\r
+use_port_rxreset=true\r
+use_port_rxrecclk=true\r
+use_port_rxbufstatus=false\r
+use_port_rxbufreset=false\r
+use_comma_detect=true\r
+dec_valid_comma_only=false\r
+comma_preset=K28.5\r
+plus_comma=0101111100\r
+minus_comma=1010000011\r
+comma_mask=1111111100\r
+comma_double=false\r
+comma_alignment=Any_Byte_Boundary\r
+use_port_enpcommaalign=true\r
+use_port_enmcommaalign=true\r
+use_port_rxslide=false\r
+use_port_rxbyteisaligned=false\r
+use_port_rxbyterealign=false\r
+use_port_rxcommadet=false\r
+preemphasis_level=0000\r
+driver_swing=1000\r
+wideband_highpass_mix=000\r
+enable_dfe=false\r
+dfe_mode=Fixed_tap_mode\r
+disable_ac_coupling=true\r
+rx_termination_voltage=MGTAVTT\r
+postemphasis_level=00000\r
+use_port_txpolarity=false\r
+use_port_txinhibit=false\r
+use_port_rxpolarity=false\r
+use_port_rxcdrreset=true\r
+pci_express_mode=false\r
+com_burst_val=15\r
+sata_burst_val=4\r
+sata_idle_val=4\r
+trans_time_to_p2=100\r
+trans_time_from_p2=60\r
+trans_time_non_p2=25\r
+use_port_loopback=false\r
+use_port_rxpowerdown=false\r
+use_port_rxstatus=true\r
+use_port_rxvalid=false\r
+use_port_cominitdet=false\r
+use_port_comsasdet=false\r
+use_port_comwakedet=false\r
+use_port_txcominit=false\r
+use_port_txcomsas=false\r
+use_port_txcomwake=false\r
+use_port_comfinish=false\r
+use_port_txpowerdown=false\r
+use_port_txdetectrx=false\r
+use_port_txelecidle=false\r
+use_port_phystatus=true\r
+use_rx_oob=false\r
+rx_oob_threshold=011\r
+use_prbs_detector=false\r
+use_port_txenprbstst=false\r
+use_port_txprbsforceerr=false\r
+use_port_rxlossofsync=true\r
+rxlossofsyncport=true\r
+errors_to_lose_sync=256\r
+bytes_to_reduce_error=8\r
+use_cb=false\r
+cb_sequence_length=1\r
+cb_sequence_1_max_skew=1\r
+use_two_cb_sequences=false\r
+cb_sequence_2_max_skew=1\r
+cb_seq_1_1_mask=true\r
+cb_seq_1_1=00000000\r
+cb_seq_1_1_k=false\r
+cb_seq_1_1_disp=false\r
+cb_seq_1_2_mask=true\r
+cb_seq_1_2=00000000\r
+cb_seq_1_2_k=false\r
+cb_seq_1_2_disp=false\r
+cb_seq_1_3_mask=true\r
+cb_seq_1_3=00000000\r
+cb_seq_1_3_k=false\r
+cb_seq_1_3_disp=false\r
+cb_seq_1_4_mask=true\r
+cb_seq_1_4=00000000\r
+cb_seq_1_4_k=false\r
+cb_seq_1_4_disp=false\r
+cb_seq_2_1_mask=true\r
+cb_seq_2_1=00000000\r
+cb_seq_2_1_k=false\r
+cb_seq_2_1_disp=false\r
+cb_seq_2_2_mask=true\r
+cb_seq_2_2=00000000\r
+cb_seq_2_2_k=false\r
+cb_seq_2_2_disp=false\r
+cb_seq_2_3_mask=true\r
+cb_seq_2_3=00000000\r
+cb_seq_2_3_k=false\r
+cb_seq_2_3_disp=false\r
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+\r
--- /dev/null
+#ChipScope Pro Analyzer Project File, Version 3.0\r
+#Thu Jul 27 15:56:09 IST 2006\r
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+\r
+\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
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0;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::5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\ No newline at end of file
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
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\ No newline at end of file
--- /dev/null
+\r
+REM\r
+REM ____ ____\r
+REM / /\/ /\r
+REM /___/ \ / Vendor: Xilinx\r
+REM \ \ \/ Version : 1.12\r
+REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+REM / / Filename : implement_bat.ejava\r
+REM /___/ /\ \r
+REM \ \ / \\r
+REM \___\/\___\\r
+REM\r
+REM\r
+REM implement.sh script\r
+REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+REM\r
+REM\r
+REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+REM \r
+REM This file contains confidential and proprietary information\r
+REM of Xilinx, Inc. and is protected under U.S. and \r
+REM international copyright and other intellectual property\r
+REM laws.\r
+REM \r
+REM DISCLAIMER\r
+REM This disclaimer is not a license and does not grant any\r
+REM rights to the materials distributed herewith. Except as\r
+REM otherwise provided in a valid license issued to you by\r
+REM Xilinx, and to the maximum extent permitted by applicable\r
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+REM (2) Xilinx shall not be liable (whether in contract or tort,\r
+REM including negligence, or under any other theory of\r
+REM liability) for any loss or damage of any kind or nature\r
+REM related to, arising under or in connection with these\r
+REM materials, including for any direct, or any indirect,\r
+REM special, incidental, or consequential loss or damage\r
+REM (including loss of data, profits, goodwill, or any type of\r
+REM loss or damage suffered as a result of any action brought\r
+REM by a third party) even if such damage or loss was\r
+REM reasonably foreseeable or Xilinx had been advised of the\r
+REM possibility of the same.\r
+REM\r
+REM CRITICAL APPLICATIONS\r
+REM Xilinx products are not designed or intended to be fail-\r
+REM safe, or for use in any application requiring fail-safe\r
+REM performance, such as life-support or safety devices or\r
+REM systems, Class III medical devices, nuclear facilities,\r
+REM applications related to the deployment of airbags, or any\r
+REM other applications that could lead to death, personal\r
+REM injury, or severe property or environmental damage\r
+REM (individually and collectively, "Critical\r
+REM Applications"). Customer assumes the sole risk and\r
+REM liability of any use of Xilinx products in Critical\r
+REM Applications, subject only to applicable laws and\r
+REM regulations governing limitations on product liability.\r
+REM\r
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+REM PART OF THIS FILE AT ALL TIMES.\r
+\r
+REM Set XST as default synthesizer\r
+\r
+REM Read command line arguments\r
+\r
+REM Change CWD to results\r
+\r
+REM Clean results directory\r
+REM Create results directory\r
+REM Change current directory to results\r
+ECHO WARNING: Removing existing results directory\r
+RMDIR /S /Q results\r
+MKDIR results\r
+COPY xst.prj .\results\\r
+COPY xst.scr .\results\\r
+COPY *.ngc .\results\\r
+\r
+REM Run Synthesis\r
+\r
+ECHO "### Running Xst - "\r
+xst -ifn xst.scr\r
+\r
+COPY gtxVirtex6FEE80_top.ngc .\results\r
+cd .\results\r
+\r
+REM Run ngdbuild\r
+\r
+ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd\r
+\r
+REM end run ngdbuild section\r
+\r
+REM Run map\r
+\r
+ECHO 'Running NGD'\r
+map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
+\r
+REM Run par\r
+\r
+ECHO 'Running par'\r
+par mapped.ncd routed.ncd \r
+\r
+REM Report par results\r
+\r
+ECHO 'Running design through bitgen'\r
+bitgen -w routed.ncd\r
+\r
+REM Trace Report\r
+\r
+ECHO 'Running trce'\r
+trce -e 10 routed.ncd mapped.pcf -o routed\r
+\r
+REM Run netgen\r
+\r
+ECHO 'Running netgen to create gate level VHDL model'\r
+netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
+\r
+REM Change directory to implement\r
+\r
+CD ..\r
+\r
--- /dev/null
+#!/bin/bash\r
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : implement_sh.ejava \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## implement.sh script \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+#-----------------------------------------------------------------------------\r
+# Script to synthesize and implement the RTL provided for the GTX wizard\r
+#-----------------------------------------------------------------------------\r
+\r
+##---------------------Change CWD to results-------------------------------------\r
+\r
+#Clean results directory\r
+#Create results directory\r
+#Change current directory to results\r
+echo "WARNING: Removing existing results directory"\r
+rm -rf results\r
+mkdir results\r
+cp xst.prj ./results\r
+cp xst.scr ./results\r
+cp *.ngc ./results\r
+\r
+##-----------------------------Run Synthesis-------------------------------------\r
+\r
+echo "### Running Xst - "\r
+xst -ifn xst.scr\r
+\r
+cp gtxVirtex6FEE80_top.ngc ./results\r
+cd ./results\r
+\r
+##-------------------------------Run ngdbuild---------------------------------------\r
+\r
+echo 'Running ngdbuild'\r
+ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd\r
+\r
+#end run ngdbuild section\r
+\r
+##-------------------------------Run map-------------------------------------------\r
+\r
+echo 'Running map'\r
+map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
+\r
+##-------------------------------Run par-------------------------------------------\r
+\r
+echo 'Running par'\r
+par mapped.ncd routed.ncd\r
+\r
+##---------------------------Report par results-------------------------------------\r
+\r
+echo 'Running design through bitgen'\r
+bitgen -w routed.ncd\r
+\r
+##-------------------------------Trace Report---------------------------------------\r
+\r
+echo 'Running trce'\r
+trce -e 10 routed.ncd mapped.pcf -o routed \r
+\r
+##-------------------------------Run netgen------------------------------------------\r
+\r
+echo 'Running netgen to create gate level VHDL model'\r
+netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
+\r
+#Change directory to implement\r
+\r
+cd ..\r
+\r
--- /dev/null
+\r
+REM\r
+REM ____ ____\r
+REM / /\/ /\r
+REM /___/ \ / Vendor: Xilinx\r
+REM \ \ \/ Version : 1.12\r
+REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+REM / / Filename : implement_synplify_bat.ejava\r
+REM /___/ /\ \r
+REM \ \ / \\r
+REM \___\/\___\\r
+REM\r
+REM\r
+REM implement_synplify.bat script\r
+REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+REM\r
+REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+REM \r
+REM This file contains confidential and proprietary information\r
+REM of Xilinx, Inc. and is protected under U.S. and \r
+REM international copyright and other intellectual property\r
+REM laws.\r
+REM \r
+REM DISCLAIMER\r
+REM This disclaimer is not a license and does not grant any\r
+REM rights to the materials distributed herewith. Except as\r
+REM otherwise provided in a valid license issued to you by\r
+REM Xilinx, and to the maximum extent permitted by applicable\r
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+REM (2) Xilinx shall not be liable (whether in contract or tort,\r
+REM including negligence, or under any other theory of\r
+REM liability) for any loss or damage of any kind or nature\r
+REM related to, arising under or in connection with these\r
+REM materials, including for any direct, or any indirect,\r
+REM special, incidental, or consequential loss or damage\r
+REM (including loss of data, profits, goodwill, or any type of\r
+REM loss or damage suffered as a result of any action brought\r
+REM by a third party) even if such damage or loss was\r
+REM reasonably foreseeable or Xilinx had been advised of the\r
+REM possibility of the same.\r
+REM\r
+REM CRITICAL APPLICATIONS\r
+REM Xilinx products are not designed or intended to be fail-\r
+REM safe, or for use in any application requiring fail-safe\r
+REM performance, such as life-support or safety devices or\r
+REM systems, Class III medical devices, nuclear facilities,\r
+REM applications related to the deployment of airbags, or any\r
+REM other applications that could lead to death, personal\r
+REM injury, or severe property or environmental damage\r
+REM (individually and collectively, "Critical\r
+REM Applications"). Customer assumes the sole risk and\r
+REM liability of any use of Xilinx products in Critical\r
+REM Applications, subject only to applicable laws and\r
+REM regulations governing limitations on product liability.\r
+REM\r
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+REM PART OF THIS FILE AT ALL TIMES.\r
+\r
+REM Set XST as default synthesizer\r
+\r
+REM Read command line arguments\r
+\r
+REM Change CWD to results\r
+\r
+REM Clean results directory\r
+REM Create results directory\r
+REM Change current directory to results\r
+ECHO WARNING: Removing existing results directory\r
+RMDIR /S /Q results\r
+MKDIR results\r
+COPY synplify.prj .\results\\r
+COPY *.ngc .\results\\r
+\r
+REM Run Synthesis\r
+\r
+ECHO "### Running Synplify Pro - "\r
+synplify_pro -batch synplify.prj\r
+\r
+COPY gtxVirtex6FEE80_top.edf .\results\r
+cd .\results\r
+\r
+REM Run ngdbuild\r
+\r
+ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd\r
+\r
+REM end run ngdbuild section\r
+\r
+REM Run map\r
+\r
+ECHO 'Running NGD'\r
+map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
+\r
+REM Run par\r
+\r
+ECHO 'Running par'\r
+par mapped.ncd routed.ncd \r
+\r
+REM Report par results\r
+\r
+ECHO 'Running design through bitgen'\r
+bitgen -w routed.ncd\r
+\r
+REM Trace Report\r
+\r
+ECHO 'Running trce'\r
+trce -e 10 routed.ncd mapped.pcf -o routed\r
+\r
+REM Run netgen\r
+\r
+ECHO 'Running netgen to create gate level VHDL model'\r
+netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
+\r
+REM Change directory to implement\r
+\r
+CD ..\r
+\r
--- /dev/null
+#!/bin/bash\r
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : implement_synplify_sh.ejava \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## implement_synplify.sh script \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+#-----------------------------------------------------------------------------\r
+# Script to synthesize and implement the RTL provided for the GTX wizard\r
+#-----------------------------------------------------------------------------\r
+\r
+##---------------------Change CWD to results-------------------------------------\r
+\r
+#Clean results directory\r
+#Create results directory\r
+#Change current directory to results\r
+echo "WARNING: Removing existing results directory"\r
+rm -rf results\r
+mkdir results\r
+cp synplify.prj ./results\r
+cp *.ngc ./results\r
+\r
+##-----------------------------Run Synthesis-------------------------------------\r
+\r
+echo "### Running Synplify Pro - "\r
+synplify_pro -batch synplify.prj\r
+\r
+cp gtxVirtex6FEE80_top.edf ./results\r
+cd ./results\r
+\r
+##-------------------------------Run ngdbuild---------------------------------------\r
+\r
+echo 'Running ngdbuild'\r
+ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd\r
+\r
+#end run ngdbuild section\r
+\r
+##-------------------------------Run map-------------------------------------------\r
+\r
+echo 'Running map'\r
+map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd\r
+\r
+##-------------------------------Run par-------------------------------------------\r
+\r
+echo 'Running par'\r
+par mapped.ncd routed.ncd\r
+\r
+##---------------------------Report par results-------------------------------------\r
+\r
+echo 'Running design through bitgen'\r
+bitgen -w routed.ncd\r
+\r
+##-------------------------------Trace Report---------------------------------------\r
+\r
+echo 'Running trce'\r
+trce -e 10 routed.ncd mapped.pcf -o routed \r
+\r
+##-------------------------------Run netgen------------------------------------------\r
+\r
+echo 'Running netgen to create gate level VHDL model'\r
+netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd\r
+\r
+#Change directory to implement\r
+\r
+cd ..\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : planAhead_ise.bat \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## planAhead_ise.bat script \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+##\r
+## planAhead_ise.bat script \r
+##\r
+################################################################################\r
+\r
+#-----------------------------------------------------------------------------\r
+# Command to run the planAhead in batch mode \r
+#-----------------------------------------------------------------------------\r
+planAhead -mode batch -source planAhead_ise.tcl\r
+#end\r
--- /dev/null
+#!/bin/bash\r
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : planAhead_ise.sh \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## planAhead_ise.sh script \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+##\r
+##\r
+################################################################################\r
+\r
+#-----------------------------------------------------------------------------\r
+# Command to run the planAhead in batch mode \r
+#-----------------------------------------------------------------------------\r
+planAhead -mode batch -source ./planAhead_ise.tcl\r
+#end\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : planAhead_ise.tcl \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## planAhead_ise.tcl script \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+##\r
+##\r
+################################################################################\r
+\r
+## Environment Setup\r
+set projDir [file dirname [info script]]\r
+set projName gtxVirtex6FEE80\r
+set topName gtxVirtex6FEE80_top\r
+set device xc6vlx130t-ff484-3\r
+\r
+## if the project directory exists, delete it and create a new clean one\r
+if {[file exists $projDir/$projName]} {\r
+file delete -force $projDir/$projName\r
+}\r
+\r
+## Create Project\r
+create_project $projName $projDir/$projName -part $device\r
+\r
+## Project Option\r
+set_property design_mode RTL [get_filesets sources_1]\r
+\r
+## Source Files\r
+add_files -norecurse ../example_design/mgt_usrclk_source_mmcm.vhd\r
+add_files -norecurse ../example_design/gtxvirtex6fee80_tx_sync.vhd\r
+add_files -norecurse ../example_design/gtxvirtex6fee80_rx_sync.vhd\r
+add_files -norecurse ../example_design/double_reset.vhd\r
+add_files -norecurse ../example_design/frame_gen.vhd\r
+add_files -norecurse ../example_design/frame_check.vhd\r
+add_files -norecurse ../../gtxvirtex6fee80_gtx.vhd\r
+add_files -norecurse ../../gtxvirtex6fee80.vhd\r
+add_files -norecurse ../example_design/gtxvirtex6fee80_top.vhd\r
+\r
+## UCF Files\r
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtxVirtex6FEE80_top.ucf\r
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtx_attributes.ucf\r
+\r
+## NGC Files\r
+import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/data_vio.ngc \r
+import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/ila.ngc \r
+import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/icon.ngc\r
+ \r
+ \r
+\r
+## Set the Top module\r
+set_property top $topName [get_property srcset [current_run]]\r
+\r
+## Run Synthesis\r
+launch_runs -runs synth_1\r
+wait_on_run synth_1\r
+\r
+## Run Implementation\r
+set_property strategy {ISE Defaults} [get_runs impl_1]\r
+\r
+\r
+#config_run -run impl_1 -program par -option -ol -value high\r
+\r
+launch_runs -runs impl_1\r
+wait_on_run impl_1\r
+\r
+## Run BitGen\r
+set_property add_step Bitgen [get_runs impl_1]\r
+launch_runs -runs impl_1\r
+wait_on_run impl_1\r
+\r
+exit\r
+## End\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : synplify.prj \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## synplify.prj\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+add_file -vhdl "../example_design/mgt_usrclk_source_mmcm.vhd"\r
+add_file -vhdl "../example_design/gtxvirtex6fee80_tx_sync.vhd"\r
+add_file -vhdl "../example_design/gtxvirtex6fee80_rx_sync.vhd"\r
+add_file -vhdl "../example_design/double_reset.vhd"\r
+add_file -vhdl "../example_design/frame_gen.vhd"\r
+add_file -vhdl "../example_design/frame_check.vhd"\r
+add_file -vhdl "../../gtxvirtex6fee80_gtx.vhd"\r
+add_file -vhdl "../../gtxvirtex6fee80.vhd"\r
+add_file -vhdl "../example_design/gtxvirtex6fee80_top.vhd"\r
+\r
+add_file -constraint "../example_design/gtxvirtex6fee80_top.sdc"\r
+\r
+project -result_file "gtxvirtex6fee80_top.edf"\r
+set_option -top_module gtxVirtex6FEE80_top\r
+set_option -technology virtex6\r
+set_option -part xc6vlx130t\r
+set_option -package ff484\r
+set_option -speed_grade -3\r
+\r
+#compilation/mapping options\r
+set_option -default_enum_encoding default\r
+set_option -symbolic_fsm_compiler 1\r
+set_option -resource_sharing 1\r
+\r
+#map options\r
+set_option -frequency 160.000\r
+set_option -fanout_limit 100\r
+set_option -disable_io_insertion 0\r
+set_option -pipe 0\r
+set_option -retiming 0\r
+\r
+#simulation options\r
+set_option -write_verilog 0\r
+set_option -write_vhdl 0\r
+set_option -vlog_std v2001\r
+\r
+#Do not generate ncf constraints file\r
+set_option -write_apr_constraint 0\r
+\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
+$400
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\ No newline at end of file
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : xst.prj \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## xst.prj\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+vhdl work "../example_design/mgt_usrclk_source_mmcm.vhd"\r
+vhdl work "../example_design/gtxvirtex6fee80_tx_sync.vhd"\r
+vhdl work "../example_design/gtxvirtex6fee80_rx_sync.vhd"\r
+vhdl work "../example_design/double_reset.vhd"\r
+vhdl work "../example_design/frame_gen.vhd"\r
+vhdl work "../example_design/frame_check.vhd"\r
+vhdl work "../../gtxvirtex6fee80_gtx.vhd"\r
+vhdl work "../../gtxvirtex6fee80.vhd"\r
+vhdl work "../example_design/gtxvirtex6fee80_top.vhd"\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : xst.scr \r
+## /___/ /\ \r
+## \ \ / \\r
+## \___\/\___\\r
+##\r
+##\r
+## xst.scr \r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+run\r
+-ifn xst.prj\r
+-ifmt mixed \r
+-ofn gtxVirtex6FEE80_top.ngc \r
+-ofmt NGC\r
+-p xc6vlx130t-3ff484\r
+-top gtxVirtex6FEE80_top\r
+-opt_mode Speed\r
+-opt_level 1\r
+-iuc NO\r
+-keep_hierarchy NO\r
+-glob_opt AllClockNets\r
+-rtlview Yes\r
+-read_cores YES\r
+-write_timing_constraints NO\r
+-cross_clock_analysis NO\r
+-hierarchy_separator /\r
+-bus_delimiter ()\r
+-case maintain\r
+-slice_utilization_ratio 100\r
+-fsm_extract YES\r
+-fsm_encoding Auto\r
+-ram_extract No\r
+-ram_style Auto\r
+-rom_extract No\r
+-rom_style Auto\r
+-shreg_extract YES\r
+-resource_sharing YES\r
+-mult_style auto\r
+-iobuf YES\r
+-max_fanout REDUCE\r
+-bufg 16\r
+-register_duplication YES\r
+-signal_encoding user\r
+-iob true\r
+-slice_utilization_ratio_maxmargin 5\r
+-uc ../example_design/gtxVirtex6FEE80_top.xcf\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : demo_tb.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module DEMO_TB\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+library std; -- for Printing\r
+use std.textio.all;\r
+\r
+entity DEMO_TB is\r
+end DEMO_TB;\r
+\r
+architecture RTL of DEMO_TB is\r
+\r
+--*************************Parameter Declarations******************************\r
+\r
+ constant TX_REFCLK_PERIOD : time := 12.5 ns;\r
+ constant RX_REFCLK_PERIOD : time := 12.5 ns; \r
+ \r
+--**************************** Component Declarations *************************\r
+\r
+ component gtxVirtex6FEE80_top \r
+ generic\r
+ (\r
+ EXAMPLE_CONFIG_INDEPENDENT_LANES: integer := 1;\r
+ EXAMPLE_LANE_WITH_START_CHAR : integer := 0;\r
+ EXAMPLE_WORDS_IN_BRAM : integer := 512;\r
+ EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1;\r
+ EXAMPLE_USE_CHIPSCOPE : integer := 0 --0 - drive resets from top level ports\r
+ );\r
+ port\r
+ (\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
+ GTXTXRESET_IN : in std_logic;\r
+ GTXRXRESET_IN : in std_logic;\r
+ TRACK_DATA_OUT : out std_logic;\r
+ RXN_IN : in std_logic;\r
+ RXP_IN : in std_logic;\r
+ TXN_OUT : out std_logic;\r
+ TXP_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component SIM_RESET_MGT_MODEL \r
+ port \r
+ (\r
+ GSR_IN : in std_logic\r
+ );\r
+ end component;\r
+\r
+--************************Internal Register Declarations***********************\r
+\r
+--************************** Register Declarations **************************** \r
+\r
+ signal tx_refclk_n_r : std_logic;\r
+ signal rx_refclk_n_r : std_logic;\r
+ signal drp_clk_r : std_logic;\r
+ signal tx_usrclk_r : std_logic;\r
+ signal rx_usrclk_r : std_logic;\r
+ signal gsr_r : std_logic;\r
+ signal gts_r : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal track_data_high_r : std_logic;\r
+ signal track_data_low_r : std_logic; \r
+\r
+--********************************Wire Declarations**********************************\r
+ \r
+ ----------------------------------- Global Signals ------------------------------\r
+ signal tx_refclk_p_r : std_logic;\r
+ signal rx_refclk_p_r : std_logic; \r
+ signal tied_to_ground_i : std_logic;\r
+ ---------------------------- Example Module Connections -------------------------\r
+ signal rxn_in_i : std_logic;\r
+ signal rxp_in_i : std_logic;\r
+ signal txn_out_i : std_logic;\r
+ signal txp_out_i : std_logic;\r
+\r
+\r
+ signal gtx0_txplllkdet_i : std_logic;\r
+ signal gtx0_rxplllkdet_i : std_logic; \r
+\r
+ signal track_data_i : std_logic;\r
+\r
+\r
+--*********************************Main Body of Code**********************************\r
+begin\r
+\r
+ -- ------------------------------- Tie offs ------------------------------- \r
+ \r
+ tied_to_ground_i <= '0';\r
+ \r
+ -- ------------------------- MGT Serial Connections -----------------------\r
+\r
+ rxn_in_i <= txn_out_i;\r
+ rxp_in_i <= txp_out_i; \r
+\r
+ ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------\r
+ ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------\r
+ ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------\r
+\r
+ sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL \r
+ port map \r
+ (\r
+ GSR_IN => reset_i\r
+ );\r
+\r
+ ---------------------- Generate Reference Clock input --------------------\r
+ \r
+ process\r
+ begin\r
+ tx_refclk_n_r <= '1';\r
+ wait for TX_REFCLK_PERIOD/2;\r
+ tx_refclk_n_r <= '0';\r
+ wait for TX_REFCLK_PERIOD/2;\r
+ end process;\r
+\r
+ tx_refclk_p_r <= not tx_refclk_n_r;\r
+ \r
+ process\r
+ begin\r
+ rx_refclk_n_r <= '1';\r
+ wait for RX_REFCLK_PERIOD/2;\r
+ rx_refclk_n_r <= '0';\r
+ wait for RX_REFCLK_PERIOD/2;\r
+ end process;\r
+\r
+ rx_refclk_p_r <= not rx_refclk_n_r;\r
+ \r
+\r
+ \r
+ \r
+ ----------------------------------- Resets ---------------------------------\r
+ \r
+ process\r
+ begin\r
+ reset_i <= '1';\r
+ wait for 100 ns;\r
+ reset_i <= '0';\r
+ wait; \r
+ end process;\r
+\r
+ -------------------------------- Track Data --------------------------------\r
+ \r
+ process\r
+\r
+ procedure tbprint (message : in string) is\r
+ variable outline : line;\r
+ begin\r
+ write(outline, string'("## Time: "));\r
+ write(outline, NOW, RIGHT, 0, ps);\r
+ write(outline, string'(" "));\r
+ write(outline, string'(message)); \r
+ writeline(output,outline);\r
+ end tbprint;\r
+\r
+\r
+ begin\r
+ track_data_high_r <= '0';\r
+ wait for 223 us;\r
+ if (track_data_i = '1') then\r
+ track_data_high_r <= '1';\r
+ end if;\r
+ wait for 2 us;\r
+ if ((track_data_high_r = '1') and (track_data_low_r = '0')) then\r
+ tbprint("------- TEST PASSED -------");\r
+ assert false report "Simulation Stopped." severity failure;\r
+ else\r
+ tbprint("####### ERROR: TEST FAILED ! #######");\r
+ assert false report "Test Failed." severity failure;\r
+ end if;\r
+ end process;\r
+ \r
+ process\r
+ begin\r
+ track_data_low_r <= '0';\r
+ wait for 223 us;\r
+ wait until track_data_i = '0';\r
+ track_data_low_r <= '1';\r
+ end process; \r
+ ------------------- Instantiate an gtxVirtex6FEE80_top module -----------------\r
+\r
+ gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top\r
+ generic map\r
+ (\r
+ EXAMPLE_SIM_GTXRESET_SPEEDUP=> 1, -- Speedup is turned on for simulation\r
+ EXAMPLE_USE_CHIPSCOPE => 0 --1 - use chipscope to drive resets,\r
+ --0 - drive resets from top level ports\r
+ )\r
+ port map\r
+ (\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN => rx_refclk_n_r,\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN => rx_refclk_p_r,\r
+ GTXTXRESET_IN => reset_i,\r
+ GTXRXRESET_IN => reset_i,\r
+ TRACK_DATA_OUT => track_data_i,\r
+ RXN_IN => rxn_in_i,\r
+ RXP_IN => rxp_in_i,\r
+ TXN_OUT => txn_out_i,\r
+ TXP_OUT => txp_out_i\r
+ );\r
+\r
+end RTL;\r
+\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : demo_tb.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module DEMO_TB_IMP\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard \r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+library std; -- for Printing\r
+use std.textio.all;\r
+\r
+entity DEMO_TB_IMP is\r
+end DEMO_TB_IMP;\r
+\r
+architecture RTL of DEMO_TB_IMP is\r
+\r
+--*************************Parameter Declarations******************************\r
+\r
+ constant TX_REFCLK_PERIOD : time := 12.5 ns;\r
+ constant RX_REFCLK_PERIOD : time := 12.5 ns; \r
+ \r
+--**************************** Component Declarations *************************\r
+\r
+ component gtxVirtex6FEE80_top \r
+ port\r
+ (\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
+ GTXTXRESET_IN : in std_logic;\r
+ GTXRXRESET_IN : in std_logic;\r
+ TRACK_DATA_OUT : out std_logic;\r
+ RXN_IN : in std_logic;\r
+ RXP_IN : in std_logic;\r
+ TXN_OUT : out std_logic;\r
+ TXP_OUT : out std_logic\r
+ );\r
+ end component;\r
+\r
+ component SIM_RESET_MGT_MODEL \r
+ port \r
+ (\r
+ GSR_IN : in std_logic\r
+ );\r
+ end component;\r
+\r
+--************************Internal Register Declarations***********************\r
+\r
+--************************** Register Declarations **************************** \r
+\r
+ signal tx_refclk_n_r : std_logic;\r
+ signal rx_refclk_n_r : std_logic;\r
+ signal drp_clk_r : std_logic;\r
+ signal tx_usrclk_r : std_logic;\r
+ signal rx_usrclk_r : std_logic;\r
+ signal gsr_r : std_logic;\r
+ signal gts_r : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal track_data_high_r : std_logic;\r
+ signal track_data_low_r : std_logic; \r
+\r
+--********************************Wire Declarations**********************************\r
+ \r
+ ----------------------------------- Global Signals ------------------------------\r
+ signal tx_refclk_p_r : std_logic;\r
+ signal rx_refclk_p_r : std_logic; \r
+ signal tied_to_ground_i : std_logic;\r
+ ---------------------------- Example Module Connections -------------------------\r
+ signal rxn_in_i : std_logic;\r
+ signal rxp_in_i : std_logic;\r
+ signal txn_out_i : std_logic;\r
+ signal txp_out_i : std_logic;\r
+\r
+\r
+ signal gtx0_txplllkdet_i : std_logic;\r
+ signal gtx0_rxplllkdet_i : std_logic; \r
+\r
+ signal track_data_i : std_logic;\r
+\r
+\r
+--*********************************Main Body of Code**********************************\r
+begin\r
+\r
+ -- ------------------------------- Tie offs ------------------------------- \r
+ \r
+ tied_to_ground_i <= '0';\r
+ \r
+ -- ------------------------- MGT Serial Connections -----------------------\r
+\r
+ rxn_in_i <= txn_out_i;\r
+ rxp_in_i <= txp_out_i; \r
+\r
+ ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------\r
+ ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------\r
+ ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------\r
+\r
+ sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL \r
+ port map \r
+ (\r
+ GSR_IN => reset_i\r
+ );\r
+\r
+ ---------------------- Generate Reference Clock input --------------------\r
+ \r
+ process\r
+ begin\r
+ tx_refclk_n_r <= '1';\r
+ wait for TX_REFCLK_PERIOD/2;\r
+ tx_refclk_n_r <= '0';\r
+ wait for TX_REFCLK_PERIOD/2;\r
+ end process;\r
+\r
+ tx_refclk_p_r <= not tx_refclk_n_r;\r
+ \r
+ process\r
+ begin\r
+ rx_refclk_n_r <= '1';\r
+ wait for RX_REFCLK_PERIOD/2;\r
+ rx_refclk_n_r <= '0';\r
+ wait for RX_REFCLK_PERIOD/2;\r
+ end process;\r
+\r
+ rx_refclk_p_r <= not rx_refclk_n_r;\r
+ \r
+\r
+ \r
+ \r
+ ----------------------------------- Resets ---------------------------------\r
+ \r
+ process\r
+ begin\r
+ reset_i <= '1';\r
+ wait for 100 ns;\r
+ reset_i <= '0';\r
+ wait; \r
+ end process;\r
+\r
+ -------------------------------- Track Data --------------------------------\r
+ \r
+ process\r
+\r
+ procedure tbprint (message : in string) is\r
+ variable outline : line;\r
+ begin\r
+ write(outline, string'("## Time: "));\r
+ write(outline, NOW, RIGHT, 0, ps);\r
+ write(outline, string'(" "));\r
+ write(outline, string'(message)); \r
+ writeline(output,outline);\r
+ end tbprint;\r
+\r
+ begin\r
+ track_data_high_r <= '0';\r
+ wait for 223 us;\r
+ if (track_data_i = '1') then\r
+ track_data_high_r <= '1';\r
+ end if;\r
+ wait for 2 us;\r
+ if ((track_data_high_r = '1') and (track_data_low_r = '0')) then\r
+ tbprint("------- TEST PASSED -------");\r
+ assert false report "Simulation Stopped." severity failure;\r
+ else\r
+ tbprint("####### ERROR: TEST FAILED ! #######");\r
+ assert false report "Test Failed." severity failure;\r
+ end if;\r
+ end process;\r
+ \r
+ process\r
+ begin\r
+ track_data_low_r <= '0';\r
+ wait for 223 us;\r
+ wait until track_data_i = '0';\r
+ track_data_low_r <= '1';\r
+ end process; \r
+ ------------------- Instantiate an gtxVirtex6FEE80_top module -----------------\r
+\r
+ gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top\r
+ port map\r
+ (\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN => rx_refclk_n_r,\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN => rx_refclk_p_r,\r
+ GTXTXRESET_IN => reset_i,\r
+ GTXRXRESET_IN => reset_i,\r
+ TRACK_DATA_OUT => track_data_i,\r
+ RXN_IN => rxn_in_i,\r
+ RXP_IN => rxp_in_i,\r
+ TXN_OUT => txn_out_i,\r
+ TXP_OUT => txp_out_i\r
+ );\r
+\r
+end RTL;\r
+\r
--- /dev/null
+REM ____ ____ \r
+REM / /\/ / \r
+REM /___/ \ / Vendor: Xilinx \r
+REM \ \ \/ Version : 1.12\r
+REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+REM / / Filename : simulate_isim.bat\r
+REM /___/ /\ \r
+REM \ \ / \ \r
+REM \___\/\___\ \r
+REM\r
+REM\r
+REM Script SIMULATE_ISIM.BAT\r
+REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+REM\r
+REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+REM\r
+REM This file contains confidential and proprietary information\r
+REM of Xilinx, Inc. and is protected under U.S. and\r
+REM international copyright and other intellectual property\r
+REM laws.\r
+REM\r
+REM DISCLAIMER\r
+REM This disclaimer is not a license and does not grant any\r
+REM rights to the materials distributed herewith. Except as\r
+REM otherwise provided in a valid license issued to you by\r
+REM Xilinx, and to the maximum extent permitted by applicable\r
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+REM (2) Xilinx shall not be liable (whether in contract or tort,\r
+REM including negligence, or under any other theory of\r
+REM liability) for any loss or damage of any kind or nature\r
+REM related to, arising under or in connection with these\r
+REM materials, including for any direct, or any indirect,\r
+REM special, incidental, or consequential loss or damage\r
+REM (including loss of data, profits, goodwill, or any type of\r
+REM loss or damage suffered as a result of any action brought\r
+REM by a third party) even if such damage or loss was\r
+REM reasonably foreseeable or Xilinx had been advised of the\r
+REM possibility of the same.\r
+REM\r
+REM CRITICAL APPLICATIONS\r
+REM Xilinx products are not designed or intended to be fail-\r
+REM safe, or for use in any application requiring fail-safe\r
+REM performance, such as life-support or safety devices or\r
+REM systems, Class III medical devices, nuclear facilities,\r
+REM applications related to the deployment of airbags, or any\r
+REM other applications that could lead to death, personal\r
+REM injury, or severe property or environmental damage\r
+REM (individually and collectively, "Critical\r
+REM Applications"). Customer assumes the sole risk and\r
+REM liability of any use of Xilinx products in Critical\r
+REM Applications, subject only to applicable laws and\r
+REM regulations governing limitations on product liability.\r
+REM \r
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+REM PART OF THIS FILE AT ALL TIMES.\r
+\r
+\r
+REM ***************************** Beginning of Script ***************************\r
+ \r
+REM Create and map work directory\r
+mkdir work\r
+\r
+REM MGT Wrapper\r
+vhpcomp -work work ..\..\..\gtxvirtex6fee80_gtx.vhd\r
+vhpcomp -work work ..\..\..\gtxvirtex6fee80.vhd\r
+\r
+\r
+REM Clock Modules \r
+vhpcomp -work work ..\..\example_design\mgt_usrclk_source_mmcm.vhd\r
+\r
+REM Example Design modules\r
+vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd\r
+vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd\r
+vhpcomp -work work ..\..\example_design\double_reset.vhd\r
+vhpcomp -work work ..\..\example_design\frame_gen.vhd\r
+vhpcomp -work work ..\..\example_design\frame_check.vhd\r
+vhpcomp -work work ..\..\example_design\gtxvirtex6fee80_top.vhd\r
+\r
+vhpcomp -work work ..\demo_tb.vhd\r
+\r
+REM Other modules\r
+vhpcomp -work work ..\sim_reset_mgt_model.vhd\r
+\r
+REM Load Design\r
+fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe\r
+\r
+.\demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim \r
+\r
--- /dev/null
+#!/bin/sh\r
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : simulate_isim.sh\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script SIMULATE_ISIM.SH\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+\r
+##***************************** Beginning of Script ***************************\r
+ \r
+## Create and map work directory\r
+mkdir work\r
+\r
+##MGT Wrapper\r
+vhpcomp -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
+vhpcomp -work work ../../../gtxvirtex6fee80.vhd;\r
+\r
+\r
+##Clock Modules \r
+vhpcomp -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
+\r
+##Example Design modules\r
+vhpcomp -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
+vhpcomp -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
+vhpcomp -work work ../../example_design/double_reset.vhd;\r
+vhpcomp -work work ../../example_design/frame_gen.vhd;\r
+vhpcomp -work work ../../example_design/frame_check.vhd;\r
+vhpcomp -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
+\r
+vhpcomp -work work ../demo_tb.vhd;\r
+\r
+##Other modules\r
+vhpcomp -work work ../sim_reset_mgt_model.vhd;\r
+\r
+##Load Design\r
+fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe\r
+\r
+./demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim \r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : simulate_mti.do\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script SIMULATE_MTI.DO\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+##***************************** Beginning of Script ***************************\r
+ \r
+## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS\r
+## This mode of mapping the unisims libraries is provided for backward \r
+## compatibility with previous wizard releases. If you don't set MTI_LIBS\r
+## the unisim libraries will be loaded from the paths set up by compxlib in\r
+## your modelsim.ini file\r
+\r
+set XILINX $env(XILINX)\r
+if [info exists env(MTI_LIBS)] { \r
+ set MTI_LIBS $env(MTI_LIBS)\r
+ vlib UNISIM\r
+ vlib SECUREIP\r
+ vmap UNISIM $MTI_LIBS/unisim\r
+ vmap SECUREIP $MTI_LIBS/secureip\r
+ \r
+}\r
+ \r
+\r
+## Create and map work directory\r
+vlib work\r
+vmap work work\r
+\r
+##MGT Wrapper\r
+vcom -93 -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
+vcom -93 -work work ../../../gtxvirtex6fee80.vhd;\r
+\r
+\r
+##Clock Modules \r
+vcom -93 -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
+\r
+\r
+##Example Design modules\r
+vcom -93 -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
+vcom -93 -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
+vcom -93 -work work ../../example_design/double_reset.vhd;\r
+vcom -93 -work work ../../example_design/frame_gen.vhd;\r
+vcom -93 -work work ../../example_design/frame_check.vhd;\r
+vcom -93 -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
+\r
+vcom -93 -work work ../demo_tb.vhd;\r
+\r
+##Other modules\r
+vcom -93 -work work ../sim_reset_mgt_model.vhd;\r
+\r
+##Load Design\r
+vsim -t 1ps work.DEMO_TB -voptargs="+acc" \r
+\r
+\r
+##Load signals in wave window\r
+view wave\r
+do wave_mti.do\r
+\r
+##Run simulation\r
+run 226 us\r
+\r
+\r
+\r
--- /dev/null
+REM ############################################################################\r
+REM ____ ____ \r
+REM / /\/ / \r
+REM /___/ \ / Vendor: Xilinx \r
+REM \ \ \/ Version : 1.12\r
+REM \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+REM / / Filename : simulate_ncsim.bat\r
+REM /___/ /\ \r
+REM \ \ / \ \r
+REM \___\/\___\ \r
+REM\r
+REM\r
+REM Script SIMULATE_NCSIM.BAT\r
+REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+REM\r
+REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+REM \r
+REM This file contains confidential and proprietary information\r
+REM of Xilinx, Inc. and is protected under U.S. and \r
+REM international copyright and other intellectual property\r
+REM laws.\r
+REM \r
+REM DISCLAIMER\r
+REM This disclaimer is not a license and does not grant any\r
+REM rights to the materials distributed herewith. Except as\r
+REM otherwise provided in a valid license issued to you by\r
+REM Xilinx, and to the maximum extent permitted by applicable\r
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+REM (2) Xilinx shall not be liable (whether in contract or tort,\r
+REM including negligence, or under any other theory of\r
+REM liability) for any loss or damage of any kind or nature\r
+REM related to, arising under or in connection with these\r
+REM materials, including for any direct, or any indirect,\r
+REM special, incidental, or consequential loss or damage\r
+REM (including loss of data, profits, goodwill, or any type of\r
+REM loss or damage suffered as a result of any action brought\r
+REM by a third party) even if such damage or loss was\r
+REM reasonably foreseeable or Xilinx had been advised of the\r
+REM possibility of the same.\r
+REM\r
+REM CRITICAL APPLICATIONS\r
+REM Xilinx products are not designed or intended to be fail-\r
+REM safe, or for use in any application requiring fail-safe\r
+REM performance, such as life-support or safety devices or\r
+REM systems, Class III medical devices, nuclear facilities,\r
+REM applications related to the deployment of airbags, or any\r
+REM other applications that could lead to death, personal\r
+REM injury, or severe property or environmental damage\r
+REM (individually and collectively, "Critical\r
+REM Applications"). Customer assumes the sole risk and\r
+REM liability of any use of Xilinx products in Critical\r
+REM Applications, subject only to applicable laws and\r
+REM regulations governing limitations on product liability.\r
+REM\r
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+REM PART OF THIS FILE AT ALL TIMES.\r
+\r
+REM **************************** Beginning of Script ***************************\r
+\r
+ \r
+REM Ensure the follwoing\r
+REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,\r
+REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.\r
+REM Variables LMC_HOME and XILINX are set \r
+REM Define the mapping for the work library in cds.lib file. DEFINE work ./work\r
+\r
+mkdir work\r
+REM MGT Wrapper\r
+ncvhdl -RELAX -V93 -work work ..\..\..\gtxvirtex6fee80_gtx.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\..\gtxvirtex6fee80.vhd\r
+\r
+\r
+ \r
+REM Clock Modules \r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\mgt_usrclk_source_mmcm.vhd\r
+\r
+REM Example Design modules\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\double_reset.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\frame_gen.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\frame_check.vhd\r
+ncvhdl -RELAX -V93 -work work ..\..\example_design\gtxvirtex6fee80_top.vhd\r
+\r
+ncvhdl -RELAX -V93 -work work ..\demo_tb.vhd\r
+\r
+REM Other modules\r
+ncvhdl -RELAX -V93 -work work ..\sim_reset_mgt_model.vhd\r
+\r
+REM Elaborate Design\r
+ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB\r
+\r
+ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" \r
+\r
--- /dev/null
+#!/bin/sh\r
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : simulate_ncsim.sh\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script SIMULATE_NCSIM.SH\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+##***************************** Beginning of Script ***************************\r
+ \r
+#Ensure the follwoing\r
+#The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,\r
+#UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.\r
+#Variables LMC_HOME and XILINX are set \r
+#Define the mapping for the work library in cds.lib file. DEFINE work ./work\r
+\r
+mkdir work\r
+##MGT Wrapper\r
+ncvhdl -RELAX -V93 -work work ../../../gtxvirtex6fee80_gtx.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../../gtxvirtex6fee80.vhd;\r
+\r
+\r
+ \r
+##Clock Modules \r
+ncvhdl -RELAX -V93 -work work ../../example_design/mgt_usrclk_source_mmcm.vhd;\r
+\r
+##Example Design modules\r
+ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_tx_sync.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_rx_sync.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../example_design/double_reset.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../example_design/frame_gen.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../example_design/frame_check.vhd;\r
+ncvhdl -RELAX -V93 -work work ../../example_design/gtxvirtex6fee80_top.vhd;\r
+\r
+ncvhdl -RELAX -V93 -work work ../demo_tb.vhd;\r
+\r
+##Other modules\r
+ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;\r
+\r
+##Elaborate Design\r
+ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB\r
+\r
+ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" \r
+\r
--- /dev/null
+#!/bin/sh\r
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : simulate_vcs.sh\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script SIMULATE_VCS.SH\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## \r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+## \r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+## \r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+##***************************** Beginning of Script ***************************\r
+\r
+\r
+rm -rf simv* csrc DVEfiles AN.DB\r
+\r
+vhdlan \\r
+ ../../../gtxvirtex6fee80_gtx.vhd \\r
+ ../../../gtxvirtex6fee80.vhd \\r
+ ../../example_design/mgt_usrclk_source_mmcm.vhd \\r
+ ../../example_design/gtxvirtex6fee80_tx_sync.vhd \\r
+ ../../example_design/gtxvirtex6fee80_rx_sync.vhd \\r
+ ../../example_design/double_reset.vhd \\r
+ ../../example_design/frame_gen.vhd \\r
+ ../../example_design/frame_check.vhd \\r
+ ../../example_design/gtxvirtex6fee80_top.vhd \\r
+ ../demo_tb.vhd\r
+\r
+vcs +vcs+lic+wait \\r
+ -debug \\r
+ DEMO_TB\r
+./simv -ucli -i ucli_commands.key\r
+dve -vpd vcdplus.vpd -session vcs_session.tcl\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : ucli_commands.key\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script UCLI_COMMANDS.KEY\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+## \r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+## \r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+## \r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+call {$vcdpluson}\r
+run\r
+call {$vcdplusclose}\r
+quit\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : vcs_session.tcl\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+##\r
+## Script VCS_SESSION.TCL\r
+## Generated by Xilinx Virtex-6 FPGA GTH Transceiver Wizard\r
+##\r
+## \r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+## \r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+## \r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+ gui_open_window Wave\r
+ gui_sg_create gtxVirtex6FEE80_Group\r
+ gui_list_add_group -id Wave.1 {gtxVirtex6FEE80_Group}\r
+\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{FRAME_CHECK_MODULE}} -divider\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT}\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{GTX0_GTXVIRTEX6FEE80}} -divider\r
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - 8b10b Decoder}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - Comma Detection and Alignment}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Data Path interface}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Elastic Buffer and Phase Alignment Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Loss-of-sync State Machine}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX PLL Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Pipe Control for PCI Express}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - 8b10b Encoder Control Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - GTX Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Data Path interface}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Driver and OOB signaling}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Elastic Buffer and Phase Alignment Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX PLL Ports}} -divider
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN}
+ gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT}
+\r
+\r
+ gui_zoom -window Wave.1 -full\r
+\r
--- /dev/null
+###############################################################################\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+\r
+\r
+wcfg new\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA\r
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT\r
+divider add "Receive Ports - 8b10b Decoder"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
+divider add "Receive Ports - Comma Detection and Alignment"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
+divider add "Receive Ports - RX Data Path interface"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
+divider add "Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
+divider add "Receive Ports - RX Elastic Buffer and Phase Alignment Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
+divider add "Receive Ports - RX Loss-of-sync State Machine"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
+divider add "Receive Ports - RX PLL Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
+divider add "Receive Ports - RX Pipe Control for PCI Express"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
+divider add "Transmit Ports - 8b10b Encoder Control Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
+divider add "Transmit Ports - GTX Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
+divider add "Transmit Ports - TX Data Path interface"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
+divider add "Transmit Ports - TX Driver and OOB signaling"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
+divider add "Transmit Ports - TX Elastic Buffer and Phase Alignment Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
+divider add "Transmit Ports - TX PLL Ports"
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
+wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
+\r
+run 226 us\r
+quit\r
+\r
+\r
+\r
--- /dev/null
+###############################################################################\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+onerror {resume}\r
+quietly WaveActivateNextPane {} 0\r
+add wave -noupdate -divider {FRAME CHECK MODULE gtx0_frame_check }\r
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r\r
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r\r
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r\r
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r\r
+add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA\r
+add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT\r
+add wave -noupdate -divider {GTX0_GTXVIRTEX6FEE80 }\r
+add wave -noupdate -divider {Receive Ports - 8b10b Decoder }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
+add wave -noupdate -divider {Receive Ports - Comma Detection and Alignment }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
+add wave -noupdate -divider {Receive Ports - RX Data Path interface }
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
+add wave -noupdate -divider {Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
+add wave -noupdate -divider {Receive Ports - RX Elastic Buffer and Phase Alignment Ports }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
+add wave -noupdate -divider {Receive Ports - RX Loss-of-sync State Machine }
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
+add wave -noupdate -divider {Receive Ports - RX PLL Ports }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
+add wave -noupdate -divider {Receive Ports - RX Pipe Control for PCI Express }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
+add wave -noupdate -divider {Transmit Ports - 8b10b Encoder Control Ports }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
+add wave -noupdate -divider {Transmit Ports - GTX Ports }
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
+add wave -noupdate -divider {Transmit Ports - TX Data Path interface }
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
+add wave -noupdate -divider {Transmit Ports - TX Driver and OOB signaling }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
+add wave -noupdate -divider {Transmit Ports - TX Elastic Buffer and Phase Alignment Ports }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
+add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
+add wave -noupdate -divider {Transmit Ports - TX PLL Ports }
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
+add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
+\r
+TreeUpdate [SetDefaultTree]\r
+WaveRestoreCursors {{Cursor 1} {0 ps} 0}\r
+configure wave -namecolwidth 282\r
+configure wave -valuecolwidth 100\r
+configure wave -justifyvalue left\r
+configure wave -signalnamewidth 1\r
+configure wave -snapdistance 10\r
+configure wave -datasetprefix 0\r
+configure wave -rowmargin 4\r
+configure wave -childrowmargin 2\r
+configure wave -gridoffset 0\r
+configure wave -gridperiod 1\r
+configure wave -griddelta 40\r
+configure wave -timeline 0\r
+update\r
+WaveRestoreZoom {0 ps} {5236 ps}\r
--- /dev/null
+\r
+###############################################################################\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+ window new WaveWindow -name "Waves for Virtex-6 GTX Wizard Example Design"\r
+ waveform using "Waves for Virtex-6 GTX Wizard Example Design"\r
+ \r
+ waveform add -label FRAME_CHECK_MODULE -comment gtx0_frame_check\r
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r\r
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r\r
+ waveform add -siganls :gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r\r
+ wavefrom add -siganls :gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r\r
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA\r
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT\r
+ waveform add -label GTX0_GTXVIRTEX6FEE80 -comment GTX0_GTXVIRTEX6FEE80\r
+ waveform add -label Receive_Ports_-_8b10b_Decoder -comment Receive_Ports_-_8b10b_Decoder
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT
+ waveform add -label Receive_Ports_-_Comma_Detection_and_Alignment -comment Receive_Ports_-_Comma_Detection_and_Alignment
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN
+ waveform add -label Receive_Ports_-_RX_Data_Path_interface -comment Receive_Ports_-_RX_Data_Path_interface
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN
+ waveform add -label Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR -comment Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN
+ waveform add -label Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports -comment Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT
+ waveform add -label Receive_Ports_-_RX_Loss-of-sync_State_Machine -comment Receive_Ports_-_RX_Loss-of-sync_State_Machine
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT
+ waveform add -label Receive_Ports_-_RX_PLL_Ports -comment Receive_Ports_-_RX_PLL_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT
+ waveform add -label Receive_Ports_-_RX_Pipe_Control_for_PCI_Express -comment Receive_Ports_-_RX_Pipe_Control_for_PCI_Express
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT
+ waveform add -label Transmit_Ports_-_8b10b_Encoder_Control_Ports -comment Transmit_Ports_-_8b10b_Encoder_Control_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN
+ waveform add -label Transmit_Ports_-_GTX_Ports -comment Transmit_Ports_-_GTX_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN
+ waveform add -label Transmit_Ports_-_TX_Data_Path_interface -comment Transmit_Ports_-_TX_Data_Path_interface
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN
+ waveform add -label Transmit_Ports_-_TX_Driver_and_OOB_signaling -comment Transmit_Ports_-_TX_Driver_and_OOB_signaling
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT
+ waveform add -label Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports -comment Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN
+ waveform add -label Transmit_Ports_-_TX_PLL_Ports -comment Transmit_Ports_-_TX_PLL_Ports
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN
+ waveform add -signals :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT
+\r
+ console submit -using simulator -wait no "run 226 us"\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____ \r
+## / /\/ / \r
+## /___/ \ / Vendor: Xilinx \r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : simulate_mti.do\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\ \r
+##\r
+##\r
+## Script SIMULATE_MTI.DO\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+##***************************** Beginning of Script ***************************\r
+ \r
+## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS\r
+## This mode of mapping the unisims libraries is provided for backward \r
+## compatibility with previous wizard releases. If you don't set MTI_LIBS\r
+## the unisim libraries will be loaded from the paths set up by compxlib in\r
+## your modelsim.ini file\r
+\r
+set XILINX $env(XILINX)\r
+if [info exists env(MTI_LIBS)] { \r
+ set MTI_LIBS $env(MTI_LIBS)\r
+ vlib SECUREIP\r
+ vlib SIMPRIM\r
+ vmap SIMPRIM $MTI_LIBS/simprim\r
+ vmap SECUREIP $MTI_LIBS/secureip\r
+ \r
+}\r
+ \r
+\r
+## Create and map work directory\r
+vlib work\r
+vmap work work\r
+\r
+vcom -93 -work work ../../implement/results/routed.vhd;\r
+\r
+vcom -93 -work work ../sim_reset_mgt_model.vhd;\r
+vcom -93 -work work ../demo_tb_imp.vhd;\r
+\r
+##Load Design\r
+vsim -t 1ps -L SECUREIP -L SIMPRIM -voptargs="+acc" -sdfmax DEMO_TB_IMP/gtxVirtex6FEE80_top_i=../../implement/results/routed.sdf +notimingchecks work.DEMO_TB_IMP\r
+\r
+##Run simulation\r
+run 226 us\r
+\r
+\r
+\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : sim_reset_mgt_model.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module SIM_RESET_MGT_MODEL\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--\r
+-- The Reset On Configuration(ROC) module is part of the UNISIM library\r
+-- and is required for emulating the GSR pulse at the beginning of functional\r
+-- simulation in order to correctly reset the VHDL MGT smart model.This module\r
+-- is required for simulation only.\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***************************** Entity Declaration *****************************\r
+\r
+entity SIM_RESET_MGT_MODEL is\r
+port \r
+(\r
+ GSR_IN : in std_logic\r
+);\r
+end SIM_RESET_MGT_MODEL;\r
+\r
+architecture BEHAVIORAL of SIM_RESET_MGT_MODEL is\r
+ \r
+ \r
+--********************************* Main Body of Code****************************\r
+ \r
+begin \r
+ GSR <= GSR_IN; \r
+ ------------------------------ ROCBUF Instantiation ----------------------- \r
+ -- This component is required for correctly resetting the VHDL GTX component on configuration\r
+ -- It is for simulation alone and will be ripped out during synthesis.\r
+ U1 : ROCBUF \r
+ port map \r
+ (\r
+ I => GSR,\r
+ O => open\r
+ ); \r
+\r
+\r
+end BEHAVIORAL;\r
+\r
--- /dev/null
+ Core name: Xilinx LogiCORE Virtex-6 GTX Transceiver Wizard
+ Version: 1.12
+ Release: 13.4
+ Release Date: January 18, 2012
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX
+Transceiver Wizard v1.12 solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/V6_GTX_Wizard.htm
+
+
+2. NEW FEATURES
+
+- ISE 13.4 software support
+- Auto Upgrade Support has been added. Older versions of the core- 1.4, 1.5, 16, 1.7,
+ 1.8,1.9,1.10,1.11 can be upgraded to 1.12
+
+
+3. SUPPORTED DEVICES
+
+The following device families are supported by the core for this release.
+
+Virtex-6 XC CXT/LXT/SXT/HXT
+Virtex-6 XQ LXT/SXT
+Virtex-6 -1L XC LXT/SXT
+Virtex-6 -1L XQ LXT/SXT
+
+
+4. RESOLVED ISSUES
+
+Format for each entry:
+
+ 1. Updates to SRIO gen2 settings
+
+ Description: Attribute values for SRIO gen2 are updated based on the hw testing results
+
+ Version(s) Fixed:
+ CR 631978
+
+
+5. KNOWN ISSUES
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes Guide
+located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+7. CORE RELEASE HISTORY
+Date By Version Description
+================================================================================
+01/18/2012 Xilinx, Inc 1.12 ISE 13.4 support
+10/19/2011 Xilinx, Inc 1.11 ISE 13.3 support
+06/22/2011 Xilinx, Inc 1.10 ISE 13.2 support
+03/01/2011 Xilinx, Inc 1.9 ISE 13.1 support
+12/14/2010 Xilinx, Inc. 1.8 ISE 12.4 support
+09/21/2010 Xilinx, Inc. 1.7 ISE 12.3 support
+07/23/2010 Xilinx, Inc. 1.6 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 1.5 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 1.4 ISE 11.4 support
+09/16/2009 Xilinx, Inc. 1.3 ISE 11.3 support
+06/24/2009 Xilinx, Inc. 1.2 ISE 11.2 support
+04/24/2009 Xilinx, Inc. 1.1 ISE 11.1 support
+================================================================================
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtxVirtex6FEE80_top.ucf\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## Device: xc6vlx130t\r
+## Package: ff484\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+################################## Clock Constraints ##########################\r
+\r
+NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";\r
+TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;\r
+\r
+\r
+\r
+# User Clock Constraints\r
+NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
+TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
+
+NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
+TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
+
+\r
+\r
+#################### locs for top level ports (ML623 Board) ###################\r
+\r
+\r
+\r
+####################### GTX reference clock constraints #######################\r
+NET Q3_CLK0_MGTREFCLK_PAD_N_IN LOC=L3;\r
+NET Q3_CLK0_MGTREFCLK_PAD_P_IN LOC=L4;\r
+\r
+\r
+################################# mgt wrapper constraints #####################\r
+\r
+##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------\r
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;\r
+\r
+\r
+\r
--- /dev/null
+################################################################################\r
+## ____ ____\r
+## / /\/ /\r
+## /___/ \ / Vendor: Xilinx\r
+## \ \ \/ Version : 1.12\r
+## \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+## / / Filename : gtx_attributes.ucf\r
+## /___/ /\ \r
+## \ \ / \ \r
+## \___\/\___\\r
+##\r
+##\r
+## GTX ATTRIBUTES \r
+## This file contains the attributes for the active GTX transceivers in the\r
+## design. If you would like to use this file in your design, please make\r
+## sure that the path to the GTX instance is correct.\r
+## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+##\r
+## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.\r
+##\r
+## This file contains confidential and proprietary information\r
+## of Xilinx, Inc. and is protected under U.S. and\r
+## international copyright and other intellectual property\r
+## laws.\r
+##\r
+## DISCLAIMER\r
+## This disclaimer is not a license and does not grant any\r
+## rights to the materials distributed herewith. Except as\r
+## otherwise provided in a valid license issued to you by\r
+## Xilinx, and to the maximum extent permitted by applicable\r
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND\r
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES\r
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING\r
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-\r
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and\r
+## (2) Xilinx shall not be liable (whether in contract or tort,\r
+## including negligence, or under any other theory of\r
+## liability) for any loss or damage of any kind or nature\r
+## related to, arising under or in connection with these\r
+## materials, including for any direct, or any indirect,\r
+## special, incidental, or consequential loss or damage\r
+## (including loss of data, profits, goodwill, or any type of\r
+## loss or damage suffered as a result of any action brought\r
+## by a third party) even if such damage or loss was\r
+## reasonably foreseeable or Xilinx had been advised of the\r
+## possibility of the same.\r
+##\r
+## CRITICAL APPLICATIONS\r
+## Xilinx products are not designed or intended to be fail-\r
+## safe, or for use in any application requiring fail-safe\r
+## performance, such as life-support or safety devices or\r
+## systems, Class III medical devices, nuclear facilities,\r
+## applications related to the deployment of airbags, or any\r
+## other applications that could lead to death, personal\r
+## injury, or severe property or environmental damage\r
+## (individually and collectively, "Critical\r
+## Applications"). Customer assumes the sole risk and\r
+## liability of any use of Xilinx products in Critical\r
+## Applications, subject only to applicable laws and\r
+## regulations governing limitations on product liability.\r
+## \r
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS\r
+## PART OF THIS FILE AT ALL TIMES.\r
+\r
+############################## Active GTX Attributes #######################\r
+ \r
+##________________________ Attributes for GTX 0_____________________\r
+ \r
+
+##--------------------------TX PLL----------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE = "RXPLL";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG = 24'h21680a;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG = 8'h07;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT = 2;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG = 3'b111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER = 4;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE = 10'b0000110100;
+
+##-----------------------TX Interface-------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH = 10;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG = 6'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL = "TXPLLREFCLK_DIV1";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY = 10'b0000000000;
+
+##------------TX Buffering and Phase Alignment----------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT = 1'b1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG = 20'h80082;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG = 6'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL = "TXUSR";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC = 4'b0100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC = 4'b0110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING = 8'b10000000;
+
+##-----------------------TX Gearbox---------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE = "FALSE";
+
+##--------------TX Driver and OOB Signalling------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE = "DIRECT";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY = 3'b101;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY = 3'b011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD = "FALSE";
+
+##------------TX Pipe Control for PCI Express/SATA------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL = 4'b1111;
+
+##----------------TX Attributes for PCI Express---------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0 = 5'b11010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1 = 5'b10000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0 = 7'b1001110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1 = 7'b1001001;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2 = 7'b1000101;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3 = 7'b1000010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4 = 7'b1000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0 = 7'b1000110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1 = 7'b1000100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2 = 7'b1000010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3 = 7'b1000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4 = 7'b1000000;
+
+##--------------------------RX PLL----------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG = 24'h21680a;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG = 8'h07;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT = 2;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG = 3'b111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER = 4;
+
+##-----------------------RX Interface-------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH = 10;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL = "RXRECCLKPMA_DIV1";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY = 16'h0000;
+
+##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME = 5'b10100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD = 3'b011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN = 27'h640404C;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG = 25'h05ce008;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG = 14'h1832;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL = 5'b00000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM = 2'b01;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG = 7'h00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG = 76'h0040000040000000003;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG = 2'b00;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG = 17'h00000;
+
+##------------RX Decision Feedback Equalizer(DFE)-------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME = 5'b01100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG = 8'b00011011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET = 8'h4C;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE = 2'b00;
+
+##-----------------------PRBS Detection-----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK = 1'b0;
+
+##----------------Comma Detection and Alignment---------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE = 10'b1111111100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE = 10'b1010000011;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE = 10'b0101111100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT = 5;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE = "OFF";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA = "TRUE";
+
+##---------------RX Loss-of-sync State Machine----------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR = 8;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD = 256;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM = "TRUE";
+
+##-----------------------RX Gearbox---------------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE = "FALSE";
+
+##-----------RX Elastic Buffer and Phase alignment------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2 = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE = "FAST";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT = 4'b1000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT = 4'b0000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL = "RXUSR";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC = 4'b1110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET = 5'b00010;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC = 4'b1110;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL = 3'b000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING = 8'b10000000;
+
+##----------------------Clock Correction----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT = 16;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT = 14;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE = "TRUE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT = 0;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4 = 10'b0100000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE = "FALSE";
+
+##----------------------Channel Bonding----------------------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4 = 10'b0000000000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG = 5'b00000;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE = "FALSE";
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN = 1;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE = "FALSE";
+
+##-----------RX Attributes for PCI Express/SATA/SAS----------
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS = 52;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS = 40;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL = 3'b100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL = 3'b100;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST = 11;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT = 34;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE = 11;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST = 6;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT = 19;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE = 6;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2 = 12'h03c;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2 = 8'h19;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE = 8'hff;
+INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2 = 10'h064;
+\r
+\r
+\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : gtxvirtex6fee80.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module GTXVIRTEX6FEE80 (a GTX Wrapper)\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+\r
+--***************************** Entity Declaration ****************************\r
+\r
+entity gtxVirtex6FEE80 is\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+ \r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+ \r
+ GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+\r
+ \r
+);\r
+\r
+\r
+end gtxVirtex6FEE80;\r
+ \r
+architecture RTL of gtxVirtex6FEE80 is\r
+\r
+ attribute CORE_GENERATION_INFO : string;\r
+ attribute CORE_GENERATION_INFO of RTL : architecture is "gtxVirtex6FEE80,v6_gtxwizard_v1_12,{protocol_file=Start_from_scratch}";\r
+\r
+--***************************** Signal Declarations *****************************\r
+\r
+ -- ground and tied_to_vcc_i signals\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+\r
+ signal gtx0_gtxtest_bit1 : std_logic;\r
+ signal gtx0_gtxtest_done : std_logic;\r
+ signal gtx0_gtxtest_i : std_logic_vector(12 downto 0);\r
+ signal gtx0_txreset_i : std_logic;\r
+ signal gtx0_rxreset_i : std_logic;\r
+ signal gtx0_rxplllkdet_i : std_logic;\r
+ \r
+\r
+ \r
+ signal gtx0_share_rxpll_i : std_logic_vector(1 downto 0);\r
+ signal gtx0_mgtrefclkrx_i : std_logic_vector(1 downto 0);\r
+ \r
+--*************************** Component Declarations **************************\r
+component gtxVirtex6FEE80_gtx\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ GTX_SIM_GTXRESET_SPEEDUP : integer := 0;\r
+ \r
+ -- Share RX PLL parameter\r
+ GTX_TX_CLK_SOURCE : string := "TXPLL";\r
+ -- Save power parameter\r
+ GTX_POWER_SAVE : bit_vector := "0000000000"\r
+);\r
+port \r
+( \r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ RXCHARISK_OUT : out std_logic;
+ RXDISPERR_OUT : out std_logic;
+ RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ RXENMCOMMAALIGN_IN : in std_logic;
+ RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ RXDATA_OUT : out std_logic_vector(7 downto 0);
+ RXRECCLK_OUT : out std_logic;
+ RXRESET_IN : in std_logic;
+ RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ RXCDRRESET_IN : in std_logic;
+ RXN_IN : in std_logic;
+ RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ RXDLYALIGNDISABLE_IN : in std_logic;
+ RXDLYALIGNMONENB_IN : in std_logic;
+ RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ RXDLYALIGNOVERRIDE_IN : in std_logic;
+ RXDLYALIGNRESET_IN : in std_logic;
+ RXENPMAPHASEALIGN_IN : in std_logic;
+ RXPMASETPHASE_IN : in std_logic;
+ RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTXRXRESET_IN : in std_logic;
+ MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
+ PLLRXRESET_IN : in std_logic;
+ RXPLLLKDET_OUT : out std_logic;
+ RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARISK_IN : in std_logic;
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTXTEST_IN : in std_logic_vector(12 downto 0);
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN : in std_logic_vector(7 downto 0);
+ TXOUTCLK_OUT : out std_logic;
+ TXRESET_IN : in std_logic;
+ TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ TXN_OUT : out std_logic;
+ TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ TXDLYALIGNDISABLE_IN : in std_logic;
+ TXDLYALIGNMONENB_IN : in std_logic;
+ TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ TXDLYALIGNRESET_IN : in std_logic;
+ TXENPMAPHASEALIGN_IN : in std_logic;
+ TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTXTXRESET_IN : in std_logic;
+ MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
+ PLLTXRESET_IN : in std_logic;
+ TXPLLLKDET_OUT : out std_logic;
+ TXRESETDONE_OUT : out std_logic
+\r
+\r
+);\r
+end component;\r
+\r
+component DOUBLE_RESET\r
+port\r
+(\r
+ CLK : in std_logic;\r
+ PLLLKDET : in std_logic;\r
+ GTXTEST_DONE : out std_logic;\r
+ GTXTEST_BIT1 : out std_logic\r
+\r
+);\r
+end component;\r
+\r
+--********************************* Main Body of Code**************************\r
+\r
+begin \r
+\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');\r
+ tied_to_vcc_i <= '1';\r
+ \r
+ gtx0_gtxtest_i <= b"10000000000" & gtx0_gtxtest_bit1 & '0';\r
+ gtx0_txreset_i <= gtx0_gtxtest_done or GTX0_TXRESET_IN;\r
+ gtx0_rxreset_i <= GTX0_RXRESET_IN;\r
+ GTX0_RXPLLLKDET_OUT <= gtx0_rxplllkdet_i;\r
+\r
+ \r
+ gtx0_mgtrefclkrx_i <= (tied_to_ground_i & GTX0_MGTREFCLKRX_IN);
+\r
+ \r
+ --------------------------- GTX Instances ------------------------------- \r
+\r
+\r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+\r
+ gtx0_gtxVirtex6FEE80_i : gtxVirtex6FEE80_gtx\r
+ generic map\r
+ (\r
+ -- Simulation attributes\r
+ GTX_SIM_GTXRESET_SPEEDUP => WRAPPER_SIM_GTXRESET_SPEEDUP,\r
+ \r
+ -- Share RX PLL parameter\r
+ GTX_TX_CLK_SOURCE => "RXPLL",\r
+ -- Save power parameter\r
+ GTX_POWER_SAVE => "0000110100"\r
+ )\r
+ port map\r
+ (\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ RXCHARISK_OUT => GTX0_RXCHARISK_OUT,
+ RXDISPERR_OUT => GTX0_RXDISPERR_OUT,
+ RXNOTINTABLE_OUT => GTX0_RXNOTINTABLE_OUT,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ RXENMCOMMAALIGN_IN => GTX0_RXENMCOMMAALIGN_IN,
+ RXENPCOMMAALIGN_IN => GTX0_RXENPCOMMAALIGN_IN,
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ RXDATA_OUT => GTX0_RXDATA_OUT,
+ RXRECCLK_OUT => GTX0_RXRECCLK_OUT,
+ RXRESET_IN => gtx0_rxreset_i,
+ RXUSRCLK2_IN => GTX0_RXUSRCLK2_IN,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ RXCDRRESET_IN => GTX0_RXCDRRESET_IN,
+ RXN_IN => GTX0_RXN_IN,
+ RXP_IN => GTX0_RXP_IN,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ RXDLYALIGNDISABLE_IN => GTX0_RXDLYALIGNDISABLE_IN,
+ RXDLYALIGNMONENB_IN => GTX0_RXDLYALIGNMONENB_IN,
+ RXDLYALIGNMONITOR_OUT => GTX0_RXDLYALIGNMONITOR_OUT,
+ RXDLYALIGNOVERRIDE_IN => GTX0_RXDLYALIGNOVERRIDE_IN,
+ RXDLYALIGNRESET_IN => GTX0_RXDLYALIGNRESET_IN,
+ RXENPMAPHASEALIGN_IN => GTX0_RXENPMAPHASEALIGN_IN,
+ RXPMASETPHASE_IN => GTX0_RXPMASETPHASE_IN,
+ RXSTATUS_OUT => GTX0_RXSTATUS_OUT,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ RXLOSSOFSYNC_OUT => GTX0_RXLOSSOFSYNC_OUT,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTXRXRESET_IN => GTX0_GTXRXRESET_IN,
+ MGTREFCLKRX_IN => gtx0_mgtrefclkrx_i,
+ PLLRXRESET_IN => GTX0_PLLRXRESET_IN,
+ RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
+ RXRESETDONE_OUT => GTX0_RXRESETDONE_OUT,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ PHYSTATUS_OUT => GTX0_PHYSTATUS_OUT,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARISK_IN => GTX0_TXCHARISK_IN,
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTXTEST_IN => gtx0_gtxtest_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN => GTX0_TXDATA_IN,
+ TXOUTCLK_OUT => GTX0_TXOUTCLK_OUT,
+ TXRESET_IN => gtx0_txreset_i,
+ TXUSRCLK2_IN => GTX0_TXUSRCLK2_IN,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ TXN_OUT => GTX0_TXN_OUT,
+ TXP_OUT => GTX0_TXP_OUT,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ TXDLYALIGNDISABLE_IN => GTX0_TXDLYALIGNDISABLE_IN,
+ TXDLYALIGNMONENB_IN => GTX0_TXDLYALIGNMONENB_IN,
+ TXDLYALIGNMONITOR_OUT => GTX0_TXDLYALIGNMONITOR_OUT,
+ TXDLYALIGNRESET_IN => GTX0_TXDLYALIGNRESET_IN,
+ TXENPMAPHASEALIGN_IN => GTX0_TXENPMAPHASEALIGN_IN,
+ TXPMASETPHASE_IN => GTX0_TXPMASETPHASE_IN,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTXTXRESET_IN => GTX0_GTXTXRESET_IN,
+ MGTREFCLKTX_IN => gtx0_mgtrefclkrx_i,
+ PLLTXRESET_IN => tied_to_ground_i,
+ TXPLLLKDET_OUT => open,
+ TXRESETDONE_OUT => GTX0_TXRESETDONE_OUT
+\r
+ );\r
+\r
+ \r
+ \r
+ gtx0_double_reset_i : DOUBLE_RESET\r
+ port map\r
+ (\r
+ CLK => GTX0_DOUBLE_RESET_CLK_IN,\r
+ PLLLKDET => gtx0_rxplllkdet_i,\r
+ GTXTEST_DONE => gtx0_gtxtest_done,\r
+ GTXTEST_BIT1 => gtx0_gtxtest_bit1\r
+ );\r
+\r
+ \r
+\r
+ \r
+end RTL;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : gtxvirtex6fee80_gtx.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module GTXVIRTEX6FEE80_GTX (a GTX Wrapper)\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***************************** Entity Declaration ****************************\r
+\r
+entity gtxVirtex6FEE80_gtx is\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset\r
+ \r
+ -- Share RX PLL parameter\r
+ GTX_TX_CLK_SOURCE : string := "TXPLL";\r
+ -- Save power parameter\r
+ GTX_POWER_SAVE : bit_vector := "0000000000"\r
+);\r
+port \r
+(\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ RXCHARISK_OUT : out std_logic;
+ RXDISPERR_OUT : out std_logic;
+ RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ RXENMCOMMAALIGN_IN : in std_logic;
+ RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ RXDATA_OUT : out std_logic_vector(7 downto 0);
+ RXRECCLK_OUT : out std_logic;
+ RXRESET_IN : in std_logic;
+ RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ RXCDRRESET_IN : in std_logic;
+ RXN_IN : in std_logic;
+ RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ RXDLYALIGNDISABLE_IN : in std_logic;
+ RXDLYALIGNMONENB_IN : in std_logic;
+ RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ RXDLYALIGNOVERRIDE_IN : in std_logic;
+ RXDLYALIGNRESET_IN : in std_logic;
+ RXENPMAPHASEALIGN_IN : in std_logic;
+ RXPMASETPHASE_IN : in std_logic;
+ RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTXRXRESET_IN : in std_logic;
+ MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
+ PLLRXRESET_IN : in std_logic;
+ RXPLLLKDET_OUT : out std_logic;
+ RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXCHARISK_IN : in std_logic;
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTXTEST_IN : in std_logic_vector(12 downto 0);
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA_IN : in std_logic_vector(7 downto 0);
+ TXOUTCLK_OUT : out std_logic;
+ TXRESET_IN : in std_logic;
+ TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ TXN_OUT : out std_logic;
+ TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ TXDLYALIGNDISABLE_IN : in std_logic;
+ TXDLYALIGNMONENB_IN : in std_logic;
+ TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ TXDLYALIGNRESET_IN : in std_logic;
+ TXENPMAPHASEALIGN_IN : in std_logic;
+ TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTXTXRESET_IN : in std_logic;
+ MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
+ PLLTXRESET_IN : in std_logic;
+ TXPLLLKDET_OUT : out std_logic;
+ TXRESETDONE_OUT : out std_logic
+\r
+\r
+);\r
+\r
+\r
+end gtxVirtex6FEE80_gtx;\r
+\r
+architecture RTL of gtxVirtex6FEE80_gtx is\r
+ \r
+--**************************** Signal Declarations ****************************\r
+\r
+ -- ground and tied_to_vcc_i signals\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+\r
+\r
+\r
+ -- RX Datapath signals\r
+ signal rxdata_i : std_logic_vector(31 downto 0); \r
+ signal rxchariscomma_float_i : std_logic_vector(2 downto 0);\r
+ signal rxcharisk_float_i : std_logic_vector(2 downto 0);\r
+ signal rxdisperr_float_i : std_logic_vector(2 downto 0);\r
+ signal rxnotintable_float_i : std_logic_vector(2 downto 0);\r
+ signal rxrundisp_float_i : std_logic_vector(2 downto 0);\r
+ \r
+\r
+\r
+ -- TX Datapath signals\r
+ signal txdata_i : std_logic_vector(31 downto 0);\r
+ signal txkerr_float_i : std_logic_vector(2 downto 0);\r
+ signal txrundisp_float_i : std_logic_vector(2 downto 0);\r
+\r
+--******************************** Main Body of Code***************************\r
+ \r
+begin \r
+\r
+ --------------------------- Static signal Assignments --------------------- \r
+\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i(63 downto 0) <= (others => '0');\r
+ tied_to_vcc_i <= '1';\r
+\r
+ ------------------- GTX Datapath byte mapping -----------------\r
+\r
+ RXDATA_OUT <= rxdata_i(7 downto 0);\r
+\r
+ txdata_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);\r
+\r
+\r
+\r
+ ----------------------------- GTX Instance -------------------------- \r
+\r
+ gtxe1_i :GTXE1\r
+ generic map\r
+ (\r
+\r
+ --_______________________ Simulation-Only Attributes ___________________\r
+\r
+ SIM_RECEIVER_DETECT_PASS => (TRUE),\r
+ \r
+ SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),\r
+\r
+ SIM_TX_ELEC_IDLE_LEVEL => ("X"),\r
+\r
+ SIM_VERSION => ("2.0"),\r
+ SIM_TXREFCLK_SOURCE => ("000"),\r
+ SIM_RXREFCLK_SOURCE => ("000"),\r
+ \r
+
+ ----------------------------TX PLL----------------------------
+ TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
+ TX_OVERSAMPLE_MODE => (FALSE),
+ TXPLL_COM_CFG => (x"21680a"),
+ TXPLL_CP_CFG => (x"07"),
+ TXPLL_DIVSEL_FB => (5),
+ TXPLL_DIVSEL_OUT => (2),
+ TXPLL_DIVSEL_REF => (1),
+ TXPLL_DIVSEL45_FB => (5),
+ TXPLL_LKDET_CFG => ("111"),
+ TX_CLK25_DIVIDER => (4),
+ TXPLL_SATA => ("00"),
+ TX_TDCC_CFG => ("00"),
+ PMA_CAS_CLK_EN => (FALSE),
+ POWER_SAVE => (GTX_POWER_SAVE),
+
+ -------------------------TX Interface-------------------------
+ GEN_TXUSRCLK => (TRUE),
+ TX_DATA_WIDTH => (10),
+ TX_USRCLK_CFG => (x"00"),
+ TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
+ TXOUTCLK_DLY => ("0000000000"),
+
+ --------------TX Buffering and Phase Alignment----------------
+ TX_PMADATA_OPT => ('1'),
+ PMA_TX_CFG => (x"80082"),
+ TX_BUFFER_USE => (FALSE),
+ TX_BYTECLK_CFG => (x"00"),
+ TX_EN_RATE_RESET_BUF => (TRUE),
+ TX_XCLK_SEL => ("TXUSR"),
+ TX_DLYALIGN_CTRINC => ("0100"),
+ TX_DLYALIGN_LPFINC => ("0110"),
+ TX_DLYALIGN_MONSEL => ("000"),
+ TX_DLYALIGN_OVRDSETTING => ("10000000"),
+
+ -------------------------TX Gearbox---------------------------
+ GEARBOX_ENDEC => ("000"),
+ TXGEARBOX_USE => (FALSE),
+
+ ----------------TX Driver and OOB Signalling------------------
+ TX_DRIVE_MODE => ("DIRECT"),
+ TX_IDLE_ASSERT_DELAY => ("101"),
+ TX_IDLE_DEASSERT_DELAY => ("011"),
+ TXDRIVE_LOOPBACK_HIZ => (FALSE),
+ TXDRIVE_LOOPBACK_PD => (FALSE),
+
+ --------------TX Pipe Control for PCI Express/SATA------------
+ COM_BURST_VAL => ("1111"),
+
+ ------------------TX Attributes for PCI Express---------------
+ TX_DEEMPH_0 => ("11010"),
+ TX_DEEMPH_1 => ("10000"),
+ TX_MARGIN_FULL_0 => ("1001110"),
+ TX_MARGIN_FULL_1 => ("1001001"),
+ TX_MARGIN_FULL_2 => ("1000101"),
+ TX_MARGIN_FULL_3 => ("1000010"),
+ TX_MARGIN_FULL_4 => ("1000000"),
+ TX_MARGIN_LOW_0 => ("1000110"),
+ TX_MARGIN_LOW_1 => ("1000100"),
+ TX_MARGIN_LOW_2 => ("1000010"),
+ TX_MARGIN_LOW_3 => ("1000000"),
+ TX_MARGIN_LOW_4 => ("1000000"),
+
+ ----------------------------RX PLL----------------------------
+ RX_OVERSAMPLE_MODE => (FALSE),
+ RXPLL_COM_CFG => (x"21680a"),
+ RXPLL_CP_CFG => (x"07"),
+ RXPLL_DIVSEL_FB => (5),
+ RXPLL_DIVSEL_OUT => (2),
+ RXPLL_DIVSEL_REF => (1),
+ RXPLL_DIVSEL45_FB => (5),
+ RXPLL_LKDET_CFG => ("111"),
+ RX_CLK25_DIVIDER => (4),
+
+ -------------------------RX Interface-------------------------
+ GEN_RXUSRCLK => (TRUE),
+ RX_DATA_WIDTH => (10),
+ RXRECCLK_CTRL => ("RXRECCLKPMA_DIV1"),
+ RXRECCLK_DLY => ("0000000000"),
+ RXUSRCLK_DLY => (x"0000"),
+
+ ----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
+ AC_CAP_DIS => (TRUE),
+ CDR_PH_ADJ_TIME => ("10100"),
+ OOBDETECT_THRESHOLD => ("011"),
+ PMA_CDR_SCAN => (x"640404C"),
+ PMA_RX_CFG => (x"05ce008"),
+ RCV_TERM_GND => (FALSE),
+ RCV_TERM_VTTRX => (TRUE),
+ RX_EN_IDLE_HOLD_CDR => (FALSE),
+ RX_EN_IDLE_RESET_FR => (FALSE),
+ RX_EN_IDLE_RESET_PH => (FALSE),
+ TX_DETECT_RX_CFG => (x"1832"),
+ TERMINATION_CTRL => ("00000"),
+ TERMINATION_OVRD => (FALSE),
+ CM_TRIM => ("01"),
+ PMA_RXSYNC_CFG => (x"00"),
+ PMA_CFG => (x"0040000040000000003"),
+ BGTEST_CFG => ("00"),
+ BIAS_CFG => (x"00000"),
+
+ --------------RX Decision Feedback Equalizer(DFE)-------------
+ DFE_CAL_TIME => ("01100"),
+ DFE_CFG => ("00011011"),
+ RX_EN_IDLE_HOLD_DFE => (TRUE),
+ RX_EYE_OFFSET => (x"4C"),
+ RX_EYE_SCANMODE => ("00"),
+
+ -------------------------PRBS Detection-----------------------
+ RXPRBSERR_LOOPBACK => ('0'),
+
+ ------------------Comma Detection and Alignment---------------
+ ALIGN_COMMA_WORD => (1),
+ COMMA_10B_ENABLE => ("1111111100"),
+ COMMA_DOUBLE => (FALSE),
+ DEC_MCOMMA_DETECT => (FALSE),
+ DEC_PCOMMA_DETECT => (FALSE),
+ DEC_VALID_COMMA_ONLY => (FALSE),
+ MCOMMA_10B_VALUE => ("1010000011"),
+ MCOMMA_DETECT => (TRUE),
+ PCOMMA_10B_VALUE => ("0101111100"),
+ PCOMMA_DETECT => (TRUE),
+ RX_DECODE_SEQ_MATCH => (TRUE),
+ RX_SLIDE_AUTO_WAIT => (5),
+ RX_SLIDE_MODE => ("OFF"),
+ SHOW_REALIGN_COMMA => (TRUE),
+
+ -----------------RX Loss-of-sync State Machine----------------
+ RX_LOS_INVALID_INCR => (8),
+ RX_LOS_THRESHOLD => (256),
+ RX_LOSS_OF_SYNC_FSM => (TRUE),
+
+ -------------------------RX Gearbox---------------------------
+ RXGEARBOX_USE => (FALSE),
+
+ -------------RX Elastic Buffer and Phase alignment------------
+ RX_BUFFER_USE => (FALSE),
+ RX_EN_IDLE_RESET_BUF => (FALSE),
+ RX_EN_MODE_RESET_BUF => (TRUE),
+ RX_EN_RATE_RESET_BUF => (TRUE),
+ RX_EN_REALIGN_RESET_BUF => (FALSE),
+ RX_EN_REALIGN_RESET_BUF2 => (FALSE),
+ RX_FIFO_ADDR_MODE => ("FAST"),
+ RX_IDLE_HI_CNT => ("1000"),
+ RX_IDLE_LO_CNT => ("0000"),
+ RX_XCLK_SEL => ("RXUSR"),
+ RX_DLYALIGN_CTRINC => ("1110"),
+ RX_DLYALIGN_EDGESET => ("00010"),
+ RX_DLYALIGN_LPFINC => ("1110"),
+ RX_DLYALIGN_MONSEL => ("000"),
+ RX_DLYALIGN_OVRDSETTING => ("10000000"),
+
+ ------------------------Clock Correction----------------------
+ CLK_COR_ADJ_LEN => (1),
+ CLK_COR_DET_LEN => (1),
+ CLK_COR_INSERT_IDLE_FLAG => (FALSE),
+ CLK_COR_KEEP_IDLE => (FALSE),
+ CLK_COR_MAX_LAT => (16),
+ CLK_COR_MIN_LAT => (14),
+ CLK_COR_PRECEDENCE => (TRUE),
+ CLK_COR_REPEAT_WAIT => (0),
+ CLK_COR_SEQ_1_1 => ("0100000000"),
+ CLK_COR_SEQ_1_2 => ("0100000000"),
+ CLK_COR_SEQ_1_3 => ("0100000000"),
+ CLK_COR_SEQ_1_4 => ("0100000000"),
+ CLK_COR_SEQ_1_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_1 => ("0100000000"),
+ CLK_COR_SEQ_2_2 => ("0100000000"),
+ CLK_COR_SEQ_2_3 => ("0100000000"),
+ CLK_COR_SEQ_2_4 => ("0100000000"),
+ CLK_COR_SEQ_2_ENABLE => ("1111"),
+ CLK_COR_SEQ_2_USE => (FALSE),
+ CLK_CORRECT_USE => (FALSE),
+
+ ------------------------Channel Bonding----------------------
+ CHAN_BOND_1_MAX_SKEW => (1),
+ CHAN_BOND_2_MAX_SKEW => (1),
+ CHAN_BOND_KEEP_ALIGN => (FALSE),
+ CHAN_BOND_SEQ_1_1 => ("0000000000"),
+ CHAN_BOND_SEQ_1_2 => ("0000000000"),
+ CHAN_BOND_SEQ_1_3 => ("0000000000"),
+ CHAN_BOND_SEQ_1_4 => ("0000000000"),
+ CHAN_BOND_SEQ_1_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_1 => ("0000000000"),
+ CHAN_BOND_SEQ_2_2 => ("0000000000"),
+ CHAN_BOND_SEQ_2_3 => ("0000000000"),
+ CHAN_BOND_SEQ_2_4 => ("0000000000"),
+ CHAN_BOND_SEQ_2_CFG => ("00000"),
+ CHAN_BOND_SEQ_2_ENABLE => ("1111"),
+ CHAN_BOND_SEQ_2_USE => (FALSE),
+ CHAN_BOND_SEQ_LEN => (1),
+ PCI_EXPRESS_MODE => (FALSE),
+
+ -------------RX Attributes for PCI Express/SATA/SAS----------
+ SAS_MAX_COMSAS => (52),
+ SAS_MIN_COMSAS => (40),
+ SATA_BURST_VAL => ("100"),
+ SATA_IDLE_VAL => ("100"),
+ SATA_MAX_BURST => (11),
+ SATA_MAX_INIT => (34),
+ SATA_MAX_WAKE => (11),
+ SATA_MIN_BURST => (6),
+ SATA_MIN_INIT => (19),
+ SATA_MIN_WAKE => (6),
+ TRANS_TIME_FROM_P2 => (x"03c"),
+ TRANS_TIME_NON_P2 => (x"19"),
+ TRANS_TIME_RATE => (x"ff"),
+ TRANS_TIME_TO_P2 => (x"064")
+\r
+\r
+ )\r
+ port map\r
+ (\r
+ ------------------------ Loopback and Powerdown Ports ----------------------
+ LOOPBACK => tied_to_ground_vec_i(2 downto 0),
+ RXPOWERDOWN => "00",
+ TXPOWERDOWN => "00",
+ -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
+ RXDATAVALID => open,
+ RXGEARBOXSLIP => tied_to_ground_i,
+ RXHEADER => open,
+ RXHEADERVALID => open,
+ RXSTARTOFSEQ => open,
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ RXCHARISCOMMA => open,
+ RXCHARISK(3 downto 1) => rxcharisk_float_i,
+ RXCHARISK(0) => RXCHARISK_OUT,
+ RXDEC8B10BUSE => tied_to_vcc_i,
+ RXDISPERR(3 downto 1) => rxdisperr_float_i,
+ RXDISPERR(0) => RXDISPERR_OUT,
+ RXNOTINTABLE(3 downto 1) => rxnotintable_float_i,
+ RXNOTINTABLE(0) => RXNOTINTABLE_OUT,
+ RXRUNDISP => open,
+ USRCODEERR => tied_to_ground_i,
+ ------------------- Receive Ports - Channel Bonding Ports ------------------
+ RXCHANBONDSEQ => open,
+ RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
+ RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
+ RXCHBONDMASTER => tied_to_ground_i,
+ RXCHBONDO => open,
+ RXCHBONDSLAVE => tied_to_ground_i,
+ RXENCHANSYNC => tied_to_ground_i,
+ ------------------- Receive Ports - Clock Correction Ports -----------------
+ RXCLKCORCNT => open,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ RXBYTEISALIGNED => open,
+ RXBYTEREALIGN => open,
+ RXCOMMADET => open,
+ RXCOMMADETUSE => tied_to_vcc_i,
+ RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN,
+ RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN,
+ RXSLIDE => tied_to_ground_i,
+ ----------------------- Receive Ports - PRBS Detection ---------------------
+ PRBSCNTRESET => tied_to_ground_i,
+ RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
+ RXPRBSERR => open,
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ RXDATA => rxdata_i,
+ RXRECCLK => RXRECCLK_OUT,
+ RXRECCLKPCS => open,
+ RXRESET => RXRESET_IN,
+ RXUSRCLK => tied_to_ground_i,
+ RXUSRCLK2 => RXUSRCLK2_IN,
+ ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
+ DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
+ DFECLKDLYADJMON => open,
+ DFEDLYOVRD => tied_to_ground_i,
+ DFEEYEDACMON => open,
+ DFESENSCAL => open,
+ DFETAP1 => tied_to_ground_vec_i(4 downto 0),
+ DFETAP1MONITOR => open,
+ DFETAP2 => tied_to_ground_vec_i(4 downto 0),
+ DFETAP2MONITOR => open,
+ DFETAP3 => tied_to_ground_vec_i(3 downto 0),
+ DFETAP3MONITOR => open,
+ DFETAP4 => tied_to_ground_vec_i(3 downto 0),
+ DFETAP4MONITOR => open,
+ DFETAPOVRD => tied_to_vcc_i,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GATERXELECIDLE => tied_to_vcc_i,
+ IGNORESIGDET => tied_to_vcc_i,
+ RXCDRRESET => RXCDRRESET_IN,
+ RXELECIDLE => open,
+ RXEQMIX => "0000000000",
+ RXN => RXN_IN,
+ RXP => RXP_IN,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ RXBUFRESET => tied_to_ground_i,
+ RXBUFSTATUS => open,
+ RXCHANISALIGNED => open,
+ RXCHANREALIGN => open,
+ RXDLYALIGNDISABLE => RXDLYALIGNDISABLE_IN,
+ RXDLYALIGNMONENB => RXDLYALIGNMONENB_IN,
+ RXDLYALIGNMONITOR => RXDLYALIGNMONITOR_OUT,
+ RXDLYALIGNOVERRIDE => RXDLYALIGNOVERRIDE_IN,
+ RXDLYALIGNRESET => RXDLYALIGNRESET_IN,
+ RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
+ RXDLYALIGNUPDSW => tied_to_ground_i,
+ RXENPMAPHASEALIGN => RXENPMAPHASEALIGN_IN,
+ RXPMASETPHASE => RXPMASETPHASE_IN,
+ RXSTATUS => RXSTATUS_OUT,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ RXLOSSOFSYNC => RXLOSSOFSYNC_OUT,
+ ---------------------- Receive Ports - RX Oversampling ---------------------
+ RXENSAMPLEALIGN => tied_to_ground_i,
+ RXOVERSAMPLEERR => open,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GREFCLKRX => tied_to_ground_i,
+ GTXRXRESET => GTXRXRESET_IN,
+ MGTREFCLKRX => MGTREFCLKRX_IN,
+ NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
+ PERFCLKRX => tied_to_ground_i,
+ PLLRXRESET => PLLRXRESET_IN,
+ RXPLLLKDET => RXPLLLKDET_OUT,
+ RXPLLLKDETEN => tied_to_vcc_i,
+ RXPLLPOWERDOWN => tied_to_ground_i,
+ RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
+ RXRATE => tied_to_ground_vec_i(1 downto 0),
+ RXRATEDONE => open,
+ RXRESETDONE => RXRESETDONE_OUT,
+ SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ PHYSTATUS => PHYSTATUS_OUT,
+ RXVALID => open,
+ ----------------- Receive Ports - RX Polarity Control Ports ----------------
+ RXPOLARITY => tied_to_ground_i,
+ --------------------- Receive Ports - RX Ports for SATA --------------------
+ COMINITDET => open,
+ COMSASDET => open,
+ COMWAKEDET => open,
+ ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
+ DADDR => tied_to_ground_vec_i(7 downto 0),
+ DCLK => tied_to_ground_i,
+ DEN => tied_to_ground_i,
+ DI => tied_to_ground_vec_i(15 downto 0),
+ DRDY => open,
+ DRPDO => open,
+ DWE => tied_to_ground_i,
+ -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
+ TXGEARBOXREADY => open,
+ TXHEADER => tied_to_ground_vec_i(2 downto 0),
+ TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
+ TXSTARTSEQ => tied_to_ground_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
+ TXCHARDISPMODE => tied_to_ground_vec_i(3 downto 0),
+ TXCHARDISPVAL => tied_to_ground_vec_i(3 downto 0),
+ TXCHARISK(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
+ TXCHARISK(0) => TXCHARISK_IN,
+ TXENC8B10BUSE => tied_to_vcc_i,
+ TXKERR => open,
+ TXRUNDISP => open,
+ ------------------------- Transmit Ports - GTX Ports -----------------------
+ GTXTEST => GTXTEST_IN,
+ MGTREFCLKFAB => open,
+ TSTCLK0 => tied_to_ground_i,
+ TSTCLK1 => tied_to_ground_i,
+ TSTIN => "11111111111111111111",
+ TSTOUT => open,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ TXDATA => txdata_i,
+ TXOUTCLK => TXOUTCLK_OUT,
+ TXOUTCLKPCS => open,
+ TXRESET => TXRESET_IN,
+ TXUSRCLK => tied_to_ground_i,
+ TXUSRCLK2 => TXUSRCLK2_IN,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ TXBUFDIFFCTRL => "100",
+ TXDIFFCTRL => "1000",
+ TXINHIBIT => tied_to_ground_i,
+ TXN => TXN_OUT,
+ TXP => TXP_OUT,
+ TXPOSTEMPHASIS => "00000",
+ --------------- Transmit Ports - TX Driver and OOB signalling --------------
+ TXPREEMPHASIS => "0000",
+ ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
+ TXBUFSTATUS => open,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ TXDLYALIGNDISABLE => TXDLYALIGNDISABLE_IN,
+ TXDLYALIGNMONENB => TXDLYALIGNMONENB_IN,
+ TXDLYALIGNMONITOR => TXDLYALIGNMONITOR_OUT,
+ TXDLYALIGNOVERRIDE => tied_to_ground_i,
+ TXDLYALIGNRESET => TXDLYALIGNRESET_IN,
+ TXDLYALIGNUPDSW => tied_to_ground_i,
+ TXENPMAPHASEALIGN => TXENPMAPHASEALIGN_IN,
+ TXPMASETPHASE => TXPMASETPHASE_IN,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GREFCLKTX => tied_to_ground_i,
+ GTXTXRESET => GTXTXRESET_IN,
+ MGTREFCLKTX => MGTREFCLKTX_IN,
+ NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
+ PERFCLKTX => tied_to_ground_i,
+ PLLTXRESET => PLLTXRESET_IN,
+ SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
+ TXPLLLKDET => TXPLLLKDET_OUT,
+ TXPLLLKDETEN => tied_to_vcc_i,
+ TXPLLPOWERDOWN => tied_to_ground_i,
+ TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
+ TXRATE => tied_to_ground_vec_i(1 downto 0),
+ TXRATEDONE => open,
+ TXRESETDONE => TXRESETDONE_OUT,
+ --------------------- Transmit Ports - TX PRBS Generator -------------------
+ TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
+ TXPRBSFORCEERR => tied_to_ground_i,
+ -------------------- Transmit Ports - TX Polarity Control ------------------
+ TXPOLARITY => tied_to_ground_i,
+ ----------------- Transmit Ports - TX Ports for PCI Express ----------------
+ TXDEEMPH => tied_to_ground_i,
+ TXDETECTRX => tied_to_ground_i,
+ TXELECIDLE => tied_to_ground_i,
+ TXMARGIN => tied_to_ground_vec_i(2 downto 0),
+ TXPDOWNASYNCH => tied_to_ground_i,
+ TXSWING => tied_to_ground_i,
+ --------------------- Transmit Ports - TX Ports for SATA -------------------
+ COMFINISH => open,
+ TXCOMINIT => tied_to_ground_i,
+ TXCOMSAS => tied_to_ground_i,
+ TXCOMWAKE => tied_to_ground_i
+\r
+ );\r
+ \r
+ end RTL;\r
+\r
+\r
+ \r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____ \r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : gtxvirtex6fee80_rx_sync.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxvirtex6fee80_rx_sync\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity gtxvirtex6fee80_rx_sync is\r
+port\r
+(\r
+ RXENPMAPHASEALIGN : out std_logic;\r
+ RXPMASETPHASE : out std_logic;\r
+ RXDLYALIGNDISABLE : out std_logic;\r
+ RXDLYALIGNOVERRIDE : out std_logic;\r
+ RXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+\r
+\r
+end gtxvirtex6fee80_rx_sync;\r
+\r
+architecture RTL of gtxvirtex6fee80_rx_sync is\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+\r
+ signal begin_r : std_logic;\r
+ signal phase_align_r : std_logic;\r
+ signal ready_r : std_logic;\r
+ signal sync_counter_r : unsigned(5 downto 0);\r
+ signal sync_done_count_r : unsigned(5 downto 0);\r
+ signal align_reset_counter_r : unsigned(4 downto 0);\r
+ signal wait_after_sync_r : std_logic;\r
+ signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
+ signal wait_before_setphase_r : std_logic;\r
+ signal align_reset_r : std_logic;\r
+ \r
+--*******************************Wire Declarations****************************\r
+ \r
+ signal count_32_setphase_complete_r : std_logic;\r
+ signal count_32_wait_complete_r : std_logic;\r
+ signal count_align_reset_complete_r : std_logic;\r
+ signal next_phase_align_c : std_logic;\r
+ signal next_align_reset_c : std_logic;\r
+ signal next_ready_c : std_logic;\r
+ signal next_wait_after_sync_c : std_logic;\r
+ signal next_wait_before_setphase_c : std_logic;\r
+ signal sync_32_times_done_r : std_logic;\r
+ \r
+ attribute max_fanout:string; \r
+ attribute max_fanout of ready_r : signal is "2";\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ --________________________________ State machine __________________________ \r
+ -- This state machine manages the phase alingment procedure of the GTX on the\r
+ -- receive side. The module is held in reset till the usrclk source is stable\r
+ -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate \r
+ -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.\r
+ -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes \r
+ -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. \r
+ -- After this, it goes into the wait_before_setphase_r state for 32 cycles. \r
+ -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the \r
+ -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. \r
+ -- After the port is deasserted, the state machine goes into a wait state for\r
+ -- 32 cycles. This procedure is repeated 32 times.\r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET='1') then\r
+ begin_r <= '1' after DLY;\r
+ align_reset_r <= '0' after DLY;\r
+ wait_before_setphase_r <= '0' after DLY;\r
+ phase_align_r <= '0' after DLY;\r
+ wait_after_sync_r <= '0' after DLY;\r
+ ready_r <= '0' after DLY;\r
+ else\r
+ begin_r <= '0' after DLY;\r
+ align_reset_r <= next_align_reset_c after DLY;\r
+ wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
+ phase_align_r <= next_phase_align_c after DLY;\r
+ wait_after_sync_r <= next_wait_after_sync_c after DLY;\r
+ ready_r <= next_ready_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_align_reset_c <= begin_r or\r
+ (align_reset_r and not count_align_reset_complete_r);\r
+ \r
+ next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or\r
+ (wait_before_setphase_r and not count_32_wait_complete_r); \r
+ \r
+ next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or\r
+ (phase_align_r and not count_32_setphase_complete_r) or\r
+ (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);\r
+ \r
+ next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or\r
+ (wait_after_sync_r and not count_32_wait_complete_r);\r
+\r
+ next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or\r
+ ready_r;\r
+\r
+ --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (align_reset_r='0') then\r
+ align_reset_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
+ end if;\r
+ end if ;\r
+ end process;\r
+ \r
+ count_align_reset_complete_r <= align_reset_counter_r(4)\r
+ and align_reset_counter_r(2);\r
+ \r
+ --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then\r
+ wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_wait_complete_r <= wait_before_setphase_counter_r(5);\r
+ \r
+ --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (phase_align_r='0') then\r
+ sync_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ sync_counter_r <= sync_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_setphase_complete_r <= sync_counter_r(5);\r
+\r
+ --__________ Counter for counting number of times sync is done ____________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (RESET='1') then\r
+ sync_done_count_r <= (others=>'0') after DLY;\r
+ elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then\r
+ sync_done_count_r <= sync_done_count_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ sync_32_times_done_r <= sync_done_count_r(5);\r
+\r
+ --_______________ Assign the phase align ports into the GTX _______________\r
+\r
+ RXDLYALIGNRESET <= align_reset_r;\r
+ RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
+ RXPMASETPHASE <= phase_align_r;\r
+ RXDLYALIGNDISABLE <= '1';\r
+ RXDLYALIGNOVERRIDE <= '1';\r
+\r
+ --_______________________ Assign the sync_done port _______________________\r
+ \r
+ SYNC_DONE <= ready_r;\r
+ \r
+ \r
+end RTL;\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : gtxvirtex6fee80_top.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxVirtex6FEE80_top\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration************************\r
+\r
+entity gtxVirtex6FEE80_top is\r
+generic\r
+(\r
+ EXAMPLE_CONFIG_INDEPENDENT_LANES : integer := 1;\r
+ EXAMPLE_LANE_WITH_START_CHAR : integer := 0; -- specifies lane with unique start frame ch\r
+ EXAMPLE_WORDS_IN_BRAM : integer := 512; -- specifies amount of data in BRAM\r
+ EXAMPLE_SIM_GTXRESET_SPEEDUP : integer := 1; -- simulation setting for GTX SecureIP model\r
+ EXAMPLE_USE_CHIPSCOPE : integer := 1 -- Set to 1 to use Chipscope to drive resets\r
+);\r
+port\r
+(\r
+ Q3_CLK0_MGTREFCLK_PAD_N_IN : in std_logic;\r
+ Q3_CLK0_MGTREFCLK_PAD_P_IN : in std_logic;\r
+ GTXTXRESET_IN : in std_logic;\r
+ GTXRXRESET_IN : in std_logic;\r
+ TRACK_DATA_OUT : out std_logic;\r
+ RXN_IN : in std_logic;\r
+ RXP_IN : in std_logic;\r
+ TXN_OUT : out std_logic;\r
+ TXP_OUT : out std_logic\r
+ \r
+);\r
+\r
+\r
+end gtxVirtex6FEE80_top;\r
+ \r
+architecture RTL of gtxVirtex6FEE80_top is\r
+\r
+--**************************Component Declarations*****************************\r
+\r
+\r
+component gtxVirtex6FEE80 \r
+generic\r
+(\r
+ -- Simulation attributes\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+\r
+ --_________________________________________________________________________\r
+ --_________________________________________________________________________\r
+ --GTX0 (X0_Y12)\r
+\r
+ GTX0_DOUBLE_RESET_CLK_IN : in std_logic;\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT : out std_logic;
+ GTX0_RXDISPERR_OUT : out std_logic;
+ GTX0_RXNOTINTABLE_OUT : out std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN : in std_logic;
+ GTX0_RXENPCOMMAALIGN_IN : in std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXRECCLK_OUT : out std_logic;
+ GTX0_RXRESET_IN : in std_logic;
+ GTX0_RXUSRCLK2_IN : in std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN : in std_logic;
+ GTX0_RXN_IN : in std_logic;
+ GTX0_RXP_IN : in std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_RXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_RXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_RXDLYALIGNOVERRIDE_IN : in std_logic;
+ GTX0_RXDLYALIGNRESET_IN : in std_logic;
+ GTX0_RXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_RXPMASETPHASE_IN : in std_logic;
+ GTX0_RXSTATUS_OUT : out std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT : out std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN : in std_logic;
+ GTX0_MGTREFCLKRX_IN : in std_logic;
+ GTX0_PLLRXRESET_IN : in std_logic;
+ GTX0_RXPLLLKDET_OUT : out std_logic;
+ GTX0_RXRESETDONE_OUT : out std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT : out std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN : in std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
+ GTX0_TXOUTCLK_OUT : out std_logic;
+ GTX0_TXRESET_IN : in std_logic;
+ GTX0_TXUSRCLK2_IN : in std_logic;
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT : out std_logic;
+ GTX0_TXP_OUT : out std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN : in std_logic;
+ GTX0_TXDLYALIGNMONENB_IN : in std_logic;
+ GTX0_TXDLYALIGNMONITOR_OUT : out std_logic_vector(7 downto 0);
+ GTX0_TXDLYALIGNRESET_IN : in std_logic;
+ GTX0_TXENPMAPHASEALIGN_IN : in std_logic;
+ GTX0_TXPMASETPHASE_IN : in std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN : in std_logic;
+ GTX0_TXRESETDONE_OUT : out std_logic
+\r
+\r
+);\r
+end component;\r
+\r
+component MGT_USRCLK_SOURCE \r
+generic\r
+(\r
+ FREQUENCY_MODE : string := "LOW"; \r
+ PERFORMANCE_MODE : string := "MAX_SPEED" \r
+);\r
+port\r
+(\r
+ DIV1_OUT : out std_logic;\r
+ DIV2_OUT : out std_logic;\r
+ DCM_LOCKED_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ DCM_RESET_IN : in std_logic\r
+\r
+);\r
+end component;\r
+\r
+component FRAME_GEN \r
+generic\r
+(\r
+ WORDS_IN_BRAM : integer := 256;\r
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+); \r
+port\r
+(\r
+ -- User Interface\r
+ TX_DATA : out std_logic_vector(39 downto 0);\r
+ TX_CHARISK : out std_logic_vector(3 downto 0); \r
+\r
+ -- System Interface\r
+ USER_CLK : in std_logic;\r
+ SYSTEM_RESET : in std_logic\r
+); \r
+end component;\r
+\r
+component FRAME_CHECK \r
+generic\r
+(\r
+ RX_DATA_WIDTH : integer := 16;\r
+ RXCTRL_WIDTH : integer := 2;\r
+ USE_COMMA : integer := 1;\r
+ NONE_MSB_FIRST_DEC : integer := 0;\r
+ COMMA_DOUBLE_DEC : integer := 0;\r
+ CHANBOND_SEQ_LEN : integer := 1;\r
+ WORDS_IN_BRAM : integer := 256;\r
+ CONFIG_INDEPENDENT_LANES : integer := 0;\r
+ START_OF_PACKET_CHAR : std_logic_vector(15 downto 0) ;\r
+ COMMA_DOUBLE_CHAR : std_logic_vector(15 downto 0) := x"f628";\r
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+ MEM_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEM_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";\r
+ MEMP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"\r
+);\r
+port\r
+(\r
+ -- User Interface\r
+ RX_DATA : in std_logic_vector((RX_DATA_WIDTH-1) downto 0);\r
+ \r
+ RXCTRL_IN : in std_logic_vector((RXCTRL_WIDTH-1) downto 0); \r
+ RX_ENMCOMMA_ALIGN : out std_logic;\r
+ RX_ENPCOMMA_ALIGN : out std_logic;\r
+ \r
+ RX_ENCHAN_SYNC : out std_logic; \r
+ RX_CHANBOND_SEQ : in std_logic; \r
+\r
+ -- Control Interface\r
+ INC_IN : in std_logic; \r
+ INC_OUT : out std_logic; \r
+ PATTERN_MATCH_N : out std_logic;\r
+ RESET_ON_ERROR : in std_logic; \r
+ \r
+ -- Error Monitoring\r
+ ERROR_COUNT : out std_logic_vector(7 downto 0);\r
+ \r
+ -- Track Data\r
+ TRACK_DATA : out std_logic;\r
+ \r
+ -- System Interface\r
+ USER_CLK : in std_logic;\r
+ SYSTEM_RESET : in std_logic\r
+ \r
+);\r
+end component;\r
+\r
+component MGT_USRCLK_SOURCE_MMCM\r
+generic\r
+(\r
+ MULT : real := 2.0;\r
+ DIVIDE : integer := 2; \r
+ CLK_PERIOD : real := 6.4; \r
+ OUT0_DIVIDE : real := 2.0;\r
+ OUT1_DIVIDE : integer := 2;\r
+ OUT2_DIVIDE : integer := 2;\r
+ OUT3_DIVIDE : integer := 2\r
+);\r
+port\r
+(\r
+ CLKFBOUT : out std_logic; \r
+ CLK0_OUT : out std_logic;\r
+ CLK1_OUT : out std_logic;\r
+ CLK2_OUT : out std_logic;\r
+ CLK3_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ MMCM_LOCKED_OUT : out std_logic;\r
+ MMCM_RESET_IN : in std_logic\r
+);\r
+end component;\r
+\r
+component gtxVirtex6FEE80_tx_sync\r
+generic\r
+(\r
+ -- Simulation attributes\r
+ SIM_TXPMASETPHASE_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset\r
+);\r
+port\r
+(\r
+ TXENPMAPHASEALIGN : out std_logic;\r
+ TXPMASETPHASE : out std_logic;\r
+ TXDLYALIGNDISABLE : out std_logic;\r
+ TXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+component gtxVirtex6FEE80_rx_sync\r
+port\r
+(\r
+ RXENPMAPHASEALIGN : out std_logic;\r
+ RXPMASETPHASE : out std_logic;\r
+ RXDLYALIGNDISABLE : out std_logic;\r
+ RXDLYALIGNOVERRIDE : out std_logic;\r
+ RXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+end component;\r
+\r
+\r
+-- Chipscope modules\r
+attribute syn_black_box : boolean;\r
+attribute syn_noprune : boolean;\r
+\r
+\r
+component data_vio\r
+port\r
+(\r
+ control : inout std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ async_in : in std_logic_vector(31 downto 0);\r
+ async_out : out std_logic_vector(31 downto 0);\r
+ sync_in : in std_logic_vector(31 downto 0);\r
+ sync_out : out std_logic_vector(31 downto 0)\r
+);\r
+end component;\r
+attribute syn_black_box of data_vio : component is TRUE;\r
+attribute syn_noprune of data_vio : component is TRUE;\r
+\r
+\r
+component icon\r
+port\r
+(\r
+ control0 : inout std_logic_vector(35 downto 0);\r
+ control1 : inout std_logic_vector(35 downto 0);\r
+ control2 : inout std_logic_vector(35 downto 0);\r
+ control3 : inout std_logic_vector(35 downto 0)\r
+);\r
+end component;\r
+attribute syn_black_box of icon : component is TRUE;\r
+attribute syn_noprune of icon : component is TRUE;\r
+\r
+\r
+component ila\r
+port\r
+(\r
+ control : inout std_logic_vector(35 downto 0);\r
+ clk : in std_logic;\r
+ trig0 : in std_logic_vector(84 downto 0)\r
+);\r
+end component;\r
+\r
+\r
+attribute syn_black_box of ila : component is TRUE;\r
+attribute syn_noprune of ila : component is TRUE;\r
+\r
+\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+ \r
+ attribute max_fanout : string; \r
+\r
+--************************** Register Declarations ****************************\r
+\r
+ signal gtx0_txresetdone_r : std_logic;\r
+ signal gtx0_txresetdone_r2 : std_logic;\r
+ signal gtx0_rxresetdone_i_r : std_logic;\r
+ signal gtx0_rxresetdone_r : std_logic;\r
+ signal gtx0_rxresetdone_r2 : std_logic;\r
+ signal gtx0_rxresetdone_r3 : std_logic;\r
+ attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";\r
+ signal gtx0_rxdata_r : std_logic_vector(7 downto 0);\r
+ signal gtx0_rxcharisk_r : std_logic_vector(0 downto 0); \r
+\r
+\r
+--**************************** Wire Declarations ******************************\r
+ -------------------------- MGT Wrapper Wires ------------------------------\r
+ --________________________________________________________________________\r
+ --________________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ signal gtx0_rxcharisk_i : std_logic;
+ signal gtx0_rxdisperr_i : std_logic;
+ signal gtx0_rxnotintable_i : std_logic;
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ signal gtx0_rxenmcommaalign_i : std_logic;
+ signal gtx0_rxenpcommaalign_i : std_logic;
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ signal gtx0_rxdata_i : std_logic_vector(7 downto 0);
+ signal gtx0_rxrecclk_i : std_logic;
+ signal gtx0_rxreset_i : std_logic;
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ signal gtx0_rxcdrreset_i : std_logic;
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ signal gtx0_rxdlyaligndisable_i : std_logic;
+ signal gtx0_rxdlyalignmonenb_i : std_logic;
+ signal gtx0_rxdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_rxdlyalignoverride_i : std_logic;
+ signal gtx0_rxdlyalignreset_i : std_logic;
+ signal gtx0_rxenpmaphasealign_i : std_logic;
+ signal gtx0_rxpmasetphase_i : std_logic;
+ signal gtx0_rxstatus_i : std_logic_vector(2 downto 0);
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ signal gtx0_rxlossofsync_i : std_logic_vector(1 downto 0);
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ signal gtx0_gtxrxreset_i : std_logic;
+ signal gtx0_pllrxreset_i : std_logic;
+ signal gtx0_rxplllkdet_i : std_logic;
+ signal gtx0_rxresetdone_i : std_logic;
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ signal gtx0_phystatus_i : std_logic;
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ signal gtx0_txcharisk_i : std_logic;
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ signal gtx0_txdata_i : std_logic_vector(7 downto 0);
+ signal gtx0_txoutclk_i : std_logic;
+ signal gtx0_txreset_i : std_logic;
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ signal gtx0_txdlyaligndisable_i : std_logic;
+ signal gtx0_txdlyalignmonenb_i : std_logic;
+ signal gtx0_txdlyalignmonitor_i : std_logic_vector(7 downto 0);
+ signal gtx0_txdlyalignreset_i : std_logic;
+ signal gtx0_txenpmaphasealign_i : std_logic;
+ signal gtx0_txpmasetphase_i : std_logic;
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ signal gtx0_gtxtxreset_i : std_logic;
+ signal gtx0_txresetdone_i : std_logic;
+\r
+\r
+\r
+\r
+ signal gtx0_tx_system_reset_c : std_logic;\r
+ signal gtx0_rx_system_reset_c : std_logic;\r
+ signal gtx0_double_reset_clk_i : std_logic;\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);\r
+ signal drp_clk_in_i : std_logic;\r
+ \r
+\r
+ ----------------------------- User Clocks ---------------------------------\r
+\r
+ signal gtx0_txusrclk2_i : std_logic;
+ signal gtx0_rxusrclk2_i : std_logic;
+ signal txoutclk_mmcm0_locked_i : std_logic;
+ signal txoutclk_mmcm0_reset_i : std_logic;
+ signal gtx0_txoutclk_to_mmcm_i : std_logic;
+\r
+\r
+ ----------------------------- Reference Clocks ----------------------------\r
+ \r
+ signal q3_clk0_refclk_i : std_logic;\r
+ signal q3_clk0_refclk_i_bufg : std_logic;\r
+\r
+ ----------------------- Frame check/gen Module Signals --------------------\r
+ \r
+ signal gtx0_matchn_i : std_logic;\r
+ \r
+ signal gtx0_txcharisk_float_i : std_logic_vector(2 downto 0);\r
+ \r
+ signal gtx0_txdata_float_i : std_logic_vector(31 downto 0);\r
+ \r
+ signal gtx0_track_data_i : std_logic;\r
+ signal gtx0_block_sync_i : std_logic;\r
+ signal gtx0_error_count_i : std_logic_vector(7 downto 0);\r
+ signal gtx0_frame_check_reset_i : std_logic;\r
+ signal gtx0_inc_in_i : std_logic;\r
+ signal gtx0_inc_out_i : std_logic;\r
+ signal gtx0_unscrambled_data_i : std_logic_vector(7 downto 0);\r
+\r
+ signal reset_on_data_error_i : std_logic;\r
+ signal track_data_out_i : std_logic;\r
+ \r
+ \r
+ ------------------------- Sync Module Signals -----------------------------\r
+\r
+ signal gtx0_rx_sync_done_i : std_logic;\r
+ signal gtx0_reset_rxsync_c : std_logic;\r
+\r
+\r
+ signal gtx0_tx_sync_done_i : std_logic;\r
+ signal gtx0_reset_txsync_c : std_logic;\r
+\r
+ ----------------------- Chipscope Signals ---------------------------------\r
+\r
+ signal tx_data_vio_control_i : std_logic_vector(35 downto 0);
+ signal rx_data_vio_control_i : std_logic_vector(35 downto 0);
+ signal shared_vio_control_i : std_logic_vector(35 downto 0);
+ signal ila_control_i : std_logic_vector(35 downto 0);
+ signal tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal shared_vio_in_i : std_logic_vector(31 downto 0);
+ signal shared_vio_out_i : std_logic_vector(31 downto 0);
+ signal ila_in_i : std_logic_vector(84 downto 0);
+
+ signal gtx0_tx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_tx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_async_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_sync_in_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_async_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_rx_data_vio_sync_out_i : std_logic_vector(31 downto 0);
+ signal gtx0_ila_in_i : std_logic_vector(84 downto 0);
+
+\r
+ signal gtxtxreset_i : std_logic;\r
+ signal gtxrxreset_i : std_logic;\r
+\r
+ signal user_tx_reset_i : std_logic;\r
+ signal user_rx_reset_i : std_logic;\r
+ signal tx_vio_clk_i : std_logic;\r
+ signal tx_vio_clk_mux_out_i : std_logic;\r
+ signal rx_vio_ila_clk_i : std_logic;\r
+ signal rx_vio_ila_clk_mux_out_i : std_logic;\r
+\r
+ \r
+--**************************** Main Body of Code *******************************\r
+begin\r
+\r
+ -- Static signal Assigments\r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= x"0000000000000000";\r
+ tied_to_vcc_i <= '1';\r
+ tied_to_vcc_vec_i <= x"ff";\r
+\r
+\r
+\r
+ \r
+ \r
+\r
+ -----------------------Dedicated GTX Reference Clock Inputs ---------------\r
+ -- The dedicated reference clock inputs you selected in the GUI are implemented using\r
+ -- IBUFDS_GTXE1 instances.\r
+ --\r
+ -- In the UCF file for this example design, you will see that each of\r
+ -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these\r
+ -- locations, we tell the tools to use the dedicated input buffers to the GTX reference\r
+ -- clock network, rather than general purpose IOs. To select other pins, consult the \r
+ -- Implementation chapter of UG___, or rerun the wizard.\r
+ --\r
+ -- This network is the highest performace (lowest jitter) option for providing clocks\r
+ -- to the GTX transceivers.\r
+ \r
+ q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1\r
+ port map\r
+ (\r
+ O => q3_clk0_refclk_i,\r
+ ODIV2 => open,\r
+ CEB => tied_to_ground_i,\r
+ I => Q3_CLK0_MGTREFCLK_PAD_P_IN,\r
+ IB => Q3_CLK0_MGTREFCLK_PAD_N_IN\r
+ );\r
+\r
+ \r
+\r
+ q3_clk0_refclk_bufg_i : BUFG\r
+ port map\r
+ (\r
+ I => q3_clk0_refclk_i,\r
+ O => q3_clk0_refclk_i_bufg\r
+ );\r
+\r
+ -----------------------Clock Input to Double Reset Module------------------\r
+ gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;\r
+\r
+\r
+ ----------------------------------- User Clocks ---------------------------\r
+ \r
+ -- The clock resources in this section were added based on userclk source selections on\r
+ -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:\r
+ -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to \r
+ -- avoid data errors in the fabric interface whenever the datapath is wider than 10 bits\r
+ -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency\r
+ -- or multiples of the same frequency can be accomadated using MMCMs. Use caution when\r
+ -- using RXRECCLK as a clock source, however - these clocks can typically only be shared if all\r
+ -- the channels using the clock are receiving data from TX channels that share a reference clock \r
+ -- source with each other.\r
+\r
+ txoutclk_mmcm0_reset_i <= not gtx0_rxplllkdet_i;
+ txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
+ generic map
+ (
+ MULT => 15.0,
+ DIVIDE => 1,
+ CLK_PERIOD => 12.5,
+ OUT0_DIVIDE => 6.0,
+ OUT1_DIVIDE => 1,
+ OUT2_DIVIDE => 1,
+ OUT3_DIVIDE => 1
+ )
+ port map
+ (
+ CLKFBOUT => open,
+ CLK0_OUT => gtx0_txusrclk2_i,
+ CLK1_OUT => open,
+ CLK2_OUT => open,
+ CLK3_OUT => open,
+ CLK_IN => gtx0_txoutclk_i,
+ MMCM_LOCKED_OUT => txoutclk_mmcm0_locked_i,
+ MMCM_RESET_IN => txoutclk_mmcm0_reset_i
+ );
+
+
+ rxrecclk_bufr1_i : BUFR
+ generic map
+ (
+ BUFR_DIVIDE => "BYPASS"
+ )
+ port map
+ (
+ CE => '1',
+ CLR => '0',
+ I => gtx0_rxrecclk_i,
+ O => gtx0_rxusrclk2_i
+ );
+
+
+\r
+\r
+ ----------------------------- The GTX Wrapper -----------------------------\r
+ \r
+ -- Use the instantiation template in the example directory to add the GTX wrapper to your design.\r
+ -- In this example, the wrapper is wired up for basic operation with a frame generator and frame \r
+ -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is \r
+ -- enabled, bonding should occur after alignment.\r
+\r
+\r
+ gtxVirtex6FEE80_i : gtxVirtex6FEE80\r
+ generic map\r
+ (\r
+ WRAPPER_SIM_GTXRESET_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
+ )\r
+ port map\r
+ (\r
+ \r
+ \r
+ \r
+ \r
+\r
+ --_____________________________________________________________________\r
+ --_____________________________________________________________________\r
+ --GTX0 (X0Y12)\r
+ GTX0_DOUBLE_RESET_CLK_IN => gtx0_double_reset_clk_i,\r
+ ----------------------- Receive Ports - 8b10b Decoder ----------------------
+ GTX0_RXCHARISK_OUT => gtx0_rxcharisk_i,
+ GTX0_RXDISPERR_OUT => gtx0_rxdisperr_i,
+ GTX0_RXNOTINTABLE_OUT => gtx0_rxnotintable_i,
+ --------------- Receive Ports - Comma Detection and Alignment --------------
+ GTX0_RXENMCOMMAALIGN_IN => gtx0_rxenmcommaalign_i,
+ GTX0_RXENPCOMMAALIGN_IN => gtx0_rxenpcommaalign_i,
+ ------------------- Receive Ports - RX Data Path interface -----------------
+ GTX0_RXDATA_OUT => gtx0_rxdata_i,
+ GTX0_RXRECCLK_OUT => gtx0_rxrecclk_i,
+ GTX0_RXRESET_IN => gtx0_rxreset_i,
+ GTX0_RXUSRCLK2_IN => gtx0_rxusrclk2_i,
+ ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
+ GTX0_RXCDRRESET_IN => gtx0_rxcdrreset_i,
+ GTX0_RXN_IN => RXN_IN,
+ GTX0_RXP_IN => RXP_IN,
+ -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
+ GTX0_RXDLYALIGNDISABLE_IN => gtx0_rxdlyaligndisable_i,
+ GTX0_RXDLYALIGNMONENB_IN => gtx0_rxdlyalignmonenb_i,
+ GTX0_RXDLYALIGNMONITOR_OUT => gtx0_rxdlyalignmonitor_i,
+ GTX0_RXDLYALIGNOVERRIDE_IN => gtx0_rxdlyalignoverride_i,
+ GTX0_RXDLYALIGNRESET_IN => gtx0_rxdlyalignreset_i,
+ GTX0_RXENPMAPHASEALIGN_IN => gtx0_rxenpmaphasealign_i,
+ GTX0_RXPMASETPHASE_IN => gtx0_rxpmasetphase_i,
+ GTX0_RXSTATUS_OUT => gtx0_rxstatus_i,
+ --------------- Receive Ports - RX Loss-of-sync State Machine --------------
+ GTX0_RXLOSSOFSYNC_OUT => gtx0_rxlossofsync_i,
+ ------------------------ Receive Ports - RX PLL Ports ----------------------
+ GTX0_GTXRXRESET_IN => gtx0_gtxrxreset_i,
+ GTX0_MGTREFCLKRX_IN => q3_clk0_refclk_i,
+ GTX0_PLLRXRESET_IN => gtx0_pllrxreset_i,
+ GTX0_RXPLLLKDET_OUT => gtx0_rxplllkdet_i,
+ GTX0_RXRESETDONE_OUT => gtx0_rxresetdone_i,
+ -------------- Receive Ports - RX Pipe Control for PCI Express -------------
+ GTX0_PHYSTATUS_OUT => gtx0_phystatus_i,
+ ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+ GTX0_TXCHARISK_IN => gtx0_txcharisk_i,
+ ------------------ Transmit Ports - TX Data Path interface -----------------
+ GTX0_TXDATA_IN => gtx0_txdata_i,
+ GTX0_TXOUTCLK_OUT => gtx0_txoutclk_i,
+ GTX0_TXRESET_IN => gtx0_txreset_i,
+ GTX0_TXUSRCLK2_IN => gtx0_txusrclk2_i,
+ ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+ GTX0_TXN_OUT => TXN_OUT,
+ GTX0_TXP_OUT => TXP_OUT,
+ -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
+ GTX0_TXDLYALIGNDISABLE_IN => gtx0_txdlyaligndisable_i,
+ GTX0_TXDLYALIGNMONENB_IN => gtx0_txdlyalignmonenb_i,
+ GTX0_TXDLYALIGNMONITOR_OUT => gtx0_txdlyalignmonitor_i,
+ GTX0_TXDLYALIGNRESET_IN => gtx0_txdlyalignreset_i,
+ GTX0_TXENPMAPHASEALIGN_IN => gtx0_txenpmaphasealign_i,
+ GTX0_TXPMASETPHASE_IN => gtx0_txpmasetphase_i,
+ ----------------------- Transmit Ports - TX PLL Ports ----------------------
+ GTX0_GTXTXRESET_IN => gtx0_gtxtxreset_i,
+ GTX0_TXRESETDONE_OUT => gtx0_txresetdone_i
+\r
+\r
+ );\r
+\r
+ -- Hold the TX in reset till the TX user clocks are stable\r
+ gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;\r
+\r
+ -- Hold the RX in reset till the RX user clocks are stable\r
+ \r
+ gtx0_rxreset_i <= not gtx0_rxplllkdet_i;\r
+\r
+\r
+\r
+ ------------------------------ TXSYNC module ------------------------------\r
+ -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It\r
+ -- waits for the user clocks to be stable, then drives the phase align signals on each\r
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
+ \r
+ -- Include the TX_SYNC module in your own design to perform phase synchronization if\r
+ -- your protocol bypasses the TX Buffers\r
+\r
+ \r
+ \r
+ gtx0_reset_txsync_c <= not gtx0_txresetdone_r2; \r
+\r
+ -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 \r
+ -- during implementation \r
+ gtx0_txsync_i : gtxVirtex6FEE80_tx_sync\r
+ generic map\r
+ (\r
+ SIM_TXPMASETPHASE_SPEEDUP => EXAMPLE_SIM_GTXRESET_SPEEDUP\r
+ )\r
+ port map\r
+ (\r
+ TXENPMAPHASEALIGN => gtx0_txenpmaphasealign_i,\r
+ TXPMASETPHASE => gtx0_txpmasetphase_i,\r
+ TXDLYALIGNDISABLE => gtx0_txdlyaligndisable_i,\r
+ TXDLYALIGNRESET => gtx0_txdlyalignreset_i,\r
+ SYNC_DONE => gtx0_tx_sync_done_i,\r
+ USER_CLK => gtx0_txusrclk2_i,\r
+ RESET => gtx0_reset_txsync_c\r
+ );\r
+\r
+ ---------------------------- RXSYNC modules -------------------------------\r
+ -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It\r
+ -- waits for the user clocks to be stable, then drives the RX phase align signals on each\r
+ -- GTX. When phase synchronization is complete, it asserts SYNC_DONE\r
+ \r
+ -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules\r
+ -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have \r
+ -- a stable clock\r
+ \r
+ \r
+ gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync\r
+ port map\r
+ (\r
+ RXENPMAPHASEALIGN => gtx0_rxenpmaphasealign_i,\r
+ RXPMASETPHASE => gtx0_rxpmasetphase_i,\r
+ RXDLYALIGNDISABLE => gtx0_rxdlyaligndisable_i,\r
+ RXDLYALIGNOVERRIDE => gtx0_rxdlyalignoverride_i,\r
+ RXDLYALIGNRESET => gtx0_rxdlyalignreset_i,\r
+ SYNC_DONE => gtx0_rx_sync_done_i,\r
+ USER_CLK => gtx0_rxusrclk2_i,\r
+ RESET => gtx0_reset_rxsync_c\r
+ );\r
+ \r
+ gtx0_reset_rxsync_c <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';\r
+ \r
+\r
+\r
+ -------------------------- User Module Resets -----------------------------\r
+ -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules\r
+ -- are held in reset till the RESETDONE goes high. \r
+ -- The RESETDONE is registered a couple of times on USRCLK2 and connected \r
+ -- to the reset of the modules\r
+ \r
+ process( gtx0_rxusrclk2_i)\r
+ begin\r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_i_r <= gtx0_rxresetdone_i after DLY;\r
+ end if; \r
+ end process; \r
+\r
+ process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)\r
+ begin\r
+ if(gtx0_rxresetdone_i_r = '0') then\r
+ gtx0_rxresetdone_r <= '0' after DLY;\r
+ gtx0_rxresetdone_r2 <= '0' after DLY;\r
+ elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_r <= gtx0_rxresetdone_i_r after DLY;\r
+ gtx0_rxresetdone_r2 <= gtx0_rxresetdone_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process( gtx0_rxusrclk2_i)\r
+ begin\r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then\r
+ gtx0_rxresetdone_r3 <= gtx0_rxresetdone_r2 after DLY;\r
+ end if; \r
+ end process; \r
+\r
+ process( gtx0_txusrclk2_i,gtx0_txresetdone_i)\r
+ begin\r
+ if(gtx0_txresetdone_i = '0') then\r
+ gtx0_txresetdone_r <= '0' after DLY;\r
+ gtx0_txresetdone_r2 <= '0' after DLY;\r
+ elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then\r
+ gtx0_txresetdone_r <= gtx0_txresetdone_i after DLY;\r
+ gtx0_txresetdone_r2 <= gtx0_txresetdone_r after DLY;\r
+ end if;\r
+ end process;\r
+\r
+\r
+ ------------------------------ Frame Generators ---------------------------\r
+ -- The example design uses Block RAM based frame generators to provide test\r
+ -- data to the GTXs for transmission. By default the frame generators are \r
+ -- loaded with an incrementing data sequence that includes commas/alignment\r
+ -- characters for alignment. If your protocol uses channel bonding, the \r
+ -- frame generator will also be preloaded with a channel bonding sequence.\r
+ \r
+ -- You can modify the data transmitted by changing the INIT values of the frame\r
+ -- generator in this file. Pay careful attention to bit order and the spacing\r
+ -- of your control and alignment characters.\r
+\r
+ gtx0_frame_gen : FRAME_GEN\r
+ generic map\r
+ (\r
+ WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
+ MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
+ )\r
+ port map\r
+ (\r
+ -- User Interface\r
+ TX_DATA(39 downto 8) => gtx0_txdata_float_i,\r
+ TX_DATA(7 downto 0) => gtx0_txdata_i,\r
+ \r
+ TX_CHARISK(3 downto 1) => gtx0_txcharisk_float_i,\r
+ TX_CHARISK(0) => gtx0_txcharisk_i,\r
+ -- System Interface\r
+ USER_CLK => gtx0_txusrclk2_i,\r
+ SYSTEM_RESET => gtx0_tx_system_reset_c\r
+ );\r
+ \r
+\r
+\r
+ ---------------------------------- Frame Checkers -------------------------\r
+ -- The example design uses Block RAM based frame checkers to verify incoming \r
+ -- data. By default the frame generators are loaded with a data sequence that \r
+ -- matches the outgoing sequence of the frame generators for the TX ports.\r
+ \r
+ -- You can modify the expected data sequence by changing the INIT values of the frame\r
+ -- checkers in this file. Pay careful attention to bit order and the spacing\r
+ -- of your control and alignment characters.\r
+ \r
+ -- When the frame checker receives data, it attempts to synchronise to the \r
+ -- incoming pattern by looking for the first sequence in the pattern. Once it \r
+ -- finds the first sequence, it increments through the sequence, and indicates an \r
+ -- error whenever the next value received does not match the expected value.\r
+\r
+ gtx0_frame_check_reset_i <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;\r
+\r
+ -- gtx0_frame_check0 is always connected to the lane with the start of char\r
+ -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off\r
+ gtx0_inc_in_i <= '0';\r
+\r
+ process(gtx0_rxusrclk2_i)\r
+ begin \r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
+ gtx0_rxdata_r <= gtx0_rxdata_i after DLY;\r
+ end if;\r
+ end process;\r
+\r
+ process(gtx0_rxusrclk2_i)\r
+ begin \r
+ if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then\r
+ gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i after DLY;\r
+ end if;\r
+ end process;\r
+ \r
+\r
+ \r
+ \r
+ gtx0_frame_check : FRAME_CHECK\r
+ generic map\r
+ (\r
+ RX_DATA_WIDTH => 8,\r
+ RXCTRL_WIDTH => 1,\r
+ USE_COMMA => 1,\r
+ WORDS_IN_BRAM => EXAMPLE_WORDS_IN_BRAM,\r
+ CONFIG_INDEPENDENT_LANES => 1,\r
+ START_OF_PACKET_CHAR => x"02bc",\r
+ MEM_00 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_01 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_02 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_03 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_04 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_05 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_06 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_07 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_08 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_09 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_0A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_0B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_0C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_0D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_0E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_0F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_10 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_11 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_12 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_13 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_14 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_15 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_16 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_17 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_18 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_19 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_1A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_1B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_1C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_1D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_1E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_1F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_20 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_21 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_22 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_23 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_24 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_25 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_26 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_27 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_28 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_29 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_2A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_2B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_2C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_2D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_2E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_2F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEM_30 => x"0000000600000005000000040000000300000002000000bc0000000100000000",
+ MEM_31 => x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
+ MEM_32 => x"000000160000001500000014000000130000001200000011000000100000000f",
+ MEM_33 => x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
+ MEM_34 => x"000000260000002500000024000000230000002200000021000000200000001f",
+ MEM_35 => x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
+ MEM_36 => x"000000360000003500000034000000330000003200000031000000300000002f",
+ MEM_37 => x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
+ MEM_38 => x"000000460000004500000044000000430000004200000041000000400000003f",
+ MEM_39 => x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
+ MEM_3A => x"000000560000005500000054000000530000005200000051000000500000004f",
+ MEM_3B => x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
+ MEM_3C => x"000000660000006500000064000000630000006200000061000000600000005f",
+ MEM_3D => x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
+ MEM_3E => x"000000760000007500000074000000730000007200000071000000700000006f",
+ MEM_3F => x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
+ MEMP_00 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_01 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_02 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_03 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_04 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_05 => x"0000000000000000000000000000000000000000000000000000000000000000",
+ MEMP_06 => x"0000000000000000000000000000000000000000000000000000000000000100",
+ MEMP_07 => x"0000000000000000000000000000000000000000000000000000000000000000"\r
+ )\r
+ port map\r
+ (\r
+ -- MGT Interface\r
+ RX_DATA => gtx0_rxdata_r,\r
+ RXCTRL_IN => gtx0_rxcharisk_r,\r
+ RX_ENMCOMMA_ALIGN => gtx0_rxenmcommaalign_i,\r
+ RX_ENPCOMMA_ALIGN => gtx0_rxenpcommaalign_i,\r
+ RX_ENCHAN_SYNC => open,\r
+ RX_CHANBOND_SEQ => tied_to_ground_i,\r
+ -- Control Interface\r
+ INC_IN => gtx0_inc_in_i,\r
+ INC_OUT => gtx0_inc_out_i,\r
+ PATTERN_MATCH_N => gtx0_matchn_i,\r
+ RESET_ON_ERROR => gtx0_frame_check_reset_i,\r
+ -- System Interface\r
+ USER_CLK => gtx0_rxusrclk2_i,\r
+ SYSTEM_RESET => gtx0_rx_system_reset_c,\r
+ ERROR_COUNT => gtx0_error_count_i,\r
+ TRACK_DATA => gtx0_track_data_i\r
+ );\r
+ \r
+\r
+\r
+ TRACK_DATA_OUT <= track_data_out_i;\r
+\r
+ track_data_out_i <= \r
+ gtx0_track_data_i ;\r
+\r
+\r
+\r
+ ----------------------------- Chipscope Connections -----------------------\r
+ -- When the example design is run in hardware, it uses chipscope to allow the\r
+ -- example design and GTX wrapper to be controlled and monitored. The \r
+ -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.\r
+ \r
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate\r
+ \r
+ \r
+ -- Shared VIO for all transievers \r
+ shared_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => shared_vio_control_i,\r
+ clk => tied_to_ground_i,\r
+ async_in => shared_vio_in_i,\r
+ async_out => shared_vio_out_i,\r
+ sync_in => tied_to_ground_vec_i(31 downto 0),\r
+ sync_out => open\r
+ );\r
+ \r
+ -- ICON for all VIOs \r
+ i_icon : icon\r
+ port map\r
+ (\r
+ control0 => shared_vio_control_i,\r
+ control1 => tx_data_vio_control_i,\r
+ control2 => rx_data_vio_control_i,\r
+ control3 => ila_control_i\r
+ );\r
+\r
+ \r
+ -- TX VIO \r
+ tx_data_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => tx_data_vio_control_i,\r
+ clk => gtx0_txusrclk2_i,\r
+ async_in => tx_data_vio_async_in_i,\r
+ async_out => tx_data_vio_async_out_i,\r
+ sync_in => tx_data_vio_sync_in_i,\r
+ sync_out => tx_data_vio_sync_out_i\r
+ );\r
+ \r
+ -- RX VIO \r
+ rx_data_vio_i : data_vio\r
+ port map\r
+ (\r
+ control => rx_data_vio_control_i,\r
+ clk => gtx0_rxusrclk2_i,\r
+ async_in => rx_data_vio_async_in_i,\r
+ async_out => rx_data_vio_async_out_i,\r
+ sync_in => rx_data_vio_sync_in_i,\r
+ sync_out => rx_data_vio_sync_out_i\r
+ );\r
+ \r
+ -- RX ILA\r
+ ila_i : ila\r
+ port map\r
+ (\r
+ control => ila_control_i,\r
+ clk => gtx0_rxusrclk2_i,\r
+ trig0 => ila_in_i\r
+ );\r
+\r
+\r
+\r
+ -- assign resets for frame_gen modules\r
+ gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i or user_tx_reset_i;\r
+ -- assign resets for frame_check modules\r
+ gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i or user_rx_reset_i;\r
+\r
+ gtx0_gtxtxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
+ gtx0_gtxrxreset_i <= gtxtxreset_i or gtxrxreset_i;\r
+
+ -- Shared VIO Outputs
+ gtxtxreset_i <= shared_vio_out_i(31);
+ gtxrxreset_i <= shared_vio_out_i(30);
+ user_tx_reset_i <= shared_vio_out_i(29);
+ user_rx_reset_i <= shared_vio_out_i(28);
+
+ -- Shared VIO Inputs
+ shared_vio_in_i(31 downto 0) <= "00000000000000000000000000000000";
+
+ -- Chipscope connections on GTX 0
+ gtx0_tx_data_vio_async_in_i(31) <= '0';
+ gtx0_tx_data_vio_async_in_i(30) <= gtx0_txresetdone_i;
+ gtx0_tx_data_vio_async_in_i(29 downto 22) <= gtx0_txdlyalignmonitor_i;
+ gtx0_tx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
+ gtx0_tx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
+ gtx0_txdlyalignmonenb_i <= tx_data_vio_async_out_i(30);
+ gtx0_rx_data_vio_async_in_i(31) <= gtx0_rxplllkdet_i;
+ gtx0_rx_data_vio_async_in_i(30) <= gtx0_rxresetdone_i;
+ gtx0_rx_data_vio_async_in_i(29 downto 22) <= gtx0_rxdlyalignmonitor_i;
+ gtx0_rx_data_vio_async_in_i(21 downto 0) <= "0000000000000000000000";
+ gtx0_rx_data_vio_sync_in_i(31 downto 0) <= "00000000000000000000000000000000";
+ gtx0_pllrxreset_i <= rx_data_vio_async_out_i(31);
+ gtx0_rxcdrreset_i <= rx_data_vio_async_out_i(30);
+ gtx0_ila_in_i(84) <= gtx0_rxcharisk_i;
+ gtx0_ila_in_i(83) <= gtx0_rxdisperr_i;
+ gtx0_ila_in_i(82) <= gtx0_rxnotintable_i;
+ gtx0_ila_in_i(81 downto 74) <= gtx0_rxdata_i;
+ gtx0_ila_in_i(73 downto 71) <= gtx0_rxstatus_i;
+ gtx0_ila_in_i(70 downto 69) <= gtx0_rxlossofsync_i;
+ gtx0_ila_in_i(68) <= gtx0_phystatus_i;
+ gtx0_ila_in_i(67 downto 60) <= gtx0_error_count_i;
+ gtx0_ila_in_i(59 downto 0) <= "000000000000000000000000000000000000000000000000000000000000";
+\r
+\r
+\r
+ tx_data_vio_async_in_i <= gtx0_tx_data_vio_async_in_i;
+\r
+\r
+ tx_data_vio_sync_in_i <= gtx0_tx_data_vio_sync_in_i;
+\r
+ rx_data_vio_async_in_i <= gtx0_rx_data_vio_async_in_i;
+\r
+\r
+ rx_data_vio_sync_in_i <= gtx0_rx_data_vio_sync_in_i;
+\r
+\r
+ ila_in_i <= gtx0_ila_in_i;
+\r
+\r
+end generate chipscope;\r
+\r
+\r
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate\r
+\r
+ -- If Chipscope is not being used, drive GTX reset signal\r
+ -- from the top level ports\r
+ gtx0_gtxtxreset_i <= GTXTXRESET_IN;\r
+ gtx0_gtxrxreset_i <= GTXRXRESET_IN;\r
+\r
+ -- assign resets for frame_gen modules\r
+ gtx0_tx_system_reset_c <= not gtx0_tx_sync_done_i;\r
+ -- assign resets for frame_check modules\r
+ gtx0_rx_system_reset_c <= not gtx0_rx_sync_done_i;\r
+\r
+ gtxtxreset_i <= tied_to_ground_i;
+ gtxrxreset_i <= tied_to_ground_i;
+ user_tx_reset_i <= tied_to_ground_i;
+ user_rx_reset_i <= tied_to_ground_i;
+ gtx0_txdlyalignmonenb_i <= tied_to_ground_i;
+ gtx0_pllrxreset_i <= tied_to_ground_i;
+ gtx0_rxcdrreset_i <= tied_to_ground_i;
+\r
+\r
+\r
+end generate no_chipscope;\r
+\r
+\r
+end RTL;\r
+\r
+\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor: Xilinx\r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard\r
+-- / / Filename : gtxvirtex6fee80_tx_sync.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\\r
+--\r
+--\r
+-- Module gtxvirtex6fee80_tx_sync\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+entity gtxvirtex6fee80_tx_sync is\r
+generic\r
+(\r
+ SIM_TXPMASETPHASE_SPEEDUP : integer:=0\r
+); \r
+port\r
+(\r
+ TXENPMAPHASEALIGN : out std_logic;\r
+ TXPMASETPHASE : out std_logic;\r
+ TXDLYALIGNDISABLE : out std_logic;\r
+ TXDLYALIGNRESET : out std_logic;\r
+ SYNC_DONE : out std_logic;\r
+ USER_CLK : in std_logic;\r
+ RESET : in std_logic\r
+);\r
+\r
+\r
+end gtxvirtex6fee80_tx_sync;\r
+\r
+architecture RTL of gtxvirtex6fee80_tx_sync is\r
+--***********************************Parameter Declarations********************\r
+\r
+ constant DLY : time := 1 ns;\r
+\r
+--*******************************Register Declarations************************\r
+\r
+ signal begin_r : std_logic;\r
+ signal phase_align_r : std_logic;\r
+ signal ready_r : std_logic;\r
+ signal sync_counter_r : unsigned(15 downto 0);\r
+ signal wait_before_setphase_counter_r : unsigned(5 downto 0);\r
+ signal align_reset_counter_r : unsigned(4 downto 0);\r
+ signal wait_before_setphase_r : std_logic;\r
+ signal align_reset_r : std_logic;\r
+ \r
+--*******************************Wire Declarations****************************\r
+ \r
+ signal count_setphase_complete_r : std_logic;\r
+ signal count_32_complete_r : std_logic;\r
+ signal count_align_reset_complete_r : std_logic;\r
+ signal next_phase_align_c : std_logic;\r
+ signal next_ready_c : std_logic;\r
+ signal next_wait_before_setphase_c : std_logic;\r
+ signal next_align_reset_c : std_logic;\r
+\r
+begin\r
+--*******************************Main Body of Code****************************\r
+\r
+ --________________________________ State machine __________________________ \r
+ -- This state machine manages the TX phase alignment procedure of the GTX.\r
+ -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE \r
+ -- is asserted, the state machine goes into the align_reset_r state, asserting\r
+ -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the \r
+ -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and \r
+ -- waiting 32 cycles, it goes into the phase_align_r state where the last \r
+ -- part of the alignment procedure is completed. This involves asserting \r
+ -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), \r
+ -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase \r
+ -- alignment procedure, TXDLYALIGNDISABLE is deasserted.\r
+ \r
+ -- State registers\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if(RESET='1') then\r
+ begin_r <= '1' after DLY;\r
+ align_reset_r <= '0' after DLY;\r
+ wait_before_setphase_r <= '0' after DLY;\r
+ phase_align_r <= '0' after DLY;\r
+ ready_r <= '0' after DLY;\r
+ else\r
+ begin_r <= '0' after DLY;\r
+ align_reset_r <= next_align_reset_c after DLY;\r
+ wait_before_setphase_r <= next_wait_before_setphase_c after DLY;\r
+ phase_align_r <= next_phase_align_c after DLY;\r
+ ready_r <= next_ready_c after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ -- Next state logic\r
+ next_align_reset_c <= begin_r or \r
+ (align_reset_r and not count_align_reset_complete_r);\r
+ \r
+ next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or \r
+ (wait_before_setphase_r and not count_32_complete_r);\r
+ \r
+ next_phase_align_c <= (wait_before_setphase_r and count_32_complete_r) or\r
+ (phase_align_r and not count_setphase_complete_r);\r
+ \r
+ next_ready_c <= (phase_align_r and count_setphase_complete_r) or\r
+ ready_r;\r
+\r
+ --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (align_reset_r='0') then\r
+ align_reset_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ align_reset_counter_r <= align_reset_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+ \r
+ count_align_reset_complete_r <= align_reset_counter_r(4) \r
+ and align_reset_counter_r(2);\r
+\r
+ --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (wait_before_setphase_r='0') then\r
+ wait_before_setphase_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ count_32_complete_r <= wait_before_setphase_counter_r(5);\r
+\r
+ --_______________ Counter for holding SYNC for SYNC_CYCLES ________________\r
+ process( USER_CLK )\r
+ begin\r
+ if(USER_CLK'event and USER_CLK = '1') then\r
+ if (phase_align_r='0') then\r
+ sync_counter_r <= (others=>'0') after DLY;\r
+ else\r
+ sync_counter_r <= sync_counter_r + 1 after DLY;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate\r
+ -- 64 cycles of setphase for simulation\r
+ count_setphase_complete_r <= sync_counter_r(6);\r
+end generate fast_simulation;\r
+\r
+no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate\r
+ -- 16384 cycles of setphase for output divider of 2\r
+ count_setphase_complete_r <= sync_counter_r(14);\r
+end generate no_fast_simulation;\r
+\r
+ --_______________ Assign the phase align ports into the GTX _______________\r
+\r
+ TXDLYALIGNRESET <= '0';\r
+ TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);\r
+ TXPMASETPHASE <= phase_align_r;\r
+ TXDLYALIGNDISABLE <= '1';\r
+\r
+ --_______________________ Assign the sync_done port _______________________\r
+ \r
+ SYNC_DONE <= ready_r;\r
+ \r
+ \r
+end RTL;\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
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--- /dev/null
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+PINATTR PinName control4[35:0]
+PINATTR Polarity BOTH
+\r
--- /dev/null
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+ <!-- ProjectNavigator created generated project file. -->\r
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+ <!-- For use in tracking generated file and other information -->\r
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+ <!-- allowing preservation of process status. -->\r
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+ <!-- -->\r
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+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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--- /dev/null
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\7fM4d<2we;4>50;3xL7e33td<5<4?:0yK6f2<ug=2>7>51zJ1g1=zf>386=4>{I0`0>{i?0>1<7?tH3a7?xh01<0;6<uG2b68yk1>>3:1=vF=c59~j2?0290:wE<l4:
\7fm3<>=83;pD?m;;|l4=<<728qC>n:4}o5:e?6=9rB9o95rn6;a>5<6sA8h86sa78a94?7|@;i?7p`89e83>4}O:j>0qc96e;295~N5k=1vb:7i:182
\7fM4d<2we;l>50;3xL7e33td<m<4?:0yK6f2<ug=j>7>51zJ1g1=zf>k86=4>{I0`0>{i?h>1<7?tH3a7?xh0i<0;6<uG2b68yk1f>3:1=vF=c59~j2g0290:wE<l4:
\7fm3d>=83;pD?m;;|l4e<<728qC>n:4}o5be?6=9rB9o95rn6ca>5<6sA8h86sa7`a94?7|@;i?7p`8ae83>4}O:j>0qc9ne;295~N5k=1vb:oi:182
\7fM4d<2we;o>50;3xL7e33td<n<4?:0yK6f2<ug=i>7>51zJ1g1=zf>h86=4>{I0`0>{i?k>1<7?tH3a7?xh0j<0;6<uG2b68yk1e>3:1=vF=c59~j2d0290:wE<l4:
\7fm3g>=83;pD?m;;|l4f<<728qC>n:4}o5ae?6=9rB9o95rn6`a>5<6sA8h86sa7ca94?7|@;i?7p`8be83>4}O:j>0qc9me;295~N5k=1vb:li:182
\7fM4d<2we;n>50;3xL7e33td<o<4?:0yK56?<@8937E<l4:
\7f~yxFGKr2o;7?643g5b0{GHKq;qMN_{|BC
\ No newline at end of file
--- /dev/null
+NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;\r
+TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;\r
+#Update Constraints\r
+NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;\r
+NET "U0/iSHIFT_OUT" TIG ;\r
+TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;\r
+TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;\r
+TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;\r
+TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2014 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 14.7\r
+-- \ \ Application: XILINX CORE Generator\r
+-- / / Filename : icon0.vhd\r
+-- /___/ /\ Timestamp : Tue Nov 25 11:13:40 W. Europe Standard Time 2014\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: VHDL Synthesis Wrapper\r
+-------------------------------------------------------------------------------\r
+-- This wrapper is used to integrate with Project Navigator and PlanAhead\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+ENTITY icon0 IS\r
+ port (\r
+ CONTROL0: inout std_logic_vector(35 downto 0);\r
+ CONTROL1: inout std_logic_vector(35 downto 0);\r
+ CONTROL2: inout std_logic_vector(35 downto 0);\r
+ CONTROL3: inout std_logic_vector(35 downto 0);\r
+ CONTROL4: inout std_logic_vector(35 downto 0));\r
+END icon0;\r
+\r
+ARCHITECTURE icon0_a OF icon0 IS\r
+BEGIN\r
+\r
+END icon0_a;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2014 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 14.7\r
+-- \ \ Application: Xilinx CORE Generator\r
+-- / / Filename : icon0.vho\r
+-- /___/ /\ Timestamp : Tue Nov 25 11:13:40 W. Europe Standard Time 2014\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: ISE Instantiation template\r
+-- Component Identifier: xilinx.com:ip:chipscope_icon:1.06.a\r
+-------------------------------------------------------------------------------\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component icon0\r
+ PORT (\r
+ CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CONTROL3 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CONTROL4 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));\r
+\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+\r
+your_instance_name : icon0\r
+ port map (\r
+ CONTROL0 => CONTROL0,\r
+ CONTROL1 => CONTROL1,\r
+ CONTROL2 => CONTROL2,\r
+ CONTROL3 => CONTROL3,\r
+ CONTROL4 => CONTROL4);\r
+\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Tue Nov 25 10:12:59 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:chipscope_icon:1.06.a\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Structural\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a\r
+# END Select\r
+# BEGIN Parameters\r
+CSET component_name=icon0\r
+CSET constraint_type=embedded\r
+CSET enable_jtag_bufg=true\r
+CSET example_design=false\r
+CSET number_control_ports=5\r
+CSET use_ext_bscan=false\r
+CSET use_softbscan=false\r
+CSET use_unused_bscan=false\r
+CSET user_scan_chain=USER1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2013-10-13T14:12:40Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: e48a616b\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="icon0.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="icon0.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="icon0.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|icon0|icon0_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="icon0.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/icon0" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="icon0" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-25T11:13:50" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="21555AEE3F8341188AED62B4D711BFDF" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings>
+ <binding xil_pn:location="/icon0" xil_pn:name="icon0.ucf"/>
+ </bindings>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+The following files were generated for 'icon0' in directory\r
+D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_V2_ADC32board_SODA2\ipcore_dir\\r
+\r
+XCO file generator:\r
+ Generate an XCO file for compatibility with legacy flows.\r
+\r
+ * icon0.xco\r
+\r
+Creates an implementation netlist:\r
+ Creates an implementation netlist for the IP.\r
+\r
+ * icon0.ngc\r
+ * icon0.ucf\r
+ * icon0.vhd\r
+ * icon0.vho\r
+\r
+Creates an HDL instantiation template:\r
+ Creates an HDL instantiation template for the IP.\r
+\r
+ * icon0.vho\r
+\r
+IP Symbol Generator:\r
+ Generate an IP symbol based on the current project options'.\r
+\r
+ * icon0.asy\r
+\r
+SYM file generator:\r
+ Generate a SYM file for compatibility with legacy flows\r
+\r
+ * icon0.sym\r
+\r
+Generate ISE metadata:\r
+ Create a metadata file for use when including this core in ISE designs\r
+\r
+ * icon0_xmdf.tcl\r
+\r
+Generate ISE subproject:\r
+ Create an ISE subproject for use when including this core in ISE designs\r
+\r
+ * _xmsgs/pn_parser.xmsgs\r
+ * icon0.gise\r
+ * icon0.xise\r
+\r
+Deliver Readme:\r
+ Readme file for the IP.\r
+\r
+ * icon0_readme.txt\r
+\r
+Generate FLIST file:\r
+ Text file listing all of the output files produced when a customized core was\r
+ generated in the CORE Generator.\r
+\r
+ * icon0_flist.txt\r
+\r
+Please see the Xilinx CORE Generator online help for further details on\r
+generated files and how to use them.\r
+\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.5e
+$c`e
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--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 ila128
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[127:0]
+PINATTR Polarity IN
+\r
--- /dev/null
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+ <!-- For tool use only. Do not edit. -->\r
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+ <!-- allowing preservation of process status. -->\r
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+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8847945868067621726" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
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+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4772126188279592210" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
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+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
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\7f5{GHYqvLM
\ No newline at end of file
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: XILINX CORE Generator\r
+-- / / Filename : ila128.vhd\r
+-- /___/ /\ Timestamp : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: VHDL Synthesis Wrapper\r
+-------------------------------------------------------------------------------\r
+-- This wrapper is used to integrate with Project Navigator and PlanAhead\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+ENTITY ila128 IS\r
+ port (\r
+ CONTROL: inout std_logic_vector(35 downto 0);\r
+ CLK: in std_logic;\r
+ TRIG0: in std_logic_vector(127 downto 0));\r
+END ila128;\r
+\r
+ARCHITECTURE ila128_a OF ila128 IS\r
+BEGIN\r
+\r
+END ila128_a;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: Xilinx CORE Generator\r
+-- / / Filename : ila128.vho\r
+-- /___/ /\ Timestamp : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: ISE Instantiation template\r
+-- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a\r
+-------------------------------------------------------------------------------\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component ila128\r
+ PORT (\r
+ CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CLK : IN STD_LOGIC;\r
+ TRIG0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0));\r
+\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+\r
+your_instance_name : ila128\r
+ port map (\r
+ CONTROL => CONTROL,\r
+ CLK => CLK,\r
+ TRIG0 => TRIG0);\r
+\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 13.3\r
+# Date: Thu Jul 19 11:24:45 2012\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Structural\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a\r
+# END Select\r
+# BEGIN Parameters\r
+CSET check_bramcount=false\r
+CSET component_name=ila128\r
+CSET constraint_type=embedded\r
+CSET counter_width_1=Disabled\r
+CSET counter_width_10=Disabled\r
+CSET counter_width_11=Disabled\r
+CSET counter_width_12=Disabled\r
+CSET counter_width_13=Disabled\r
+CSET counter_width_14=Disabled\r
+CSET counter_width_15=Disabled\r
+CSET counter_width_16=Disabled\r
+CSET counter_width_2=Disabled\r
+CSET counter_width_3=Disabled\r
+CSET counter_width_4=Disabled\r
+CSET counter_width_5=Disabled\r
+CSET counter_width_6=Disabled\r
+CSET counter_width_7=Disabled\r
+CSET counter_width_8=Disabled\r
+CSET counter_width_9=Disabled\r
+CSET data_port_width=0\r
+CSET data_same_as_trigger=true\r
+CSET disable_save_keep=false\r
+CSET enable_storage_qualification=true\r
+CSET enable_trigger_output_port=false\r
+CSET example_design=false\r
+CSET exclude_from_data_storage_1=false\r
+CSET exclude_from_data_storage_10=false\r
+CSET exclude_from_data_storage_11=false\r
+CSET exclude_from_data_storage_12=false\r
+CSET exclude_from_data_storage_13=false\r
+CSET exclude_from_data_storage_14=false\r
+CSET exclude_from_data_storage_15=false\r
+CSET exclude_from_data_storage_16=false\r
+CSET exclude_from_data_storage_2=false\r
+CSET exclude_from_data_storage_3=false\r
+CSET exclude_from_data_storage_4=false\r
+CSET exclude_from_data_storage_5=false\r
+CSET exclude_from_data_storage_6=false\r
+CSET exclude_from_data_storage_7=false\r
+CSET exclude_from_data_storage_8=false\r
+CSET exclude_from_data_storage_9=false\r
+CSET match_type_1=basic_with_edges\r
+CSET match_type_10=basic_with_edges\r
+CSET match_type_11=basic_with_edges\r
+CSET match_type_12=basic_with_edges\r
+CSET match_type_13=basic_with_edges\r
+CSET match_type_14=basic_with_edges\r
+CSET match_type_15=basic_with_edges\r
+CSET match_type_16=basic_with_edges\r
+CSET match_type_2=basic_with_edges\r
+CSET match_type_3=basic_with_edges\r
+CSET match_type_4=basic_with_edges\r
+CSET match_type_5=basic_with_edges\r
+CSET match_type_6=basic_with_edges\r
+CSET match_type_7=basic_with_edges\r
+CSET match_type_8=basic_with_edges\r
+CSET match_type_9=basic_with_edges\r
+CSET match_units_1=1\r
+CSET match_units_10=1\r
+CSET match_units_11=1\r
+CSET match_units_12=1\r
+CSET match_units_13=1\r
+CSET match_units_14=1\r
+CSET match_units_15=1\r
+CSET match_units_16=1\r
+CSET match_units_2=1\r
+CSET match_units_3=1\r
+CSET match_units_4=1\r
+CSET match_units_5=1\r
+CSET match_units_6=1\r
+CSET match_units_7=1\r
+CSET match_units_8=1\r
+CSET match_units_9=1\r
+CSET max_sequence_levels=1\r
+CSET number_of_trigger_ports=1\r
+CSET sample_data_depth=1024\r
+CSET sample_on=Rising\r
+CSET trigger_port_width_1=128\r
+CSET trigger_port_width_10=8\r
+CSET trigger_port_width_11=8\r
+CSET trigger_port_width_12=8\r
+CSET trigger_port_width_13=8\r
+CSET trigger_port_width_14=8\r
+CSET trigger_port_width_15=8\r
+CSET trigger_port_width_16=8\r
+CSET trigger_port_width_2=8\r
+CSET trigger_port_width_3=8\r
+CSET trigger_port_width_4=8\r
+CSET trigger_port_width_5=8\r
+CSET trigger_port_width_6=8\r
+CSET trigger_port_width_7=8\r
+CSET trigger_port_width_8=8\r
+CSET trigger_port_width_9=8\r
+CSET use_rpms=true\r
+# END Parameters\r
+GENERATE\r
+# CRC: 6cc4b31f\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="ila128.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="ila128.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila128|ila128_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="ila128.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila128" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="ila128" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:26:50" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1DE8ABD5641346EB8572BE2AB4C22B42" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+The following files were generated for 'ila128' in directory\r
+D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\\r
+\r
+XCO file generator:\r
+ Generate an XCO file for compatibility with legacy flows.\r
+\r
+ * ila128.xco\r
+\r
+Creates an implementation netlist:\r
+ Creates an implementation netlist for the IP.\r
+\r
+ * ila128.cdc\r
+ * ila128.ngc\r
+ * ila128.vhd\r
+ * ila128.vho\r
+\r
+Creates an HDL instantiation template:\r
+ Creates an HDL instantiation template for the IP.\r
+\r
+ * ila128.vho\r
+\r
+IP Symbol Generator:\r
+ Generate an IP symbol based on the current project options'.\r
+\r
+ * ila128.asy\r
+\r
+SYM file generator:\r
+ Generate a SYM file for compatibility with legacy flows\r
+\r
+ * ila128.sym\r
+\r
+Generate ISE metadata:\r
+ Create a metadata file for use when including this core in ISE designs\r
+\r
+ * ila128_xmdf.tcl\r
+\r
+Generate ISE subproject:\r
+ Create an ISE subproject for use when including this core in ISE designs\r
+\r
+ * _xmsgs/pn_parser.xmsgs\r
+ * ila128.gise\r
+ * ila128.xise\r
+\r
+Deliver Readme:\r
+ Readme file for the IP.\r
+\r
+ * ila128_readme.txt\r
+\r
+Generate FLIST file:\r
+ Text file listing all of the output files produced when a customized core was\r
+ generated in the CORE Generator.\r
+\r
+ * ila128_flist.txt\r
+\r
+Please see the Xilinx CORE Generator online help for further details on\r
+generated files and how to use them.\r
+\r
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 ila36
+RECTANGLE Normal 32 32 288 704
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Wide 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName trig0[35:0]
+PINATTR Polarity IN
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ila36.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="ila36.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ila36.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="ila36.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1343040841" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343040841">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="9113925850006466910" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3435590971552100386" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3403158479962426638" xil_pn:start_ts="1383914820">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$80a
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\7fa<1>=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;02<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c:72?6=;3:1<v*<9b82a5=O0k<0D567;%041?743`3<6=44id694?=h;;21<75rb966>5<4290;w)=6c;3f4>N?j?1C4564$356>45<a0=1<75fe583>>i4:10;66sm85694?5=83:p(>7l:0g3?M>e>2B3455+267956=n1>0;66gj4;29?j5503:17pl74283>6<729q/?4m51d28L=d13A2346*=74827>o>?3:17dk;:188k64?2900qo6;2;297?6=8r.85n4>e19K<g0<@1237)<85;30?l?02900eh:50;9l77>=831vn5:>:180>5<7s-92o7?j0:J;f3=O0120(?9::018m<1=831bi94?::m06=<722wi4;=50;194?6|,:3h6<k?;I:a2>N?011/>:;5129j=2<722cn87>5;n11<?6=3th3:?4?:283>5}#;0i1=h>4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44o20;>5<<uk2==7>53;294~"41j0:i=5G8c48L=>?3-8<97?<;h;4>5<<al>1<75`33:94?=zj1<;6=4<:183
\7f!5>k3;n<6F7b79K<=><,;=>6<=4i8594?=nm=0;66a<2983>>{e0<l1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1=>5f9683>>ob<3:17b==8;29?xd?=l0;6>4?:1y'7<e=9l:0D5l9;I:;<>"5?<0:?6g67;29?lc32900c><7:188yg>2l3:1?7>50z&0=f<6m91C4o84H9:;?!40=3;87d78:188m`2=831d??650;9~f=3129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::
\7fa<1d=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;05<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c5;1?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3;6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm78`94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i;0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo9n3;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2g3290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;l;50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4e3<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=j;7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6c;>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1<1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88683>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?03:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:66:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa3=g=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<4o4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5;g?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>2o6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm79g94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd00o0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo961;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2?5290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;4=50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4=1<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=297>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6;5>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?0=1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl89983>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1>13:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:7n:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa3<e=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<5i4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5:a?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3m6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm7`294?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i80;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo991;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20d290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:950;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43`<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=<j7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6:3>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1;1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88383>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?;3:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:6;:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa334=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<:>4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c550?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj><>6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm77494?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0>>0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo998;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20>290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;;o50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`42g<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk==h7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb64f>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e??l1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl87183>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1093:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:9=:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::
\7fa325=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<;94?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c541?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>==6=4;:183
\7f!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm76:94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0?00;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo98a;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f21e290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:m50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43a<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk<i57>54;294~"41j0:i?5G8c48L=>?3-8<97<4i8594?=njk0;66gj4;29?j5503:17pl9b`83>1<729q/?4m51d08L=d13A2346*=7481?l?02900eol50;9ja1<722e8>54?::
\7fa2g4=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th=n<4?:583>5}#;0i1=h<4H9`5?M>?02.9;84=;h;4>5<<akh1<75fe583>>i4:10;66sm6df94?2=83:p(>7l:0g1?M>e>2B3455+26796>o>?3:17dlm:188m`2=831d??650;9~f31129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::
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\ No newline at end of file
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: XILINX CORE Generator\r
+-- / / Filename : ila36.vhd\r
+-- /___/ /\ Timestamp : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: VHDL Synthesis Wrapper\r
+-------------------------------------------------------------------------------\r
+-- This wrapper is used to integrate with Project Navigator and PlanAhead\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+ENTITY ila36 IS\r
+ port (\r
+ CONTROL: inout std_logic_vector(35 downto 0);\r
+ CLK: in std_logic;\r
+ TRIG0: in std_logic_vector(35 downto 0));\r
+END ila36;\r
+\r
+ARCHITECTURE ila36_a OF ila36 IS\r
+BEGIN\r
+\r
+END ila36_a;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: Xilinx CORE Generator\r
+-- / / Filename : ila36.vho\r
+-- /___/ /\ Timestamp : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: ISE Instantiation template\r
+-- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a\r
+-------------------------------------------------------------------------------\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component ila36\r
+ PORT (\r
+ CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ CLK : IN STD_LOGIC;\r
+ TRIG0 : IN STD_LOGIC_VECTOR(35 DOWNTO 0));\r
+\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+\r
+your_instance_name : ila36\r
+ port map (\r
+ CONTROL => CONTROL,\r
+ CLK => CLK,\r
+ TRIG0 => TRIG0);\r
+\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 13.3\r
+# Date: Thu Jul 19 11:21:13 2012\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:chipscope_ila:1.05.a\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Structural\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a\r
+# END Select\r
+# BEGIN Parameters\r
+CSET check_bramcount=false\r
+CSET component_name=ila36\r
+CSET constraint_type=embedded\r
+CSET counter_width_1=Disabled\r
+CSET counter_width_10=Disabled\r
+CSET counter_width_11=Disabled\r
+CSET counter_width_12=Disabled\r
+CSET counter_width_13=Disabled\r
+CSET counter_width_14=Disabled\r
+CSET counter_width_15=Disabled\r
+CSET counter_width_16=Disabled\r
+CSET counter_width_2=Disabled\r
+CSET counter_width_3=Disabled\r
+CSET counter_width_4=Disabled\r
+CSET counter_width_5=Disabled\r
+CSET counter_width_6=Disabled\r
+CSET counter_width_7=Disabled\r
+CSET counter_width_8=Disabled\r
+CSET counter_width_9=Disabled\r
+CSET data_port_width=0\r
+CSET data_same_as_trigger=true\r
+CSET disable_save_keep=false\r
+CSET enable_storage_qualification=true\r
+CSET enable_trigger_output_port=false\r
+CSET example_design=false\r
+CSET exclude_from_data_storage_1=false\r
+CSET exclude_from_data_storage_10=false\r
+CSET exclude_from_data_storage_11=false\r
+CSET exclude_from_data_storage_12=false\r
+CSET exclude_from_data_storage_13=false\r
+CSET exclude_from_data_storage_14=false\r
+CSET exclude_from_data_storage_15=false\r
+CSET exclude_from_data_storage_16=false\r
+CSET exclude_from_data_storage_2=false\r
+CSET exclude_from_data_storage_3=false\r
+CSET exclude_from_data_storage_4=false\r
+CSET exclude_from_data_storage_5=false\r
+CSET exclude_from_data_storage_6=false\r
+CSET exclude_from_data_storage_7=false\r
+CSET exclude_from_data_storage_8=false\r
+CSET exclude_from_data_storage_9=false\r
+CSET match_type_1=basic_with_edges\r
+CSET match_type_10=basic_with_edges\r
+CSET match_type_11=basic_with_edges\r
+CSET match_type_12=basic_with_edges\r
+CSET match_type_13=basic_with_edges\r
+CSET match_type_14=basic_with_edges\r
+CSET match_type_15=basic_with_edges\r
+CSET match_type_16=basic_with_edges\r
+CSET match_type_2=basic_with_edges\r
+CSET match_type_3=basic_with_edges\r
+CSET match_type_4=basic_with_edges\r
+CSET match_type_5=basic_with_edges\r
+CSET match_type_6=basic_with_edges\r
+CSET match_type_7=basic_with_edges\r
+CSET match_type_8=basic_with_edges\r
+CSET match_type_9=basic_with_edges\r
+CSET match_units_1=1\r
+CSET match_units_10=1\r
+CSET match_units_11=1\r
+CSET match_units_12=1\r
+CSET match_units_13=1\r
+CSET match_units_14=1\r
+CSET match_units_15=1\r
+CSET match_units_16=1\r
+CSET match_units_2=1\r
+CSET match_units_3=1\r
+CSET match_units_4=1\r
+CSET match_units_5=1\r
+CSET match_units_6=1\r
+CSET match_units_7=1\r
+CSET match_units_8=1\r
+CSET match_units_9=1\r
+CSET max_sequence_levels=1\r
+CSET number_of_trigger_ports=1\r
+CSET sample_data_depth=1024\r
+CSET sample_on=Rising\r
+CSET trigger_port_width_1=36\r
+CSET trigger_port_width_10=8\r
+CSET trigger_port_width_11=8\r
+CSET trigger_port_width_12=8\r
+CSET trigger_port_width_13=8\r
+CSET trigger_port_width_14=8\r
+CSET trigger_port_width_15=8\r
+CSET trigger_port_width_16=8\r
+CSET trigger_port_width_2=8\r
+CSET trigger_port_width_3=8\r
+CSET trigger_port_width_4=8\r
+CSET trigger_port_width_5=8\r
+CSET trigger_port_width_6=8\r
+CSET trigger_port_width_7=8\r
+CSET trigger_port_width_8=8\r
+CSET trigger_port_width_9=8\r
+CSET use_rpms=true\r
+# END Parameters\r
+GENERATE\r
+# CRC: d7d162a4\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="ila36.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="ila36.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila36|ila36_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="ila36.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="ila36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:23:19" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BE66BF3D7764410AB7EAAD8952DDFFD8" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+The following files were generated for 'ila36' in directory\r
+D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\\r
+\r
+XCO file generator:\r
+ Generate an XCO file for compatibility with legacy flows.\r
+\r
+ * ila36.xco\r
+\r
+Creates an implementation netlist:\r
+ Creates an implementation netlist for the IP.\r
+\r
+ * ila36.cdc\r
+ * ila36.ngc\r
+ * ila36.vhd\r
+ * ila36.vho\r
+\r
+Creates an HDL instantiation template:\r
+ Creates an HDL instantiation template for the IP.\r
+\r
+ * ila36.vho\r
+\r
+IP Symbol Generator:\r
+ Generate an IP symbol based on the current project options'.\r
+\r
+ * ila36.asy\r
+\r
+SYM file generator:\r
+ Generate a SYM file for compatibility with legacy flows\r
+\r
+ * ila36.sym\r
+\r
+Generate ISE metadata:\r
+ Create a metadata file for use when including this core in ISE designs\r
+\r
+ * ila36_xmdf.tcl\r
+\r
+Generate ISE subproject:\r
+ Create an ISE subproject for use when including this core in ISE designs\r
+\r
+ * _xmsgs/pn_parser.xmsgs\r
+ * ila36.gise\r
+ * ila36.xise\r
+\r
+Deliver Readme:\r
+ Readme file for the IP.\r
+\r
+ * ila36_readme.txt\r
+\r
+Generate FLIST file:\r
+ Text file listing all of the output files produced when a customized core was\r
+ generated in the CORE Generator.\r
+\r
+ * ila36_flist.txt\r
+\r
+Please see the Xilinx CORE Generator online help for further details on\r
+generated files and how to use them.\r
+\r
--- /dev/null
+------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ / \r
+-- /___/ \ / Vendor: Xilinx \r
+-- \ \ \/ Version : 1.12\r
+-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard \r
+-- / / Filename : mgt_usrclk_source_mmcm.vhd\r
+-- /___/ /\ \r
+-- \ \ / \ \r
+-- \___\/\___\ \r
+--\r
+--\r
+-- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)\r
+-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard\r
+--
+--
+-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+use ieee.std_logic_unsigned.all;\r
+library UNISIM;\r
+use UNISIM.VCOMPONENTS.ALL;\r
+\r
+--***********************************Entity Declaration*******************************\r
+entity MGT_USRCLK_SOURCE_MMCM is\r
+generic\r
+(\r
+ MULT : real := 2.0;\r
+ DIVIDE : integer := 2; \r
+ CLK_PERIOD : real := 6.4; \r
+ OUT0_DIVIDE : real := 2.0;\r
+ OUT1_DIVIDE : integer := 2;\r
+ OUT2_DIVIDE : integer := 2;\r
+ OUT3_DIVIDE : integer := 2\r
+);\r
+port\r
+(\r
+ CLKFBOUT : out std_logic; \r
+ CLK0_OUT : out std_logic;\r
+ CLK1_OUT : out std_logic;\r
+ CLK2_OUT : out std_logic;\r
+ CLK3_OUT : out std_logic;\r
+ CLK_IN : in std_logic;\r
+ MMCM_LOCKED_OUT : out std_logic;\r
+ MMCM_RESET_IN : in std_logic\r
+);\r
+\r
+\r
+end MGT_USRCLK_SOURCE_MMCM;\r
+\r
+architecture RTL of MGT_USRCLK_SOURCE_MMCM is\r
+--*********************************Wire Declarations**********************************\r
+\r
+ signal tied_to_ground_vec_i : std_logic_vector(15 downto 0);\r
+ signal tied_to_ground_i : std_logic;\r
+ signal tied_to_vcc_i : std_logic;\r
+ signal clkout0_i : std_logic;\r
+ signal clkout1_i : std_logic;\r
+ signal clkout2_i : std_logic;\r
+ signal clkout3_i : std_logic;\r
+ signal clkfbout_i : std_logic;\r
+ signal clkfbout_buf : std_logic;\r
+\r
+begin\r
+\r
+--*********************************** Beginning of Code *******************************\r
+\r
+ -- Static signal Assigments \r
+ tied_to_ground_i <= '0';\r
+ tied_to_ground_vec_i <= (others=>'0');\r
+ tied_to_vcc_i <= '1';\r
+\r
+ -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback\r
+ -- for improved jitter performance, and to avoid consuming an additional BUFG\r
+ mmcm_adv_i : MMCM_ADV\r
+ generic map\r
+ (\r
+ COMPENSATION => "ZHOLD",\r
+ CLKFBOUT_MULT_F => MULT,\r
+ DIVCLK_DIVIDE => DIVIDE,\r
+ CLKFBOUT_PHASE => 0.0,\r
+ CLKIN1_PERIOD => CLK_PERIOD,\r
+ CLKIN2_PERIOD => 10.0, -- Not used\r
+ CLKOUT0_DIVIDE_F => OUT0_DIVIDE,\r
+ CLKOUT0_PHASE => 0.0,\r
+ CLKOUT1_DIVIDE => OUT1_DIVIDE,\r
+ CLKOUT1_PHASE => 0.0,\r
+ CLKOUT2_DIVIDE => OUT2_DIVIDE,\r
+ CLKOUT2_PHASE => 0.0,\r
+ CLKOUT3_DIVIDE => OUT3_DIVIDE,\r
+ CLKOUT3_PHASE => 0.0,\r
+ CLOCK_HOLD => TRUE \r
+ )\r
+ port map\r
+ (\r
+ CLKIN1 => CLK_IN,\r
+ CLKIN2 => tied_to_ground_i,\r
+ CLKINSEL => tied_to_vcc_i,\r
+ CLKFBIN => clkfbout_buf,\r
+ CLKOUT0 => clkout0_i,\r
+ CLKOUT0B => open,\r
+ CLKOUT1 => clkout1_i,\r
+ CLKOUT1B => open,\r
+ CLKOUT2 => clkout2_i,\r
+ CLKOUT2B => open,\r
+ CLKOUT3 => clkout3_i,\r
+ CLKOUT3B => open,\r
+ CLKOUT4 => open,\r
+ CLKOUT5 => open,\r
+ CLKOUT6 => open,\r
+ CLKFBOUT => clkfbout_i,\r
+ CLKFBOUTB => open,\r
+ CLKFBSTOPPED => open,\r
+ CLKINSTOPPED => open,\r
+ DO => open,\r
+ DRDY => open,\r
+ DADDR => tied_to_ground_vec_i(6 downto 0),\r
+ DCLK => tied_to_ground_i,\r
+ DEN => tied_to_ground_i,\r
+ DI => tied_to_ground_vec_i(15 downto 0),\r
+ DWE => tied_to_ground_i,\r
+ LOCKED => MMCM_LOCKED_OUT,\r
+ PSCLK => tied_to_ground_i,\r
+ PSEN => tied_to_ground_i, \r
+ PSINCDEC => tied_to_ground_i, \r
+ PSDONE => open, \r
+ PWRDWN => tied_to_ground_i,\r
+ RST => MMCM_RESET_IN \r
+ );\r
+ \r
+ clkfb_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => clkfbout_buf, \r
+ I => clkfbout_i\r
+ ); \r
+ CLKFBOUT <= clkfbout_buf;\r
+ \r
+ clkout0_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK0_OUT, \r
+ I => clkout0_i\r
+ ); \r
+\r
+\r
+ clkout1_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK1_OUT,\r
+ I => clkout1_i\r
+ );\r
+ \r
+ \r
+ clkout2_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK2_OUT, \r
+ I => clkout2_i\r
+ ); \r
+\r
+\r
+ clkout3_bufg_i : BUFG \r
+ port map\r
+ (\r
+ O => CLK3_OUT,\r
+ I => clkout3_i\r
+ ); \r
+ \r
+end RTL;\r
+ \r
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 sync_fifo_512x41
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[40:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[40:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_512x41.xise"/>\r
+\r
+ <files xmlns="http://www.xilinx.com/XMLSchema">\r
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_512x41.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_512x41.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_512x41.vho" xil_pn:origination="imported"/>\r
+ </files>\r
+\r
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">\r
+ <transform xil_pn:end_ts="1411385153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411385153">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="517927155140597448" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1475527042133781192" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2025323555865192840" xil_pn:start_ts="1418036842">\r
+ <status xil_pn:value="SuccessfullyRun"/>\r
+ <status xil_pn:value="ReadyToRun"/>\r
+ </transform>\r
+ </transforms>\r
+\r
+</generated_project>\r
--- /dev/null
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$5g;
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\7f9o>:181
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\7f96?:181
\7f[2?827?<94>2c9~w1>62909wS:71:?741<6:j1v
\7f96=:181
\7f[2?:27?<94>2e9~w1>42909wS:73:?741<6:l1v
\7f96;:181
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\7fm1<2=838pD9<=;|l6=0<72;qC8?<4}o7:2?6=:rB?>?5rn4;4>5<5sA>9>6sa58:94?4|@=897p`:9883>7}O<;80qc;6a;296~N3:;1vb87m:181
\7fM25:2we94m50;0xL1453td>5i4?:3yK074<ug?2i7>52zJ767=zf<3m6=4={I616>{i=h:1<7<tH501?xh2i80;6?uG4308yk3f:3:1>vF;239~j0g42909wE:=2:
\7fm1d2=838pD9<=;|l6e0<72;qC8?<4}o7b2?6=:rB?>?5rn4c4>5<5sA>9>6sa5`:94?4|@=897p`:a883>7}O<;80qc;na;296~N3:;1vb8om:181
\7fM25:2we9lm50;0xL1453td>mi4?:3yK074<ug?ji7>52zJ767=zf<km6=4={I616>{i=k:1<7<tH501?xh2j80;6?uG4308yk3e:3:1>vF;239~j0d42909wE:=2:
\7fm1g2=838pD9<=;|l6f0<72;qC8?<4}o7a2?6=:rB?>?5rn4`4>5<5sA>9>6sa5c:94?4|@=897p`:b883>7}O<;80qc;ma;296~N3:;1vb8lm:181
\7fM25:2we9om50;0xL1453td>ni4?:0yK074<ug?ii7>51zJ767=zf<hm6=4>{I616>{i=j:1<7?tH501?xh2k80;6<uG4308yk3d:3:1=vF;239~j0e42909wE:=2:
\7fm1f2=839pD9<=;|l6g0<72:qC8?<4}o7`2?6=:rB?>?5rn4a4>5<5sA>9>6sa5b:94?4|@=897p`:c883>7}O<;80qc;la;296~N3:;1vb8mm:181
\7fM25:2we9nm50;0xL1453td>oi4?:3yK074<ug?hi7>52zJ767=zf<im6=4={I616>{i=m:1<7<tH501?xh2l80;6?uG4308yk3c:3:1>vF;239~j0b42909wE:=2:
\7fm1a2=838pD9<=;|l6`0<72;qC8?<4}o7g2?6=:rB?>?5rn4f4>5<5sA>9>6sa5e:94?4|@=897p`:d883>7}O<;80qc;ka;296~N3:;1vb8jm:181
\7fM25:2we9im50;0xL1453td>hi4?:3yK074<ug?oi7>52zJ767=zf<nm6=4={I616>{i=l:1<7<tH501?xh2m80;6?uG4308yk3b:3:1>vF;239~j0c42909wE:=2:
\7fm1`2=838pD9<=;|l6a0<72;qC8?<4}o7f2?6=:rB?>?5rn4g4>5<5sA>9>6sa5d:94?4|@=897p`:e883>7}O<;80qc;ja;296~N3:;1vb8km:181
\7fM25:2we9hm50;0xL1453td>ii4?:3yK074<ug?ni7>52zJ767=zf<om6=4={I616>{i=o:1<7<tH501?xh2n80;6?uG4308yk3a:3:1>vF;239~j0`42909wE:=2:
\7fm1c2=838pD9<=;|l6b0<72;qC8?<4}o7e2?6=:rB?>?5rn4d4>5<5sA>9>6sa5g:94?4|@=897p`:f883>7}O<;80qc;ia;296~N3:;1vb8hm:181
\7fM25:2we9km50;0xL1453td>ji4?:3yK074<ug?mi7>52zJ767=zf<lm6=4={I616>{i>9:1<7<tH501?xh1880;6<uG4308yk07:3:1=vF;239~j364290:wE:=2:
\7fm252=83;pD9<=;|l540<728qC8?<4}o432?6=9rB?>?5rn724>5<6sA>9>6sa61:94?7|@=897p`90883>4}O<;80qc8?a;295~N3:;1vb;>m:182
\7fM25:2we:=m50;3xL1453td=<i4?:0yK074<ug<;i7>51zJ767=zf?:m6=4>{I616>{i>8:1<7?tH501?xh1980;6<uG4308yk06:3:1=vF;239~j374290:wE:=2:
\7fm242=83;pD9<=;|l550<728qC8?<4}o422?6=9rB?>?5rn734>5<6sA>9>6sa60:94?7|@=897p`91883>4}O<;80qc8>a;295~N3:;1vb;?m:182
\7fM25:2we:<m50;3xL1453td==i4?:0yK074<ug<:i7>51zJ767=zf?;m6=4>{I616>{i>;:1<7?tH501?xh1:80;6<uG4308yk05:3:1=vF;239~j344290:wE:=2:
\7fm272=83;pD9<=;|l560<728qC8?<4}o412?6=9rB?>?5rn704>5<6sA>9>6sa63:94?7|@=897p`92883>4}O<;80qc8=a;295~N3:;1vb;<m:182
\7fM25:2we:?m50;3xL1453td=>i4?:0yK074<ug<9i7>51zJ767=zf?8m6=4>{I616>{i>::1<7?tH501?xh1;80;6<uG4308yk04:3:1=vF;239~j354290:wE:=2:
\7fm262=83;pD9<=;|l570<728qC8?<4}o402?6=9rB?>?5rn714>5<6sA>9>6sa62:94?7|@=897p`93883>4}O<;80qc8<a;295~N3:;1vb;=m:182
\7fM25:2we:>m50;3xL1453td=?i4?:0yK074<ug<8i7>51zJ767=zf?9m6=4>{I616>{i>=:1<7?tH501?xh1<80;6<uG4308yk03:3:1=vF;239~j324290:wE:=2:
\7fm212=83;pD9<=;|l500<728qC8?<4}o472?6=9rB?>?5rn764>5<6sA>9>6sa65:94?7|@=897p`94883>4}O<;80qc8;a;295~N3:;1vb;:m:182
\7fM25:2we:9m50;3xL1453td=8i4?:0yK074<ug<?i7>51zJ767=zf?>m6=4>{I616>{i><:1<7?tH501?xh1=80;6<uG4308yk02:3:1=vF;239~j334290:wE:=2:
\7fm202=83;pD9<=;|l510<728qC8?<4}o462?6=9rB?>?5rn774>5<6sA>9>6sa64:94?7|@=897p`95883>4}O<;80qc8:a;295~N3:;1vb;;m:182
\7fM25:2we:8m50;0xL1453td88h4?:0yK074<ug9?j7>51zJ767=zutwKLNu82g84e5ge<;>vLMLt0|BCT~{GH
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file sync_fifo_512x41.vhd when simulating\r
+-- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY sync_fifo_512x41 IS\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END sync_fifo_512x41;\r
+\r
+ARCHITECTURE sync_fifo_512x41_a OF sync_fifo_512x41 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_sync_fifo_512x41\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_sync_fifo_512x41 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 1,\r
+ c_count_type => 0,\r
+ c_data_count_width => 9,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 41,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 41,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 0,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 1,\r
+ c_preload_regs => 0,\r
+ c_prim_fifo_type => "512x72",\r
+ c_prog_empty_thresh_assert_val => 2,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 3,\r
+ c_prog_empty_type => 0,\r
+ c_prog_empty_type_axis => 0,\r
+ c_prog_empty_type_rach => 0,\r
+ c_prog_empty_type_rdch => 0,\r
+ c_prog_empty_type_wach => 0,\r
+ c_prog_empty_type_wdch => 0,\r
+ c_prog_empty_type_wrch => 0,\r
+ c_prog_full_thresh_assert_val => 510,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 509,\r
+ c_prog_full_type => 0,\r
+ c_prog_full_type_axis => 0,\r
+ c_prog_full_type_rach => 0,\r
+ c_prog_full_type_rdch => 0,\r
+ c_prog_full_type_wach => 0,\r
+ c_prog_full_type_wdch => 0,\r
+ c_prog_full_type_wrch => 0,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 9,\r
+ c_rd_depth => 512,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 9,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_synchronizer_stage => 2,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 0,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 9,\r
+ c_wr_depth => 512,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 9,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_sync_fifo_512x41\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END sync_fifo_512x41_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
+-- --\r
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
+-- memory queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+-- master_aclk\r
+-- slave_aclk\r
+-- slave_aresetn\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT sync_fifo_512x41\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : sync_fifo_512x41\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file sync_fifo_512x41.vhd when simulating\r
+-- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Fri Sep 19 14:11:57 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=sync_fifo_512x41\r
+CSET data_count=false\r
+CSET data_count_width=9\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=2\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=3\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Common_Clock_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=510\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=509\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=41\r
+CSET input_depth=512\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=41\r
+CSET output_depth=512\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=Standard_FIFO\r
+CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
+CSET programmable_full_type=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=9\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET synchronization_stages=2\r
+CSET synchronization_stages_axi=2\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=false\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=9\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-11-19T12:39:56Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: 2a3474ef\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="sync_fifo_512x41.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="sync_fifo_512x41.vhd" xil_pn:type="FILE_VHDL">
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+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_512x41|sync_fifo_512x41_a" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_512x41" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-19T16:13:50" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
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+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
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+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
+\r
+ <!-- -->\r
+\r
+ <!-- For tool use only. Do not edit. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- ProjectNavigator created generated project file. -->\r
+\r
+ <!-- For use in tracking generated file and other information -->\r
+\r
+ <!-- allowing preservation of process status. -->\r
+\r
+ <!-- -->\r
+\r
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
+\r
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>\r
+\r
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_FWFT_512x36.xise"/>\r
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+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_FWFT_512x36.asy" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_FWFT_512x36.sym" xil_pn:origination="imported"/>\r
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_FWFT_512x36.vho" xil_pn:origination="imported"/>\r
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+ </transform>\r
+ <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1600854814650439684" xil_pn:start_ts="1418036842">\r
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+\r
+</generated_project>\r
--- /dev/null
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating\r
+-- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY sync_fifo_FWFT_512x36 IS\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END sync_fifo_FWFT_512x36;\r
+\r
+ARCHITECTURE sync_fifo_FWFT_512x36_a OF sync_fifo_FWFT_512x36 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_sync_fifo_FWFT_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_sync_fifo_FWFT_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 1,\r
+ c_count_type => 0,\r
+ c_data_count_width => 10,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 36,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 36,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 0,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 0,\r
+ c_preload_regs => 1,\r
+ c_prim_fifo_type => "512x36",\r
+ c_prog_empty_thresh_assert_val => 4,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 5,\r
+ c_prog_empty_type => 0,\r
+ c_prog_empty_type_axis => 0,\r
+ c_prog_empty_type_rach => 0,\r
+ c_prog_empty_type_rdch => 0,\r
+ c_prog_empty_type_wach => 0,\r
+ c_prog_empty_type_wdch => 0,\r
+ c_prog_empty_type_wrch => 0,\r
+ c_prog_full_thresh_assert_val => 511,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 510,\r
+ c_prog_full_type => 0,\r
+ c_prog_full_type_axis => 0,\r
+ c_prog_full_type_rach => 0,\r
+ c_prog_full_type_rdch => 0,\r
+ c_prog_full_type_wach => 0,\r
+ c_prog_full_type_wdch => 0,\r
+ c_prog_full_type_wrch => 0,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 10,\r
+ c_rd_depth => 512,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 9,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_synchronizer_stage => 2,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 1,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 10,\r
+ c_wr_depth => 512,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 9,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_sync_fifo_FWFT_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END sync_fifo_FWFT_512x36_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
+-- --\r
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
+-- memory queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+-- master_aclk\r
+-- slave_aclk\r
+-- slave_aresetn\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT sync_fifo_FWFT_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : sync_fifo_FWFT_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating\r
+-- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Fri Sep 19 14:17:44 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=sync_fifo_FWFT_512x36\r
+CSET data_count=false\r
+CSET data_count_width=10\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=4\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=5\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Common_Clock_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=511\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=510\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=36\r
+CSET input_depth=512\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=36\r
+CSET output_depth=512\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=First_Word_Fall_Through\r
+CSET programmable_empty_type=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
+CSET programmable_full_type=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=10\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET synchronization_stages=2\r
+CSET synchronization_stages_axi=2\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=true\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=10\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-11-19T12:39:56Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: c1caed69\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="sync_fifo_FWFT_512x36.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="sync_fifo_FWFT_512x36.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_FWFT_512x36|sync_fifo_FWFT_512x36_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_FWFT_512x36.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-19T16:19:35" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="46168A5A1EB549528AEB437BD4FABD6F" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 sync_fifo_progfull364_progempty128_512x36
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
+PIN 0 112 LEFT 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 464 32 464
+PIN 0 464 LEFT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 0 528 32 528
+PIN 0 528 LEFT 36
+PINATTR PinName prog_full
+PINATTR Polarity OUT
+LINE Wide 832 272 800 272
+PIN 832 272 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 832 304 800 304
+PIN 832 304 RIGHT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 832 496 800 496
+PIN 832 496 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Normal 832 560 800 560
+PIN 832 560 RIGHT 36
+PINATTR PinName prog_empty
+PINATTR Polarity OUT
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>\r
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">\r
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+ <!-- -->\r
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+ <!-- For tool use only. Do not edit. -->\r
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+ <!-- -->\r
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+ <!-- allowing preservation of process status. -->\r
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+ <!-- -->\r
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+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->\r
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--- /dev/null
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\7f>k50;0xZ6c<5=896;=4}r1g>5<5sW9o70:=2;41?xu4k3:1>vP<c:?767<1n2wx?o4?:3y]7g=:<;81:h5rs2c94?4|V:k019<=:7f8yv5>2909wS=6;<616?0d3ty847>52z\0<>;3:;0=n6s|d583>7}Yl=168?<51148yvb52909wSj=;<616?gc3tyo=7>52z\g5>;3:;0jn6s|d183>7}Yl9168?<5a`9~wf`=838pRnh4=501>d?<uzin6=4={_af?825:3k37p}lc;296~Xdk27?>?4n7:
\7fpgg<72;qUoo524309f3=z{jk1<7<t^bc891452k?0q~m6:181
\7f[e>34>9>7??4:
\7fpg=<72;qUo5524309f1=z{j=1<7<t^b5891452k90q~m9:181
\7f[e134>9>7l=;|q`1?6=:rTh963;238a5>{tk=0;6?uQc59>074=j91v
\7fn=50;0xZf5<5=896lh4}ra2>5<5sWi:70:=2;cf?xud83:1>vPl0:?767<f>2wxnk4?:3y]fc=:<;81===4}r`f>5<5sWhn70:=2;;`?xuel3:1>vPmd:?767<>i2wxnn4?:3y]ff=:<;81545rsc`94?4|Vkh019<=:8:8yvdf2909wSln;<616??03tyi57>52z\a=>;3:;02:6s|b983>7}Yj1168?<5a49~wad=838pRil4=501>d2<uznj6=4={_fb?825:3;;=6s|d883>7}Yl0168?<5a29~wa>=838pRi64=501>d4<uzn<6=4={_f4?825:3k:7p}k6;296~Xc>27?>?4n0:
\7fp`0<72;qUh8524309=c=z{jn1<7<t^bf8914520o0q~m=:181
\7f[e534>9>77k;|qa3?6=:rTi;63;238:1>{t:8o1<7=t^33f?825:38:j63;238165=z{<n1<7<t^4f891452==0q~;m:181
\7f[3e34>9>7::;|q6e?6=:rT>m63;23870>{t=00;6?uQ589>074=<:1v
\7f8650;0xZ0><5=8968>4}r74>5<5sW?<70:=2;6e?xu2>3:1>vP:6:?767<3m2wx984?:3y]10=:<;818i5rs4694?4|V<>019<=:5a8yv1b2909wS9j;<616?>13ty:;o4?:3y]52d<5=896<9j;|q;0?6=:rT3863;238;7>{t9>n1<7<t^05g?825:3;<o6s|16194?4|V8=870:=2;304>{t9>;1<7<t^052?825:3;9<6s|16294?4|V8=;70:=2;32a>{t9?l1<7<t^04e?825:3;:h6s|17g94?4|V8<n70:=2;32g>{t9?n1<7<t^04g?825:3;:n6s|17`94?4|V8<i70:=2;32e>{t9?k1<7<t^04b?825:3;956s|17;94?4|V8<270:=2;31<>{t9?21<7<t^04;?825:3;9i6s|17594?4|V8<<70:=2;313>{t9?<1<7<t^045?825:3;9:6s|17794?4|V8<>70:=2;311>{t9?>1<7<t^047?825:3;986s|17194?4|V8<870:=2;317>{t9?81<7<t^041?825:3;9>6s|17294?4|V8<;70:=2;315>{t9<l1<7<t^07e?825:3;:56s|14g94?4|V8?n70:=2;31`>{t9<n1<7<t^07g?825:3;;i6s|14a94?4|V8?h70:=2;33g>{t9<h1<7<t^07a?825:3;;n6s|14c94?4|V8?j70:=2;33e>{t9<31<7<t^07:?825:3;;56s|14:94?4|V8?370:=2;33<>{t9<=1<7<t^074?825:3;:;6s|16c94?4|V8=j70:=2;322>{t9>31<7<t^05:?825:3;9n6s|16:94?4|V8=370:=2;321>{t9>=1<7<t^054?825:3;:86s|16494?4|V8==70:=2;327>{t9>?1<7<t^056?825:3;:>6s|16694?4|V8=?70:=2;325>{t9?i1<7<t^04`?825:3;:<6s|17394?4|V8<:70:=2;33b>{t9<<1<7<t^075?825:3;;;6s|9383>16|5:kn6<6m;_;1?[45?2T9<i5Q21`8Z76f3W8;56P=099]651<V;:=7S<?5:\141=:<;81><;4=501>1d<5=8969o4=501>1?<5=896964=501>14<5=896;o4=501>3?<5=896;64=501>31<5=896;?4=501>6?234>9>7=64:?767<59?168?<5233891452;897S?<1:\27f=Y9==0R<:i;_364>X6=81U=8<4^070?[72<2T:985Q1208Z4543W;886P>349]560<V89<7S?<8:\27<=Y9:k0R<=m;_30`>X6;l1U=>h4^063?[7392T:8?5Q1518Z4233W;?96P>479]51><V8>27S?;a:\20g=Y9=i0R<:j;|
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\7fa61c=8391<7>t$310>6gd3A9jh6F<919j32<722c:i>4?::m2b2<722wi>9j50;194?6|,;986>ol;I1b`>N4191b;:4?::k2a6<722e:j:4?::
\7fa66e=83>1<7>t$310>4cc3A9jh6F<919j32<722c287>5;h011?6=3f;m;7>5;|`10f<72:0;6=u+22197de<@:ko7E=60:k43?6=3`;n?7>5;n3e3?6=3th9?o4?:583>5}#::91=hj4H2cg?M5>82c<;7>5;h;7>5<<a;8>6=44o0d4>5<<uk8?n7>53;294~"5;:08mn5G3`f8L6?73`=<6=44i0g0>5<<g8l<6=44}c00e?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb36b>5<4290;w)<<3;1bg>N4im1C?4>4i6594?=n9l91<75`1g594?=zj;926=4;:183
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\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating\r
+-- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY sync_fifo_progfull364_progempty128_512x36 IS\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END sync_fifo_progfull364_progempty128_512x36;\r
+\r
+ARCHITECTURE sync_fifo_progfull364_progempty128_512x36_a OF sync_fifo_progfull364_progempty128_512x36 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_sync_fifo_progfull364_progempty128_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_sync_fifo_progfull364_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 1,\r
+ c_count_type => 0,\r
+ c_data_count_width => 9,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 36,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 36,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 0,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 1,\r
+ c_preload_regs => 0,\r
+ c_prim_fifo_type => "512x36",\r
+ c_prog_empty_thresh_assert_val => 128,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 129,\r
+ c_prog_empty_type => 1,\r
+ c_prog_empty_type_axis => 0,\r
+ c_prog_empty_type_rach => 0,\r
+ c_prog_empty_type_rdch => 0,\r
+ c_prog_empty_type_wach => 0,\r
+ c_prog_empty_type_wdch => 0,\r
+ c_prog_empty_type_wrch => 0,\r
+ c_prog_full_thresh_assert_val => 364,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 363,\r
+ c_prog_full_type => 1,\r
+ c_prog_full_type_axis => 0,\r
+ c_prog_full_type_rach => 0,\r
+ c_prog_full_type_rdch => 0,\r
+ c_prog_full_type_wach => 0,\r
+ c_prog_full_type_wdch => 0,\r
+ c_prog_full_type_wrch => 0,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 9,\r
+ c_rd_depth => 512,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 9,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_synchronizer_stage => 2,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 0,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 9,\r
+ c_wr_depth => 512,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 9,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_sync_fifo_progfull364_progempty128_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty,\r
+ prog_full => prog_full,\r
+ prog_empty => prog_empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END sync_fifo_progfull364_progempty128_512x36_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
+-- --\r
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
+-- memory queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+-- master_aclk\r
+-- slave_aclk\r
+-- slave_aresetn\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT sync_fifo_progfull364_progempty128_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : sync_fifo_progfull364_progempty128_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty,\r
+ prog_full => prog_full,\r
+ prog_empty => prog_empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating\r
+-- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Mon Oct 20 06:54:50 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=sync_fifo_progfull364_progempty128_512x36\r
+CSET data_count=false\r
+CSET data_count_width=9\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=128\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=129\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Common_Clock_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=364\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=363\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=36\r
+CSET input_depth=512\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=36\r
+CSET output_depth=512\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=Standard_FIFO\r
+CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant\r
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant\r
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=9\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET synchronization_stages=2\r
+CSET synchronization_stages_axi=2\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=false\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=9\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-11-19T12:39:56Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: 5a086950\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
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--- /dev/null
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+SymbolType BLOCK
+TEXT 32 32 LEFT 4 sync_fifo_progfull504_progempty128_512x36
+RECTANGLE Normal 32 32 800 4064
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk
+PINATTR Polarity IN
+LINE Normal 0 112 32 112
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+LINE Normal 0 464 32 464
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+LINE Normal 832 496 800 496
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+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Normal 832 560 800 560
+PIN 832 560 RIGHT 36
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+PINATTR Polarity OUT
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--- /dev/null
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\7fM5>82we:h?50;3xL6?73td=i?4?:0yK7<6<ug<n?7>51zJ0=5=zf?o?6=4>{I1:4>{i>l?1<7?tH2;3?xh1m?0;6<uG3828yk0b?3:1=vF<919~j3c?290:wE=60:
\7fm2`?=83;pD>7?;|l5ad<728qC?4>4}o4ff?6=9rB85=5rn7g`>5<6sA92<6sa6df94?7|@:3;7p`9ed83>4}O;0:0qc8jf;295~N4191vb;h?:182
\7fM5>82we:k?50;3xL6?73td=j?4?:0yK7<6<ug<m?7>51zJ0=5=zf?l?6=4>{I1:4>{i>o?1<7?tH2;3?xh1n?0;6<uG3828yk0a?3:1=vF<919~j3`?290:wE=60:
\7fm2c?=83;pD>7?;|l5bd<728qC?4>4}o4ef?6=9rB85=5rn7d`>5<6sA92<6sa6gf94?7|@:3;7p`9fd83>4}O;0:0qc8if;295~N4191vb:>?:182
\7fM5>82we;=?50;3xL6?73td<<?4?:0yK7<6<ug=;?7>51zJ0=5=zf>:?6=4>{I1:4>{i?9?1<7?tH2;3?xh08?0;6<uG3828yk17?3:1=vF<919~j26?290:wE=60:
\7fm35?=83;pD>7?;|l44d<728qC?4>4}o53f?6=9rB85=5rn62`>5<6sA92<6sa71f94?7|@:3;7p`80d83>4}O;0:0qc9?f;295~N4191vb:??:182
\7fM5>82we;<?50;3xL6?73td<=?4?:0yK7<6<ug=:?7>51zJ0=5=zf>;?6=4>{I1:4>{i?8?1<7?tH2;3?xh09?0;6<uG3828yk16?3:1=vF<919~j27?290:wE=60:
\7fm34?=83;pD>7?;|l45d<728qC?4>4}o52f?6=9rB85=5rn63`>5<6sA92<6sa70f94?7|@:3;7p`81d83>4}O;0:0qc9>f;295~N4191vb:<?:182
\7fM5>82we;??50;3xL6?73td<>?4?:0yK7<6<ug=9?7>51zJ0=5=zf>8?6=4>{I1:4>{i?;?1<7?tH2;3?xh0:?0;6<uG3828yk15?3:1=vF<919~j24?290:wE=60:
\7fm37?=83;pD>7?;|l46d<728qC?4>4}o51f?6=9rB85=5rn60`>5<6sA92<6sa73f94?7|@:3;7p`82d83>4}O;0:0qc9=f;295~N4191vb:=?:182
\7fM5>82we;>?50;3xL6?73td<??4?:0yK7<6<ug=8?7>51zJ0=5=zf>9?6=4>{I1:4>{i?:?1<7?tH2;3?xh0;?0;6<uG3828yk14?3:1=vF<919~j25?290:wE=60:
\7fm36?=83;pD>7?;|l47d<728qC?4>4}o50f?6=9rB85=5rn61`>5<6sA92<6sa72f94?7|@:3;7p`83d83>7}O;0:0qc9<f;295~N4191vb::?:182
\7fM5>82we;9?50;3xL6?73td<8?4?:0yK7<6<ug=??7>51zJ0=5=zf;?86=4>{I1:4>{zutJKOv691;0f=db60owKLOu?}ABS
\7fxFG
\ No newline at end of file
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+--------------------------------------------------------------------------------\r
+-- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating\r
+-- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
+-- The synthesis directives "translate_off/translate_on" specified\r
+-- below are supported by Xilinx, Mentor Graphics and Synplicity\r
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+-- synthesis translate_off\r
+LIBRARY XilinxCoreLib;\r
+-- synthesis translate_on\r
+ENTITY sync_fifo_progfull504_progempty128_512x36 IS\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END sync_fifo_progfull504_progempty128_512x36;\r
+\r
+ARCHITECTURE sync_fifo_progfull504_progempty128_512x36_a OF sync_fifo_progfull504_progempty128_512x36 IS\r
+-- synthesis translate_off\r
+COMPONENT wrapped_sync_fifo_progfull504_progempty128_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+\r
+-- Configuration specification\r
+ FOR ALL : wrapped_sync_fifo_progfull504_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)\r
+ GENERIC MAP (\r
+ c_add_ngc_constraint => 0,\r
+ c_application_type_axis => 0,\r
+ c_application_type_rach => 0,\r
+ c_application_type_rdch => 0,\r
+ c_application_type_wach => 0,\r
+ c_application_type_wdch => 0,\r
+ c_application_type_wrch => 0,\r
+ c_axi_addr_width => 32,\r
+ c_axi_aruser_width => 1,\r
+ c_axi_awuser_width => 1,\r
+ c_axi_buser_width => 1,\r
+ c_axi_data_width => 64,\r
+ c_axi_id_width => 4,\r
+ c_axi_ruser_width => 1,\r
+ c_axi_type => 0,\r
+ c_axi_wuser_width => 1,\r
+ c_axis_tdata_width => 64,\r
+ c_axis_tdest_width => 4,\r
+ c_axis_tid_width => 8,\r
+ c_axis_tkeep_width => 4,\r
+ c_axis_tstrb_width => 4,\r
+ c_axis_tuser_width => 4,\r
+ c_axis_type => 0,\r
+ c_common_clock => 1,\r
+ c_count_type => 0,\r
+ c_data_count_width => 9,\r
+ c_default_value => "BlankString",\r
+ c_din_width => 36,\r
+ c_din_width_axis => 1,\r
+ c_din_width_rach => 32,\r
+ c_din_width_rdch => 64,\r
+ c_din_width_wach => 32,\r
+ c_din_width_wdch => 64,\r
+ c_din_width_wrch => 2,\r
+ c_dout_rst_val => "0",\r
+ c_dout_width => 36,\r
+ c_enable_rlocs => 0,\r
+ c_enable_rst_sync => 1,\r
+ c_error_injection_type => 0,\r
+ c_error_injection_type_axis => 0,\r
+ c_error_injection_type_rach => 0,\r
+ c_error_injection_type_rdch => 0,\r
+ c_error_injection_type_wach => 0,\r
+ c_error_injection_type_wdch => 0,\r
+ c_error_injection_type_wrch => 0,\r
+ c_family => "virtex6",\r
+ c_full_flags_rst_val => 1,\r
+ c_has_almost_empty => 0,\r
+ c_has_almost_full => 0,\r
+ c_has_axi_aruser => 0,\r
+ c_has_axi_awuser => 0,\r
+ c_has_axi_buser => 0,\r
+ c_has_axi_rd_channel => 0,\r
+ c_has_axi_ruser => 0,\r
+ c_has_axi_wr_channel => 0,\r
+ c_has_axi_wuser => 0,\r
+ c_has_axis_tdata => 0,\r
+ c_has_axis_tdest => 0,\r
+ c_has_axis_tid => 0,\r
+ c_has_axis_tkeep => 0,\r
+ c_has_axis_tlast => 0,\r
+ c_has_axis_tready => 1,\r
+ c_has_axis_tstrb => 0,\r
+ c_has_axis_tuser => 0,\r
+ c_has_backup => 0,\r
+ c_has_data_count => 0,\r
+ c_has_data_counts_axis => 0,\r
+ c_has_data_counts_rach => 0,\r
+ c_has_data_counts_rdch => 0,\r
+ c_has_data_counts_wach => 0,\r
+ c_has_data_counts_wdch => 0,\r
+ c_has_data_counts_wrch => 0,\r
+ c_has_int_clk => 0,\r
+ c_has_master_ce => 0,\r
+ c_has_meminit_file => 0,\r
+ c_has_overflow => 0,\r
+ c_has_prog_flags_axis => 0,\r
+ c_has_prog_flags_rach => 0,\r
+ c_has_prog_flags_rdch => 0,\r
+ c_has_prog_flags_wach => 0,\r
+ c_has_prog_flags_wdch => 0,\r
+ c_has_prog_flags_wrch => 0,\r
+ c_has_rd_data_count => 0,\r
+ c_has_rd_rst => 0,\r
+ c_has_rst => 1,\r
+ c_has_slave_ce => 0,\r
+ c_has_srst => 0,\r
+ c_has_underflow => 0,\r
+ c_has_valid => 0,\r
+ c_has_wr_ack => 0,\r
+ c_has_wr_data_count => 0,\r
+ c_has_wr_rst => 0,\r
+ c_implementation_type => 0,\r
+ c_implementation_type_axis => 1,\r
+ c_implementation_type_rach => 1,\r
+ c_implementation_type_rdch => 1,\r
+ c_implementation_type_wach => 1,\r
+ c_implementation_type_wdch => 1,\r
+ c_implementation_type_wrch => 1,\r
+ c_init_wr_pntr_val => 0,\r
+ c_interface_type => 0,\r
+ c_memory_type => 1,\r
+ c_mif_file_name => "BlankString",\r
+ c_msgon_val => 1,\r
+ c_optimization_mode => 0,\r
+ c_overflow_low => 0,\r
+ c_preload_latency => 1,\r
+ c_preload_regs => 0,\r
+ c_prim_fifo_type => "512x36",\r
+ c_prog_empty_thresh_assert_val => 128,\r
+ c_prog_empty_thresh_assert_val_axis => 1022,\r
+ c_prog_empty_thresh_assert_val_rach => 1022,\r
+ c_prog_empty_thresh_assert_val_rdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wach => 1022,\r
+ c_prog_empty_thresh_assert_val_wdch => 1022,\r
+ c_prog_empty_thresh_assert_val_wrch => 1022,\r
+ c_prog_empty_thresh_negate_val => 129,\r
+ c_prog_empty_type => 1,\r
+ c_prog_empty_type_axis => 0,\r
+ c_prog_empty_type_rach => 0,\r
+ c_prog_empty_type_rdch => 0,\r
+ c_prog_empty_type_wach => 0,\r
+ c_prog_empty_type_wdch => 0,\r
+ c_prog_empty_type_wrch => 0,\r
+ c_prog_full_thresh_assert_val => 504,\r
+ c_prog_full_thresh_assert_val_axis => 1023,\r
+ c_prog_full_thresh_assert_val_rach => 1023,\r
+ c_prog_full_thresh_assert_val_rdch => 1023,\r
+ c_prog_full_thresh_assert_val_wach => 1023,\r
+ c_prog_full_thresh_assert_val_wdch => 1023,\r
+ c_prog_full_thresh_assert_val_wrch => 1023,\r
+ c_prog_full_thresh_negate_val => 503,\r
+ c_prog_full_type => 1,\r
+ c_prog_full_type_axis => 0,\r
+ c_prog_full_type_rach => 0,\r
+ c_prog_full_type_rdch => 0,\r
+ c_prog_full_type_wach => 0,\r
+ c_prog_full_type_wdch => 0,\r
+ c_prog_full_type_wrch => 0,\r
+ c_rach_type => 0,\r
+ c_rd_data_count_width => 9,\r
+ c_rd_depth => 512,\r
+ c_rd_freq => 1,\r
+ c_rd_pntr_width => 9,\r
+ c_rdch_type => 0,\r
+ c_reg_slice_mode_axis => 0,\r
+ c_reg_slice_mode_rach => 0,\r
+ c_reg_slice_mode_rdch => 0,\r
+ c_reg_slice_mode_wach => 0,\r
+ c_reg_slice_mode_wdch => 0,\r
+ c_reg_slice_mode_wrch => 0,\r
+ c_synchronizer_stage => 2,\r
+ c_underflow_low => 0,\r
+ c_use_common_overflow => 0,\r
+ c_use_common_underflow => 0,\r
+ c_use_default_settings => 0,\r
+ c_use_dout_rst => 1,\r
+ c_use_ecc => 0,\r
+ c_use_ecc_axis => 0,\r
+ c_use_ecc_rach => 0,\r
+ c_use_ecc_rdch => 0,\r
+ c_use_ecc_wach => 0,\r
+ c_use_ecc_wdch => 0,\r
+ c_use_ecc_wrch => 0,\r
+ c_use_embedded_reg => 0,\r
+ c_use_fifo16_flags => 0,\r
+ c_use_fwft_data_count => 0,\r
+ c_valid_low => 0,\r
+ c_wach_type => 0,\r
+ c_wdch_type => 0,\r
+ c_wr_ack_low => 0,\r
+ c_wr_data_count_width => 9,\r
+ c_wr_depth => 512,\r
+ c_wr_depth_axis => 1024,\r
+ c_wr_depth_rach => 16,\r
+ c_wr_depth_rdch => 1024,\r
+ c_wr_depth_wach => 16,\r
+ c_wr_depth_wdch => 1024,\r
+ c_wr_depth_wrch => 16,\r
+ c_wr_freq => 1,\r
+ c_wr_pntr_width => 9,\r
+ c_wr_pntr_width_axis => 10,\r
+ c_wr_pntr_width_rach => 4,\r
+ c_wr_pntr_width_rdch => 10,\r
+ c_wr_pntr_width_wach => 4,\r
+ c_wr_pntr_width_wdch => 10,\r
+ c_wr_pntr_width_wrch => 4,\r
+ c_wr_response_latency => 1,\r
+ c_wrch_type => 0\r
+ );\r
+-- synthesis translate_on\r
+BEGIN\r
+-- synthesis translate_off\r
+U0 : wrapped_sync_fifo_progfull504_progempty128_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty,\r
+ prog_full => prog_full,\r
+ prog_empty => prog_empty\r
+ );\r
+-- synthesis translate_on\r
+\r
+END sync_fifo_progfull504_progempty128_512x36_a;\r
--- /dev/null
+--------------------------------------------------------------------------------\r
+-- This file is owned and controlled by Xilinx and must be used solely --\r
+-- for design, simulation, implementation and creation of design files --\r
+-- limited to Xilinx devices or technologies. Use with non-Xilinx --\r
+-- devices or technologies is expressly prohibited and immediately --\r
+-- terminates your license. --\r
+-- --\r
+-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --\r
+-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --\r
+-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --\r
+-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --\r
+-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --\r
+-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --\r
+-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --\r
+-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --\r
+-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --\r
+-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --\r
+-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --\r
+-- PARTICULAR PURPOSE. --\r
+-- --\r
+-- Xilinx products are not intended for use in life support appliances, --\r
+-- devices, or systems. Use in such applications are expressly --\r
+-- prohibited. --\r
+-- --\r
+-- (c) Copyright 1995-2014 Xilinx, Inc. --\r
+-- All rights reserved. --\r
+--------------------------------------------------------------------------------\r
+\r
+--------------------------------------------------------------------------------\r
+-- Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 --\r
+-- --\r
+-- Rev 1. The FIFO Generator is a parameterizable first-in/first-out --\r
+-- memory queue generator. Use it to generate resource and performance --\r
+-- optimized FIFOs with common or independent read/write clock domains, --\r
+-- and optional fixed or programmable full and empty flags and --\r
+-- handshaking signals. Choose from a selection of memory resource --\r
+-- types for implementation. Optional Hamming code based error --\r
+-- detection and correction as well as error injection capability for --\r
+-- system test help to insure data integrity. FIFO width and depth are --\r
+-- parameterizable, and for native interface FIFOs, asymmetric read and --\r
+-- write port widths are also supported. --\r
+--------------------------------------------------------------------------------\r
+\r
+-- Interfaces:\r
+-- AXI4Stream_MASTER_M_AXIS\r
+-- AXI4Stream_SLAVE_S_AXIS\r
+-- AXI4_MASTER_M_AXI\r
+-- AXI4_SLAVE_S_AXI\r
+-- AXI4Lite_MASTER_M_AXI\r
+-- AXI4Lite_SLAVE_S_AXI\r
+-- master_aclk\r
+-- slave_aclk\r
+-- slave_aresetn\r
+\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+COMPONENT sync_fifo_progfull504_progempty128_512x36\r
+ PORT (\r
+ clk : IN STD_LOGIC;\r
+ rst : IN STD_LOGIC;\r
+ din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ wr_en : IN STD_LOGIC;\r
+ rd_en : IN STD_LOGIC;\r
+ dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ full : OUT STD_LOGIC;\r
+ empty : OUT STD_LOGIC;\r
+ prog_full : OUT STD_LOGIC;\r
+ prog_empty : OUT STD_LOGIC\r
+ );\r
+END COMPONENT;\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+your_instance_name : sync_fifo_progfull504_progempty128_512x36\r
+ PORT MAP (\r
+ clk => clk,\r
+ rst => rst,\r
+ din => din,\r
+ wr_en => wr_en,\r
+ rd_en => rd_en,\r
+ dout => dout,\r
+ full => full,\r
+ empty => empty,\r
+ prog_full => prog_full,\r
+ prog_empty => prog_empty\r
+ );\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
+\r
+-- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating\r
+-- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to\r
+-- reference the XilinxCoreLib VHDL simulation library. For detailed\r
+-- instructions, please refer to the "CORE Generator Help".\r
+\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 14.7\r
+# Date: Mon Oct 20 06:51:31 2014\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:fifo_generator:9.3\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Behavioral\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3\r
+# END Select\r
+# BEGIN Parameters\r
+CSET add_ngc_constraint_axi=false\r
+CSET almost_empty_flag=false\r
+CSET almost_full_flag=false\r
+CSET aruser_width=1\r
+CSET awuser_width=1\r
+CSET axi_address_width=32\r
+CSET axi_data_width=64\r
+CSET axi_type=AXI4_Stream\r
+CSET axis_type=FIFO\r
+CSET buser_width=1\r
+CSET clock_enable_type=Slave_Interface_Clock_Enable\r
+CSET clock_type_axi=Common_Clock\r
+CSET component_name=sync_fifo_progfull504_progempty128_512x36\r
+CSET data_count=false\r
+CSET data_count_width=9\r
+CSET disable_timing_violations=false\r
+CSET disable_timing_violations_axi=false\r
+CSET dout_reset_value=0\r
+CSET empty_threshold_assert_value=128\r
+CSET empty_threshold_assert_value_axis=1022\r
+CSET empty_threshold_assert_value_rach=1022\r
+CSET empty_threshold_assert_value_rdch=1022\r
+CSET empty_threshold_assert_value_wach=1022\r
+CSET empty_threshold_assert_value_wdch=1022\r
+CSET empty_threshold_assert_value_wrch=1022\r
+CSET empty_threshold_negate_value=129\r
+CSET enable_aruser=false\r
+CSET enable_awuser=false\r
+CSET enable_buser=false\r
+CSET enable_common_overflow=false\r
+CSET enable_common_underflow=false\r
+CSET enable_data_counts_axis=false\r
+CSET enable_data_counts_rach=false\r
+CSET enable_data_counts_rdch=false\r
+CSET enable_data_counts_wach=false\r
+CSET enable_data_counts_wdch=false\r
+CSET enable_data_counts_wrch=false\r
+CSET enable_ecc=false\r
+CSET enable_ecc_axis=false\r
+CSET enable_ecc_rach=false\r
+CSET enable_ecc_rdch=false\r
+CSET enable_ecc_wach=false\r
+CSET enable_ecc_wdch=false\r
+CSET enable_ecc_wrch=false\r
+CSET enable_read_channel=false\r
+CSET enable_read_pointer_increment_by2=false\r
+CSET enable_reset_synchronization=true\r
+CSET enable_ruser=false\r
+CSET enable_tdata=false\r
+CSET enable_tdest=false\r
+CSET enable_tid=false\r
+CSET enable_tkeep=false\r
+CSET enable_tlast=false\r
+CSET enable_tready=true\r
+CSET enable_tstrobe=false\r
+CSET enable_tuser=false\r
+CSET enable_write_channel=false\r
+CSET enable_wuser=false\r
+CSET fifo_application_type_axis=Data_FIFO\r
+CSET fifo_application_type_rach=Data_FIFO\r
+CSET fifo_application_type_rdch=Data_FIFO\r
+CSET fifo_application_type_wach=Data_FIFO\r
+CSET fifo_application_type_wdch=Data_FIFO\r
+CSET fifo_application_type_wrch=Data_FIFO\r
+CSET fifo_implementation=Common_Clock_Block_RAM\r
+CSET fifo_implementation_axis=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wach=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM\r
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM\r
+CSET full_flags_reset_value=1\r
+CSET full_threshold_assert_value=504\r
+CSET full_threshold_assert_value_axis=1023\r
+CSET full_threshold_assert_value_rach=1023\r
+CSET full_threshold_assert_value_rdch=1023\r
+CSET full_threshold_assert_value_wach=1023\r
+CSET full_threshold_assert_value_wdch=1023\r
+CSET full_threshold_assert_value_wrch=1023\r
+CSET full_threshold_negate_value=503\r
+CSET id_width=4\r
+CSET inject_dbit_error=false\r
+CSET inject_dbit_error_axis=false\r
+CSET inject_dbit_error_rach=false\r
+CSET inject_dbit_error_rdch=false\r
+CSET inject_dbit_error_wach=false\r
+CSET inject_dbit_error_wdch=false\r
+CSET inject_dbit_error_wrch=false\r
+CSET inject_sbit_error=false\r
+CSET inject_sbit_error_axis=false\r
+CSET inject_sbit_error_rach=false\r
+CSET inject_sbit_error_rdch=false\r
+CSET inject_sbit_error_wach=false\r
+CSET inject_sbit_error_wdch=false\r
+CSET inject_sbit_error_wrch=false\r
+CSET input_data_width=36\r
+CSET input_depth=512\r
+CSET input_depth_axis=1024\r
+CSET input_depth_rach=16\r
+CSET input_depth_rdch=1024\r
+CSET input_depth_wach=16\r
+CSET input_depth_wdch=1024\r
+CSET input_depth_wrch=16\r
+CSET interface_type=Native\r
+CSET output_data_width=36\r
+CSET output_depth=512\r
+CSET overflow_flag=false\r
+CSET overflow_flag_axi=false\r
+CSET overflow_sense=Active_High\r
+CSET overflow_sense_axi=Active_High\r
+CSET performance_options=Standard_FIFO\r
+CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant\r
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold\r
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold\r
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant\r
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold\r
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold\r
+CSET rach_type=FIFO\r
+CSET rdch_type=FIFO\r
+CSET read_clock_frequency=1\r
+CSET read_data_count=false\r
+CSET read_data_count_width=9\r
+CSET register_slice_mode_axis=Fully_Registered\r
+CSET register_slice_mode_rach=Fully_Registered\r
+CSET register_slice_mode_rdch=Fully_Registered\r
+CSET register_slice_mode_wach=Fully_Registered\r
+CSET register_slice_mode_wdch=Fully_Registered\r
+CSET register_slice_mode_wrch=Fully_Registered\r
+CSET reset_pin=true\r
+CSET reset_type=Asynchronous_Reset\r
+CSET ruser_width=1\r
+CSET synchronization_stages=2\r
+CSET synchronization_stages_axi=2\r
+CSET tdata_width=64\r
+CSET tdest_width=4\r
+CSET tid_width=8\r
+CSET tkeep_width=4\r
+CSET tstrb_width=4\r
+CSET tuser_width=4\r
+CSET underflow_flag=false\r
+CSET underflow_flag_axi=false\r
+CSET underflow_sense=Active_High\r
+CSET underflow_sense_axi=Active_High\r
+CSET use_clock_enable=false\r
+CSET use_dout_reset=true\r
+CSET use_embedded_registers=false\r
+CSET use_extra_logic=false\r
+CSET valid_flag=false\r
+CSET valid_sense=Active_High\r
+CSET wach_type=FIFO\r
+CSET wdch_type=FIFO\r
+CSET wrch_type=FIFO\r
+CSET write_acknowledge_flag=false\r
+CSET write_acknowledge_sense=Active_High\r
+CSET write_clock_frequency=1\r
+CSET write_data_count=false\r
+CSET write_data_count_width=9\r
+CSET wuser_width=1\r
+# END Parameters\r
+# BEGIN Extra information\r
+MISC pkg_timestamp=2012-11-19T12:39:56Z\r
+# END Extra information\r
+GENERATE\r
+# CRC: d742ac77\r
--- /dev/null
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--- /dev/null
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+RECTANGLE Normal 32 32 320 224
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName control[35:0]
+PINATTR Polarity BOTH
+LINE Wide 352 80 320 80
+PIN 352 80 RIGHT 36
+PINATTR PinName async_out[35:0]
+PINATTR Polarity OUT
+\r
--- /dev/null
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\ No newline at end of file
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: XILINX CORE Generator\r
+-- / / Filename : vio36.vhd\r
+-- /___/ /\ Timestamp : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: VHDL Synthesis Wrapper\r
+-------------------------------------------------------------------------------\r
+-- This wrapper is used to integrate with Project Navigator and PlanAhead\r
+\r
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+ENTITY vio36 IS\r
+ port (\r
+ CONTROL: inout std_logic_vector(35 downto 0);\r
+ ASYNC_OUT: out std_logic_vector(35 downto 0));\r
+END vio36;\r
+\r
+ARCHITECTURE vio36_a OF vio36 IS\r
+BEGIN\r
+\r
+END vio36_a;\r
--- /dev/null
+-------------------------------------------------------------------------------\r
+-- Copyright (c) 2012 Xilinx, Inc.\r
+-- All Rights Reserved\r
+-------------------------------------------------------------------------------\r
+-- ____ ____\r
+-- / /\/ /\r
+-- /___/ \ / Vendor : Xilinx\r
+-- \ \ \/ Version : 13.3\r
+-- \ \ Application: Xilinx CORE Generator\r
+-- / / Filename : vio36.vho\r
+-- /___/ /\ Timestamp : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012\r
+-- \ \ / \\r
+-- \___\/\___\\r
+--\r
+-- Design Name: ISE Instantiation template\r
+-- Component Identifier: xilinx.com:ip:chipscope_vio:1.05.a\r
+-------------------------------------------------------------------------------\r
+-- The following code must appear in the VHDL architecture header:\r
+\r
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG\r
+component vio36\r
+ PORT (\r
+ CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);\r
+ ASYNC_OUT : OUT STD_LOGIC_VECTOR(35 DOWNTO 0));\r
+\r
+end component;\r
+\r
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------\r
+-- The following code must appear in the VHDL architecture\r
+-- body. Substitute your own instance name and net names.\r
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG\r
+\r
+your_instance_name : vio36\r
+ port map (\r
+ CONTROL => CONTROL,\r
+ ASYNC_OUT => ASYNC_OUT);\r
+\r
+-- INST_TAG_END ------ End INSTANTIATION Template ------------\r
--- /dev/null
+##############################################################\r
+#\r
+# Xilinx Core Generator version 13.3\r
+# Date: Mon Jul 23 13:39:49 2012\r
+#\r
+##############################################################\r
+#\r
+# This file contains the customisation parameters for a\r
+# Xilinx CORE Generator IP GUI. It is strongly recommended\r
+# that you do not manually alter this file as it may cause\r
+# unexpected and unsupported behavior.\r
+#\r
+##############################################################\r
+#\r
+# Generated from component: xilinx.com:ip:chipscope_vio:1.05.a\r
+#\r
+##############################################################\r
+#\r
+# BEGIN Project Options\r
+SET addpads = false\r
+SET asysymbol = true\r
+SET busformat = BusFormatAngleBracketNotRipped\r
+SET createndf = false\r
+SET designentry = VHDL\r
+SET device = xc6vlx130t\r
+SET devicefamily = virtex6\r
+SET flowvendor = Other\r
+SET formalverification = false\r
+SET foundationsym = false\r
+SET implementationfiletype = Ngc\r
+SET package = ff484\r
+SET removerpms = false\r
+SET simulationfiles = Structural\r
+SET speedgrade = -3\r
+SET verilogsim = false\r
+SET vhdlsim = true\r
+# END Project Options\r
+# BEGIN Select\r
+SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a\r
+# END Select\r
+# BEGIN Parameters\r
+CSET asynchronous_input_port_width=8\r
+CSET asynchronous_output_port_width=36\r
+CSET component_name=vio36\r
+CSET constraint_type=embedded\r
+CSET enable_asynchronous_input_port=false\r
+CSET enable_asynchronous_output_port=true\r
+CSET enable_synchronous_input_port=false\r
+CSET enable_synchronous_output_port=false\r
+CSET example_design=false\r
+CSET invert_clock_input=false\r
+CSET synchronous_input_port_width=8\r
+CSET synchronous_output_port_width=8\r
+# END Parameters\r
+GENERATE\r
+# CRC: f58807c1\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="vio36.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="vio36.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|vio36|vio36_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="vio36.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/vio36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="vio36" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-23T15:40:35" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6A1216FFFD084649B921E416A2F662FE" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
--- /dev/null
+The following files were generated for 'vio36' in directory\r
+D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_test_ADC32\ipcore_dir\\r
+\r
+XCO file generator:\r
+ Generate an XCO file for compatibility with legacy flows.\r
+\r
+ * vio36.xco\r
+\r
+Creates an implementation netlist:\r
+ Creates an implementation netlist for the IP.\r
+\r
+ * vio36.cdc\r
+ * vio36.ngc\r
+ * vio36.vhd\r
+ * vio36.vho\r
+\r
+Creates an HDL instantiation template:\r
+ Creates an HDL instantiation template for the IP.\r
+\r
+ * vio36.vho\r
+\r
+IP Symbol Generator:\r
+ Generate an IP symbol based on the current project options'.\r
+\r
+ * vio36.asy\r
+\r
+SYM file generator:\r
+ Generate a SYM file for compatibility with legacy flows\r
+\r
+ * vio36.sym\r
+\r
+Generate ISE metadata:\r
+ Create a metadata file for use when including this core in ISE designs\r
+\r
+ * vio36_xmdf.tcl\r
+\r
+Generate ISE subproject:\r
+ Create an ISE subproject for use when including this core in ISE designs\r
+\r
+ * _xmsgs/pn_parser.xmsgs\r
+ * vio36.gise\r
+ * vio36.xise\r
+\r
+Deliver Readme:\r
+ Readme file for the IP.\r
+\r
+ * vio36_readme.txt\r
+\r
+Generate FLIST file:\r
+ Text file listing all of the output files produced when a customized core was\r
+ generated in the CORE Generator.\r
+\r
+ * vio36_flist.txt\r
+\r
+Please see the Xilinx CORE Generator online help for further details on\r
+generated files and how to use them.\r
+\r
--- /dev/null
+<?xml version='1.0' encoding='utf-8'?>\r
+<!--This is an ISE project configuration file.-->\r
+<!--It holds project specific layout data for the projectmgr plugin.-->\r
+<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->\r
+<Project version="2" owner="projectmgr" name="FEE_ADC32board" >\r
+ <!--This is an ISE project configuration file.-->\r
+ <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>2</ClosedNodesVersion>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_1 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>\r
+ </ClosedNodes>\r
+ <SelectedItems>\r
+ <SelectedItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</SelectedItem>\r
+ </SelectedItems>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000487000000020000000000000000000000000200000064ffffffff000000810000000300000002000004870000000100000003000000000000000100000003</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>\r
+ <CurrentItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</CurrentItem>\r
+ </ItemView>\r
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>1</ClosedNodesVersion>\r
+ <ClosedNode>Configure Target Device</ClosedNode>\r
+ <ClosedNode>Design Utilities</ClosedNode>\r
+ <ClosedNode>Implement Design</ClosedNode>\r
+ <ClosedNode>Synthesize - XST</ClosedNode>\r
+ <ClosedNode>User Constraints</ClosedNode>\r
+ </ClosedNodes>\r
+ <SelectedItems>\r
+ <SelectedItem></SelectedItem>\r
+ </SelectedItems>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
+ <CurrentItem></CurrentItem>\r
+ </ItemView>\r
+ <ItemView guiview="File" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>1</ClosedNodesVersion>\r
+ </ClosedNodes>\r
+ <SelectedItems/>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003ce000000040101000100000000000000000000000064ffffffff0000008100000000000000040000022d0000000100000000000000d70000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
+ <CurrentItem>D:\Project\Panda\GIT\FEE_ADC32board\FEE_modules\blockmem.vhd</CurrentItem>\r
+ </ItemView>\r
+ <ItemView guiview="Library" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>1</ClosedNodesVersion>\r
+ <ClosedNode>work</ClosedNode>\r
+ </ClosedNodes>\r
+ <SelectedItems/>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
+ <CurrentItem>work</CurrentItem>\r
+ </ItemView>\r
+ <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>1</ClosedNodesVersion>\r
+ <ClosedNode>Design Utilities</ClosedNode>\r
+ </ClosedNodes>\r
+ <SelectedItems>\r
+ <SelectedItem/>\r
+ </SelectedItems>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
+ <CurrentItem/>\r
+ </ItemView>\r
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >\r
+ <ClosedNodes>\r
+ <ClosedNodesVersion>1</ClosedNodesVersion>\r
+ </ClosedNodes>\r
+ <SelectedItems>\r
+ <SelectedItem/>\r
+ </SelectedItems>\r
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>\r
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>\r
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>\r
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>\r
+ <CurrentItem/>\r
+ </ItemView>\r
+ <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>\r
+ <CurrentView>Implementation</CurrentView>\r
+</Project>\r
--- /dev/null
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+ <DateModified>2014-12-11T14:19:21</DateModified>
+ <ModuleName>top</ModuleName>
+ <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+ <SavedFilePath>D:/Project/Panda/GIT/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>D:/Project/Panda/GIT/FEE_ADC32board/project</ImplementationReportsDirectory>
+ <DateInitialized>2014-12-11T14:19:21</DateInitialized>
+ <EnableMessageFiltering>true</EnableMessageFiltering>
+ </header>
+ <body>
+ <viewgroup label="Design Overview" >
+ <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" >
+ <toc-item title="Design Overview" target="Design Overview" />
+ <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+ <toc-item title="Performance Summary" target="Performance Summary" />
+ <toc-item title="Failing Constraints" target="Failing Constraints" />
+ <toc-item title="Detailed Reports" target="Detailed Reports" />
+ </view>
+ <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="top_envsettings.html" label="System Settings" />
+ <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" />
+ <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="top_map.xrpt" label="Module Level Utilization" />
+ <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+ <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" />
+ <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="top_par.xrpt" label="Clock Report" />
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="top.twx" label="Static Timing" />
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/fit/report.htm" label="CPLD Fitter Report" />
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/tim/report.htm" label="CPLD Timing Report" />
+ </viewgroup>
+ <viewgroup label="XPS Errors and Warnings" >
+ <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+ <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+ <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+ </viewgroup>
+ <viewgroup label="XPS Reports" >
+ <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+ <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+ <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+ <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" />
+ </viewgroup>
+ <viewgroup label="Errors and Warnings" >
+ <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+ <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+ <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+ <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+ <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+ <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+ <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+ <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+ <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+ <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+ <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+ </viewgroup>
+ <viewgroup label="Detailed Reports" >
+ <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="top.syr" label="Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+ <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
+ <toc-item title="HDL Compilation" target=" HDL Compilation " />
+ <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
+ <toc-item title="HDL Analysis" target=" HDL Analysis " />
+ <toc-item title="HDL Parsing" target=" HDL Parsing " />
+ <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
+ <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
+ <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+ <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
+ <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+ <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
+ <toc-item title="Partition Report" target=" Partition Report " />
+ <toc-item title="Final Report" target=" Final Report " />
+ <toc-item title="Design Summary" target=" Design Summary " />
+ <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+ <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+ <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+ <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+ <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+ <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+ <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+ <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+ <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+ </view>
+ <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="top.srr" label="Synplify Report" />
+ <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="top.prec_log" label="Precision Report" />
+ <view inputState="Synthesized" program="ngdbuild" type="Report" file="top.bld" label="Translation Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Command Line" target="Command Line:" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+ </view>
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="top_map.mrp" label="Map Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+ <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+ <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+ <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+ <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+ <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+ <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+ <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+ <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+ <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+ <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+ <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+ <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+ <toc-item title="Router Information" target="Starting Router" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Clock Report" target="Generating Clock Report" />
+ <toc-item title="Timing Results" target="Timing Score:" />
+ <toc-item title="Final Summary" target="Peak Memory Usage:" />
+ </view>
+ <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" >
+ <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+ <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
+ <toc-item title="Pin Resources" target="** Pin Resources **" />
+ <toc-item title="Global Resources" target="** Global Control Resources **" />
+ </view>
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" >
+ <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+ <toc-item title="Performance Summary" target="Performance Summary:" />
+ </view>
+ <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Power summary" target="Power summary" />
+ <toc-item title="Thermal summary" target="Thermal summary" />
+ </view>
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+ <toc-item title="Final Summary" target="DRC detected" />
+ </view>
+ </viewgroup>
+ <viewgroup label="Secondary Reports" >
+ <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+ <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Design Information" target="Design Information" />
+ <toc-item title="Design Summary" target="Design Summary" />
+ </view>
+ <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+ <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.twr" label="Post-Map Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/top_map.nlf" label="Post-Map Simulation Model Report" />
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_map.psr" label="Physical Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="top_pad.txt" label="Pad Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top.unroutes" label="Unroutes Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.grf" label="Guide Results Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.dly" label="Asynchronous Delay Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.clk_rgn" label="Clock Region Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.tsi" label="Post-Place and Route Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+ <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_sta.nlf" label="Primetime Netlist Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="top.ibs" label="IBIS Model" >
+ <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+ <toc-item title="Component" target="Component " />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
+ <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+ <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
+ <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+ <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+ </view>
+ <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+ </viewgroup>
+ </body>
+</report-views>
--- /dev/null
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+ <DateModified>2014-12-11T14:50:59</DateModified>
+ <ModuleName>top</ModuleName>
+ <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+ <SavedFilePath>D:/Project/Panda/GIT/FEE_ADC32board/project/iseconfig/top.xreport</SavedFilePath>
+ <ImplementationReportsDirectory>D:/Project/Panda/GIT/FEE_ADC32board/project\</ImplementationReportsDirectory>
+ <DateInitialized>2014-12-11T14:33:13</DateInitialized>
+ <EnableMessageFiltering>true</EnableMessageFiltering>
+ </header>
+ <body>
+ <viewgroup label="Design Overview" >
+ <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" >
+ <toc-item title="Design Overview" target="Design Overview" />
+ <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+ <toc-item title="Performance Summary" target="Performance Summary" />
+ <toc-item title="Failing Constraints" target="Failing Constraints" />
+ <toc-item title="Detailed Reports" target="Detailed Reports" />
+ </view>
+ <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="top_envsettings.html" label="System Settings" />
+ <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" />
+ <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="top_map.xrpt" label="Module Level Utilization" />
+ <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+ <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" />
+ <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="top_par.xrpt" label="Clock Report" />
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="top.twx" label="Static Timing" />
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/fit/report.htm" label="CPLD Fitter Report" />
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/tim/report.htm" label="CPLD Timing Report" />
+ </viewgroup>
+ <viewgroup label="XPS Errors and Warnings" >
+ <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+ <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+ <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+ </viewgroup>
+ <viewgroup label="XPS Reports" >
+ <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+ <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+ <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+ <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" />
+ </viewgroup>
+ <viewgroup label="Errors and Warnings" >
+ <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+ <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+ <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+ <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+ <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+ <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+ <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+ <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+ <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+ <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+ <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+ </viewgroup>
+ <viewgroup label="Detailed Reports" >
+ <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="top.syr" label="Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+ <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
+ <toc-item title="HDL Compilation" target=" HDL Compilation " />
+ <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
+ <toc-item title="HDL Analysis" target=" HDL Analysis " />
+ <toc-item title="HDL Parsing" target=" HDL Parsing " />
+ <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
+ <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
+ <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+ <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
+ <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+ <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
+ <toc-item title="Partition Report" target=" Partition Report " />
+ <toc-item title="Final Report" target=" Final Report " />
+ <toc-item title="Design Summary" target=" Design Summary " />
+ <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+ <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+ <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+ <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+ <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+ <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+ <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+ <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+ <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+ </view>
+ <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="top.srr" label="Synplify Report" />
+ <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="top.prec_log" label="Precision Report" />
+ <view inputState="Synthesized" program="ngdbuild" type="Report" file="top.bld" label="Translation Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Command Line" target="Command Line:" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+ </view>
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="top_map.mrp" label="Map Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+ <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+ <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+ <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+ <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+ <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+ <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+ <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+ <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+ <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+ <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+ <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+ <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+ <toc-item title="Router Information" target="Starting Router" />
+ <toc-item title="Partition Status" target="Partition Implementation Status" />
+ <toc-item title="Clock Report" target="Generating Clock Report" />
+ <toc-item title="Timing Results" target="Timing Score:" />
+ <toc-item title="Final Summary" target="Peak Memory Usage:" />
+ </view>
+ <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" >
+ <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+ <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
+ <toc-item title="Pin Resources" target="** Pin Resources **" />
+ <toc-item title="Global Resources" target="** Global Control Resources **" />
+ </view>
+ <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" >
+ <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+ <toc-item title="Performance Summary" target="Performance Summary:" />
+ </view>
+ <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Power summary" target="Power summary" />
+ <toc-item title="Thermal summary" target="Thermal summary" />
+ </view>
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+ <toc-item title="Final Summary" target="DRC detected" />
+ </view>
+ </viewgroup>
+ <viewgroup label="Secondary Reports" >
+ <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+ <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+ <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ <toc-item title="Design Information" target="Design Information" />
+ <toc-item title="Design Summary" target="Design Summary" />
+ </view>
+ <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+ <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.twr" label="Post-Map Static Timing Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ <toc-item title="Timing Report Description" target="Device,package,speed:" />
+ <toc-item title="Informational Messages" target="INFO:" />
+ <toc-item title="Warning Messages" target="WARNING:" />
+ <toc-item title="Timing Constraints" target="Timing constraint:" />
+ <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+ <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+ <toc-item title="Timing Summary" target="Timing summary:" />
+ <toc-item title="Trace Settings" target="Trace Settings:" />
+ </view>
+ <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/top_map.nlf" label="Post-Map Simulation Model Report" />
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_map.psr" label="Physical Synthesis Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="top_pad.txt" label="Pad Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top.unroutes" label="Unroutes Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.grf" label="Guide Results Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.dly" label="Asynchronous Delay Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.clk_rgn" label="Clock Region Report" />
+ <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.tsi" label="Post-Place and Route Constraints Interaction Report" >
+ <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+ <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+ <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_sta.nlf" label="Primetime Netlist Report" >
+ <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+ </view>
+ <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="top.ibs" label="IBIS Model" >
+ <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+ <toc-item title="Component" target="Component " />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
+ <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+ <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+ </view>
+ <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
+ <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+ <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+ </view>
+ <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+ <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+ </viewgroup>
+ </body>
+</report-views>
jspc29 / soda.git / commitdiff