fixed length zero problem in random fwd tester

diff --git a/gbe_trb/base/fwd_test_random.vhd b/gbe_trb/base/fwd_test_random.vhd
index 57f23d5f93556fee8ed0e4eebc6015339f615398..81076fb24f62043ae9e10c640fa6c3dd3ede7890 100644 (file)
--- a/gbe_trb/base/fwd_test_random.vhd
+++ b/gbe_trb/base/fwd_test_random.vhd
@@ -53,22 +53,18 @@ architecture fwd_test_random_arch of fwd_test_random is
 \r
 -- Signals\r
   signal sop_x            : std_logic;\r
-  signal sop              : std_logic;\r
   signal eop_x            : std_logic;\r
-  signal eop              : std_logic;\r
   signal rst_x            : std_logic;\r
-  signal rst              : std_logic;\r
   \r
   signal frame_len        : std_logic_vector(15 downto 0);\r
 \r
   signal test_cnt         : unsigned(15 downto 0);\r
   signal test_data        : std_logic_vector(15 downto 0);\r
   signal test_done_x      : std_logic;\r
-  signal test_done        : std_logic;\r
-  signal test_ce_x        : std_logic;\r
+  signal new_prng_x       : std_logic;\r
   signal delay_ce_x       : std_logic;\r
-\r
   signal data_valid_x     : std_logic;\r
+  signal decrement_x      : std_logic;\r
 \r
 begin\r
 \r
@@ -87,47 +83,46 @@ begin
     RESEED_IN   => '0',\r
     NEWKEY_IN   => (others => '0'),\r
     NEWIV_IN    => (others => '0'),\r
-    READY_IN    => test_ce_x,\r
+    READY_IN    => new_prng_x,\r
     VALID_OUT   => open,\r
     DATA_OUT    => test_data \r
   );\r
 \r
   -- store the random frame length\r
+  -- we allow 0..2047 bytes, the length will be 2 bytes\r
   THE_FL_PROC: process( CLK )\r
   begin\r
     if( rising_edge(CLK) ) then\r
       if   ( RESET = '1' ) then\r
         frame_len <= (others => '0');\r
-      elsif( sop = '1' ) then\r
-        frame_len <= b"00000" & test_data(8 downto 0) & b"11";\r
+      elsif( sop_x = '1' ) then\r
+        frame_len <= b"00000" & test_data(10 downto 0);\r
       end if;\r
     end if;\r
   end process THE_FL_PROC;\r
-\r
-  -- TAKE CARE HERE: we write two bytes "length"... must be considered carefully.\r
-\r
+  \r
   -- new PRNG data is produced when we are idle and in case we wrote a byte \r
-  test_ce_x <= '1' when ((STATE = IDLE) or (data_valid_x = '1'))\r
-                   else '0';\r
+  new_prng_x <= '1' when (STATE = IDLE) or \r
+                         (STATE = FLL) or \r
+                         ((STATE = DATA) and (FWD_FULL_IN = '0'))\r
+                    else '0';\r
                    \r
   -- test data is only written when we are ready\r
   data_valid_x <= '1' when ((STATE = DATA) or (STATE = FLH) or (STATE = FLL)) and (FWD_FULL_IN = '0')\r
                       else '0';\r
 \r
+  -- length counter is only active when data is written, not during length field\r
+  decrement_x <= '1' when ((STATE = DATA) and (FWD_FULL_IN = '0'))\r
+                     else '0';\r
+\r
   -- multiplex output data\r
   FWD_DATA_OUT <= frame_len(15 downto 8) when (STATE = FLH) else\r
-                  frame_len(7 downto 0) when (STATE = FLL) else\r
-                  test_data(7 downto 0) when (STATE = DATA);\r
+                  frame_len(7 downto 0)  when (STATE = FLL) else\r
+                  test_data(7 downto 0)  when (STATE = DATA);\r
 \r
   -- write signal for next stage\r
   FWD_DATA_VALID_OUT <= data_valid_x;\r
 \r
---------------------------------------------------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------------------------------------------------\r
---------------------------------------------------------------------------------------------------------------------------\r
-\r
-\r
-\r
   -----------------------------------------------------------\r
   -- Test counter\r
   -----------------------------------------------------------\r
@@ -136,11 +131,11 @@ begin
     if( rising_edge(CLK) ) then\r
       if   ( RESET = '1' ) then\r
         test_cnt <= (others => '1');\r
-      elsif( sop = '1' ) then\r
-        test_cnt <= unsigned(b"00000" & test_data(8 downto 0) & b"11");\r
-      elsif( rst = '1' ) then\r
+      elsif( sop_x = '1' ) then\r
+        test_cnt <= unsigned(b"00000" & test_data(10 downto 0));\r
+      elsif( rst_x = '1' ) then\r
         test_cnt <= unsigned(FWD_DELAY_IN);\r
-      elsif( (data_valid_x = '1') or (delay_ce_x = '1') ) then\r
+      elsif( (decrement_x = '1') or (delay_ce_x = '1') ) then\r
         test_cnt <= test_cnt - 1;\r
       end if;\r
     end if;\r
@@ -150,12 +145,12 @@ begin
 \r
   test_done_x <= '1' when (test_cnt = x"0000") else '0';\r
 \r
-  test_done <= test_done_x when rising_edge(CLK);\r
-\r
   eop_x <= '1' when ((test_cnt = x"0000") and (STATE = DATA)) else '0';\r
 \r
-  eop <= eop_x when rising_edge(CLK);\r
-\r
+  sop_x <= '1' when (STATE = START) else '0';\r
+  \r
+  rst_x <= '1' when (STATE = CLEANUP) else '0';\r
+  \r
   -----------------------------------------------------------\r
   -- statemachine: clocked process\r
   -----------------------------------------------------------\r
@@ -164,12 +159,8 @@ begin
     if( rising_edge(CLK) ) then\r
       if( RESET = '1' ) then\r
         STATE <= IDLE;\r
-        sop   <= '0';\r
-        rst   <= '0';\r
       else\r
         STATE <= NEXT_STATE;\r
-        sop   <= sop_x;\r
-        rst   <= rst_x;\r
       end if;\r
     end if;\r
   end process THE_FSM;\r
@@ -177,17 +168,13 @@ begin
   -----------------------------------------------------------\r
   --\r
   -----------------------------------------------------------\r
-  THE_STATE_TRANSITIONS: process( STATE, FWD_ENABLE_IN, FWD_START_IN, test_done )\r
+  THE_STATE_TRANSITIONS: process( STATE, FWD_ENABLE_IN, FWD_START_IN, test_done_x )\r
   begin\r
-    sop_x <= '0';\r
-    rst_x <= '0';\r
-\r
     case STATE is\r
 \r
       when IDLE =>\r
         if( (FWD_ENABLE_IN = '1') and (FWD_START_IN = '1') and (FWD_READY_IN = '1') and (FWD_FULL_IN = '0') ) then\r
           NEXT_STATE <= START;\r
-          sop_x <= '1';\r
         else\r
           NEXT_STATE <= IDLE;\r
         end if;\r
@@ -214,9 +201,8 @@ begin
         end if;\r
 \r
       when DATA =>\r
-        if( test_done = '1' ) then\r
+        if( test_done_x = '1' ) then\r
           NEXT_STATE <= CLEANUP;\r
-          rst_x <= '1';\r
         else\r
           NEXT_STATE <= DATA;\r
         end if;\r
@@ -225,7 +211,7 @@ begin
         NEXT_STATE <= DELAY;\r
 \r
       when DELAY =>\r
-        if( test_done = '1' ) then\r
+        if( test_done_x = '1' ) then\r
           NEXT_STATE <= IDLE;\r
         else\r
           NEXT_STATE <= DELAY;\r
@@ -236,8 +222,8 @@ begin
     end case;\r
   end process THE_STATE_TRANSITIONS;\r
 \r
-  FWD_SOP_OUT <= sop;\r
-  FWD_EOP_OUT <= eop;\r
+  FWD_SOP_OUT <= sop_x;\r
+  FWD_EOP_OUT <= eop_x;\r
 \r
   FWD_BUSY_OUT <= '1' when (STATE /= IDLE) else '0';\r
 \r