generic (
API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
- FIFO_TO_INT_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH;
- FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH;
+ FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
+ FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
case out_select is
when HDR => next_INT_MASTER_DATA_OUT <= current_combined_header;
when TRM => next_INT_MASTER_DATA_OUT <= current_registered_trailer;
- when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer;
+-- when TRM_COMB => next_INT_MASTER_DATA_OUT <= current_combined_trailer;
when others => next_INT_MASTER_DATA_OUT <= current_data;
end case;
end process;
when "01" =>
current_combined_header <= combined_header_F1;
current_registered_trailer <= registered_trailer_F1;
- current_combined_trailer <= combined_trailer_F1;
+-- current_combined_trailer <= combined_trailer_F1;
current_data <= fifo_to_int_data_out;
when "10" =>
current_combined_header <= combined_header_F2;
current_registered_trailer <= registered_trailer_F2;
- current_combined_trailer <= combined_trailer_F2;
+-- current_combined_trailer <= combined_trailer_F2;
current_data <= fifo_to_int_data_out;
when "11" =>
current_combined_header <= combined_header_F3;
current_registered_trailer <= registered_trailer_F3;
- current_combined_trailer <= combined_trailer_F3;
+-- current_combined_trailer <= combined_trailer_F3;
current_data <= fifo_to_int_data_out;
when others =>
current_combined_header <= "0000000000000" & TYPE_HDR;
current_registered_trailer <= "0000000000000" & TYPE_TRM;
- current_combined_trailer <= "0000000000000" & TYPE_TRM;
+-- current_combined_trailer <= "0000000000000" & TYPE_TRM;
current_data <= "0000000000000" & TYPE_DAT;
end case;
end process;
end if;
when SHUTDOWN =>
fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter);
- next_INT_MASTER_DATAREADY_OUT <= sbuf_free and fifo_to_int_read_before;
+ next_INT_MASTER_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter));
if master_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then
--implicit: fill with padding words
next_state_to_int <= SEND_TRAILER;
generic (
API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- INIT_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- REPLY_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
- FIFO_TO_INT_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
- FIFO_TO_APL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
+ INIT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
+ REPLY_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL;
MUX_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE;
+ API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE;
+ API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_NON_SECURE_MODE;
OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
FIFO_TO_APL_DEPTH : integer range 1 to 6 := std_FIFO_DEPTH;
USE_REPLY_CHANNEL : integer range 0 to 1 := std_USE_REPLY_CHANNEL;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
- SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
+ SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES
);
port(
entity trb_net16_fifo is
generic (
- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+ DEPTH : integer := 3 -- Depth of the FIFO, 2^(n+1) 64Bit packets
);
port (
CLK : in std_logic;
end entity;
---architecture trb_net16_fifo_arch of trb_net16_fifo is
---
--- component trb_net16_fifo is
--- generic (
--- WIDTH : integer := c_DATA_WIDTH + c_NUM_WIDTH; -- FIFO word width
--- DEPTH : integer := DEPTH + 2;
--- FORCE_LUT : integer := 0
--- );
--- port (
--- CLK : in std_logic;
--- RESET : in std_logic;
--- CLK_EN : in std_logic;
--- DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
--- WRITE_ENABLE_IN : in std_logic;
--- DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data
--- READ_ENABLE_IN : in std_logic;
--- FULL_OUT : out std_logic; -- Full Flag
--- EMPTY_OUT : out std_logic;
--- DEPTH_OUT : out std_logic_vector(7 downto 0)
--- );
--- end component;
---
--- signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0);
--- signal depth16 : std_logic_vector(7 downto 0);
---
---begin
--- din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
--- din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
--- DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
--- PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH);
--- DEPTH_OUT <= conv_std_logic_vector(DEPTH, 8);
---
--- fifo : trb_net_fifo
--- port map(
--- CLK => CLK,
--- RESET => RESET,
--- CLK_EN => CLK_EN,
--- DATA_IN => din,
--- WRITE_ENABLE_IN => WRITE_ENABLE_IN,
--- DATA_OUT => dout,
--- READ_ENABLE_IN => READ_ENABLE_IN,
--- FULL_OUT => FULL_OUT,
--- EMPTY_OUT => EMPTY_OUT,
--- DEPTH_OUT => depth16
--- );
---end architecture;
entity trb_net16_ibuf is
generic (
- DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
+ DEPTH : integer range 0 to 7 := c_FIFO_SMALL;
+ USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- SECURE_MODE : integer range 0 to 1 := c_YES
+ SECURE_MODE : integer range 0 to 1 := c_NO
--use sbuf in med_to_api direction?
);
port(
end generate;
- -- this process controls what will be forwarded to the internal point
--- DATA_OUT : process (INT_HEADER_IN, fifo_data_out,
--- release_locked, is_locked, sbuf_free, fifo_empty,
--- fifo_packet_num_out, current_fifo_packet_type)
--- begin
--- tmp_INT_DATA_OUT <= fifo_data_out;
--- tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out;
--- tmp_INT_DATAREADY_OUT <= '0';
--- got_eob_out <= '0';
--- got_locked <= is_locked;
--- if SECURE_MODE = 1 then
--- fifo_read <= sbuf_free and not fifo_empty;
--- else
--- fifo_read <= INT_READ_IN and buf_INT_DATAREADY_OUT and not fifo_empty;
--- end if;
--- -- if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "00" and USE_ACKNOWLEDGE = 1 then
--- -- tmp_INT_DATA_OUT(2 downto 0) <= TYPE_DAT;
--- -- end if;
--- if fifo_empty = '0' and sbuf_free = '1' then
--- if current_fifo_packet_type /= TYPE_EOB then
--- tmp_INT_DATAREADY_OUT <= '1';
--- end if;
--- if USE_ACKNOWLEDGE = 1 then
--- if (current_fifo_packet_type = TYPE_EOB or current_fifo_packet_type = TYPE_TRM)
--- and fifo_packet_num_out = "11" then
--- got_eob_out <= '1';
--- end if;
--- if current_fifo_packet_type = TYPE_TRM then
--- got_locked <= is_locked or not release_locked;
--- end if;
--- end if;
--- end if;
--- end process;
-
-
---gen_secure_output : if SECURE_MODE = 0 generate
process(fifo_data_out, fifo_packet_num_out, is_locked, sbuf_free, fifo_empty, last_fifo_read, current_fifo_packet_type,
release_locked)
begin
end if;
end if;
end process;
---end generate;
-
release_locked <= CTRL_LOCKED(0);
entity trb_net16_iobuf is
generic (
- INIT_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH;
- REPLY_DEPTH : integer range 0 to 6 := std_FIFO_DEPTH;
- IBUF_SECURE_MODE : integer range 0 to 1 := std_IBUF_SECURE_MODE;
+ INIT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
+ REPLY_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH;
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_YES;--std_IBUF_SECURE_MODE;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
signal next_SEND_ACK_IN, reg_SEND_ACK_IN : STD_LOGIC;
signal send_ACK, send_EOB, send_DATA : STD_LOGIC;
- signal CURRENT_DATA_COUNT, next_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
+ signal CURRENT_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
-- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
signal TRANSMITTED_BUFFERS, next_TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0);
type sending_state_t is (idle, sending_ack, sending_eob);
signal next_sending_state, sending_state : sending_state_t;
signal sending_state_bits : std_logic;
-
-begin
- SBUF: trb_net16_sbuf
- generic map (
- VERSION => SBUF_VERSION
- )
- port map (
- CLK => CLK,
- RESET => RESET,
- CLK_EN => CLK_EN,
- COMB_DATAREADY_IN => comb_dataready,
- COMB_next_READ_OUT => comb_next_read,
- COMB_READ_IN => comb_read,
- COMB_DATA_IN => current_output_data_buffer,
- COMB_PACKET_NUM_IN => current_output_num_buffer,
- SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
- SYN_DATA_OUT => MED_DATA_OUT,
- SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
- SYN_READ_IN => MED_READ_IN
- );
+ signal reset_DATA_COUNT : std_logic;
+ signal increase_DATA_COUNT : std_logic;
+begin
+-- gen_sbuf : if SECURE_MODE = 1 generate
+ SBUF: trb_net16_sbuf
+ generic map (
+ VERSION => SBUF_VERSION
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => comb_dataready,
+ COMB_next_READ_OUT => comb_next_read,
+ COMB_READ_IN => comb_read,
+ COMB_DATA_IN => current_output_data_buffer,
+ COMB_PACKET_NUM_IN => current_output_num_buffer,
+ SYN_DATAREADY_OUT => MED_DATAREADY_OUT,
+ SYN_DATA_OUT => MED_DATA_OUT,
+ SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ SYN_READ_IN => MED_READ_IN
+ );
+
+ comb_read <= '1';
+ sbuf_free <= comb_next_read;
+-- end generate;
+-- gen_non_sbuf : if SECURE_MODE = 0 generate
+-- MED_DATAREADY_OUT <= comb_dataready;
+-- MED_DATA_OUT <= current_output_data_buffer;
+-- MED_PACKET_NUM_OUT <= current_output_num_buffer;
+-- sbuf_free <= MED_READ_IN;
+-- end generate;
+
+ INT_READ_OUT <= reg_INT_READ_OUT;
- comb_read <= '1';
- INT_READ_OUT <= reg_INT_READ_OUT;
- sbuf_free <= comb_next_read;
gen1 : if USE_ACKNOWLEDGE = 1 generate
decrease_TRANSMITTED_BUFFERS <= GOT_ACK_IN;
next_TRANSMITTED_BUFFERS <= (others => '0');
end generate;
- GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN)
+ GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN, CURRENT_DATA_COUNT)
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
current_EOB_word <= (others => '0');
--- current_EOB_word <= INT_DATA_IN;
current_DATA_word <= INT_DATA_IN;
if transfer_counter = "10" then
current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN;
current_NOP_word(2 downto 0) <= TYPE_ILLEGAL;
current_ACK_word(2 downto 0) <= TYPE_ACK;
current_EOB_word(2 downto 0) <= TYPE_EOB;
- -- or INT_DATA_IN(2 downto 0) this makes an EOB out of an DAT and keeps a TRM
- end if;
+ end if;
end process;
REG_TRANSFER_COUNTER : process(CLK)
reg_INT_READ_OUT, saved_packet_type, sending_state,
current_DATA_word, send_ACK, send_EOB, sbuf_free,
current_ACK_word, current_EOB_word,
- next_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS, send_DATA)
+ TRANSMITTED_BUFFERS, send_DATA)
begin
current_output_data_buffer <= current_NOP_word;
current_output_num_buffer <= transfer_counter;
next_INT_READ_OUT <= '1';
increase_TRANSMITTED_BUFFERS <= '0';
- next_DATA_COUNT <= CURRENT_DATA_COUNT;
+ increase_DATA_COUNT <= '0';
+ reset_DATA_COUNT <= '0';
next_SEND_ACK_IN <= send_ACK;
comb_dataready <= '0';
next_sending_state <= sending_state;
if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
--can only happen if idle or sending_data
--- if send_EOB = '1' then
--- current_output_data_buffer <= current_EOB_word;
--- else
- current_output_data_buffer <= current_DATA_word;
--- end if;
- comb_dataready <= '1'; --I hope sbuf can store
+ current_output_data_buffer <= current_DATA_word;
+ comb_dataready <= '1';
if transfer_counter = "10" then
- next_DATA_COUNT <= CURRENT_DATA_COUNT +1;
+ increase_DATA_COUNT <= '1'; --transfer_counter(1) and not transfer_counter(0);
end if;
if transfer_counter = "11" then
if saved_packet_type = TYPE_TRM then -- or saved_packet_type = TYPE_EOB
- next_DATA_COUNT <= (others => '0');
+ reset_DATA_COUNT <= '1';
increase_TRANSMITTED_BUFFERS <= '1';
if TRANSMITTED_BUFFERS(0) = '1' then
next_INT_READ_OUT <= '0';
end if;
end if;
end if;
-
if sending_state = sending_eob then
next_INT_READ_OUT <= '0';
current_output_data_buffer <= current_EOB_word;
comb_dataready <= '1';
if (transfer_counter = "11") then
next_sending_state <= idle;
- next_DATA_COUNT <= (others => '0');
+ reset_DATA_COUNT <= '1';
increase_TRANSMITTED_BUFFERS <= '1';
- if TRANSMITTED_BUFFERS(0) = '1' then
- next_INT_READ_OUT <= '0';
- end if;
end if;
end if;
end if;
end generate;
gen2 : if USE_ACKNOWLEDGE = 1 generate
+ REG_DATA_COUNT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_DATA_COUNT = '1' then
+ CURRENT_DATA_COUNT <= (others => '0');
+ elsif CLK_EN = '1' and increase_DATA_COUNT = '1' then
+ CURRENT_DATA_COUNT <= CURRENT_DATA_COUNT + 1;
+ end if;
+ end if;
+ end process;
+
REG : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
reg_SEND_ACK_IN <= '0';
reg_SEND_ACK_IN_2 <= '0';
- CURRENT_DATA_COUNT <= (others => '0');
elsif CLK_EN = '1' then
reg_SEND_ACK_IN <= next_SEND_ACK_IN;
reg_SEND_ACK_IN_2 <= next_SEND_ACK_IN_2;
- CURRENT_DATA_COUNT <= next_DATA_COUNT;
end if;
end if;
end process;
-
- next_max_DATA_COUNT_minus_one <=
- conv_std_logic_vector(3, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0010" else
- conv_std_logic_vector(7, DATA_COUNT_WIDTH) when REC_BUFFER_SIZE_IN="0011" else
- conv_std_logic_vector(127, DATA_COUNT_WIDTH)when REC_BUFFER_SIZE_IN(3 downto 1)="011" else --this is bram or infty
- conv_std_logic_vector(1, DATA_COUNT_WIDTH);
-
- reg_max_DATA_COUNT : process(CLK)
+ process(CLK)
begin
- if rising_edge(CLK) then
- if RESET = '1' then
- max_DATA_COUNT_minus_one(0) <= '1';
- max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 1) <= (others => '0');
- else
- max_DATA_COUNT_minus_one <= next_max_DATA_COUNT_minus_one(DATA_COUNT_WIDTH-1 downto 0);
- end if;
- end if;
- end process;
-
- comb_TRANSMITTED_BUFFERS : process (increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS, TRANSMITTED_BUFFERS)
- begin
- if (increase_TRANSMITTED_BUFFERS = '1' and decrease_TRANSMITTED_BUFFERS = '0') then
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS +1;
- elsif (increase_TRANSMITTED_BUFFERS = '0' and decrease_TRANSMITTED_BUFFERS = '1') then
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS -1;
- else
- next_TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS;
- end if;
- end process;
-
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ max_DATA_COUNT_minus_one <= (0 => '1', others => '0');
+ else
+ case REC_BUFFER_SIZE_IN is
+ when "-010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(3, DATA_COUNT_WIDTH);
+ when "-011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(7, DATA_COUNT_WIDTH);
+ when "-11-" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(127, DATA_COUNT_WIDTH);
+ when others => max_DATA_COUNT_minus_one <= conv_std_logic_vector(1, DATA_COUNT_WIDTH);
+ end case;
+ end if;
+ end if;
+ end process;
+
reg_TRANSMITTED_BUFFERS : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
TRANSMITTED_BUFFERS <= "00";
elsif CLK_EN = '1' then
- TRANSMITTED_BUFFERS <= next_TRANSMITTED_BUFFERS;
+ if (increase_TRANSMITTED_BUFFERS = '1' and decrease_TRANSMITTED_BUFFERS = '0') then
+ TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS +1;
+ elsif (increase_TRANSMITTED_BUFFERS = '0' and decrease_TRANSMITTED_BUFFERS = '1') then
+ TRANSMITTED_BUFFERS <= TRANSMITTED_BUFFERS -1;
+ end if;
end if;
end if;
end process;
-- entity trb_net16_fifo is
-- generic (
+-- USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
-- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets
-- );
-- port (
);
end component;
-
component xilinx_fifo_18x64
port (
clk: IN std_logic;
);
end component;
+ component xilinx_fifo_lut
+ generic (
+ WIDTH : integer := 18;
+ DEPTH : integer := 3
+ );
+ port (
+ clk: IN std_logic;
+ sinit: IN std_logic;
+ din: IN std_logic_VECTOR(17 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout: OUT std_logic_VECTOR(17 downto 0);
+ full: OUT std_logic;
+ empty: OUT std_logic
+ );
+ end component;
+
signal din, dout : std_logic_vector(c_DATA_WIDTH + c_NUM_WIDTH-1 downto 0);
signal depth16 : std_logic_vector(7 downto 0);
din(c_DATA_WIDTH + c_NUM_WIDTH -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
PACKET_NUM_OUT <= dout(c_DATA_WIDTH + c_NUM_WIDTH - 1 downto c_DATA_WIDTH);
-
+ DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
gen_FIFO6 : if DEPTH = 6 generate
fifo:xilinx_fifo_18x1k
);
end generate;
-
- gen_FIFO1 : if DEPTH = 1 generate
- fifo:xilinx_fifo_18x16
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- sinit => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
- end generate;
-
- gen_FIFO2 : if DEPTH = 2 generate
- fifo:xilinx_fifo_18x32
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- sinit => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
+ gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate
+ gen_FIFO_LUT : if DEPTH < 6 generate
+ fifo:xilinx_fifo_lut
+ generic map (
+ WIDTH => c_DATA_WIDTH + c_NUM_WIDTH,
+ DEPTH => ((DEPTH+3))
+ )
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ end generate;
end generate;
-
- gen_FIFO3 : if DEPTH = 3 generate
- fifo:xilinx_fifo_18x64
- port map (
- clk => CLK,
- rd_en => READ_ENABLE_IN,
- wr_en => WRITE_ENABLE_IN,
- din => din,
- sinit => RESET,
- dout => dout,
- full => FULL_OUT,
- empty => EMPTY_OUT
- );
+ gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+ gen_FIFO1 : if DEPTH = 1 generate
+ fifo:xilinx_fifo_18x16
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ end generate;
+
+ gen_FIFO2 : if DEPTH = 2 generate
+ fifo:xilinx_fifo_18x32
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ end generate;
+
+
+ gen_FIFO3 : if DEPTH = 3 generate
+ fifo:xilinx_fifo_18x64
+ port map (
+ clk => CLK,
+ rd_en => READ_ENABLE_IN,
+ wr_en => WRITE_ENABLE_IN,
+ din => din,
+ sinit => RESET,
+ dout => dout,
+ full => FULL_OUT,
+ empty => EMPTY_OUT
+ );
+ end generate;
end generate;
- DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8));
-
end architecture;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE IEEE.numeric_std.ALL;
+use work.trb_net_std.all;
+
+entity xilinx_fifo_lut IS
+ generic (
+ WIDTH : integer := 18;
+ DEPTH : integer := 16
+ );
+ port (
+ clk : IN std_logic;
+ sinit: IN std_logic;
+ din : IN std_logic_VECTOR(WIDTH-1 downto 0);
+ wr_en: IN std_logic;
+ rd_en: IN std_logic;
+ dout : OUT std_logic_VECTOR(WIDTH-1 downto 0);
+ full : OUT std_logic;
+ empty: OUT std_logic
+ );
+end entity;
+
+architecture xilinx_fifo_lut_arch OF xilinx_fifo_lut is
+
+ component shift_lut_x16
+ generic (
+ ADDRESS_WIDTH : integer := 0
+ );
+ port (
+ D : in std_logic;
+ CE : in std_logic;
+ CLK : in std_logic;
+ A : in std_logic_vector (ADDRESS_WIDTH+3 downto 0);
+ Q : out std_logic
+ );
+ end component;
+
+ signal current_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
+ signal next_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
+ signal real_ADDRESS_SRL : std_logic_vector(DEPTH+1 downto 0);
+ signal current_DOUT : std_logic_vector(WIDTH -1 downto 0);
+ signal next_DOUT : std_logic_vector(WIDTH -1 downto 0);
+
+ signal current_FULL, next_FULL : std_logic;
+ signal current_EMPTY, next_EMPTY : std_logic;
+ signal do_shift, do_shift_internal : std_logic;
+ signal fifocount : std_logic_vector(3 downto 0);
+
+begin
+
+ FULL <= current_FULL;
+ EMPTY <= current_EMPTY;
+ do_shift <= do_shift_internal;
+ dout <= current_DOUT;
+
+ inst_shift_lut_x16 : for i in 0 to (WIDTH - 1) generate
+ U1 : shift_lut_x16
+ generic map (
+ ADDRESS_WIDTH => DEPTH - 3
+ )
+ port map (
+ D => din(i),
+ CE => do_shift,
+ CLK => CLK,
+ A => current_ADDRESS_SRL(DEPTH downto 0),
+ Q => next_DOUT(i)
+ );
+ end generate;
+
+ reg_counter: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if sinit = '1' then
+ current_ADDRESS_SRL <= (others => '0');
+ else
+ current_ADDRESS_SRL <= next_ADDRESS_SRL;
+ end if;
+ end if;
+ end process;
+
+-- reg_output: process(CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if sinit = '1' then
+-- current_DOUT <= (others => '0');
+-- else
+-- current_DOUT <= next_DOUT;
+-- end if;
+-- end if;
+-- end process;
+ current_DOUT <= next_DOUT;
+
+ comb_counter: process(rd_en, wr_en, current_ADDRESS_SRL,
+ current_EMPTY, current_FULL)
+ begin
+ do_shift_internal <= wr_en and not current_FULL;
+ next_ADDRESS_SRL <= current_ADDRESS_SRL;
+ if wr_en = '0' and rd_en = '0' then --nothing
+ next_ADDRESS_SRL <= current_ADDRESS_SRL;
+ elsif wr_en = '0' and rd_en = '1' then --read
+ if current_EMPTY = '0' then
+ next_ADDRESS_SRL <= current_ADDRESS_SRL - 1;
+ end if;
+ elsif wr_en = '1' and rd_en = '0' then --write
+ if current_FULL = '0' then
+ next_ADDRESS_SRL <= current_ADDRESS_SRL + 1;
+ end if;
+ elsif wr_en = '1' and rd_en = '1' then --both
+ next_ADDRESS_SRL <= current_ADDRESS_SRL;
+ end if;
+ end process;
+
+
+ -- Comparator Block
+ next_FULL <= next_ADDRESS_SRL(DEPTH+1);
+ -- Empty flag is generated when reading from the last location
+ next_EMPTY <= '1' when (next_ADDRESS_SRL(DEPTH+1 downto 0) = 0) else '0';
+
+ reg_empty: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if sinit = '1' then
+ current_EMPTY <= '1';
+ current_FULL <= '0';
+ else
+ current_EMPTY <= next_EMPTY;
+ current_FULL <= next_FULL;
+ end if;
+ end if;
+ end process;
+
+end architecture;
+
jspc29 / trbnet.git / commitdiff