-------------------------------------------------------------------------------
-- TRBNet interfaces
-------------------------------------------------------------------------------
-component slave_bus
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
- REGIO_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_READ_ENABLE_IN : in std_logic;
- REGIO_WRITE_ENABLE_IN : in std_logic;
- REGIO_TIMEOUT_IN : in std_logic;
- REGIO_DATAREADY_OUT : out std_logic;
- REGIO_WRITE_ACK_OUT : out std_logic;
- REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic;
- SDA_IN : in std_logic;
- SDA_OUT : out std_logic;
- SCL_IN : in std_logic;
- SCL_OUT : out std_logic;
- SPI_CS_OUT : out std_logic;
- SPI_SCK_OUT : out std_logic;
- SPI_SDI_IN : in std_logic;
- SPI_SDO_OUT : out std_logic);
-end component slave_bus;
-
component slv_register
generic (
STAT : out std_logic_vector(31 downto 0));
end component slv_register;
-
component slv_ped_thr_mem
port (
CLK_IN : in std_logic;
SLV_ACK_OUT : out std_logic;
SLV_DATA_IN : in std_logic_vector(31 downto 0);
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- BACKPLANE_IN : in std_logic_vector(2 downto 0);
MEM_CLK_IN : in std_logic;
MEM_ADDR_IN : in std_logic_vector(6 downto 0);
MEM_0_D_OUT : out std_logic_vector(17 downto 0);
- MEM_1_D_OUT : out std_logic_vector(17 downto 0);
- MEM_2_D_OUT : out std_logic_vector(17 downto 0);
- MEM_3_D_OUT : out std_logic_vector(17 downto 0);
- MEM_4_D_OUT : out std_logic_vector(17 downto 0);
- MEM_5_D_OUT : out std_logic_vector(17 downto 0);
- MEM_6_D_OUT : out std_logic_vector(17 downto 0);
- MEM_7_D_OUT : out std_logic_vector(17 downto 0);
- MEM_8_D_OUT : out std_logic_vector(17 downto 0);
- MEM_9_D_OUT : out std_logic_vector(17 downto 0);
- MEM_10_D_OUT : out std_logic_vector(17 downto 0);
- MEM_11_D_OUT : out std_logic_vector(17 downto 0);
- MEM_12_D_OUT : out std_logic_vector(17 downto 0);
- MEM_13_D_OUT : out std_logic_vector(17 downto 0);
- MEM_14_D_OUT : out std_logic_vector(17 downto 0);
- MEM_15_D_OUT : out std_logic_vector(17 downto 0);
STAT : out std_logic_vector(31 downto 0));
-end component slv_ped_thr_mem;
+end component;
+
+component ped_thr_true
+ port (
+ DataInA : in std_logic_vector(17 downto 0);
+ DataInB : in std_logic_vector(17 downto 0);
+ AddressA : in std_logic_vector(6 downto 0);
+ AddressB : in std_logic_vector(6 downto 0);
+ ClockA : in std_logic;
+ ClockB : in std_logic;
+ ClockEnA : in std_logic;
+ ClockEnB : in std_logic;
+ WrA : in std_logic;
+ WrB : in std_logic;
+ ResetA : in std_logic;
+ ResetB : in std_logic;
+ QA : out std_logic_vector(17 downto 0);
+ QB : out std_logic_vector(17 downto 0));
+end component;
-------------------------------------------------------------------------------
-- I2C INterfaces
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- Module Version: 5.4
+--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 8 -depth 512 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e
+
+-- Fri Oct 12 14:39:06 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity fifo_dc_8to32 is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_dc_8to32;
+
+architecture Structure of fifo_dc_8to32 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal rptr_0: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rptr_7: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4: std_logic;
+ signal wcount_9: std_logic;
+ signal co3: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co3_1: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_1: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal wcount_r8: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_6: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal rcount_w6: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_8: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_dc_8to32.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_dc_8to32.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t18: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t17: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t16: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t9: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t8: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t7: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t0: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ LUT4_21: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>w_gcount_r29,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_20: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_19: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r8);
+
+ LUT4_18: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_17: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+ LUT4_16: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
+
+ LUT4_15: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>r_gcount_w27,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>r_gcount_w23,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w6);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>scuba_vlo, DO0=>rcount_w5);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>rcount_w6, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22,
+ AD1=>r_gcount_w23, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r29,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_7, AD2=>rcount_7, AD1=>w_gcount_r29,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w27,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w27,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_1: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
+ ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>scuba_vlo,
+ ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i,
+ CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2,
+ ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6,
+ ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
+ CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3),
+ DOB4=>Q(8), DOB5=>Q(9), DOB6=>Q(10), DOB7=>Q(11), DOB8=>open,
+ DOB9=>Q(16), DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19),
+ DOB13=>Q(24), DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27),
+ DOB17=>open);
+
+ pdp_ram_0_1_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
+ DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
+ ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>scuba_vlo,
+ ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i,
+ CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2,
+ ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6,
+ ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
+ CEB=>rden_i, CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo,
+ CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo,
+ RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open,
+ DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open,
+ DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open,
+ DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open,
+ DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7),
+ DOB4=>Q(12), DOB5=>Q(13), DOB6=>Q(14), DOB7=>Q(15),
+ DOB8=>open, DOB9=>Q(20), DOB10=>Q(21), DOB11=>Q(22),
+ DOB12=>Q(23), DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30),
+ DOB16=>Q(31), DOB17=>open);
+
+ FF_91: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_90: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_89: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_88: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_87: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_86: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_85: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_84: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_83: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_82: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_81: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_80: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_79: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_78: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_77: FD1P3DX
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_76: FD1P3DX
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_75: FD1P3DX
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_74: FD1P3DX
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_73: FD1P3DX
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_72: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_71: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_70: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_69: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_68: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_67: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_66: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_65: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_64: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_63: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_62: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_61: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_60: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_59: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_58: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_57: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_56: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_55: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_54: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_53: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_52: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_51: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_50: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_49: FD1P3DX
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_48: FD1P3DX
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_47: FD1P3DX
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_46: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_45: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_44: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_43: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_42: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_41: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_40: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_39: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_38: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_37: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_36: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_35: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_34: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_33: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_32: FD1S3DX
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_31: FD1S3DX
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_30: FD1S3DX
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_29: FD1S3DX
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_28: FD1S3DX
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_27: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_26: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_25: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_24: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_23: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_19: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_18: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_17: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_16: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_15: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_14: FD1S3DX
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_13: FD1S3DX
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_12: FD1S3DX
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_11: FD1S3DX
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_10: FD1S3DX
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_9: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_8: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_7: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_6: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_5: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_4: FD1S3DX
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_3: FD1S3DX
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_2: FD1S3DX
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_1: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_2);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co0_2, GE=>co1_2);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r7, CI=>co1_2, GE=>co2_2);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>empty_cmp_set, B0=>wcount_r8,
+ B1=>empty_cmp_clr, CI=>co2_2, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_3);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>co0_3, GE=>co1_3);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co1_3, GE=>co2_3);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w5, CI=>co2_3, GE=>co3_2);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w6,
+ B1=>full_cmp_clr, CI=>co3_2, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of fifo_dc_8to32 is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:OR2 use entity ecp3.OR2(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
WIDTH : integer := 12); -- Register Width
port (
- -- Inputs
- GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0);
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- Input
+ GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0);
- -- OUTPUTS
+ -- OUTPUT
BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
);
begin -- Gray_Decoder
- -- purpose: decode input
- -- type : combinational
- -- inputs : GRAY_IN
- -- outputs: binary_o
- PROC_DECODER: process (GRAY_IN)
+ PROC_DECODER: process (CLK_IN)
begin
- binary_o(WIDTH - 1) <= GRAY_IN(WIDTH - 1);
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ binary_o <= (others => '0');
+ else
+ binary_o(WIDTH - 1) <= GRAY_IN(WIDTH - 1);
- for I in (WIDTH - 2) to 0 loop
- binary_o(I) <= binary_o(I + 1) xor GRAY_IN(I);
- end loop;
+ for I in (WIDTH - 2) to 0 loop
+ binary_o(I) <= binary_o(I + 1) xor GRAY_IN(I);
+ end loop;
+ end if;
+ end if;
end process PROC_DECODER;
- -- purpose: drive output ports
- -- type : combinational
- -- inputs : binary_o
- -- outputs: BINARY_OUT
- PROC_OUT: process (binary_o)
- begin
- BINARY_OUT <= binary_o;
+ -- Output
+ BINARY_OUT <= binary_o;
- end process PROC_OUT;
-
end Gray_Decoder;
--- /dev/null
+-----------------------------------------------------------------------------
+--
+-- Gray EnCcoder
+--
+-----------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity Gray_Encoder is
+ generic (
+ WIDTH : integer := 12 -- Register Width
+ );
+
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- Input
+ BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0);
+
+ -- OUTPUT
+ GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
+ );
+
+end Gray_Encoder;
+
+architecture Behavioral of Gray_Encoder is
+
+ signal gray_o : std_logic_vector(WIDTH - 1 downto 0);
+
+begin
+
+ PROC_ENCODER: process (CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ gray_o <= (others => '0');
+ else
+ gray_o(WIDTH - 1) <= BINARY_IN(WIDTH -1);
+ for I in (WIDTH - 2) to 0 loop
+ gray_o(I) <= BINARY_IN(I + 1) xor BINARY_IN(I);
+ end loop;
+ end if;
+ end if;
+
+ GRAY_O <= gray_o;
+ end process PROC_ENCODER;
+
+ -- Output
+ GRAY_OUT <= gray_o;
+
+end Behavioral;
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.adcmv3_components.all;\r
+use work.nxyter_components.all;\r
+\r
+entity nx_timestamp_fifo_read is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ \r
+ -- nXyter Timestamp Ports\r
+ NX_TIMESTAMP_CLK_IN : in std_logic;\r
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);\r
+ NX_FRAME_CLOCK_OUT : out std_logic;\r
+ NX_FRAME_SYNC_OUT : out std_logic;\r
+ \r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_timestamp_fifo_read is\r
+\r
+\r
+ -- FIFO Input Handler\r
+ signal fifo_skip_write_x : std_logic;\r
+ signal fifo_skip_write_l : std_logic;\r
+ signal fifo_skip_write : std_logic;\r
+ signal fifo_full_i : std_logic;\r
+ signal fifo_write_enable_o : std_logic;\r
+ signal fifo_write_skip_ctr : unsigned(7 downto 0);\r
+ signal nx_frame_clock_o : std_logic;\r
+ signal frame_clock_ctr : unsigned(1 downto 0);\r
+\r
+ -- FIFO Output Handler\r
+ signal fifo_empty_i : std_logic; \r
+ signal fifo_empty_x : std_logic; \r
+ signal fifo_empty : std_logic; \r
+ signal fifo_full_x : std_logic;\r
+ signal fifo_full : std_logic;\r
+ signal fifo_out : std_logic_vector(31 downto 0);\r
+ signal fifo_read_enable_o : std_logic;\r
+ signal fifo_skip_write_o : std_logic;\r
+ signal fifo_skip_write_r : std_logic;\r
+ signal fifo_skip_write_s : std_logic;\r
+\r
+ -- SYNC NX Frame Process\r
+ signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
+ signal nx_frame_synced_o : std_logic;\r
+ signal frame_sync_wait_ctr : unsigned (7 downto 0);\r
+ \r
+ -- Slave Bus\r
+ signal register_fifo_data : std_logic_vector(31 downto 0);\r
+ signal register_fifo_status : std_logic_vector(31 downto 0);\r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ signal fifo_write_enable_x : std_logic;\r
+ signal fifo_write_enable : std_logic;\r
+ signal fifo_read_enable_x : std_logic;\r
+ signal fifo_read_enable : std_logic;\r
+ signal fifo_write_skip_ctr_x : std_logic_vector(7 downto 0);\r
+ signal fifo_write_skip_ctr_o : std_logic_vector(7 downto 0);\r
+ \r
+ type STATES is (IDLE,\r
+ READ_FIFO\r
+ );\r
+ signal STATE : STATES;\r
+\r
+ type STATES_SYNC is (SYNC_CHECK,\r
+ SYNC_RESYNC,\r
+ SYNC_WAIT\r
+ );\r
+ signal STATE_SYNC : STATES_SYNC;\r
+ \r
+begin\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Dual Clock FIFO 8bit to 32bit\r
+ -----------------------------------------------------------------------------\r
+\r
+ fifo_dc_8to32_1: fifo_dc_8to32\r
+ port map (\r
+ Data => NX_TIMESTAMP_IN,\r
+ WrClock => NX_TIMESTAMP_CLK_IN,\r
+ RdClock => CLK_IN,\r
+ WrEn => fifo_write_enable_o,\r
+ RdEn => fifo_read_enable_o,\r
+ Reset => RESET_IN,\r
+ RPReset => RESET_IN,\r
+ Q => fifo_out,\r
+ Empty => fifo_empty_i,\r
+ Full => fifo_full_i\r
+ );\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- FIFO Input Handler\r
+ -----------------------------------------------------------------------------\r
+\r
+ -- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal\r
+ -- fifo_skip_write\r
+ PROC_FIFO_IN_HANDLER_SYNC: process(NX_TIMESTAMP_CLK_IN)\r
+ begin\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ fifo_skip_write_x <= '0';\r
+ fifo_skip_write_l <= '0';\r
+ else\r
+ fifo_skip_write_x <= fifo_skip_write_o;\r
+ fifo_skip_write_l <= fifo_skip_write_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_FIFO_IN_HANDLER_SYNC;\r
+\r
+ -- Signal fifo_skip_write might 2 clocks long --> I need 1\r
+ level_to_pulse_1: level_to_pulse\r
+ port map (\r
+ CLK_IN => NX_TIMESTAMP_CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ LEVEL_IN => fifo_skip_write_l,\r
+ PULSE_OUT => fifo_skip_write\r
+ );\r
+ \r
+ -- Write only in case FIFO is not full, skip one write cycle in case\r
+ -- fifo_skip_write is true (needed by the synchronization process\r
+ -- to genrate the NX Frame Clock which I don't have, grrrr) \r
+ PROC_FIFO_IN_HANDLER: process(NX_TIMESTAMP_CLK_IN)\r
+ begin\r
+ if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ fifo_write_enable_o <= '0';\r
+ frame_clock_ctr <= (others => '0');\r
+ fifo_write_skip_ctr <= (others => '0'); \r
+ else\r
+ fifo_write_enable_o <= '1';\r
+\r
+ if (fifo_full_i = '1') then\r
+ fifo_write_enable_o <= '0';\r
+ elsif (fifo_skip_write = '1') then\r
+ fifo_write_skip_ctr <= fifo_write_skip_ctr + 1;\r
+ fifo_write_enable_o <= '0';\r
+ end if;\r
+\r
+ if (frame_clock_ctr < 2) then\r
+ nx_frame_clock_o <= '1';\r
+ else\r
+ nx_frame_clock_o <= '0';\r
+ end if;\r
+\r
+ if (fifo_skip_write = '1') then\r
+ frame_clock_ctr <= (others => '0');\r
+ else\r
+ frame_clock_ctr <= frame_clock_ctr + 1;\r
+ end if;\r
+ \r
+ end if;\r
+ end if;\r
+ end process PROC_FIFO_IN_HANDLER; \r
+\r
+ NX_FRAME_CLOCK_OUT <= nx_frame_clock_o;\r
+ \r
+\r
+ -----------------------------------------------------------------------------\r
+ -- FIFO Output Handler and Sync FIFO\r
+ -----------------------------------------------------------------------------\r
+\r
+ -- Read only in case FIFO is not empty\r
+ PROC_FIFO_READ: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ fifo_read_enable_o <= '0';\r
+ STATE <= IDLE;\r
+ else\r
+ fifo_read_enable_o <= '0';\r
+ case STATE is\r
+\r
+ when IDLE =>\r
+ if (fifo_empty_i = '1') then\r
+ STATE <= IDLE;\r
+ else\r
+ fifo_read_enable_o <= '1';\r
+ STATE <= READ_FIFO;\r
+ end if;\r
+ \r
+ when READ_FIFO =>\r
+ register_fifo_data <= fifo_out;\r
+ STATE <= IDLE;\r
+ \r
+ when others => null;\r
+ end case;\r
+ end if;\r
+ end if;\r
+ end process PROC_FIFO_READ;\r
+\r
+\r
+ -- Sync to NX NO_DATA FRAME\r
+ PROC_SYNC_TO_NO_DATA: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ nx_frame_synced_o <= '0';\r
+ nx_frame_resync_ctr <= (others => '0');\r
+ frame_sync_wait_ctr <= (others => '0');\r
+ fifo_skip_write_s <= '0';\r
+ STATE_SYNC <= SYNC_CHECK;\r
+ else\r
+ fifo_skip_write_s <= '0';\r
+\r
+ case STATE_SYNC is\r
+\r
+ when SYNC_CHECK =>\r
+ case fifo_out is\r
+ when x"7f7f7f06" =>\r
+ nx_frame_synced_o <= '1';\r
+ STATE_SYNC <= SYNC_CHECK;\r
+\r
+ when x"067f7f7f" =>\r
+ nx_frame_synced_o <= '0';\r
+ STATE_SYNC <= SYNC_RESYNC;\r
+\r
+ when x"7f067f7f" =>\r
+ nx_frame_synced_o <= '0';\r
+ STATE_SYNC <= SYNC_RESYNC;\r
+ \r
+ when x"7f7f067f" =>\r
+ nx_frame_synced_o <= '0';\r
+ STATE_SYNC <= SYNC_RESYNC;\r
+\r
+ when others =>\r
+ nx_frame_synced_o <= nx_frame_synced_o;\r
+ STATE_SYNC <= SYNC_CHECK;\r
+ \r
+ end case;\r
+\r
+ when SYNC_RESYNC =>\r
+ fifo_skip_write_s <= '1';\r
+ nx_frame_resync_ctr <= nx_frame_resync_ctr + 1;\r
+ frame_sync_wait_ctr <= x"ff";\r
+ STATE_SYNC <= SYNC_WAIT;\r
+\r
+ when SYNC_WAIT =>\r
+ if (frame_sync_wait_ctr > 0) then\r
+ frame_sync_wait_ctr <= frame_sync_wait_ctr -1;\r
+ STATE_SYNC <= SYNC_WAIT;\r
+ else\r
+ STATE_SYNC <= SYNC_CHECK;\r
+ end if;\r
+\r
+ end case;\r
+\r
+ end if;\r
+ end if;\r
+ end process PROC_SYNC_TO_NO_DATA;\r
+\r
+ NX_FRAME_SYNC_OUT <= nx_frame_synced_o;\r
+ \r
+-------------------------------------------------------------------------------\r
+-- TRBNet Slave Bus\r
+-------------------------------------------------------------------------------\r
+\r
+ -- Cross ClockDomain NX_TIMESTAMP_CLK_IN --> CLK_IN, for simplicity just\r
+ -- cross all signals, even the CLK_IN ones\r
+ PROC_SYNC_FIFO_SIGNALS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ fifo_empty_x <= '0';\r
+ fifo_empty <= '0';\r
+\r
+ fifo_full_x <= '0';\r
+ fifo_full <= '0';\r
+\r
+ fifo_write_enable_x <= '0';\r
+ fifo_write_enable <= '0';\r
+ \r
+ fifo_read_enable_x <= '0';\r
+ fifo_read_enable <= '0';\r
+\r
+ fifo_write_skip_ctr_x <= (others => '0');\r
+ fifo_write_skip_ctr_o <= (others => '0');\r
+ else\r
+ fifo_empty_x <= fifo_empty_i;\r
+ fifo_empty <= fifo_empty_x;\r
+\r
+ fifo_full_x <= fifo_full_i;\r
+ fifo_full <= fifo_full_x;\r
+\r
+ fifo_write_enable_x <= fifo_write_enable_o;\r
+ fifo_write_enable <= fifo_write_enable_x;\r
+\r
+ fifo_read_enable_x <= fifo_read_enable_o;\r
+ fifo_read_enable <= fifo_read_enable_x;\r
+\r
+ fifo_write_skip_ctr_x <= fifo_write_skip_ctr;\r
+ fifo_write_skip_ctr_o <= fifo_write_skip_ctr_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_SYNC_FIFO_SIGNALS;\r
+\r
+ register_fifo_status(0) <= fifo_write_enable;\r
+ register_fifo_status(1) <= fifo_full;\r
+ register_fifo_status(3 downto 2) <= (others => '0');\r
+ register_fifo_status(4) <= fifo_read_enable;\r
+ register_fifo_status(5) <= fifo_empty;\r
+ register_fifo_status(7 downto 6) <= (others => '0');\r
+ register_fifo_status(15 downto 8) <= fifo_write_skip_ctr_o;\r
+ register_fifo_status(23 downto 16) <= nx_frame_resync_ctr;\r
+ register_fifo_status(30 downto 24) <= (others => '0');\r
+ register_fifo_status(31) <= nx_frame_synced_o;\r
+\r
+\r
+ -- Give status info to the TRB Slow Control Channel\r
+ PROC_FIFO_REGISTERS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ slv_data_out_o <= (others => '0');\r
+ slv_ack_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ fifo_skip_write_r <= '0';\r
+ else\r
+ slv_data_out_o <= (others => '0');\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ fifo_skip_write_r <= '0';\r
+\r
+ if (SLV_READ_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0000" => slv_data_out_o <= register_fifo_data;\r
+ when x"0001" => slv_data_out_o <= register_fifo_status;\r
+ when others => slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0'; \r
+ end case;\r
+ \r
+ elsif (SLV_WRITE_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0001" => fifo_skip_write_r <= '1';\r
+ when others => slv_unknown_addr_o <= '1'; \r
+ slv_ack_o <= '0';\r
+ end case; \r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if;\r
+ end process PROC_FIFO_REGISTERS;\r
+\r
+ fifo_skip_write_o <= fifo_skip_write_r or fifo_skip_write_s;\r
+ \r
+-- Output Signals\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o;\r
+\r
+\r
+end Behavioral;\r
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity nxyter_timestamp_sim is\r
+ port(\r
+ CLK_IN : in std_logic; -- Clock 128MHz\r
+ RESET_IN : in std_logic;\r
+ \r
+ TIMESTAMP_OUT : out std_logic_vector(7 downto 0);\r
+ CLK128_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nxyter_timestamp_sim is\r
+ \r
+ signal timestamp_n : std_logic_vector(7 downto 0);\r
+ signal timestamp_g : std_logic_vector(7 downto 0);\r
+ signal timestamp : unsigned(31 downto 0);\r
+ signal counter : unsigned(1 downto 0);\r
+ \r
+begin\r
+\r
+ timestamp <= x"7f7f7f06";\r
+\r
+ PROC_NX_TIMESTAMP: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ timestamp_n <= (others => '0');\r
+-- timestamp <= (others => '0');\r
+ counter <= (others => '0');\r
+ else\r
+ case counter is\r
+ -- when "00" => timestamp_n <= timestamp(7 downto 0);\r
+ -- when "01" => timestamp_n <= timestamp(15 downto 8);\r
+ -- when "10" => timestamp_n <= timestamp(23 downto 16);\r
+ -- when "11" => timestamp_n <= timestamp(31 downto 24);\r
+ -- timestamp <= timestamp + 1;\r
+ when "00" => timestamp_n <= timestamp(7 downto 0);\r
+ when "01" => timestamp_n <= timestamp(15 downto 8);\r
+ when "10" => timestamp_n <= timestamp(23 downto 16);\r
+ when "11" => timestamp_n <= timestamp(31 downto 24);\r
+\r
+ when others => null; \r
+ end case;\r
+\r
+ counter <= counter + 1;\r
+ end if;\r
+ end if; \r
+ end process PROC_NX_TIMESTAMP;\r
+\r
+ \r
+\r
+-- Gray_Encoder_1: Gray_Encoder\r
+-- generic map (\r
+-- WIDTH => 8\r
+-- )\r
+-- port map (\r
+-- CLK_IN => CLK_IN,\r
+-- RESET_IN => RESET_IN,\r
+-- BINARY_IN => timestamp_n,\r
+-- GRAY_OUT => timestamp_g \r
+-- );\r
+-- \r
+\r
+-- Output Signals\r
+ TIMESTAMP_OUT <= timestamp_n;\r
+ CLK128_OUT <= CLK_IN;\r
+ \r
+end Behavioral;\r
use ieee.numeric_std.all;
library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
use work.adcmv3_components.all;
+use work.nxyter_components.all;
entity nXyter_FEE_board is
-- Signals
-------------------------------------------------------------------------------
- -- nXyter related signals
- signal i2c_sda_o : std_logic; -- I2C SDA
- signal i2c_sda_i : std_logic;
- signal i2c_scl_o : std_logic; -- I2C SCL
- signal i2c_scl_i : std_logic;
-
- signal spi_sdi : std_logic;
- signal spi_sdo : std_logic;
+ -- Bus Handler
+ signal slv_read : std_logic_vector(8-1 downto 0);
+ signal slv_write : std_logic_vector(8-1 downto 0);
+ signal slv_busy : std_logic_vector(8-1 downto 0);
+ signal slv_ack : std_logic_vector(8-1 downto 0);
+ signal slv_addr : std_logic_vector(8*16-1 downto 0);
+ signal slv_data_rd : std_logic_vector(8*32-1 downto 0);
+ signal slv_data_wr : std_logic_vector(8*32-1 downto 0);
+ signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
+ -- I2C Master
+ signal i2c_sda_o : std_logic; -- I2C SDA
+ signal i2c_sda_i : std_logic;
+ signal i2c_scl_o : std_logic; -- I2C SCL
+ signal i2c_scl_i : std_logic;
+ -- SPI Interface ADC
+ signal spi_sdi : std_logic;
+ signal spi_sdo : std_logic;
begin
-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------
-
- -- slave bus signals
- THE_SLAVE_BUS_1: slave_bus
+
+ -- TRBNet Bus Handler
+ THE_BUS_HANDLER: trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
+ 1 => x"0040", -- I2C master
+ 2 => x"0100", -- Timestamp Fifo
+ -- 3 => x"d100", -- SPI data memory
+ others => x"0000"),
+ PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
+ 1 => 0, -- I2C master
+ 2 => 1, -- Timestamp Fifo
+ -- 3 => 6, -- SPI data memory
+ others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DAT_ADDR_IN => REGIO_ADDR_IN,
+ DAT_DATA_IN => REGIO_DATA_IN,
+ DAT_DATA_OUT => REGIO_DATA_OUT,
+ DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,
+ DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,
+ DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,
+ DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,
+ DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,
+ DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
+ DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
+
+ -- Control Registers
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),
+ BUS_ADDR_OUT(0*16+2 downto 0*16) => slv_addr(0*16+2 downto 0*16),
+ BUS_ADDR_OUT(0*16+15 downto 0*16+3) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATAREADY_IN(0) => slv_ack(0),
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),
+ BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0),
+
+ -- I2C master
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATAREADY_IN(1) => slv_ack(1),
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ -- Timestamp Fifo
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),
+-- BUS_ADDR_OUT(2*16+0 downto 2*16) => slv_addr(2*16+0 downto 0*16),
+ BUS_ADDR_OUT(2*16+0) => slv_addr(2*16+0),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATAREADY_IN(2) => slv_ack(2),
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),
+ BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2),
+
+ ---- SPI control registers
+ --BUS_READ_ENABLE_OUT(4) => slv_read(4),
+ --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
+ --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),
+ --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),
+ --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),
+ --BUS_TIMEOUT_OUT(4) => open,
+ --BUS_DATAREADY_IN(4) => slv_ack(4),
+ --BUS_WRITE_ACK_IN(4) => slv_ack(4),
+ --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),
+ --BUS_UNKNOWN_ADDR_IN(4) => '0',
+
+ ---- SPI data memory
+ --BUS_READ_ENABLE_OUT(5) => slv_read(5),
+ --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
+ --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
+ --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
+ --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),
+ --BUS_TIMEOUT_OUT(5) => open,
+ --BUS_DATAREADY_IN(5) => slv_ack(5),
+ --BUS_WRITE_ACK_IN(5) => slv_ack(5),
+ --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),
+ --BUS_UNKNOWN_ADDR_IN(5) => '0',
+
+ ---- debug
+ --STAT_DEBUG => stat
+ STAT_DEBUG => open
+ );
+
+
+-------------------------------------------------------------------------------
+-- Registers
+-------------------------------------------------------------------------------
+ nxyter_registers_1: nxyter_registers
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
-
- REGIO_ADDR_IN => REGIO_ADDR_IN,
- REGIO_DATA_IN => REGIO_DATA_IN,
- REGIO_DATA_OUT => REGIO_DATA_OUT,
- REGIO_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,
- REGIO_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,
- REGIO_TIMEOUT_IN => REGIO_TIMEOUT_IN,
- REGIO_DATAREADY_OUT => REGIO_DATAREADY_OUT,
- REGIO_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,
- REGIO_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
- REGIO_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
-
- SDA_IN => i2c_sda_i,
- SDA_OUT => i2c_sda_o,
- SCL_IN => i2c_scl_i,
- SCL_OUT => i2c_scl_o,
-
- SPI_CS_OUT => SPI_CSB_OUT,
- SPI_SCK_OUT => SPI_SCLK_OUT,
- SPI_SDI_IN => spi_sdi,
- SPI_SDO_OUT => spi_sdo
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ SLV_READ_IN => slv_read(0),
+ SLV_WRITE_IN => slv_write(0),
+ SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
+ SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
+ SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16),
+ SLV_ACK_OUT => slv_ack(0),
+ SLV_NO_MORE_DATA_OUT => slv_busy(0),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0)
+ );
+
+-------------------------------------------------------------------------------
+-- I2C master block for accessing the nXyter
+-------------------------------------------------------------------------------
+ THE_I2C_MASTER: i2c_master
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ SLV_READ_IN => slv_read(1),
+ SLV_WRITE_IN => slv_write(1),
+ SLV_BUSY_OUT => slv_busy(1),
+ SLV_ACK_OUT => slv_ack(1),
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+
+ -- I2C connections
+ SDA_IN => open,
+ SDA_OUT => open,
+ SCL_IN => open,
+ SCL_OUT => open,
+
+ -- Status lines
+ STAT => open
+ );
+
+-------------------------------------------------------------------------------
+-- nXyter TimeStamp Read
+-------------------------------------------------------------------------------
+
+ nx_timestamp_fifo_read_1: nx_timestamp_fifo_read
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_TIMESTAMP_CLK_IN => NX_CLK128_IN,
+ NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
+ NX_FRAME_CLOCK_OUT => open,
+
+ SLV_READ_IN => slv_read(2),
+ SLV_WRITE_IN => slv_write(2),
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
+ SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
+ SLV_ACK_OUT => slv_ack(2),
+ SLV_NO_MORE_DATA_OUT => slv_busy(2),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2)
);
-----------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use IEEE.numeric_std.ALL;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
package nxyter_components is
REGIO_DATAREADY_OUT : out std_logic;
REGIO_WRITE_ACK_OUT : out std_logic;
REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic);
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic
+ );
+end component;
+
+component nxyter_registers
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+end component;
+
+component fifo_dc_8to32
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
end component;
+component nx_timestamp_fifo_read
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NX_TIMESTAMP_CLK_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_FRAME_CLOCK_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+end component;
+component level_to_pulse
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ LEVEL_IN : in std_logic;
+ PULSE_OUT : out std_logic
+ );
+end component;
component Gray_Decoder
generic (
WIDTH : integer);
port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0);
BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0));
end component;
+
+component Gray_Encoder
+ generic (
+ WIDTH : integer);
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0);
+ GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0));
+end component;
+
+-------------------------------------------------------------------------------
+-- Simulations
+-------------------------------------------------------------------------------
+
+component nxyter_timestamp_sim
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMESTAMP_OUT : out std_logic_vector(7 downto 0);
+ CLK128_OUT : out std_logic
+ );
+end component;
+
+
end package;
--- /dev/null
+library IEEE;\r
+use IEEE.STD_LOGIC_1164.ALL;\r
+use IEEE.STD_LOGIC_ARITH.ALL;\r
+use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
+\r
+library work;\r
+\r
+entity nxyter_registers is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+ \r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nxyter_registers is\r
+\r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+\r
+ type reg_32bit_t is array (0 to 7) of std_logic_vector(31 downto 0);\r
+ signal reg_data : reg_32bit_t;\r
+ \r
+begin\r
+\r
+ PROC_NX_REGISTERS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ reg_data(0) <= x"babe_0000";\r
+ reg_data(1) <= x"babe_0001";\r
+ reg_data(2) <= x"babe_0002";\r
+ reg_data(3) <= x"babe_0003";\r
+ reg_data(4) <= x"babe_0004";\r
+ reg_data(5) <= x"babe_0005";\r
+ reg_data(6) <= x"babe_0006";\r
+ reg_data(7) <= x"babe_0007";\r
+\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ else\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ slv_data_out_o <= (others => '0'); \r
+\r
+ if (SLV_WRITE_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0000" => reg_data(0) <= SLV_DATA_IN;\r
+ when x"0001" => reg_data(1) <= SLV_DATA_IN;\r
+ when x"0002" => reg_data(2) <= SLV_DATA_IN;\r
+ when x"0003" => reg_data(3) <= SLV_DATA_IN;\r
+ when x"0004" => reg_data(4) <= SLV_DATA_IN;\r
+ when x"0005" => reg_data(5) <= SLV_DATA_IN;\r
+ when x"0006" => reg_data(6) <= SLV_DATA_IN;\r
+ when x"0007" => reg_data(7) <= SLV_DATA_IN;\r
+ when others => slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
+ end case;\r
+ \r
+ elsif (SLV_READ_IN = '1') then\r
+ case SLV_ADDR_IN is\r
+ when x"0000" => slv_data_out_o <= reg_data(0);\r
+ when x"0001" => slv_data_out_o <= reg_data(1);\r
+ when x"0002" => slv_data_out_o <= reg_data(2);\r
+ when x"0003" => slv_data_out_o <= reg_data(3);\r
+ when x"0004" => slv_data_out_o <= reg_data(4);\r
+ when x"0005" => slv_data_out_o <= reg_data(5);\r
+ when x"0006" => slv_data_out_o <= reg_data(6);\r
+ when x"0007" => slv_data_out_o <= reg_data(7);\r
+ when others => slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
+ end case;\r
+\r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if; \r
+ end process PROC_NX_REGISTERS;\r
+\r
+-- Output Signals\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
+\r
+end Behavioral;\r
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
-use work.adcmv3_components.all;\r
-\r
-\r
-entity slave_bus is\r
- port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
-\r
- -- RegIO signals\r
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus\r
- REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint\r
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint\r
- REGIO_READ_ENABLE_IN : in std_logic; -- read pulse\r
- REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse\r
- REGIO_TIMEOUT_IN : in std_logic; -- access timed out\r
- REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested\r
- REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted\r
- REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now\r
- REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request\r
-\r
- -- I2C connections\r
- SDA_IN : in std_logic;\r
- SDA_OUT : out std_logic;\r
- SCL_IN : in std_logic;\r
- SCL_OUT : out std_logic;\r
- \r
- -- SPI connections\r
- SPI_CS_OUT : out std_logic;\r
- SPI_SCK_OUT : out std_logic;\r
- SPI_SDI_IN : in std_logic;\r
- SPI_SDO_OUT : out std_logic\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of slave_bus is\r
-\r
--- Signals\r
- signal slv_read : std_logic_vector(18-1 downto 0);\r
- signal slv_write : std_logic_vector(18-1 downto 0);\r
- signal slv_busy : std_logic_vector(18-1 downto 0);\r
- signal slv_ack : std_logic_vector(18-1 downto 0);\r
- signal slv_addr : std_logic_vector(18*16-1 downto 0);\r
- signal slv_data_rd : std_logic_vector(18*32-1 downto 0);\r
- signal slv_data_wr : std_logic_vector(18*32-1 downto 0);\r
-\r
--- SPI controller BRAM lines\r
- signal spi_bram_addr : std_logic_vector(7 downto 0);\r
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);\r
- signal spi_bram_we : std_logic;\r
-\r
- signal spi_cs : std_logic;\r
- signal spi_sck : std_logic;\r
- signal spi_sdi : std_logic;\r
- signal spi_sdo : std_logic;\r
- signal spi_debug : std_logic_vector(31 downto 0);\r
-\r
- signal ctrl_lvl : std_logic_vector(31 downto 0);\r
- signal ctrl_trg : std_logic_vector(31 downto 0);\r
- signal ctrl_pll : std_logic_vector(15 downto 0);\r
-\r
- signal debug : std_logic_vector(63 downto 0);\r
- signal onewire_debug : std_logic_vector(63 downto 0);\r
- \r
- -- do not know at the moment, have no backplanes, needed by Slave-Bus\r
- signal bp_module_qq : std_logic_vector(2 downto 0);\r
-\r
- -- Pedestal and threshold stuff\r
- type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
-\r
- signal buf_addr : std_logic_vector(6 downto 0);\r
- signal thr_addr : std_logic_vector(6 downto 0);\r
- signal thr_data : reg_18bit_t;\r
- signal ped_data : reg_18bit_t;\r
-\r
-begin\r
-\r
--- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus\r
- THE_BUS_HANDLER: trb_net16_regio_bus_handler\r
- generic map(\r
- PORT_NUMBER => 3,\r
- PORT_ADDRESSES => ( 0 => x"a000", -- pedestal memories\r
- 1 => x"a800", -- threshold memories\r
- 2 => x"8040", -- I2C master\r
- -- 3 => x"c000", -- 1Wire master + memory\r
- -- 4 => x"d000", -- SPI master\r
- -- 5 => x"d100", -- SPI data memory\r
- -- 6 => x"d010", -- ADC0 SPI\r
- -- 7 => x"d020", -- ADC1 SPI\r
- -- 8 => x"b000", -- APV control / status\r
- -- 9 => x"b010", -- ADC level settings\r
- -- 10 => x"b020", -- trigger settings\r
- -- 11 => x"b030", -- PLL settings\r
- -- 12 => x"f000", -- ADC 0 snooper\r
- -- 13 => x"f800", -- ADC 1 snooper\r
- -- 14 => x"8000", -- test register (busy)\r
- -- 15 => x"7100", -- data buffer status registers\r
- -- 16 => x"7200", -- LVL1 release status register\r
- -- 17 => x"7202", -- IPU handler status register\r
- others => x"0000"),\r
- PORT_ADDR_MASK => ( 0 => 16, -- pedestal memories\r
- 1 => 16, -- threshold memories\r
- 2 => 0, -- I2C master\r
- -- 3 => 6, -- 1Wire master + memory\r
- -- 4 => 1, -- SPI master\r
- -- 5 => 6, -- SPI data memory\r
- -- 6 => 0, -- ADC0 SPI\r
- -- 7 => 0, -- ADC1 SPI\r
- -- 8 => 4, -- APV control / status\r
- -- 9 => 0, -- ADC level settings\r
- -- 10 => 0, -- trigger settings\r
- -- 11 => 0, -- PLL settings\r
- -- 12 => 10, -- ADC 0 snooper\r
- -- 13 => 10, -- ADC 1 snooper\r
- -- 14 => 0, -- test register (normal)\r
- -- 15 => 4, -- FIFO status registers\r
- -- 16 => 0, -- LVL1 release status register\r
- -- 17 => 0, -- IPU handler status register\r
- others => 0)\r
- )\r
- port map(\r
- CLK => CLK_IN,\r
- RESET => RESET_IN,\r
- DAT_ADDR_IN => REGIO_ADDR_IN,\r
- DAT_DATA_IN => REGIO_DATA_IN,\r
- DAT_DATA_OUT => REGIO_DATA_OUT,\r
- DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,\r
- DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,\r
- DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,\r
- DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,\r
- DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,\r
- DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,\r
- DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,\r
-\r
- -- pedestal memories\r
- BUS_READ_ENABLE_OUT(0) => slv_read(0),\r
- BUS_WRITE_ENABLE_OUT(0) => slv_write(0),\r
- BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),\r
- BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),\r
- BUS_ADDR_OUT(0*16+15 downto 0*16) => slv_addr(0*16+15 downto 0*16),\r
- BUS_TIMEOUT_OUT(0) => open,\r
- BUS_DATAREADY_IN(0) => slv_ack(0),\r
- BUS_WRITE_ACK_IN(0) => slv_ack(0),\r
- BUS_NO_MORE_DATA_IN(0) => slv_busy(0),\r
- BUS_UNKNOWN_ADDR_IN(0) => '0',\r
-\r
- -- threshold memories\r
- BUS_READ_ENABLE_OUT(1) => slv_read(1),\r
- BUS_WRITE_ENABLE_OUT(1) => slv_write(1),\r
- BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),\r
- BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),\r
- BUS_ADDR_OUT(1*16+15 downto 1*16) => slv_addr(1*16+15 downto 1*16),\r
- BUS_TIMEOUT_OUT(1) => open,\r
- BUS_DATAREADY_IN(1) => slv_ack(1),\r
- BUS_WRITE_ACK_IN(1) => slv_ack(1),\r
- BUS_NO_MORE_DATA_IN(1) => slv_busy(1),\r
- BUS_UNKNOWN_ADDR_IN(1) => '0',\r
-\r
- -- I2C master\r
- BUS_READ_ENABLE_OUT(2) => slv_read(2),\r
- BUS_WRITE_ENABLE_OUT(2) => slv_write(2),\r
- BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),\r
- BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),\r
- BUS_ADDR_OUT(2*16+15 downto 2*16) => open,\r
- BUS_TIMEOUT_OUT(2) => open,\r
- BUS_DATAREADY_IN(2) => slv_ack(2),\r
- BUS_WRITE_ACK_IN(2) => slv_ack(2),\r
- BUS_NO_MORE_DATA_IN(2) => slv_busy(2),\r
- BUS_UNKNOWN_ADDR_IN(2) => '0',\r
-\r
- -- OneWire master\r
- --BUS_READ_ENABLE_OUT(3) => slv_read(3),\r
- --BUS_WRITE_ENABLE_OUT(3) => slv_write(3),\r
- --BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),\r
- --BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),\r
- --BUS_ADDR_OUT(3*16+15 downto 3*16) => slv_addr(3*16+15 downto 3*16),\r
- --BUS_TIMEOUT_OUT(3) => open,\r
- --BUS_DATAREADY_IN(3) => slv_ack(3),\r
- --BUS_WRITE_ACK_IN(3) => slv_ack(3),\r
- --BUS_NO_MORE_DATA_IN(3) => slv_busy(3),\r
- --BUS_UNKNOWN_ADDR_IN(3) => '0',\r
- ---- SPI control registers\r
- --BUS_READ_ENABLE_OUT(4) => slv_read(4),\r
- --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),\r
- --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),\r
- --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),\r
- --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),\r
- --BUS_TIMEOUT_OUT(4) => open,\r
- --BUS_DATAREADY_IN(4) => slv_ack(4),\r
- --BUS_WRITE_ACK_IN(4) => slv_ack(4),\r
- --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),\r
- --BUS_UNKNOWN_ADDR_IN(4) => '0',\r
- ---- SPI data memory\r
- --BUS_READ_ENABLE_OUT(5) => slv_read(5),\r
- --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),\r
- --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),\r
- --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),\r
- --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),\r
- --BUS_TIMEOUT_OUT(5) => open,\r
- --BUS_DATAREADY_IN(5) => slv_ack(5),\r
- --BUS_WRITE_ACK_IN(5) => slv_ack(5),\r
- --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),\r
- --BUS_UNKNOWN_ADDR_IN(5) => '0',\r
- ---- ADC 0 SPI control registers\r
- --BUS_READ_ENABLE_OUT(6) => slv_read(6),\r
- --BUS_WRITE_ENABLE_OUT(6) => slv_write(6),\r
- --BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32),\r
- --BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32),\r
- --BUS_ADDR_OUT(6*16+15 downto 6*16) => open,\r
- --BUS_TIMEOUT_OUT(6) => open,\r
- --BUS_DATAREADY_IN(6) => slv_ack(6),\r
- --BUS_WRITE_ACK_IN(6) => slv_ack(6),\r
- --BUS_NO_MORE_DATA_IN(6) => slv_busy(6),\r
- --BUS_UNKNOWN_ADDR_IN(6) => '0',\r
- ---- ADC 1 SPI control registers\r
- --BUS_READ_ENABLE_OUT(7) => slv_read(7),\r
- --BUS_WRITE_ENABLE_OUT(7) => slv_write(7),\r
- --BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32),\r
- --BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32),\r
- --BUS_ADDR_OUT(7*16+15 downto 7*16) => open,\r
- --BUS_TIMEOUT_OUT(7) => open,\r
- --BUS_DATAREADY_IN(7) => slv_ack(7),\r
- --BUS_WRITE_ACK_IN(7) => slv_ack(7),\r
- --BUS_NO_MORE_DATA_IN(7) => slv_busy(7),\r
- --BUS_UNKNOWN_ADDR_IN(7) => '0',\r
- ---- APV control / status registers\r
- --BUS_READ_ENABLE_OUT(8) => slv_read(8),\r
- --BUS_WRITE_ENABLE_OUT(8) => slv_write(8),\r
- --BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32),\r
- --BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32),\r
- --BUS_ADDR_OUT(8*16+15 downto 8*16) => slv_addr(8*16+15 downto 8*16),\r
- --BUS_TIMEOUT_OUT(8) => open,\r
- --BUS_DATAREADY_IN(8) => slv_ack(8),\r
- --BUS_WRITE_ACK_IN(8) => slv_ack(8),\r
- --BUS_NO_MORE_DATA_IN(8) => slv_busy(8),\r
- --BUS_UNKNOWN_ADDR_IN(8) => '0',\r
- ---- ADC / PLL / trigger ctrl register\r
- --BUS_READ_ENABLE_OUT(11 downto 9) => slv_read(11 downto 9),\r
- --BUS_WRITE_ENABLE_OUT(11 downto 9) => slv_write(11 downto 9),\r
- --BUS_DATA_OUT(11*32+31 downto 9*32) => slv_data_wr(11*32+31 downto 9*32),\r
- --BUS_DATA_IN(11*32+31 downto 9*32) => slv_data_rd(11*32+31 downto 9*32),\r
- --BUS_ADDR_OUT(11*16+15 downto 9*16) => open,\r
- --BUS_TIMEOUT_OUT(11 downto 9) => open,\r
- --BUS_DATAREADY_IN(11 downto 9) => slv_ack(11 downto 9),\r
- --BUS_WRITE_ACK_IN(11 downto 9) => slv_ack(11 downto 9),\r
- --BUS_NO_MORE_DATA_IN(11 downto 9) => slv_busy(11 downto 9),\r
- --BUS_UNKNOWN_ADDR_IN(11 downto 9) => (others => '0'),\r
- ---- ADC0 snooper\r
- --BUS_READ_ENABLE_OUT(12) => slv_read(12),\r
- --BUS_WRITE_ENABLE_OUT(12) => slv_write(12),\r
- --BUS_DATA_OUT(12*32+31 downto 12*32) => slv_data_wr(12*32+31 downto 12*32),\r
- --BUS_DATA_IN(12*32+31 downto 12*32) => slv_data_rd(12*32+31 downto 12*32),\r
- --BUS_ADDR_OUT(12*16+15 downto 12*16) => slv_addr(12*16+15 downto 12*16),\r
- --BUS_TIMEOUT_OUT(12) => open,\r
- --BUS_DATAREADY_IN(12) => slv_ack(12),\r
- --BUS_WRITE_ACK_IN(12) => slv_ack(12),\r
- --BUS_NO_MORE_DATA_IN(12) => slv_busy(12),\r
- --BUS_UNKNOWN_ADDR_IN(12) => '0',\r
- ---- ADC1 snooper\r
- --BUS_READ_ENABLE_OUT(13) => slv_read(13),\r
- --BUS_WRITE_ENABLE_OUT(13) => slv_write(13),\r
- --BUS_DATA_OUT(13*32+31 downto 13*32) => slv_data_wr(13*32+31 downto 13*32),\r
- --BUS_DATA_IN(13*32+31 downto 13*32) => slv_data_rd(13*32+31 downto 13*32),\r
- --BUS_ADDR_OUT(13*16+15 downto 13*16) => slv_addr(13*16+15 downto 13*16),\r
- --BUS_TIMEOUT_OUT(13) => open,\r
- --BUS_DATAREADY_IN(13) => slv_ack(13),\r
- --BUS_WRITE_ACK_IN(13) => slv_ack(13),\r
- --BUS_NO_MORE_DATA_IN(13) => slv_busy(13),\r
- --BUS_UNKNOWN_ADDR_IN(13) => '0',\r
- ---- Test register\r
- --BUS_READ_ENABLE_OUT(14) => slv_read(14),\r
- --BUS_WRITE_ENABLE_OUT(14) => slv_write(14),\r
- --BUS_DATA_OUT(14*32+31 downto 14*32) => slv_data_wr(14*32+31 downto 14*32),\r
- --BUS_DATA_IN(14*32+31 downto 14*32) => slv_data_rd(14*32+31 downto 14*32),\r
- --BUS_ADDR_OUT(14*16+15 downto 14*16) => open,\r
- --BUS_TIMEOUT_OUT(14) => open,\r
- --BUS_DATAREADY_IN(14) => slv_ack(14),\r
- --BUS_WRITE_ACK_IN(14) => slv_ack(14),\r
- --BUS_NO_MORE_DATA_IN(14) => slv_busy(14),\r
- --BUS_UNKNOWN_ADDR_IN(14) => '0',\r
- ---- data buffer status registers\r
- --BUS_READ_ENABLE_OUT(15) => slv_read(15),\r
- --BUS_WRITE_ENABLE_OUT(15) => slv_write(15),\r
- --BUS_DATA_OUT(15*32+31 downto 15*32) => slv_data_wr(15*32+31 downto 15*32),\r
- --BUS_DATA_IN(15*32+31 downto 15*32) => slv_data_rd(15*32+31 downto 15*32),\r
- --BUS_ADDR_OUT(15*16+15 downto 15*16) => slv_addr(15*16+15 downto 15*16),\r
- --BUS_TIMEOUT_OUT(15) => open,\r
- --BUS_DATAREADY_IN(15) => slv_ack(15),\r
- --BUS_WRITE_ACK_IN(15) => slv_ack(15),\r
- --BUS_NO_MORE_DATA_IN(15) => slv_busy(15),\r
- --BUS_UNKNOWN_ADDR_IN(15) => '0',\r
- ---- LVL1 release status register\r
- --BUS_READ_ENABLE_OUT(16) => slv_read(16),\r
- --BUS_WRITE_ENABLE_OUT(16) => slv_write(16),\r
- --BUS_DATA_OUT(16*32+31 downto 16*32) => slv_data_wr(16*32+31 downto 16*32),\r
- --BUS_DATA_IN(16*32+31 downto 16*32) => slv_data_rd(16*32+31 downto 16*32),\r
- --BUS_ADDR_OUT(16*16+15 downto 16*16) => slv_addr(16*16+15 downto 16*16),\r
- --BUS_TIMEOUT_OUT(16) => open,\r
- --BUS_DATAREADY_IN(16) => slv_ack(16),\r
- --BUS_WRITE_ACK_IN(16) => slv_ack(16),\r
- --BUS_NO_MORE_DATA_IN(16) => slv_busy(16),\r
- --BUS_UNKNOWN_ADDR_IN(16) => '0',\r
- ---- IPU handler status register\r
- --BUS_READ_ENABLE_OUT(17) => slv_read(17),\r
- --BUS_WRITE_ENABLE_OUT(17) => slv_write(17),\r
- --BUS_DATA_OUT(17*32+31 downto 17*32) => slv_data_wr(17*32+31 downto 17*32),\r
- --BUS_DATA_IN(17*32+31 downto 17*32) => slv_data_rd(17*32+31 downto 17*32),\r
- --BUS_ADDR_OUT(17*16+15 downto 17*16) => slv_addr(17*16+15 downto 17*16),\r
- --BUS_TIMEOUT_OUT(17) => open,\r
- --BUS_DATAREADY_IN(17) => slv_ack(17),\r
- --BUS_WRITE_ACK_IN(17) => slv_ack(17),\r
- --BUS_NO_MORE_DATA_IN(17) => slv_busy(17),\r
- --BUS_UNKNOWN_ADDR_IN(17) => '0',\r
- ---- debug\r
- --STAT_DEBUG => stat\r
- STAT_DEBUG => open\r
- );\r
-\r
-\r
-------------------------------------------------------------------------------------\r
--- pedestal memories (16x128 = 2048, 18bit)\r
-------------------------------------------------------------------------------------\r
- THE_PED_MEM: slv_ped_thr_mem\r
- port map(\r
- CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(0*16+10 downto 0*16),\r
- SLV_READ_IN => slv_read(0),\r
- SLV_WRITE_IN => slv_write(0),\r
- SLV_ACK_OUT => slv_ack(0),\r
- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),\r
- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),\r
- -- backplane identifier\r
- BACKPLANE_IN => bp_module_qq,\r
- -- I/O to the backend\r
- MEM_CLK_IN => CLK_IN,\r
- MEM_ADDR_IN => buf_addr,\r
- MEM_0_D_OUT => ped_data(0),\r
- MEM_1_D_OUT => ped_data(1),\r
- MEM_2_D_OUT => ped_data(2),\r
- MEM_3_D_OUT => ped_data(3),\r
- MEM_4_D_OUT => ped_data(4),\r
- MEM_5_D_OUT => ped_data(5),\r
- MEM_6_D_OUT => ped_data(6),\r
- MEM_7_D_OUT => ped_data(7),\r
- MEM_8_D_OUT => ped_data(8),\r
- MEM_9_D_OUT => ped_data(9),\r
- MEM_10_D_OUT => ped_data(10),\r
- MEM_11_D_OUT => ped_data(11),\r
- MEM_12_D_OUT => ped_data(12),\r
- MEM_13_D_OUT => ped_data(13),\r
- MEM_14_D_OUT => ped_data(14),\r
- MEM_15_D_OUT => ped_data(15),\r
- -- Status lines\r
- STAT => open\r
- );\r
- slv_busy(0) <= '0';\r
-\r
-------------------------------------------------------------------------------------\r
--- threshold memories (16x128 = 2048, 18bit)\r
-------------------------------------------------------------------------------------\r
- THE_THR_MEM: slv_ped_thr_mem\r
- port map(\r
- CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
- -- Slave bus\r
- SLV_ADDR_IN => slv_addr(1*16+10 downto 1*16),\r
- SLV_READ_IN => slv_read(1),\r
- SLV_WRITE_IN => slv_write(1),\r
- SLV_ACK_OUT => slv_ack(1),\r
- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),\r
- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),\r
- -- backplane identifier\r
- BACKPLANE_IN => bp_module_qq,\r
- -- I/O to the backend\r
- MEM_CLK_IN => CLK_IN,\r
- MEM_ADDR_IN => thr_addr,\r
- MEM_0_D_OUT => thr_data(0),\r
- MEM_1_D_OUT => thr_data(1),\r
- MEM_2_D_OUT => thr_data(2),\r
- MEM_3_D_OUT => thr_data(3),\r
- MEM_4_D_OUT => thr_data(4),\r
- MEM_5_D_OUT => thr_data(5),\r
- MEM_6_D_OUT => thr_data(6),\r
- MEM_7_D_OUT => thr_data(7),\r
- MEM_8_D_OUT => thr_data(8),\r
- MEM_9_D_OUT => thr_data(9),\r
- MEM_10_D_OUT => thr_data(10),\r
- MEM_11_D_OUT => thr_data(11),\r
- MEM_12_D_OUT => thr_data(12),\r
- MEM_13_D_OUT => thr_data(13),\r
- MEM_14_D_OUT => thr_data(14),\r
- MEM_15_D_OUT => thr_data(15),\r
- -- Status lines\r
- STAT => open\r
- );\r
- slv_busy(1) <= '0';\r
-\r
-------------------------------------------------------------------------------------\r
--- I2C master block for accessing APVs\r
-------------------------------------------------------------------------------------\r
- THE_I2C_MASTER: i2c_master\r
- port map(\r
- CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
- -- Slave bus\r
- SLV_READ_IN => slv_read(2),\r
- SLV_WRITE_IN => slv_write(2),\r
- SLV_BUSY_OUT => slv_busy(2),\r
- SLV_ACK_OUT => slv_ack(2),\r
- SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),\r
- SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),\r
- -- I2C connections\r
- SDA_IN => SDA_IN,\r
- SDA_OUT => SDA_OUT,\r
- SCL_IN => SCL_IN,\r
- SCL_OUT => SCL_OUT,\r
- -- Status lines\r
- STAT => open\r
- );\r
-\r
--- ------------------------------------------------------------------------------------\r
--- -- SPI master\r
--- ------------------------------------------------------------------------------------\r
--- THE_SPI_MASTER: spi_master\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- BUS_READ_IN => slv_read(4),\r
--- BUS_WRITE_IN => slv_write(4),\r
--- BUS_BUSY_OUT => slv_busy(4),\r
--- BUS_ACK_OUT => slv_ack(4),\r
--- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),\r
--- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),\r
--- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),\r
--- -- SPI connections\r
--- SPI_CS_OUT => spi_cs,\r
--- SPI_SDI_IN => spi_sdi,\r
--- SPI_SDO_OUT => spi_sdo,\r
--- SPI_SCK_OUT => spi_sck,\r
--- -- BRAM for read/write data\r
--- BRAM_A_OUT => spi_bram_addr,\r
--- BRAM_WR_D_IN => spi_bram_wr_d,\r
--- BRAM_RD_D_OUT => spi_bram_rd_d,\r
--- BRAM_WE_OUT => spi_bram_we,\r
--- -- Status lines\r
--- STAT => spi_debug --open\r
--- );\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- data memory for SPI accesses\r
--- ------------------------------------------------------------------------------------\r
--- THE_SPI_MEMORY: spi_databus_memory\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),\r
--- BUS_READ_IN => slv_read(5),\r
--- BUS_WRITE_IN => slv_write(5),\r
--- BUS_ACK_OUT => slv_ack(5),\r
--- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),\r
--- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),\r
--- -- state machine connections\r
--- BRAM_ADDR_IN => spi_bram_addr,\r
--- BRAM_WR_D_OUT => spi_bram_wr_d,\r
--- BRAM_RD_D_IN => spi_bram_rd_d,\r
--- BRAM_WE_IN => spi_bram_we,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- slv_busy(5) <= '0';\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- ADC0 SPI master\r
--- ------------------------------------------------------------------------------------\r
--- THE_SPI_ADC0_MASTER: spi_adc_master\r
--- generic map(\r
--- RESET_VALUE_CTRL => x"60"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(6),\r
--- SLV_WRITE_IN => slv_write(6),\r
--- SLV_BUSY_OUT => slv_busy(6),\r
--- SLV_ACK_OUT => slv_ack(6),\r
--- SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),\r
--- SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),\r
--- -- SPI connections\r
--- SPI_CS_OUT => SPI_ADC0_CS_OUT,\r
--- SPI_SDO_OUT => SPI_ADC0_SDO_OUT,\r
--- SPI_SCK_OUT => SPI_ADC0_SCK_OUT,\r
--- -- ADC connections\r
--- ADC_LOCKED_IN => ADC0_PLL_LOCKED_IN,\r
--- ADC_PD_OUT => ADC0_PD_OUT,\r
--- ADC_RST_OUT => ADC0_RST_OUT,\r
--- ADC_DEL_OUT => ADC0_DEL_OUT,\r
--- -- APV connections\r
--- APV_RST_OUT => APV0_RST_OUT,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- ADC1 SPI master\r
--- ------------------------------------------------------------------------------------\r
--- THE_SPI_ADC1_MASTER: spi_adc_master\r
--- generic map(\r
--- RESET_VALUE_CTRL => x"60"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(7),\r
--- SLV_WRITE_IN => slv_write(7),\r
--- SLV_BUSY_OUT => slv_busy(7),\r
--- SLV_ACK_OUT => slv_ack(7),\r
--- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),\r
--- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),\r
--- -- SPI connections\r
--- SPI_CS_OUT => SPI_ADC1_CS_OUT,\r
--- SPI_SDO_OUT => SPI_ADC1_SDO_OUT,\r
--- SPI_SCK_OUT => SPI_ADC1_SCK_OUT,\r
--- -- ADC connections\r
--- ADC_LOCKED_IN => ADC1_PLL_LOCKED_IN,\r
--- ADC_PD_OUT => ADC1_PD_OUT,\r
--- ADC_RST_OUT => ADC1_RST_OUT,\r
--- ADC_DEL_OUT => ADC1_DEL_OUT,\r
--- -- APV connections\r
--- APV_RST_OUT => APV1_RST_OUT,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- APV control / status registers\r
--- ------------------------------------------------------------------------------------\r
--- THE_SLV_REGISTER_BANK: slv_register_bank\r
--- generic map(\r
--- RESET_VALUE => x"0001"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_ADDR_IN => slv_addr(8*16+3 downto 8*16),\r
--- SLV_READ_IN => slv_read(8),\r
--- SLV_WRITE_IN => slv_write(8),\r
--- SLV_ACK_OUT => slv_ack(8),\r
--- SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32),\r
--- SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32),\r
--- -- I/O to the backend\r
--- BACKPLANE_IN => BACKPLANE_IN,\r
--- CTRL_0_OUT => CTRL_0_OUT,\r
--- CTRL_1_OUT => CTRL_1_OUT,\r
--- CTRL_2_OUT => CTRL_2_OUT,\r
--- CTRL_3_OUT => CTRL_3_OUT,\r
--- CTRL_4_OUT => CTRL_4_OUT,\r
--- CTRL_5_OUT => CTRL_5_OUT,\r
--- CTRL_6_OUT => CTRL_6_OUT,\r
--- CTRL_7_OUT => CTRL_7_OUT,\r
--- CTRL_8_OUT => CTRL_8_OUT,\r
--- CTRL_9_OUT => CTRL_9_OUT,\r
--- CTRL_10_OUT => CTRL_10_OUT,\r
--- CTRL_11_OUT => CTRL_11_OUT,\r
--- CTRL_12_OUT => CTRL_12_OUT,\r
--- CTRL_13_OUT => CTRL_13_OUT,\r
--- CTRL_14_OUT => CTRL_14_OUT,\r
--- CTRL_15_OUT => CTRL_15_OUT,\r
--- STAT_0_IN => STAT_0_IN,\r
--- STAT_1_IN => STAT_1_IN,\r
--- STAT_2_IN => STAT_2_IN,\r
--- STAT_3_IN => STAT_3_IN,\r
--- STAT_4_IN => STAT_4_IN,\r
--- STAT_5_IN => STAT_5_IN,\r
--- STAT_6_IN => STAT_6_IN,\r
--- STAT_7_IN => STAT_7_IN,\r
--- STAT_8_IN => STAT_8_IN,\r
--- STAT_9_IN => STAT_9_IN,\r
--- STAT_10_IN => STAT_10_IN,\r
--- STAT_11_IN => STAT_11_IN,\r
--- STAT_12_IN => STAT_12_IN,\r
--- STAT_13_IN => STAT_13_IN,\r
--- STAT_14_IN => STAT_14_IN,\r
--- STAT_15_IN => STAT_15_IN,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- slv_busy(8) <= '0';\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- Data buffer status registers\r
--- ------------------------------------------------------------------------------------\r
--- THE_FIFO_STATUS_BANK: slv_status_bank\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_ADDR_IN => slv_addr(15*16+3 downto 15*16),\r
--- SLV_READ_IN => slv_read(15),\r
--- SLV_WRITE_IN => slv_write(15),\r
--- SLV_ACK_OUT => slv_ack(15),\r
--- SLV_DATA_OUT => slv_data_rd(15*32+31 downto 15*32),\r
--- -- I/O to the backend\r
--- STAT_0_IN => FIFO_STATUS_0_IN,\r
--- STAT_1_IN => FIFO_STATUS_1_IN,\r
--- STAT_2_IN => FIFO_STATUS_2_IN,\r
--- STAT_3_IN => FIFO_STATUS_3_IN,\r
--- STAT_4_IN => FIFO_STATUS_4_IN,\r
--- STAT_5_IN => FIFO_STATUS_5_IN,\r
--- STAT_6_IN => FIFO_STATUS_6_IN,\r
--- STAT_7_IN => FIFO_STATUS_7_IN,\r
--- STAT_8_IN => FIFO_STATUS_8_IN,\r
--- STAT_9_IN => FIFO_STATUS_9_IN,\r
--- STAT_10_IN => FIFO_STATUS_10_IN,\r
--- STAT_11_IN => FIFO_STATUS_11_IN,\r
--- STAT_12_IN => FIFO_STATUS_12_IN,\r
--- STAT_13_IN => FIFO_STATUS_13_IN,\r
--- STAT_14_IN => FIFO_STATUS_14_IN,\r
--- STAT_15_IN => FIFO_STATUS_15_IN\r
--- );\r
--- slv_busy(15) <= '0';\r
--- \r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- LVL1 release status\r
--- ------------------------------------------------------------------------------------\r
--- THE_LVL1_RELEASE_STATUS: slv_status\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(16),\r
--- SLV_WRITE_IN => slv_write(16),\r
--- SLV_ACK_OUT => slv_ack(16),\r
--- SLV_DATA_OUT => slv_data_rd(16*32+31 downto 16*32),\r
--- -- I/O to the backend\r
--- STATUS_IN => RELEASE_STATUS_IN\r
--- );\r
--- slv_busy(16) <= '0';\r
--- \r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- IPU handler status\r
--- ------------------------------------------------------------------------------------\r
--- THE_IPU_HANDLER_STATUS: slv_status\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(17),\r
--- SLV_WRITE_IN => slv_write(17),\r
--- SLV_ACK_OUT => slv_ack(17),\r
--- SLV_DATA_OUT => slv_data_rd(17*32+31 downto 17*32),\r
--- -- I/O to the backend\r
--- STATUS_IN => IPU_STATUS_IN\r
--- );\r
--- slv_busy(17) <= '0';\r
--- \r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- ADC level register\r
--- ------------------------------------------------------------------------------------\r
--- THE_ADC_LVL_REG: slv_register\r
--- generic map(\r
--- RESET_VALUE => x"d0_20_88_78"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN, -- general reset\r
--- BUSY_IN => '0',\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(9),\r
--- SLV_WRITE_IN => slv_write(9),\r
--- SLV_BUSY_OUT => slv_busy(9),\r
--- SLV_ACK_OUT => slv_ack(9),\r
--- SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),\r
--- SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),\r
--- -- I/O to the backend\r
--- REG_DATA_IN => ctrl_lvl,\r
--- REG_DATA_OUT => ctrl_lvl,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- trigger control register\r
--- ------------------------------------------------------------------------------------\r
--- THE_TRG_CTRL_REG: slv_register\r
--- generic map(\r
--- RESET_VALUE => x"10_10_10_10"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN, -- general reset\r
--- BUSY_IN => '0',\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(10),\r
--- SLV_WRITE_IN => slv_write(10),\r
--- SLV_BUSY_OUT => slv_busy(10),\r
--- SLV_ACK_OUT => slv_ack(10),\r
--- SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32),\r
--- SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),\r
--- -- I/O to the backend\r
--- REG_DATA_IN => ctrl_trg,\r
--- REG_DATA_OUT => ctrl_trg,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- PLL control register\r
--- ------------------------------------------------------------------------------------\r
--- THE_PLL_CTRL_REG: slv_half_register\r
--- generic map(\r
--- RESET_VALUE => x"00_02"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN, -- general reset\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(11),\r
--- SLV_WRITE_IN => slv_write(11),\r
--- SLV_ACK_OUT => slv_ack(11),\r
--- SLV_DATA_IN => slv_data_wr(11*32+31 downto 11*32),\r
--- SLV_DATA_OUT => slv_data_rd(11*32+31 downto 11*32),\r
--- -- I/O to the backend\r
--- STATUS_REG_IN => STATUS_PLL_IN,\r
--- CTRL_REG_OUT => ctrl_pll,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- slv_busy(11) <= '0';\r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- ADC0 snooper\r
--- ------------------------------------------------------------------------------------\r
--- THE_ADC0_SNOOPER: slv_adc_snoop\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_ADDR_IN => slv_addr(12*16+9 downto 12*16),\r
--- SLV_READ_IN => slv_read(12),\r
--- SLV_WRITE_IN => slv_write(12),\r
--- SLV_ACK_OUT => slv_ack(12),\r
--- SLV_DATA_IN => slv_data_wr(12*32+31 downto 12*32),\r
--- SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32),\r
--- -- I/O to the backend\r
--- ADC_SEL_OUT => ADC0_SEL_OUT,\r
--- ADC_CLK_IN => ADC0_CLK_IN,\r
--- ADC_DATA_IN => ADC0_DATA_IN,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- slv_busy(12) <= '0';\r
--- \r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- ADC1 snooper\r
--- ------------------------------------------------------------------------------------\r
--- THE_ADC1_SNOOPER: slv_adc_snoop\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- -- Slave bus\r
--- SLV_ADDR_IN => slv_addr(13*16+9 downto 13*16),\r
--- SLV_READ_IN => slv_read(13),\r
--- SLV_WRITE_IN => slv_write(13),\r
--- SLV_ACK_OUT => slv_ack(13),\r
--- SLV_DATA_IN => slv_data_wr(13*32+31 downto 13*32),\r
--- SLV_DATA_OUT => slv_data_rd(13*32+31 downto 13*32),\r
--- -- I/O to the backend\r
--- ADC_SEL_OUT => ADC1_SEL_OUT,\r
--- ADC_CLK_IN => ADC1_CLK_IN,\r
--- ADC_DATA_IN => ADC1_DATA_IN,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- slv_busy(13) <= '0';\r
--- \r
--- \r
--- ------------------------------------------------------------------------------------\r
--- -- test register (normal)\r
--- ------------------------------------------------------------------------------------\r
--- THE_GOOD_TEST_REG: slv_register\r
--- generic map(\r
--- RESET_VALUE => x"dead_beef"\r
--- )\r
--- port map(\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN, -- general reset\r
--- BUSY_IN => '0',\r
--- -- Slave bus\r
--- SLV_READ_IN => slv_read(14),\r
--- SLV_WRITE_IN => slv_write(14),\r
--- SLV_BUSY_OUT => slv_busy(14),\r
--- SLV_ACK_OUT => slv_ack(14),\r
--- SLV_DATA_IN => slv_data_wr(14*32+31 downto 14*32),\r
--- SLV_DATA_OUT => slv_data_rd(14*32+31 downto 14*32),\r
--- -- I/O to the backend\r
--- REG_DATA_IN => TEST_REG_IN, --x"5a3c_87e1",\r
--- REG_DATA_OUT => TEST_REG_OUT,\r
--- -- Status lines\r
--- STAT => open\r
--- );\r
--- \r
--- \r
-\r
-\r
--- unusable pins\r
- debug(63 downto 43) <= (others => '0');\r
--- connected pins\r
- debug(42 downto 0) <= (others => '0');\r
-\r
--- input signals\r
- spi_sdi <= SPI_SDI_IN;\r
-\r
--- Output signals\r
- SPI_CS_OUT <= spi_cs;\r
- SPI_SCK_OUT <= spi_sck;\r
- SPI_SDO_OUT <= spi_sdo;\r
-\r
- -- CTRL_LVL_OUT <= ctrl_lvl;\r
- -- CTRL_TRG_OUT <= ctrl_trg;\r
- -- CTRL_PLL_OUT <= ctrl_pll;\r
-\r
- -- DEBUG_OUT <= debug;\r
-\r
-end Behavioral;\r
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.adcmv3_components.all;
+use work.nxyter_components.all;
+
+entity slave_bus is
+ port(
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- RegIO signals
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint
+ REGIO_READ_ENABLE_IN : in std_logic; -- read pulse
+ REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse
+ REGIO_TIMEOUT_IN : in std_logic; -- access timed out
+ REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested
+ REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted
+ REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request
+
+ -- I2C connections
+ SDA_IN : in std_logic;
+ SDA_OUT : out std_logic;
+ SCL_IN : in std_logic;
+ SCL_OUT : out std_logic;
+
+ -- SPI connections
+ SPI_CS_OUT : out std_logic;
+ SPI_SCK_OUT : out std_logic;
+ SPI_SDI_IN : in std_logic;
+ SPI_SDO_OUT : out std_logic;
+
+ -- Timestamp Read
+ NX_CLK128_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector(7 downto 0)
+ );
+end entity;
+
+architecture Behavioral of slave_bus is
+
+-- Signals
+ signal slv_read : std_logic_vector(8-1 downto 0);
+ signal slv_write : std_logic_vector(8-1 downto 0);
+ signal slv_busy : std_logic_vector(8-1 downto 0);
+ signal slv_ack : std_logic_vector(8-1 downto 0);
+ signal slv_addr : std_logic_vector(8*16-1 downto 0);
+ signal slv_data_rd : std_logic_vector(8*32-1 downto 0);
+ signal slv_data_wr : std_logic_vector(8*32-1 downto 0);
+ signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
+
+-- SPI controller BRAM lines
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal spi_cs : std_logic;
+ signal spi_sck : std_logic;
+ signal spi_sdi : std_logic;
+ signal spi_sdo : std_logic;
+ signal spi_debug : std_logic_vector(31 downto 0);
+
+ signal ctrl_lvl : std_logic_vector(31 downto 0);
+ signal ctrl_trg : std_logic_vector(31 downto 0);
+ signal ctrl_pll : std_logic_vector(15 downto 0);
+
+ signal debug : std_logic_vector(63 downto 0);
+
+ -- Register Stuff
+ -- type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);
+
+ signal reg_data : std_logic_vector(31 downto 0);
+
+
+begin
+
+-- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus
+ THE_BUS_HANDLER: trb_net16_regio_bus_handler
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
+ 1 => x"0040", -- I2C master
+ 2 => x"0100", -- Timestamp Fifo
+ -- 3 => x"d100", -- SPI data memory
+ others => x"0000"),
+ PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
+ 1 => 0, -- I2C master
+ 2 => 2, -- Timestamp Fifo
+ -- 3 => 6, -- SPI data memory
+ others => 0)
+ )
+ port map(
+ CLK => CLK_IN,
+ RESET => RESET_IN,
+ DAT_ADDR_IN => REGIO_ADDR_IN,
+ DAT_DATA_IN => REGIO_DATA_IN,
+ DAT_DATA_OUT => REGIO_DATA_OUT,
+ DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN,
+ DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN,
+ DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN,
+ DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT,
+ DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT,
+ DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT,
+ DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT,
+
+ -- Control Registers
+ BUS_READ_ENABLE_OUT(0) => slv_read(0),
+ BUS_WRITE_ENABLE_OUT(0) => slv_write(0),
+ BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32),
+ BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32),
+ BUS_ADDR_OUT(0*16+2 downto 0*16) => slv_addr(0*16+2 downto 0*16),
+ BUS_ADDR_OUT(0*16+15 downto 0*16+3) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATAREADY_IN(0) => slv_ack(0),
+ BUS_WRITE_ACK_IN(0) => slv_ack(0),
+ BUS_NO_MORE_DATA_IN(0) => slv_busy(0),
+ BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0),
+
+ -- I2C master
+ BUS_READ_ENABLE_OUT(1) => slv_read(1),
+ BUS_WRITE_ENABLE_OUT(1) => slv_write(1),
+ BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32),
+ BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32),
+ BUS_ADDR_OUT(1*16+15 downto 1*16) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATAREADY_IN(1) => slv_ack(1),
+ BUS_WRITE_ACK_IN(1) => slv_ack(1),
+ BUS_NO_MORE_DATA_IN(1) => slv_busy(1),
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
+
+ -- Timestamp Fifo
+ BUS_READ_ENABLE_OUT(2) => slv_read(2),
+ BUS_WRITE_ENABLE_OUT(2) => slv_write(2),
+ BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32),
+ BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32),
+ BUS_ADDR_OUT(2*16+1 downto 2*16) => slv_addr(2*16+1 downto 2*16),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open,
+ BUS_TIMEOUT_OUT(2) => open,
+ BUS_DATAREADY_IN(2) => slv_ack(2),
+ BUS_WRITE_ACK_IN(2) => slv_ack(2),
+ BUS_NO_MORE_DATA_IN(2) => slv_busy(2),
+ BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2),
+
+ ---- SPI control registers
+ --BUS_READ_ENABLE_OUT(4) => slv_read(4),
+ --BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
+ --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),
+ --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),
+ --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16),
+ --BUS_TIMEOUT_OUT(4) => open,
+ --BUS_DATAREADY_IN(4) => slv_ack(4),
+ --BUS_WRITE_ACK_IN(4) => slv_ack(4),
+ --BUS_NO_MORE_DATA_IN(4) => slv_busy(4),
+ --BUS_UNKNOWN_ADDR_IN(4) => '0',
+ ---- SPI data memory
+ --BUS_READ_ENABLE_OUT(5) => slv_read(5),
+ --BUS_WRITE_ENABLE_OUT(5) => slv_write(5),
+ --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32),
+ --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32),
+ --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16),
+ --BUS_TIMEOUT_OUT(5) => open,
+ --BUS_DATAREADY_IN(5) => slv_ack(5),
+ --BUS_WRITE_ACK_IN(5) => slv_ack(5),
+ --BUS_NO_MORE_DATA_IN(5) => slv_busy(5),
+ --BUS_UNKNOWN_ADDR_IN(5) => '0',
+
+ ---- debug
+ --STAT_DEBUG => stat
+ STAT_DEBUG => open
+ );
+
+-------------------------------------------------------------------------------
+-- Registers
+-------------------------------------------------------------------------------
+ nxyter_registers_1: nxyter_registers
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+
+ SLV_READ_IN => slv_read(0),
+ SLV_WRITE_IN => slv_write(0),
+ SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
+ SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
+ SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16),
+ SLV_ACK_OUT => slv_ack(0),
+ SLV_NO_MORE_DATA_OUT => slv_busy(0),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0)
+ );
+
+-------------------------------------------------------------------------------
+-- I2C master block for accessing APVs
+-------------------------------------------------------------------------------
+ THE_I2C_MASTER: i2c_master
+ port map(
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ -- Slave bus
+ SLV_READ_IN => slv_read(1),
+ SLV_WRITE_IN => slv_write(1),
+ SLV_BUSY_OUT => slv_busy(1),
+ SLV_ACK_OUT => slv_ack(1),
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+ -- I2C connections
+ SDA_IN => SDA_IN,
+ SDA_OUT => SDA_OUT,
+ SCL_IN => SCL_IN,
+ SCL_OUT => SCL_OUT,
+ -- Status lines
+ STAT => open
+ );
+-------------------------------------------------------------------------------
+-- TimeStamp Read
+-------------------------------------------------------------------------------
+ nx_timestamp_read_1: nx_timestamp_read
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NX_CLK128_IN => NX_CLK128_IN,
+ NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
+
+ SLV_READ_IN => slv_read(2),
+ SLV_WRITE_IN => slv_write(2),
+ SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
+ SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32),
+ SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16),
+ SLV_ACK_OUT => slv_ack(2),
+ SLV_NO_MORE_DATA_OUT => slv_busy(2),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2)
+ );
+
+-----------------------------------------------------------------------------
+-- Test Register
+-----------------------------------------------------------------------------
+-- slv_register_1: slv_register
+-- generic map (
+-- RESET_VALUE => x"dead_beef"
+-- )
+-- port map (
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- BUSY_IN => '0',
+--
+-- SLV_READ_IN => slv_read(0),
+-- SLV_WRITE_IN => slv_write(0),
+-- SLV_BUSY_OUT => slv_busy(0),
+-- SLV_ACK_OUT => slv_ack(0),
+-- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32),
+-- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32),
+--
+-- REG_DATA_IN => reg_data_in,
+-- REG_DATA_OUT => reg_data_out,
+-- STAT => open
+-- );
+-- slv_busy(0) <= '0';
+
+-- ------------------------------------------------------------------------------------
+-- -- SPI master
+-- ------------------------------------------------------------------------------------
+-- THE_SPI_MASTER: spi_master
+-- port map(
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- -- Slave bus
+-- BUS_READ_IN => slv_read(4),
+-- BUS_WRITE_IN => slv_write(4),
+-- BUS_BUSY_OUT => slv_busy(4),
+-- BUS_ACK_OUT => slv_ack(4),
+-- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16),
+-- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
+-- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
+-- -- SPI connections
+-- SPI_CS_OUT => spi_cs,
+-- SPI_SDI_IN => spi_sdi,
+-- SPI_SDO_OUT => spi_sdo,
+-- SPI_SCK_OUT => spi_sck,
+-- -- BRAM for read/write data
+-- BRAM_A_OUT => spi_bram_addr,
+-- BRAM_WR_D_IN => spi_bram_wr_d,
+-- BRAM_RD_D_OUT => spi_bram_rd_d,
+-- BRAM_WE_OUT => spi_bram_we,
+-- -- Status lines
+-- STAT => spi_debug --open
+-- );
+--
+-- ------------------------------------------------------------------------------------
+-- -- data memory for SPI accesses
+-- ------------------------------------------------------------------------------------
+-- THE_SPI_MEMORY: spi_databus_memory
+-- port map(
+-- CLK_IN => CLK_IN,
+-- RESET_IN => RESET_IN,
+-- -- Slave bus
+-- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16),
+-- BUS_READ_IN => slv_read(5),
+-- BUS_WRITE_IN => slv_write(5),
+-- BUS_ACK_OUT => slv_ack(5),
+-- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
+-- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32),
+-- -- state machine connections
+-- BRAM_ADDR_IN => spi_bram_addr,
+-- BRAM_WR_D_OUT => spi_bram_wr_d,
+-- BRAM_RD_D_IN => spi_bram_rd_d,
+-- BRAM_WE_IN => spi_bram_we,
+-- -- Status lines
+-- STAT => open
+-- );
+-- slv_busy(5) <= '0';
+--
+
+-- unusable pins
+ debug(63 downto 43) <= (others => '0');
+-- connected pins
+ debug(42 downto 0) <= (others => '0');
+
+-- input signals
+ spi_sdi <= SPI_SDI_IN;
+
+-- Output signals
+ SPI_CS_OUT <= spi_cs;
+ SPI_SCK_OUT <= spi_sck;
+ SPI_SDO_OUT <= spi_sdo;
+
+end Behavioral;
SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
\r
- -- backplane identifier\r
- BACKPLANE_IN : in std_logic_vector(2 downto 0);\r
-\r
-- I/O to the backend\r
MEM_CLK_IN : in std_logic;\r
MEM_ADDR_IN : in std_logic_vector(6 downto 0);\r
MEM_0_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_1_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_2_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_3_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_4_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_5_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_6_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_7_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_8_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_9_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_10_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_11_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_12_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_13_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_14_D_OUT : out std_logic_vector(17 downto 0);\r
- MEM_15_D_OUT : out std_logic_vector(17 downto 0);\r
\r
-- Status lines\r
STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
\r
signal block_addr : std_logic_vector(3 downto 0);\r
\r
- type ped_data_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
- signal ped_data : ped_data_t;\r
- signal mem_data : ped_data_t;\r
+ signal ped_data : std_logic_vector(17 downto 0);\r
+ signal mem_data : std_logic_vector(17 downto 0);\r
\r
- signal mem_wr_x : std_logic_vector(15 downto 0);\r
- signal mem_wr : std_logic_vector(15 downto 0);\r
- signal mem_sel : std_logic_vector(15 downto 0);\r
+ signal mem_wr_x : std_logic;\r
+ signal mem_wr : std_logic;\r
+ signal mem_sel : std_logic;\r
\r
signal rdback_data : std_logic_vector(17 downto 0);\r
\r
---------------------------------------------------------\r
-- Mapping of backplanes --\r
---------------------------------------------------------\r
- THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
- port map (\r
- ADDRESS(6 downto 4) => backplane_in,\r
- ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
- Q => block_addr\r
- );\r
-\r
+-- THE_APV_ADC_MAP_MEM: apv_adc_map_mem\r
+-- port map (\r
+-- ADDRESS(6 downto 4) => backplane_in,\r
+-- ADDRESS(3 downto 0) => slv_addr_in(10 downto 7),\r
+-- Q => block_addr\r
+-- );\r
+--\r
THE_MEM_SEL_PROC: process( clk_in )\r
begin\r
if( rising_edge(clk_in) ) then\r
- case block_addr is\r
- when x"0" => mem_sel <= b"0000_0000_0000_0001";\r
- rdback_data <= mem_data(0);\r
- when x"1" => mem_sel <= b"0000_0000_0000_0010";\r
- rdback_data <= mem_data(1);\r
- when x"2" => mem_sel <= b"0000_0000_0000_0100";\r
- rdback_data <= mem_data(2);\r
- when x"3" => mem_sel <= b"0000_0000_0000_1000";\r
- rdback_data <= mem_data(3);\r
- when x"4" => mem_sel <= b"0000_0000_0001_0000";\r
- rdback_data <= mem_data(4);\r
- when x"5" => mem_sel <= b"0000_0000_0010_0000";\r
- rdback_data <= mem_data(5);\r
- when x"6" => mem_sel <= b"0000_0000_0100_0000";\r
- rdback_data <= mem_data(6);\r
- when x"7" => mem_sel <= b"0000_0000_1000_0000";\r
- rdback_data <= mem_data(7);\r
- when x"8" => mem_sel <= b"0000_0001_0000_0000";\r
- rdback_data <= mem_data(8);\r
- when x"9" => mem_sel <= b"0000_0010_0000_0000";\r
- rdback_data <= mem_data(9);\r
- when x"a" => mem_sel <= b"0000_0100_0000_0000";\r
- rdback_data <= mem_data(10);\r
- when x"b" => mem_sel <= b"0000_1000_0000_0000";\r
- rdback_data <= mem_data(11);\r
- when x"c" => mem_sel <= b"0001_0000_0000_0000";\r
- rdback_data <= mem_data(12);\r
- when x"d" => mem_sel <= b"0010_0000_0000_0000";\r
- rdback_data <= mem_data(13);\r
- when x"e" => mem_sel <= b"0100_0000_0000_0000";\r
- rdback_data <= mem_data(14);\r
- when x"f" => mem_sel <= b"1000_0000_0000_0000";\r
- rdback_data <= mem_data(15);\r
- when others => mem_sel <= b"0000_0000_0000_0000"; -- never used\r
- rdback_data <= (others => '0');\r
- end case;\r
+ mem_sel <= '1';\r
+ rdback_data <= mem_data;\r
end if;\r
end process THE_MEM_SEL_PROC;\r
\r
---------------------------------------------------------\r
-- block memories --\r
---------------------------------------------------------\r
- GEN_PED_MEM: for i in 0 to 15 generate\r
- -- Port A: SLV_BUS\r
- -- Port B: state machine\r
- THE_PED_MEM: ped_thr_true\r
- port map(\r
- DATAINA => slv_data_in(17 downto 0),\r
- DATAINB => b"00_0000_0000_0000_0000",\r
- ADDRESSA => slv_addr_in(6 downto 0),\r
- ADDRESSB => mem_addr_in,\r
- CLOCKA => clk_in,\r
- CLOCKB => mem_clk_in,\r
- CLOCKENA => '1',\r
- CLOCKENB => '1',\r
- WRA => mem_wr(i), -- BUGBUGBUG\r
- WRB => '0', -- state machine never writes!\r
- RESETA => reset_in,\r
- RESETB => reset_in,\r
- QA => mem_data(i),\r
- QB => ped_data(i)\r
- );\r
- -- Write signals\r
- mem_wr_x(i) <= '1' when ( (mem_sel(i) = '1') and (store_wr = '1') ) else '0';\r
- end generate GEN_PED_MEM;\r
+ -- Port A: SLV_BUS\r
+ -- Port B: state machine\r
+ THE_PED_MEM: ped_thr_true\r
+ port map(\r
+ DATAINA => slv_data_in(17 downto 0),\r
+ DATAINB => b"00_0000_0000_0000_0000",\r
+ ADDRESSA => slv_addr_in(6 downto 0),\r
+ ADDRESSB => mem_addr_in,\r
+ CLOCKA => clk_in,\r
+ CLOCKB => mem_clk_in,\r
+ CLOCKENA => '1',\r
+ CLOCKENB => '1',\r
+ WRA => mem_wr, -- BUGBUGBUG\r
+ WRB => '0', -- state machine never writes!\r
+ RESETA => reset_in,\r
+ RESETB => reset_in,\r
+ QA => mem_data,\r
+ QB => ped_data\r
+ );\r
+-- Write signals\r
+ mem_wr_x <= '1' when ( (mem_sel = '1') and (store_wr = '1') ) else '0';\r
+\r
\r
-- Synchronize\r
THE_SYNC_PROC: process(clk_in)\r
slv_ack_out <= slv_ack;\r
slv_data_out <= b"0000_0000_0000_00" & rdback_data;\r
\r
- mem_0_d_out <= ped_data(0);\r
- mem_1_d_out <= ped_data(1);\r
- mem_2_d_out <= ped_data(2);\r
- mem_3_d_out <= ped_data(3);\r
- mem_4_d_out <= ped_data(4);\r
- mem_5_d_out <= ped_data(5);\r
- mem_6_d_out <= ped_data(6);\r
- mem_7_d_out <= ped_data(7);\r
- mem_8_d_out <= ped_data(8);\r
- mem_9_d_out <= ped_data(9);\r
- mem_10_d_out <= ped_data(10);\r
- mem_11_d_out <= ped_data(11);\r
- mem_12_d_out <= ped_data(12);\r
- mem_13_d_out <= ped_data(13);\r
- mem_14_d_out <= ped_data(14);\r
- mem_15_d_out <= ped_data(15);\r
+ mem_0_d_out <= ped_data;\r
\r
stat(31 downto 20) <= (others => '0');\r
stat(19 downto 16) <= block_addr;\r
- stat(15 downto 0) <= mem_sel;\r
+ stat(15 downto 1) <= (others => '0');\r
+ stat(0) <= mem_sel;\r
\r
end Behavioral;\r
+++ /dev/null
-library IEEE;\r
-use IEEE.STD_LOGIC_1164.ALL;\r
-use IEEE.STD_LOGIC_ARITH.ALL;\r
-use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
-\r
-library work;\r
-use work.adcmv3_components.all;\r
-\r
-entity slv_register is\r
- generic(\r
- RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000"\r
- );\r
- port(\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
- BUSY_IN : in std_logic;\r
- -- Slave bus\r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_BUSY_OUT : out std_logic;\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- I/O to the backend\r
- REG_DATA_IN : in std_logic_vector(31 downto 0);\r
- REG_DATA_OUT : out std_logic_vector(31 downto 0);\r
- -- Status lines\r
- STAT : out std_logic_vector(31 downto 0) -- DEBUG\r
- );\r
-end entity;\r
-\r
-architecture Behavioral of slv_register is\r
-\r
--- Signals\r
- type STATES is (SLEEP,\r
- RD_BSY,\r
- WR_BSY,\r
- RD_RDY,\r
- WR_RDY,\r
- RD_ACK,\r
- WR_ACK,\r
- DONE\r
- );\r
- signal CURRENT_STATE, NEXT_STATE: STATES;\r
-\r
--- slave bus signals\r
- signal slv_busy_x : std_logic;\r
- signal slv_busy : std_logic;\r
- signal slv_ack_x : std_logic;\r
- signal slv_ack : std_logic;\r
- signal store_wr_x : std_logic;\r
- signal store_wr : std_logic;\r
- signal store_rd_x : std_logic;\r
- signal store_rd : std_logic;\r
-\r
- signal reg_slv_data_in : std_logic_vector(31 downto 0); -- registered data input\r
- signal reg_slv_data_out : std_logic_vector(31 downto 0); -- read back data\r
- signal reg_busy : std_logic;\r
-\r
-begin\r
-\r
--- Fake\r
- reg_busy <= busy_in;\r
- stat <= (others => '0');\r
-\r
----------------------------------------------------------\r
--- Statemachine --\r
----------------------------------------------------------\r
--- State memory process\r
- PROC_STATE_MEM: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- if( reset_in = '1' ) then\r
- CURRENT_STATE <= SLEEP;\r
- slv_busy <= '0';\r
- slv_ack <= '0';\r
- store_wr <= '0';\r
- store_rd <= '0';\r
- else\r
- CURRENT_STATE <= NEXT_STATE;\r
- slv_busy <= slv_busy_x;\r
- slv_ack <= slv_ack_x;\r
- store_wr <= store_wr_x;\r
- store_rd <= store_rd_x;\r
- end if;\r
- end if;\r
- end process PROC_STATE_MEM;\r
-\r
--- Transition matrix\r
- PROC_TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy)\r
- begin\r
- NEXT_STATE <= SLEEP;\r
- slv_busy_x <= '0';\r
- slv_ack_x <= '0';\r
- store_wr_x <= '0';\r
- store_rd_x <= '0';\r
-\r
- case CURRENT_STATE is\r
-\r
- when SLEEP =>\r
- if ( (reg_busy = '0') and (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_RDY;\r
- store_rd_x <= '1';\r
- elsif( (reg_busy = '0') and (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_RDY;\r
- store_wr_x <= '1';\r
- elsif( (reg_busy = '1') and (slv_read_in = '1') ) then\r
- NEXT_STATE <= RD_BSY;\r
- slv_busy_x <= '1'; \r
- elsif( (reg_busy = '1') and (slv_write_in = '1') ) then\r
- NEXT_STATE <= WR_BSY;\r
- slv_busy_x <= '1'; \r
- else\r
- NEXT_STATE <= SLEEP;\r
- end if;\r
-\r
- when RD_RDY =>\r
- NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
-\r
- when WR_RDY =>\r
- NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
-\r
- when RD_ACK =>\r
- if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
-\r
- when WR_ACK =>\r
- if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_ACK;\r
- slv_ack_x <= '1';\r
- end if;\r
-\r
- when RD_BSY =>\r
- if( slv_read_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= RD_BSY;\r
- slv_busy_x <= '1';\r
- end if;\r
-\r
- when WR_BSY =>\r
- if( slv_write_in = '0' ) then\r
- NEXT_STATE <= DONE;\r
- else\r
- NEXT_STATE <= WR_BSY;\r
- slv_busy_x <= '1';\r
- end if;\r
-\r
- when DONE =>\r
- NEXT_STATE <= SLEEP;\r
-\r
- when others =>\r
- NEXT_STATE <= SLEEP;\r
-\r
- end case;\r
- end process PROC_TRANSFORM;\r
-\r
----------------------------------------------------------\r
--- data handling --\r
----------------------------------------------------------\r
-\r
--- register write\r
- PROC_WRITE_REG: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- reg_slv_data_in <= RESET_VALUE;\r
- elsif( store_wr = '1' ) then\r
- reg_slv_data_in <= slv_data_in;\r
- end if;\r
- end if;\r
- end process PROC_WRITE_REG;\r
-\r
--- register read\r
- PROC_READ_REG: process( clk_in )\r
- begin\r
- if( rising_edge(clk_in) ) then\r
- if ( reset_in = '1' ) then\r
- reg_slv_data_out <= (others => '0');\r
- elsif( store_rd = '1' ) then\r
- reg_slv_data_out <= reg_data_in;\r
- end if;\r
- end if;\r
- end process PROC_READ_REG;\r
-\r
--- output signals\r
- slv_ack_out <= slv_ack;\r
- slv_busy_out <= slv_busy;\r
- slv_data_out <= reg_slv_data_out;\r
-\r
----------------------------------------------------------\r
--- signals to backend --\r
----------------------------------------------------------\r
-\r
- reg_data_out <= reg_slv_data_in;\r
-\r
-end Behavioral;\r
jspc29 / trb3.git / commitdiff