*** empty log message ***

diff --git a/lattice/trb_net16_bram_fifo.vhd b/lattice/lattice_scm_bram_fifo.vhd
similarity index 96%
rename from lattice/trb_net16_bram_fifo.vhd
rename to lattice/lattice_scm_bram_fifo.vhd
index e9f375e319afaf87f1f2f9babcc799c64f4f3c09..d65b10aec536e901749f7578df031921e987a2ba 100644 (file)
--- a/lattice/trb_net16_bram_fifo.vhd
+++ b/lattice/lattice_scm_bram_fifo.vhd
@@ -1,6 +1,6 @@
 -- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55)
 -- Module  Version: 4.2
---/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n trb_net16_bram_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e 
+--/opt/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_bram_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -e
 
 -- Wed Jan 16 16:32:24 2008
 
@@ -11,7 +11,7 @@ library SCM;
 use SCM.COMPONENTS.all;
 -- synopsys translate_on
 
-entity trb_net16_bram_fifo is
+entity lattice_scm_bram_fifo is
     port (
         Data: in  std_logic_vector(17 downto 0); 
         WrClock: in  std_logic; 
@@ -25,9 +25,9 @@ entity trb_net16_bram_fifo is
         Full: out  std_logic; 
         AlmostEmpty: out  std_logic; 
         AlmostFull: out  std_logic);
-end trb_net16_bram_fifo;
+end lattice_scm_bram_fifo;
 
-architecture Structure of trb_net16_bram_fifo is
+architecture Structure of lattice_scm_bram_fifo is
 
     -- internal signal declarations
     signal scuba_vhi: std_logic;
@@ -170,7 +170,7 @@ end Structure;
 
 -- synopsys translate_off
 library SCM;
-configuration Structure_CON of trb_net16_bram_fifo is
+configuration Structure_CON of lattice_scm_bram_fifo is
     for Structure
         for all:VHI use entity SCM.VHI(V); end for;
         for all:VLO use entity SCM.VLO(V); end for;

diff --git a/lattice/trb_net_fifo_arch.vhd b/lattice/trb_net_fifo_arch.vhd
new file mode 100644 (file)
index 0000000..2c1d9be
--- /dev/null
+++ b/lattice/trb_net_fifo_arch.vhd
@@ -0,0 +1,90 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+-- entity trb_net_fifo is
+--   generic (
+--    WIDTH : integer := 18;   -- FIFO word width
+--    DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
+--    FORCE_LUT : integer range 0 to 1 := 0 --don't allow use of BlockRAM
+--    );
+--   port (
+--     CLK    : in std_logic;      
+--     RESET  : in std_logic;    
+--     CLK_EN : in std_logic;
+-- 
+--     DATA_IN         : in  std_logic_vector(WIDTH - 1 downto 0);  -- Input data
+--     WRITE_ENABLE_IN : in  std_logic;      
+--     DATA_OUT        : out std_logic_vector(WIDTH - 1 downto 0);  -- Output data
+--        --output data MUST BE 0 if no data is available
+--     READ_ENABLE_IN  : in  std_logic; 
+--     FULL_OUT        : out std_logic;    -- Full Flag
+--     EMPTY_OUT       : out std_logic;
+--     DEPTH_OUT       : out std_logic_vector(7 downto 0)
+--     );
+-- 
+-- end trb_net_fifo;
+
+architecture Structure of trb_net_fifo_arch is
+  component lattice_scm_bram_fifo is
+    port (
+      Data: in  std_logic_vector(17 downto 0);
+      WrClock: in  std_logic;
+      RdClock: in  std_logic;
+      WrEn: in  std_logic;
+      RdEn: in  std_logic;
+      Reset: in  std_logic;
+      RPReset: in  std_logic;
+      Q: out  std_logic_vector(17 downto 0);
+      Empty: out  std_logic;
+      Full: out  std_logic;
+      AlmostEmpty: out  std_logic;
+      AlmostFull: out  std_logic
+      );
+  end component lattice_scm_bram_fifo;
+
+  signal fifo_write_enable, fifo_read_enable : std_logic;
+  signal fifo_data_out                       : std_logic_vector(17 downto 0);
+  signal fifo_empty, fifo_full               : std_logic;
+
+begin
+
+  gen_BRAM : if (DEPTH = 8 and WIDTH = 18) and FORCE_LUT = 0 generate
+   bram_fifo:lattice_scm_bram_fifo
+    port map (
+      Data             => DATA_IN,
+      WrClock          => CLK,
+      RdClock          => CLK,
+      WrEn             => fifo_write_enable,
+      RdEn             => fifo_read_enable,
+      Reset            => RESET,
+      RPReset          => RESET,
+      Q                => fifo_data_out,
+      Empty            => fifo_empty,
+      Full             => fifo_full,
+      AlmostEmpty      => open,
+      AlmostFull       => open
+      );
+  end generate;
+
+
+
+
+  fifo_write_enable <= WRITE_ENABLE_IN;
+  FULL_OUT  <= fifo_full;
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          buf_DATA_OUT <= (others => '0');
+        elsif last_fifo_read_enable = '1' then
+          buf_DATA_OUT <= fifo_data_out;
+        end if;
+      end if;
+    end process;
+
+end architecture;
\ No newline at end of file