dirich5s1 new reset routine and more stable CDR settings, mt

diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx b/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx
deleted file mode 100644 (file)
index 4dfcdb9..0000000
--- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx
+++ /dev/null
@@ -1,7 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_0" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 11 25 09:50:53.703" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-               <File name="serdes_sync_0.lpc" type="lpc" modified="2020 08 10 15:47:35.000"/>
-               <File name="serdes_sync_0.vhd" type="top_level_vhdl" modified="2020 08 10 15:47:35.000"/>
-  </Package>
-</DiamondModule>

diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc b/media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc
index 92d3d19e03501acc1ee6f9f549e1d167874aec21..c03475e62a37a4bd18a888e931fa3422147e21a3 100644 (file)
--- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc
+++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc
@@ -11,11 +11,11 @@ CoreName=PCS
 CoreRevision=8.2
 CoreStatus=Demo
 CoreType=LPM
-Date=07/13/2017
-ModuleName=serdes_sync_0
+Date=01/19/2023
+ModuleName=channel0_0
 ParameterFileVersion=1.0
 SourceFormat=vhdl
-Time=15:33:51
+Time=23:23:30
 VendorName=Lattice Semiconductor Corporation
 [Parameters]
 ;ACHARA=0 00H
@@ -23,8 +23,8 @@ VendorName=Lattice Semiconductor Corporation
 ;ACHARM=0 00H
 ;RXMCAENABLE=Disabled
 CDRLOLACTION=Full Recalibration
-CDRLOLRANGE=3
-CDR_MAX_RATE=2
+CDRLOLRANGE=0
+CDR_MAX_RATE=2.0000
 CDR_MULT=10X
 CDR_REF_RATE=200.0000
 CH_MODE=Rx and Tx
@@ -33,7 +33,7 @@ EDIF=1
 Expression=BusA(0 to 7)
 IO=0
 IO_TYPE=G8B10B
-LEQ=Disabled
+LEQ=0
 LOOPBACK=Disabled
 LOSPORT=Enabled
 NUM_CHS=1
@@ -47,9 +47,9 @@ RCSRC=Disabled
 REFCLK_RATE=200.0000
 RSTSEQSEL=Enabled
 RX8B10B=Enabled
-RXCOMMAA=1100000100
-RXCOMMAB=0011111000
-RXCOMMAM=1111111100
+RXCOMMAA=0010000011
+RXCOMMAB=0001111100
+RXCOMMAM=0011111111
 RXCOUPLING=AC
 RXCTC=Disabled
 RXCTCBYTEN=0 00H
@@ -61,7 +61,7 @@ RXDIFFTERM=50 ohms
 RXFIFO_ENABLE=Enabled
 RXINVPOL=Non-invert
 RXLDR=Off
-RXLOSTHRESHOLD=0
+RXLOSTHRESHOLD=4
 RXLSM=Enabled
 RXSC=K28P157
 RXWA=Barrel Shift
@@ -79,19 +79,19 @@ TXDIFFTERM=50 ohms
 TXFIFO_ENABLE=Enabled
 TXINVPOL=Non-invert
 TXLDR=Off
-TXPLLLOLTHRESHOLD=1
+TXPLLLOLTHRESHOLD=0
 TXPLLMULT=10X
 TX_DATA_WIDTH=8/10-Bit
 TX_FICLK_RATE=200.0000
 TX_LINE_RATE=2.0000
-TX_MAX_RATE=2
+TX_MAX_RATE=2.000
 TX_RATE_DIV=Full Rate
 VHDL=1
 Verilog=0
 [FilesGenerated]
-serdes_sync_0.pp=pp
-serdes_sync_0.sym=sym
-serdes_sync_0.tft=tft
-serdes_sync_0.txt=pcs_module
+channel0_0.pp=pp
+channel0_0.sym=sym
+channel0_0.tft=tft
+channel0_0.txt=pcs_module
 [SYSTEMPNR]
 LN0=DCU0_CH0

diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
index c8b0baaf60fccdb82e711c9a87c6aa049892fceb..4b80203c05eefe072bdff40ff580c2d1ee5918f7 100644 (file)
--- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
+++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
@@ -88,53 +88,53 @@ architecture v1 of serdes_sync_0 is
             pwait_tx_rdy: integer := 3000;
             pport_rx_rdy: string := "ENABLED";
             pwait_rx_rdy: integer := 3000);
-        port (rui_rst: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
-            rui_serdes_rst_dual_c: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
-            rui_rst_dual_c: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
-            rui_rsl_disable: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
-            rui_tx_ref_clk: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
-            rui_tx_serdes_rst_c: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
-            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
-            rdi_pll_lol: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
-            rui_rx_ref_clk: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
-            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
-            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
-            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
-            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
-            rdo_serdes_rst_dual_c: out std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
-            rdo_rst_dual_c: out std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
-            ruo_tx_rdy: out std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
-            rdo_tx_serdes_rst_c: out std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
-            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
-            ruo_rx_rdy: out std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
-            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
-            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+        port (rui_rst: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+            rui_serdes_rst_dual_c: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+            rui_rst_dual_c: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+            rui_rsl_disable: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+            rui_tx_ref_clk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+            rui_tx_serdes_rst_c: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+            rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+            rdi_pll_lol: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+            rui_rx_ref_clk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+            rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+            rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+            rdi_rx_los_low_s: in std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+            rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+            rdo_serdes_rst_dual_c: out std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+            rdo_rst_dual_c: out std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+            ruo_tx_rdy: out std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+            rdo_tx_serdes_rst_c: out std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+            rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+            ruo_rx_rdy: out std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+            rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+            rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0)   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(158)
         );
         
-    end component serdes_sync_0rsl_core; -- syn_black_box=1    -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+    end component serdes_sync_0rsl_core; -- syn_black_box=1    -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/rsl_core_syn.v(88)
     component serdes_sync_0sll_core is
         generic (PPROTOCOL: string := "G8B10B";
-            PLOL_SETTING: integer := 1;
+            PLOL_SETTING: integer := 0;
             PDYN_RATE_CTRL: string := "DISABLED";
             PPCIE_MAX_RATE: string := "2.5";
             PDIFF_VAL_LOCK: integer := 20;
-            PDIFF_VAL_UNLOCK: integer := 132;
+            PDIFF_VAL_UNLOCK: integer := 39;
             PPCLK_TC: integer := 65536;
             PDIFF_DIV11_VAL_LOCK: integer := 0;
             PDIFF_DIV11_VAL_UNLOCK: integer := 0;
             PPCLK_DIV11_TC: integer := 0);
-        port (sli_rst: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
-            sli_refclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
-            sli_pclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
-            sli_div2_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
-            sli_div11_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
-            sli_gear_mode: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
-            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
-            sli_pcie_mode: in std_logic;   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
-            slo_plol: out std_logic   -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+        port (sli_rst: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(125)
+            sli_refclk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(126)
+            sli_pclk: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(127)
+            sli_div2_rate: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(128)
+            sli_div11_rate: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(129)
+            sli_gear_mode: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(130)
+            sli_cpri_mode: in std_logic_vector(2 downto 0);   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(131)
+            sli_pcie_mode: in std_logic;   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(132)
+            slo_plol: out std_logic   -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(135)
         );
         
-    end component serdes_sync_0sll_core; -- syn_black_box=1    -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+    end component serdes_sync_0sll_core; -- syn_black_box=1    -- /opt/lattice/diamond/3.12/ispfpga/sa5p00/data/sll_core_template.v(107)
     signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
         n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17,
         n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,
@@ -159,7 +159,7 @@ begin
     pll_lol <= pll_lol_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
@@ -187,7 +187,7 @@ begin
         CH0_RXIN_CM=>"0b11",CH0_LEQ_OFFSET_SEL=>"0b0",CH0_LEQ_OFFSET_TRIM=>"0b000",
         CH0_RLOS_SEL=>"0b1",CH0_RX_LOS_LVL=>"0b100",CH0_RX_LOS_CEQ=>"0b11",
         CH0_RX_LOS_HYST_EN=>"0b0",CH0_RX_LOS_EN=>"0b1",CH0_LDR_RX2CORE_SEL=>"0b0",
-        CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH0_CDR_MAX_RATE=>"2",
+        CH0_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2.000",CH0_CDR_MAX_RATE=>"2.0000",
         CH0_TXAMPLITUDE=>"0d800",CH0_TXDEPRE=>"DISABLED",CH0_TXDEPOST=>"DISABLED",
         CH0_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01",
         D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001",
@@ -204,7 +204,7 @@ begin
         D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
         D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
         D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH0_RX_RATE_SEL=>"0d10",
-        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01",
+        D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b00",
         D_RG_EN=>"0b0",D_RG_SET=>"0b00")
      port map (CH0_HDINP=>hdinp,CH1_HDINP=>n106,CH0_HDINN=>hdinn,CH1_HDINN=>n106,
     D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,

diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd
index 5a8cdca3474162bfc30fe726f8f42cbd22116fc8..7faf134a8ee96db6a82094b20684fb0835e69b05 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync.vhd
@@ -148,7 +148,7 @@ gen_pcs0 : if SERDES_NUM = 0 or SERDES_NUM = 1 generate -- same entity in any ca
       serdes_sync_0_rx_cv_err(0)     => rx_error,
       
       serdes_sync_0_tx_idle_c        => '0',
-      serdes_sync_0_signal_detect_c  => '0', 
+      serdes_sync_0_signal_detect_c  => '1', 
       serdes_sync_0_rx_los_low_s     => rx_los_low,
       serdes_sync_0_lsm_status_s     => lsm_status,
       serdes_sync_0_rx_cdr_lol_s     => rx_cdr_lol,
@@ -262,7 +262,7 @@ gen_pcs2 : if SERDES_NUM = 2 generate
       serdes_sync_0_rx_cv_err(0)     => rx_error,
       
       serdes_sync_0_tx_idle_c        => '0',
-      serdes_sync_0_signal_detect_c  => '0', 
+      serdes_sync_0_signal_detect_c  => '1', 
       serdes_sync_0_rx_los_low_s     => rx_los_low,
       serdes_sync_0_lsm_status_s     => lsm_status,
       serdes_sync_0_rx_cdr_lol_s     => rx_cdr_lol,
@@ -320,6 +320,8 @@ THE_MED_CONTROL : entity work.med_sync_control
     
     SFP_LOS     => SD_LOS_IN,
     TX_LOL      => tx_pll_lol,
+    RX_CV       => rx_error, -- NEW
+    RX_LSM      => lsm_status, -- NEW
     RX_CDR_LOL  => rx_cdr_lol,
     RX_LOS      => rx_los_low,
     WA_POSITION => wa_position_sel,
@@ -380,10 +382,12 @@ THE_SCI_READER : entity work.sci_reader
     DEBUG_OUT   => open
     );
 
-STAT_DEBUG(11 downto 0)  <= debug_med_sync_control_i(11 downto 0);
-STAT_DEBUG(15 downto 12) <= (others => '0');
-STAT_DEBUG(31 downto 16) <= wa_position;
-STAT_DEBUG(63 downto 32) <= (others => '0');
+STAT_DEBUG(12 downto 0)  <= debug_med_sync_control_i(12 downto 0);
+STAT_DEBUG(13)           <= lsm_status;
+STAT_DEBUG(14)           <= rx_cdr_lol;
+STAT_DEBUG(15)           <= rx_error;
+STAT_DEBUG(19 downto 16) <= debug_med_sync_control_i(16 downto 13);
+STAT_DEBUG(63 downto 20) <= (others => '0');
 
 stat_med(0) <= rst_qd; 
 stat_med(1) <= rx_pcs_rst;

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index c91f378c82473187a84e3513d5acf071a6582bd7..5b98bc425dd6577084e93cd130999f12c1e2e287 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -23,6 +23,8 @@ entity med_sync_control is
     
     SFP_LOS     : in  std_logic;
     TX_LOL      : in  std_logic;
+    RX_CV       : in  std_logic; -- NEW
+    RX_LSM      : in  std_logic; -- NEW
     RX_CDR_LOL  : in  std_logic;
     RX_LOS      : in  std_logic;
     WA_POSITION : in  std_logic_vector(3 downto 0);
@@ -91,6 +93,7 @@ signal send_link_reset_sys_i  : std_logic := '0';
 
 signal reset_i                : std_logic;
 signal rst_n                  : std_logic;
+--signal rst                    : std_logic;
 signal rst_n_tx               : std_logic;
 signal finished_reset_rx      : std_logic;
 signal finished_reset_rx_q    : std_logic;
@@ -108,12 +111,15 @@ signal rx_pcs_rst_i_q         : std_logic_vector(2 downto 0);
 signal tx_pcs_rst_i           : std_logic;
 signal quad_rst_i             : std_logic;
 
+
 begin
 
+
 rst_n_tx  <=       not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1)
               else not (CLEAR or make_link_reset_real_i or RESET);
 
 rst_n     <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET);
+--rst       <=     (CLEAR or sd_los_i or make_link_reset_real_i or RESET);
 reset_i   <=     (RESET or sd_los_i or make_link_reset_real_i);
 
 media_med2int_i.clk_half <= CLK_RXHALF;
@@ -122,20 +128,37 @@ media_med2int_i.clk_full <= CLK_RXI;
 -------------------------------------------------      
 -- Reset RX FSM
 -------------------------------------------------      
-THE_RX_FSM : rx_reset_fsm
+--THE_RX_FSM : rx_reset_fsm
+--  port map(
+--    RST_N                => rst_n,
+--    RX_REFCLK            => CLK_REF,
+--    TX_PLL_LOL_QD_S      => TX_LOL,
+--    RX_SERDES_RST_CH_C   => rx_serdes_rst_i,
+--    RX_CDR_LOL_CH_S      => RX_CDR_LOL,
+--    RX_LOS_LOW_CH_S      => RX_LOS,
+--    RX_PCS_RST_CH_C      => rx_pcs_rst_i,
+--    WA_POSITION          => wa_position_rx,
+--    NORMAL_OPERATION_OUT => finished_reset_rx,
+--    STATE_OUT            => rx_fsm_state
+--    );
+    
+THE_MAIN_RX_RST: main_rx_reset_RS 
   port map(
-    RST_N                => rst_n,
-    RX_REFCLK            => CLK_REF,
-    TX_PLL_LOL_QD_S      => TX_LOL,
-    RX_SERDES_RST_CH_C   => rx_serdes_rst_i,
-    RX_CDR_LOL_CH_S      => RX_CDR_LOL,
-    RX_LOS_LOW_CH_S      => RX_LOS,
-    RX_PCS_RST_CH_C      => rx_pcs_rst_i,
-    WA_POSITION          => wa_position_rx,
-    NORMAL_OPERATION_OUT => finished_reset_rx,
-    STATE_OUT            => rx_fsm_state
-    );
-
+    CLEAR             => CLEAR, -- should work
+    CLK_REF           => CLK_REF, -- ok
+    CDR_LOL_IN        => RX_CDR_LOL, -- ok
+    CV_IN             => RX_CV, -- ok
+    LSM_IN            => RX_LSM, -- ok
+    LOS_IN            => RX_LOS, -- ok
+    WAP_ZERO_IN       => '1', -- not needed
+    -- outputs
+    WAP_REQ_OUT       => open, -- not needed
+    RX_SERDES_RST_OUT => rx_serdes_rst_i, -- ok -- CLK_REF based
+    RX_PCS_RST_OUT    => rx_pcs_rst_i, -- ok -- CLK_REF based
+    LINK_RX_READY_OUT => finished_reset_rx, -- should work -- CLK_REF based
+    STATE_OUT         => rx_fsm_state
+  );
+    
 -- crossing the abbyss
 THE_ABBYSS_PROC: process( CLK_RXI )
 begin 
@@ -151,17 +174,29 @@ RX_PCS_RST    <= rx_pcs_rst_i_q(2);
 -------------------------------------------------      
 -- Reset TX FSM
 -------------------------------------------------      
-THE_TX_FSM : tx_reset_fsm
-  port map(
-    RST_N                => rst_n_tx,
-    TX_REFCLK            => CLK_REF,
-    TX_PLL_LOL_QD_S      => TX_LOL,
-    RST_QD_C             => quad_rst_i,
-    TX_PCS_RST_CH_C      => tx_pcs_rst_i,
-    NORMAL_OPERATION_OUT => finished_reset_tx,
-    STATE_OUT            => tx_fsm_state
-    );
-
+--THE_TX_FSM : tx_reset_fsm
+--  port map(
+--    RST_N                => rst_n_tx,
+--    TX_REFCLK            => CLK_REF,
+--    TX_PLL_LOL_QD_S      => TX_LOL,
+--    RST_QD_C             => quad_rst_i,
+--    TX_PCS_RST_CH_C      => tx_pcs_rst_i,
+--    NORMAL_OPERATION_OUT => finished_reset_tx,
+--    STATE_OUT            => tx_fsm_state
+--    );
+
+THE_MAIN_TX_RST: main_tx_reset_RS
+  port map (
+    CLEAR                => CLEAR, -- should work
+    CLK_REF              => CLK_REF, -- should work
+    TX_PLL_LOL_IN        => TX_LOL, -- ok
+    TX_CLOCK_AVAIL_IN    => '1', -- not needed
+    TX_PCS_RST_CH_C_OUT  => tx_pcs_rst_i, -- ok
+    SYNC_TX_QUAD_OUT     => open,
+    LINK_TX_READY_OUT    => finished_reset_tx, -- should work
+    STATE_OUT            => open
+  );
+  
 -- may also need sync?
 TX_PCS_RST    <= tx_pcs_rst_i;
 QUAD_RST      <= quad_rst_i;
@@ -375,6 +410,8 @@ DEBUG_OUT(8)  <= rx_serdes_rst_i;
 DEBUG_OUT(9)  <= finished_reset_rx;
 DEBUG_OUT(10) <= finished_reset_tx;
 DEBUG_OUT(11) <= reset_i;
-DEBUG_OUT(31 downto 12) <= (others => '0');
+DEBUG_OUT(12) <= CLEAR;
+DEBUG_OUT(16 downto 13) <= rx_fsm_state;
+DEBUG_OUT(31 downto 17) <= (others => '0');
 
 end architecture;

diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd
index 9eaf330fbd0d9bff557a1d518a01230723ce4fc3..4aa9731e2ffd083aa29d3d85ab7f2a254dd81edf 100644 (file)
--- a/media_interfaces/sync/med_sync_define.vhd
+++ b/media_interfaces/sync/med_sync_define.vhd
@@ -184,6 +184,35 @@ component med_ecp3_sfp_sync is
    );
 end component;
 
+component main_tx_reset_RS is
+  port(
+    CLEAR                : in  std_logic; -- async reset, active high, should not be used!
+    CLK_REF              : in  std_logic; -- usually local oscillator sourced   
+    TX_PLL_LOL_IN        : in  std_logic; -- externally or'ed
+    TX_CLOCK_AVAIL_IN    : in  std_logic; -- suitable TX clock available 
+    TX_PCS_RST_CH_C_OUT  : out std_logic; -- PCS reset
+    SYNC_TX_QUAD_OUT     : out std_logic; -- sync all QUADs to TX bit 0
+    LINK_TX_READY_OUT    : out std_logic; -- TX lane can use used now
+    STATE_OUT            : out std_logic_vector(3 downto 0)
+  );
+end component;
 
+component main_rx_reset_RS is
+  port (
+    CLEAR             : in  std_logic; -- do not use
+    CLK_REF           : in  std_logic; -- usually local oscillator sourced
+    CDR_LOL_IN        : in  std_logic;
+    CV_IN             : in  std_logic;
+    LSM_IN            : in  std_logic;
+    LOS_IN            : in  std_logic;
+    WAP_ZERO_IN       : in  std_logic;
+    -- outputs
+    WAP_REQ_OUT       : out std_logic;
+    RX_SERDES_RST_OUT : out std_logic;
+    RX_PCS_RST_OUT    : out std_logic;
+    LINK_RX_READY_OUT : out std_logic;
+    STATE_OUT         : out std_logic_vector(3 downto 0)
+  );
+end component;
 
 end package;