signal debug_data_handler_i : std_logic_vector(31 downto 0);
signal reset_ipu_i : std_logic;
signal buf_STAT_DATA_BUFFER_LEVEL : std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
-
+ signal buf_STAT_HEADER_BUFFER_LEVEL : std_logic_vector(31 downto 0);
begin
TMG_TRG_ERROR_IN => TMG_TRG_ERROR_IN,
-- Status
STAT_DATA_BUFFER_LEVEL => buf_STAT_DATA_BUFFER_LEVEL,
- STAT_HEADER_BUFFER_LEVEL => STAT_HEADER_BUFFER_LEVEL,
+ STAT_HEADER_BUFFER_LEVEL => buf_STAT_HEADER_BUFFER_LEVEL,
-- Debug
DEBUG_OUT => debug_data_handler_i
);
timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
end if;
end loop;
- if STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
+ if buf_STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
timer_lvl1_almost_full <= timer_lvl1_almost_full + to_unsigned(1,1);
end if;
- if STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
+ if buf_STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
timer_lvl1_idle <= timer_lvl1_idle + to_unsigned(1,1);
end if;
- if (STAT_HEADER_BUFFER_LEVEL(21) = '1' or STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
+ if (buf_STAT_HEADER_BUFFER_LEVEL(21) = '1' or buf_STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
timer_lvl1_working <= timer_lvl1_working + to_unsigned(1,1);
end if;
end if;
-- Debug
-----------------------------------------------------------------------
+ STAT_DATA_BUFFER_LEVEL <= buf_STAT_DATA_BUFFER_LEVEL;
+ STAT_HEADER_BUFFER_LEVEL <= buf_STAT_HEADER_BUFFER_LEVEL;
+
STATUS_OUT(DATA_INTERFACE_NUMBER downto 0) <= fee_trg_release;
STATUS_OUT(31 downto DATA_INTERFACE_NUMBER+1) <= (others => '1');