]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Tue, 7 Dec 2010 21:24:13 +0000 (21:24 +0000)
committerhadeshyp <hadeshyp>
Tue, 7 Dec 2010 21:24:13 +0000 (21:24 +0000)
special/handler_trigger_and_data.vhd

index 9a0b4e3a24d949b75f625b0e32a6d9ff486fcb1c..8f80f10f05dd70410769d640cc4cd25d38c940f5 100644 (file)
@@ -125,7 +125,7 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is
   signal debug_data_handler_i    : std_logic_vector(31 downto 0);
   signal reset_ipu_i             : std_logic;
   signal buf_STAT_DATA_BUFFER_LEVEL : std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
-
+  signal buf_STAT_HEADER_BUFFER_LEVEL : std_logic_vector(31 downto 0);
 
 begin
 
@@ -201,7 +201,7 @@ begin
       TMG_TRG_ERROR_IN             => TMG_TRG_ERROR_IN,
 --       Status
       STAT_DATA_BUFFER_LEVEL       => buf_STAT_DATA_BUFFER_LEVEL,
-      STAT_HEADER_BUFFER_LEVEL     => STAT_HEADER_BUFFER_LEVEL,
+      STAT_HEADER_BUFFER_LEVEL     => buf_STAT_HEADER_BUFFER_LEVEL,
 --       Debug
       DEBUG_OUT                    => debug_data_handler_i
       );
@@ -268,13 +268,13 @@ begin
               timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
             end if;
           end loop;
-          if STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
+          if buf_STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
             timer_lvl1_almost_full <= timer_lvl1_almost_full + to_unsigned(1,1);
           end if;
-          if STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
+          if buf_STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
             timer_lvl1_idle <= timer_lvl1_idle + to_unsigned(1,1);
           end if;
-          if (STAT_HEADER_BUFFER_LEVEL(21) = '1' or STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
+          if (buf_STAT_HEADER_BUFFER_LEVEL(21) = '1' or buf_STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
             timer_lvl1_working <= timer_lvl1_working + to_unsigned(1,1);
           end if;
         end if;
@@ -336,6 +336,9 @@ begin
 -- Debug
 -----------------------------------------------------------------------
 
+  STAT_DATA_BUFFER_LEVEL   <= buf_STAT_DATA_BUFFER_LEVEL;
+  STAT_HEADER_BUFFER_LEVEL <= buf_STAT_HEADER_BUFFER_LEVEL;
+
   STATUS_OUT(DATA_INTERFACE_NUMBER downto 0)     <= fee_trg_release;
   STATUS_OUT(31 downto DATA_INTERFACE_NUMBER+1)  <= (others => '1');