synch of DCA clock signals to sysclock for FSM to relax timing

diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd
index 67df8b5e102a2ef7bb16cf98d567cd3f89bf59bc..eddf4db34100749122819284e7fbe07641d6c4c9 100644 (file)
--- a/src/cri_trbnet_dca_bridge.vhd
+++ b/src/cri_trbnet_dca_bridge.vhd
@@ -77,7 +77,7 @@ signal dca_init_dataready       : std_logic;
 signal dca_init_dataready_q       : std_logic;
 
 signal tx_data_ctr              : std_logic_vector(15 downto 0);
-signal tx_loaded_ctr            : std_logic_vector(15 downto 0);
+signal tx_loaded_ctr, tx_loaded_ctr_sync : std_logic_vector(15 downto 0);
 signal tx_frame_loaded          : std_logic_vector(15 downto 0);
 
 signal packet_num               : std_logic_vector(2 downto 0);
@@ -122,11 +122,12 @@ signal tx_rd_size_ack, last_tx_rd_size_ack, tx_rd_size_ack_sync : std_logic;
 signal WB_RESPONSE_READY : std_logic;
 signal tx_data_size_dca  : std_logic_vector(15 downto 0);
 
-signal preload_word_tx_fifo : std_logic;
+signal preload_word_tx_fifo    : std_logic;
 
-signal tx_data_out          : std_logic_vector(31 downto 0);
+signal tx_data_out             : std_logic_vector(31 downto 0);
 
-signal wait_cnt             : unsigned(1 downto 0) := "00";
+signal wait_cnt                : unsigned(1 downto 0) := "00";
+signal wait_dca, wait_dca_sync : std_logic := '0';
 
 begin
   reset_dca <= not RST_N_DCA;
@@ -380,9 +381,39 @@ begin
       wait_cnt <= "00";
     end if;
     
+    if wait_cnt = "10" then
+      wait_dca <= '1';
+    else
+      wait_dca <= '0';
+    end if;
   end if;
 end process TX_FIFO_READ_PROC;
 
+THE_SYNC_WAIT_DCA : entity work.pulse_sync
+ port map(
+   RESET_A_IN  => reset_dca,
+   CLK_A_IN    => CLK_DCA,
+   PULSE_A_IN  => wait_dca,
+   
+   RESET_B_IN  => RESET,
+   CLK_B_IN    => CLK,
+   PULSE_B_OUT => wait_dca_sync
+ ); 
+ 
+THE_SYNC_TX_LOAD_CTR : entity work.signal_sync
+ generic map(
+   WIDTH => 16,
+   DEPTH => 3
+ )
+ port map(
+   RESET => RESET,
+   CLK0  => CLK_DCA,
+   CLK1  => CLK,
+
+   D_IN  => tx_loaded_ctr,
+   D_OUT => tx_loaded_ctr_sync
+ );
+ 
 TX_FIFO_SYNC_PROC : process(CLK)
 begin
   if rising_edge(CLK) then
@@ -462,7 +493,7 @@ begin
   end if;
 end process DISSECT_MACHINE_PROC;
 
-DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, rx_data_wr_sync, rx_data_dca_sync, preload_word_tx_fifo, DCA_INIT_READ_IN, DCA_REPLY_DATAREADY_IN, tx_loaded_ctr, tx_rd_size_ack_sync, tx_data_ctr, rx_fifo_q, DCA_BUSY_IN)
+DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, rx_data_wr_sync, rx_data_dca_sync, preload_word_tx_fifo, DCA_INIT_READ_IN, DCA_REPLY_DATAREADY_IN, tx_loaded_ctr_sync, tx_rd_size_ack_sync, tx_data_ctr, rx_fifo_q, DCA_BUSY_IN, wait_dca_sync)
 begin
   state <= x"0";
 
@@ -528,7 +559,7 @@ begin
       dissect_next_state <= WAIT_CNTR;
     
     when WAIT_CNTR =>
-      if wait_cnt = 2 then
+      if wait_dca_sync = '1' then
         dissect_next_state <= WAIT_FOR_LOAD;
       else
         dissect_next_state <= WAIT_CNTR;
@@ -544,7 +575,7 @@ begin
 
     when LOAD_FRAME =>
       state <= x"9";
-      if (tx_loaded_ctr = tx_data_ctr) then
+      if (tx_loaded_ctr_sync = tx_data_ctr) then
         dissect_next_state <= CLEANUP;
       else
         dissect_next_state <= LOAD_FRAME;