--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.version.all;
+
+library machxo2;
+use machxo2.all;
+
+
+entity uart_sctrl is
+ generic(
+ CLOCK_SPEED : integer := 33250000
+ );
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ UART_RX : in std_logic;
+ UART_TX : out std_logic;
+
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATA_IN : in std_logic_vector(31 downto 0);
+ ADDR_OUT : out std_logic_vector(7 downto 0);
+ WRITE_OUT : out std_logic;
+ READ_OUT : out std_logic;
+ READY_IN : in std_logic;
+
+ DEBUG : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+
+architecture uart_sctrl_arch of uart_sctrl is
+
+constant CLK_DIV : integer := CLOCK_SPEED/115200;
+
+signal rx_data : std_logic_vector(7 downto 0);
+signal tx_data : std_logic_vector(7 downto 0);
+signal rx_ready : std_logic;
+signal tx_send : std_logic;
+signal tx_ready : std_logic;
+signal bytecount : integer range 0 to 15;
+type rx_state_t is (IDLE,START,START2,DO_COMMAND,DO_READ,SEND_BYTE1,SEND_BYTE2,SEND_BYTE3,SEND_TERM,SEND_FINISH);
+signal state : rx_state_t;
+signal addr_data : std_logic_vector(39 downto 0);
+
+signal timer : unsigned(25 downto 0) := (others => '0');
+signal timeout : std_logic := '0';
+signal cmd_wr : std_logic := '0';
+signal cmd_rd : std_logic := '0';
+
+begin
+
+
+THE_RX : entity work.uart_rec
+ port map(
+ CLK_DIV => CLK_DIV,
+ CLK => CLK,
+ RST => RESET,
+ RX => UART_RX,
+ DATA_OUT => rx_data,
+ DATA_WAITING => rx_ready
+ );
+
+THE_TX : entity work.uart_trans
+ port map(
+ CLK_DIV => CLK_DIV,
+ CLK => CLK,
+ RST => RESET,
+ DATA_IN => tx_data,
+ SEND => tx_send,
+ READY => tx_ready,
+ TX => UART_TX
+ );
+
+PROC_RX : process
+ variable tmp,tmp2 : unsigned(7 downto 0);
+begin
+ wait until rising_edge(CLK);
+ READ_OUT <= '0';
+ WRITE_OUT <= '0';
+ tx_send <= '0';
+ timer <= timer + 1;
+ case state is
+ when IDLE =>
+ cmd_rd <= '0';
+ cmd_wr <= '0';
+ bytecount <= 9;
+ timer <= (others => '0');
+ if rx_ready = '1' then
+ state <= START;
+ if rx_data = x"52" then
+ cmd_rd <= '1';
+ elsif rx_data = x"57" then
+ cmd_wr <= '1';
+ end if;
+ end if;
+
+ when START =>
+ if rx_ready = '1' then
+ if rx_data >= x"40" then
+ tmp2 := unsigned(rx_data) + x"09";
+ else
+ tmp2 := unsigned(rx_data);
+ end if;
+ state <= START2;
+ end if;
+
+ when START2 =>
+ addr_data(bytecount*4+3 downto bytecount*4) <= std_logic_vector(tmp2(3 downto 0));
+ if (bytecount = 0 and cmd_wr = '1') or (bytecount = 8 and cmd_rd = '1') then
+ state <= DO_COMMAND;
+ else
+ bytecount <= bytecount - 1;
+ state <= START;
+ end if;
+
+ when DO_COMMAND =>
+ WRITE_OUT <= cmd_wr;
+ READ_OUT <= cmd_rd;
+ DATA_OUT <= addr_data(31 downto 0);
+ ADDR_OUT <= addr_data(39 downto 32);
+ if cmd_rd = '1' then
+ state <= DO_READ;
+ else
+ state <= IDLE;
+ end if;
+
+--Read cycle
+ when DO_READ =>
+ if READY_IN = '1' then
+ addr_data(31 downto 0) <= DATA_IN;
+ tx_send <= '1';
+ tx_data <= x"52";
+ state <= SEND_BYTE1;
+ bytecount <= 7;
+ end if;
+
+ when SEND_BYTE1 =>
+ tmp := x"0" & unsigned(addr_data(bytecount*4+3 downto bytecount*4));
+ state <= SEND_BYTE2;
+
+ when SEND_BYTE2 =>
+ if tmp > x"09" then
+ tmp := tmp + x"41" - x"0a";
+ else
+ tmp := tmp + x"30";
+ end if;
+ state <= SEND_BYTE3;
+
+
+ when SEND_BYTE3 =>
+
+ if tx_ready = '1' then
+ tx_data <= std_logic_vector(tmp);
+ tx_send <= '1';
+ if bytecount = 0 then
+ state <= SEND_TERM;
+ else
+ bytecount <= bytecount - 1;
+ state <= SEND_BYTE1;
+ end if;
+ end if;
+
+
+
+ when SEND_TERM=>
+ if tx_ready = '1' then
+ tx_send <= '1';
+ tx_data <= x"0a";
+ state <= SEND_FINISH;
+ end if;
+ when SEND_FINISH=>
+ if tx_ready = '1' then
+ tx_send <= '1';
+ tx_data <= x"0d";
+ state <= IDLE;
+ end if;
+
+ end case;
+
+ if RESET = '1' or timeout = '1' then
+ state <= IDLE;
+ timer <= (others => '0');
+ end if;
+end process;
+
+
+timeout <= timer(25);
+
+
+
+end architecture;
\ No newline at end of file
architecture arch of logicbox is\r
signal clk_i, clk_osc : std_logic;\r
signal led_i : std_logic_vector(3 downto 0);\r
- signal timer_i : unsigned(23 downto 0) := (others => '0');\r
+ signal timer_i : unsigned(31 downto 0) := (others => '0');\r
signal config : std_logic_vector(3 downto 0);\r
+ signal led_highz : std_logic;\r
+ \r
+ type led_timer_t is array(0 to 3) of unsigned(24 downto 0);\r
+ signal led_timer : led_timer_t;\r
+ signal led_state : std_logic_vector(3 downto 0);\r
\r
signal uart_rx_data : std_logic_vector(31 downto 0);\r
signal uart_tx_data : std_logic_vector(31 downto 0);\r
signal bus_read : std_logic := '0';\r
signal bus_write : std_logic := '0';\r
signal bus_ready : std_logic; \r
+ \r
+ signal input_i : std_logic_vector(3 downto 0);\r
+ signal input_selected : std_logic_vector(3 downto 0); \r
+ signal input_stretched, input_hold : std_logic_vector(3 downto 0);\r
+ signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);\r
+ \r
+ signal edge_rising, edge_falling : std_logic_vector(3 downto 0);\r
+ signal pulser : std_logic;\r
+ signal reg : std_logic_vector(31 downto 0);\r
+ signal last_config : std_logic_vector(3 downto 0);\r
\r
component OSCH\r
generic (NOM_FREQ: string := "133.00");\r
\r
\r
---------------------------------------------------------------------------\r
--- I don't care what you do, as long as you do it!\r
+-- I/O Logic\r
---------------------------------------------------------------------------\r
+-- 0 1:1,\r
+-- 1 1:4 fan-out,\r
+-- 2 1:1, O1 is or of inputs\r
+\r
+-- 3 1:1, invert\r
+-- 4 1:4 fan-out, invert\r
+-- 5 1:1, O1 is or of inputs, invert\r
+\r
+-- 6 1:1, rising_edge to 14-21 ns\r
+-- 7 1:1, falling_edge to 14-21 ns\r
+\r
+-- 8 1:1, stretching by +14-21ns\r
+-- 9 1:4 fan-out, stretching\r
+-- a 1:1, O1 is or of inputs, stretching\r
+\r
+-- e pulser, default 8.1 kHz, 60ns \r
+-- f pulser, default 8.1 kHz, 60ns, negative\r
\r
--- RX_OUT <= TX_IN when rising_edge(clk_i);\r
-OUTPUT <= INPUT xor (STATUSI & STATUSO & CBUS & CBUS);\r
-led_i <= INPUT when rising_edge(clk_i);\r
+input_i <= INPUT when STATUSI = '0' else INPUT(2) & INPUT(3) & INPUT(0) & INPUT(1);\r
+input_selected <= not input_i when config = x"3" or config = x"4" or config = x"5" else input_i;\r
\r
-bus_ready <= bus_read or bus_write; \r
+input_stretched <= input_hold or input_reg_0 or input_reg_1;\r
+\r
+--Stretcher needs to work with negative signals as well\r
+input_hold <= input_selected or (input_hold and not input_reg_0);\r
+\r
+input_reg_0 <= input_selected or input_hold when rising_edge(clk_i);\r
+input_reg_1 <= input_reg_0 when rising_edge(clk_i);\r
+input_reg_2 <= input_reg_1 when rising_edge(clk_i);\r
+\r
+edge_rising <= input_stretched and not input_reg_2;\r
+edge_falling <= not input_stretched and input_reg_2;\r
+\r
+process(INPUT,config, STATUSI)\r
+ begin\r
+ case config is \r
+ when x"0" => \r
+ OUTPUT <= input_selected;\r
+ when x"1" => \r
+ OUTPUT <= (others => input_selected(0));\r
+ when x"2" =>\r
+ OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & (input_selected(0) or input_selected(2)) & input_selected(0);\r
+ when x"3" => \r
+ OUTPUT <= input_selected;\r
+ when x"4" => \r
+ OUTPUT <= (others => input_selected(0));\r
+ when x"5" =>\r
+ OUTPUT <= (input_selected(0) and input_selected(2)) & input_selected(2) & \r
+ (input_selected(0) or input_selected(2)) & input_selected(0);\r
+ when x"6" =>\r
+ OUTPUT <= edge_rising;\r
+ when x"7" => \r
+ OUTPUT <= edge_falling;\r
+ when x"8" => \r
+ OUTPUT <= input_stretched;\r
+ when x"9" => \r
+ OUTPUT <= (others => input_stretched(0));\r
+ when x"a" =>\r
+ OUTPUT <= (input_stretched(0) and input_stretched(2)) & input_stretched(2) & (input_stretched(0) or input_stretched(2)) & input_stretched(0);\r
+ when x"e" =>\r
+ OUTPUT <= (others => pulser);\r
+ when x"f" =>\r
+ OUTPUT <= (others => not pulser);\r
+ when others => \r
+ OUTPUT <= input_selected;\r
+ end case;\r
+ end process;\r
+\r
+---------------------------------------------------------------------------\r
+-- Pulser\r
+---------------------------------------------------------------------------\r
+ PROC_PULSER : process begin\r
+ wait until rising_edge(clk_i);\r
+ if timer_i(13 downto 0) = "00"&x"000" then\r
+ pulser <= '1';\r
+ elsif timer_i(13 downto 0) = "00"&x"008" then\r
+ pulser <= '0';\r
+ end if; \r
+ end process; \r
\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+ PROC_LED : process begin\r
+ wait until rising_edge(clk_i);\r
+ if not (config = last_config) and timer_i(27) = '0' then\r
+ led_i <= config; \r
+ elsif STATUSI = '0' then\r
+ led_i <= led_state;\r
+ else\r
+ led_i <= led_state(2) & led_state(3) & led_state(0) & led_state(1);\r
+ end if; \r
+ end process;\r
\r
+ PROC_LED_STATE : process begin\r
+ wait until rising_edge(clk_i);\r
+ for i in 0 to 3 loop\r
+ if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then\r
+ led_state(i) <= not led_state(i);\r
+ led_timer(i) <= 0;\r
+ elsif led_timer(i)(23) = '1' then\r
+ led_state(i) <= input_reg_1(i);\r
+ else\r
+ led_timer(i) <= led_timer(i) + 1;\r
+ end if;\r
+ end loop;\r
+ end process; \r
+ \r
+ \r
---------------------------------------------------------------------------\r
-- Clock\r
---------------------------------------------------------------------------\r
clk_source: OSCH\r
- generic map ( NOM_FREQ => "33.25" )\r
+ generic map ( NOM_FREQ => "133" )\r
port map (\r
STDBY => '0',\r
OSC => clk_osc,\r
---------------------------------------------------------------------------\r
process begin\r
wait until rising_edge(clk_i);\r
- if timer_i(23 downto 4) = 0 then\r
- if timer_i(3 downto 0) = x"0" then\r
- LED <= (others => 'Z');\r
- elsif timer_i(3 downto 0) = x"8" then\r
- config <= LED;\r
+ \r
+\r
+ if timer_i(27 downto 10) = 0 then\r
+ led_highz <= '1';\r
+ last_config <= config;\r
+ if timer_i(9 downto 0) = "11"&x"ff" then\r
+ config <= not LED;\r
end if;\r
else\r
- LED <= led_i;\r
+ led_highz <= '0';\r
end if;\r
end process; \r
\r
+LED <= led_i when led_highz = '0' else "ZZZZ";\r
+\r
---------------------------------------------------------------------------\r
-- UART\r
---------------------------------------------------------------------------\r
THE_UART : entity work.uart_sctrl\r
generic map(\r
- CLOCK_SPEED => 33250000\r
+ CLOCK_SPEED => 133000000\r
)\r
port map(\r
CLK => clk_i,\r
DEBUG => open\r
);\r
\r
----------------------------------------------------------------------------\r
--- UART\r
----------------------------------------------------------------------------\r
+\r
+PROC_REGS : process begin\r
+ wait until rising_edge(clk_i);\r
+ bus_ready <= '0';\r
+ if bus_read = '1' then\r
+ bus_ready <= '1';\r
+ case uart_addr is\r
+ when x"00" => uart_tx_data <= x"0000000" & config;\r
+ when x"10" => uart_tx_data <= reg;\r
+ end case;\r
+ elsif bus_write = '1' then\r
+ case uart_addr is\r
+ when x"10" => reg <= uart_rx_data;\r
+ end case;\r
+ end if;\r
+end process;\r
+\r
\r
\r
end architecture;\r
jspc29 / logicbox.git / commitdiff