signal pcs_an_ready : std_logic;
signal link_active : std_logic;
- signal debug : std_logic_vector(127 downto 0);
signal sniffer_data : std_logic_vector(7 downto 0); -- SCTRL endpoint
signal sniffer_wr : std_logic;
signal dlm_ctr : unsigned(23 downto 0);
signal rst_dlm_ctr_x : std_logic;
signal rst_dlm_ctr : std_logic;
-
signal dlm_tag_ctr : unsigned(7 downto 0);
signal inc_dlm_tag : std_logic;
+ signal dlm_enable_int : std_logic;
+ signal dlm_period_int : std_logic_vector(23 downto 0);
signal master_clk : std_logic;
signal global_reset_i : std_logic;
signal wap_pscb : std_logic_vector(15 downto 0);
signal wap_pscc : std_logic_vector(15 downto 0);
signal wap_pscd : std_logic_vector(15 downto 0);
+ signal sync_tx_pll_i : std_logic;
+ signal dlm_rx_int : std_logic;
+ signal dlm_rx_pl_int : std_logic_vector(7 downto 0);
+
+ signal debug_pcsa : std_logic_vector(127 downto 0);
+ signal debug_pcsb : std_logic_vector(127 downto 0);
+ signal debug_pcsc : std_logic_vector(127 downto 0);
+ signal debug_pcsd : std_logic_vector(127 downto 0);
begin
LED_GREEN_OUT => LED_RJ_GREEN(1)
);
- HDR_IO(1) <= '0';
+ HDR_IO(1) <= dlm_inject_int;
HDR_IO(2) <= '0';
HDR_IO(3) <= '0';
HDR_IO(4) <= '0';
---------------------------------------------------------------------------
-- DLM timing generator
---------------------------------------------------------------------------
+ dlm_enable_int <= aux_reg(31);
+ dlm_period_int <= aux_reg(23 downto 0);
+
+ -- generates an adjustable period signal for sending DLMs
+ -- BUG: better use count down and preload
THE_DLM_SEND_PROC: process( clk_sys )
begin
if( rising_edge(clk_sys) ) then
inc_dlm_tag <= rst_dlm_ctr;
rst_dlm_ctr <= rst_dlm_ctr_x;
- if( (reset_i = '1') or (rst_dlm_ctr = '1') or (aux_reg(31) = '0') ) then
+ if( (reset_i = '1') or (rst_dlm_ctr = '1') or (dlm_enable_int = '0') ) then
dlm_ctr <= (others => '0');
- elsif( aux_reg(31) = '1' ) then
+ elsif( dlm_enable_int = '1' ) then
dlm_ctr <= dlm_ctr + 1;
end if;
end if;
end process THE_DLM_SEND_PROC;
- rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = aux_reg(23 downto 0)) and (aux_reg(31) = '1')) else '0';
+ rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = dlm_period_int) and (dlm_enable_int = '1')) else '0';
-- DLM "tag" for blinking LEDs :)
THE_DLM_TAG_CTR_PROC: process( clk_sys )
begin
if( rising_edge(clk_sys) ) then
- if( (reset_i = '1') or (aux_reg(31) = '0') ) then
+ if( (reset_i = '1') or (dlm_enable_int = '0') ) then
dlm_tag_ctr <= (others => '0');
elsif( inc_dlm_tag = '1' ) then
dlm_tag_ctr <= dlm_tag_ctr + 1;
end if;
end process THE_DLM_TAG_CTR_PROC;
- dlm_inject_int <= rst_dlm_ctr;
- dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr);
-
+ -- we use received information unless switched to local
+ dlm_inject_int <= rst_dlm_ctr when dlm_enable_int = '1' else dlm_rx_int;
+ dlm_tx_data_int <= std_logic_vector(dlm_tag_ctr) when dlm_enable_int = '1' else dlm_rx_pl_int;
+
---------------------------------------------------------------------------
-- FiFo controller
---------------------------------------------------------------------------
-- 8 : fifo_eof
-- 7..0: data
- DBG(31 downto 0) <= debug(31 downto 0);
+ DBG(15 downto 0) <= debug_pcsd(15 downto 0);
+ DBG(31 downto 16) <= debug_pcsc(111 downto 96);
DBG(32) <= '0';
DBG(33) <= master_clk;
THE_GBE_MED_PCSA: entity gbe_med_fifo
generic map(
LINK_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER),
- INCLUDE_DLM => (0,0,0,1)
+ INCLUDE_DLM => (0,0,0,0)
+-- INCLUDE_DLM => (0,0,0,1)
)
port map(
RESET => reset_i,
MASTER_CLK_IN => master_clk,
MASTER_CLK_OUT => open,
TX_CLK_AVAIL_OUT => open,
- SYNC_TX_PLL_IN => '0',
+ SYNC_TX_PLL_IN => sync_tx_pll_i,
WAP_REQUESTED_IN => control_reg(3 downto 0),
-- DLM
- DLM_INJECT_IN(0) => dlm_inject_int,
- DLM_DATA_IN(7 downto 0) => dlm_tx_data_int,
- DLM_FOUND_OUT => open,
- DLM_DATA_OUT => open,
- DLM_CLK_OUT => open,
+ DLM_RX_OUT => open,
+ DLM_RX_PL_OUT => open,
+ DLM_TX_IN => dlm_inject_int,
+ DLM_TX_PL_IN => dlm_tx_data_int,
-- Debug
WAP_OUT => wap_psca,
STATUS_OUT => status_raw(1 * 32 - 1 downto 0 * 32),
- DEBUG_OUT => open
+ DEBUG_OUT => debug_pcsa
);
---------------------------------------------------------------------------
THE_GBE_MED_PCSB: entity gbe_med_fifo
generic map(
LINK_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
- INCLUDE_DLM => (1,1,1,1)
+ INCLUDE_DLM => (0,0,0,0)
+-- INCLUDE_DLM => (1,1,1,1)
)
port map(
RESET => reset_i,
MASTER_CLK_IN => master_clk,
MASTER_CLK_OUT => open,
TX_CLK_AVAIL_OUT => open,
- SYNC_TX_PLL_IN => '0',
+ SYNC_TX_PLL_IN => sync_tx_pll_i,
WAP_REQUESTED_IN => control_reg(3 downto 0),
-- DLM
- DLM_INJECT_IN(0) => dlm_inject_int,
- DLM_INJECT_IN(1) => dlm_inject_int,
- DLM_INJECT_IN(2) => dlm_inject_int,
- DLM_INJECT_IN(3) => dlm_inject_int,
- DLM_DATA_IN(7 downto 0) => dlm_tx_data_int,
- DLM_DATA_IN(15 downto 8) => dlm_tx_data_int,
- DLM_DATA_IN(23 downto 16) => dlm_tx_data_int,
- DLM_DATA_IN(31 downto 24) => dlm_tx_data_int,
- DLM_FOUND_OUT => open,
- DLM_DATA_OUT => open,
- DLM_CLK_OUT => open,
+ DLM_RX_OUT => open,
+ DLM_RX_PL_OUT => open,
+ DLM_TX_IN => dlm_inject_int,
+ DLM_TX_PL_IN => dlm_tx_data_int,
-- Debug
WAP_OUT => wap_pscb,
STATUS_OUT => status_raw(2 * 32 - 1 downto 1 * 32),
- DEBUG_OUT => open
+ DEBUG_OUT => debug_pcsb
);
---------------------------------------------------------------------------
THE_GBE_MED_PCSC: entity gbe_med_fifo
generic map(
LINK_MODE => (c_IS_MASTER, c_IS_MASTER, c_IS_MASTER, c_IS_MASTER),
- INCLUDE_DLM => (1,1,1,1)
+ INCLUDE_DLM => (0,0,0,0)
+-- INCLUDE_DLM => (1,1,1,1)
)
port map(
RESET => reset_i,
CLEAR => clear_i,
CLEAR_N => clear_n_i,
CLK_125 => clk_sys,
- -- SerDes 0 -- DOWNLINK
+ -- SerDes 0 -- DOWNLINKdlm_tx_pl_in
-- FIFO interface RX
FIFO_FULL_IN(0) => '0', -- BUG
FIFO_WR_OUT(0) => dl_rx_data(5)(9),
MASTER_CLK_IN => master_clk,
MASTER_CLK_OUT => open,
TX_CLK_AVAIL_OUT => open,
- SYNC_TX_PLL_IN => '0',
+ SYNC_TX_PLL_IN => sync_tx_pll_i,
WAP_REQUESTED_IN => control_reg(3 downto 0),
-- DLM
- DLM_INJECT_IN(0) => dlm_inject_int,
- DLM_INJECT_IN(1) => dlm_inject_int,
- DLM_INJECT_IN(2) => dlm_inject_int,
- DLM_INJECT_IN(3) => dlm_inject_int,
- DLM_DATA_IN(7 downto 0) => dlm_tx_data_int,
- DLM_DATA_IN(15 downto 8) => dlm_tx_data_int,
- DLM_DATA_IN(23 downto 16) => dlm_tx_data_int,
- DLM_DATA_IN(31 downto 24) => dlm_tx_data_int,
- DLM_FOUND_OUT => open,
- DLM_DATA_OUT => open,
- DLM_CLK_OUT => open,
+ DLM_RX_OUT => open,
+ DLM_RX_PL_OUT => open,
+ DLM_TX_IN => dlm_inject_int,
+ DLM_TX_PL_IN => dlm_tx_data_int,
-- Debug
WAP_OUT => wap_pscc,
STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32),
- DEBUG_OUT => open
+ DEBUG_OUT => debug_pcsc
);
---------------------------------------------------------------------------
THE_GBE_MED_PCSD: entity gbe_med_fifo
generic map(
LINK_MODE => (c_IS_UNUSED, c_IS_UNUSED, c_IS_MASTER, c_IS_SLAVE),
- INCLUDE_DLM => (0,0,1,1)
+ INCLUDE_DLM => (0,0,0,0)
+-- INCLUDE_DLM => (0,0,1,1)
)
port map(
RESET => reset_i,
FRAME_START_OUT(0) => ul_rx_data(10),
FRAME_REQ_IN(0) => ul_rx_frame_req,
FRAME_ACK_OUT(0) => ul_rx_frame_ack,
- FRAME_AVAIL_OUT(0) => ul_rx_frame_avail,
+ --FRAME_AVAIL_OUT(0) => ul_rx_frame_avail,
-- FIFO interface TX
FIFO_WR_IN(0) => ul_tx_data(9),
FIFO_DATA_IN(8 downto 0) => ul_tx_data(8 downto 0),
MASTER_CLK_IN => master_clk,
MASTER_CLK_OUT => master_clk,
TX_CLK_AVAIL_OUT => tx_clk_avail_i,
- SYNC_TX_PLL_IN => '0',
+ SYNC_TX_PLL_IN => sync_tx_pll_i,
WAP_REQUESTED_IN => control_reg(3 downto 0),
-- DLM
- DLM_INJECT_IN => (others => '0'),
- DLM_DATA_IN => (others => '0'),
- DLM_FOUND_OUT => open,
- DLM_DATA_OUT => open,
- DLM_CLK_OUT => open,
+ DLM_RX_OUT => dlm_rx_int, -- from slave port
+ DLM_RX_PL_OUT => dlm_rx_pl_int, -- from slave port
+ DLM_TX_IN => dlm_inject_int,
+ DLM_TX_PL_IN => dlm_tx_data_int,
-- Debug
WAP_OUT => wap_pscd,
STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32),
- DEBUG_OUT => debug --open
+ DEBUG_OUT => debug_pcsd
);
---------------------------------------------------------------------------
TX_PLL_LOL_IN => tx_pll_lol_i,
TX_CLOCK_AVAIL_IN => tx_clk_avail_i,
TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i,
- SYNC_TX_QUAD_OUT => open, --not needed here
+ SYNC_TX_QUAD_OUT => sync_tx_pll_i,
LINK_TX_READY_OUT => link_tx_ready_i,
STATE_OUT => open
);
-- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
LED_GREEN <= not status(0); --'0';
LED_ORANGE <= not tx_clk_avail_i; --'0';
- LED_RED <= not '0';
+ LED_RED <= not link_tx_ready_i;
LED_YELLOW <= not '0';
- LED_HUB_LINKOK(1) <= not status_raw(10 * 8 + 6); --'0'; -- C2
- LED_HUB_TX(1) <= not status_raw(10 * 8 + 5); --'0';
+ LED_HUB_LINKOK(1) <= not status_raw(10 * 8 + 7); --'0'; -- C2
+ LED_HUB_TX(1) <= not status_raw(10 * 8 + 2); --'0';
LED_HUB_RX(1) <= not '0';
- LED_HUB_LINKOK(2) <= not status_raw(11 * 8 + 6); --'0'; -- C3
- LED_HUB_TX(2) <= not status_raw(11 * 8 + 5); --'0';
+ LED_HUB_LINKOK(2) <= not status_raw(11 * 8 + 7); --'0'; -- C3
+ LED_HUB_TX(2) <= not status_raw(11 * 8 + 2); --'0';
LED_HUB_RX(2) <= not '0';
- LED_HUB_LINKOK(3) <= not status_raw(8 * 8 + 6); --'0'; -- C0
- LED_HUB_TX(3) <= not status_raw(8 * 8 + 5); --'0';
+ LED_HUB_LINKOK(3) <= not status_raw(8 * 8 + 7); --'0'; -- C0
+ LED_HUB_TX(3) <= not status_raw(8 * 8 + 2); --'0';
LED_HUB_RX(3) <= not '0';
- LED_HUB_LINKOK(4) <= not status_raw(9 * 8 + 6); --'0'; -- C1
- LED_HUB_TX(4) <= not status_raw(9 * 8 + 5); --'0';
+ LED_HUB_LINKOK(4) <= not status_raw(9 * 8 + 7); --'0'; -- C1
+ LED_HUB_TX(4) <= not status_raw(9 * 8 + 2); --'0';
LED_HUB_RX(4) <= not '0';
- LED_HUB_LINKOK(5) <= not status_raw(4 * 8 + 6); --'0'; -- B0
- LED_HUB_TX(5) <= not status_raw(4 * 8 + 5); --'0';
+ LED_HUB_LINKOK(5) <= not status_raw(4 * 8 + 7); --'0'; -- B0
+ LED_HUB_TX(5) <= not status_raw(4 * 8 + 2); --'0';
LED_HUB_RX(5) <= not '0';
- LED_HUB_LINKOK(6) <= not status_raw(5 * 8 + 6); --'0'; -- B1
- LED_HUB_TX(6) <= not status_raw(5 * 8 + 5); --'0';
+ LED_HUB_LINKOK(6) <= not status_raw(5 * 8 + 7); --'0'; -- B1
+ LED_HUB_TX(6) <= not status_raw(5 * 8 + 2); --'0';
LED_HUB_RX(6) <= not '0';
- LED_HUB_LINKOK(7) <= not status_raw(6 * 8 + 6); --'0'; -- B2
- LED_HUB_TX(7) <= not status_raw(6 * 8 + 5); --'0';
+ LED_HUB_LINKOK(7) <= not status_raw(6 * 8 + 7); --'0'; -- B2
+ LED_HUB_TX(7) <= not status_raw(6 * 8 + 2); --'0';
LED_HUB_RX(7) <= not '0';
- LED_HUB_LINKOK(8) <= not status_raw(7 * 8 + 6); --'0'; -- B3
- LED_HUB_TX(8) <= not status_raw(7 * 8 + 5); --'0';
+ LED_HUB_LINKOK(8) <= not status_raw(7 * 8 + 7); --'0'; -- B3
+ LED_HUB_TX(8) <= not status_raw(7 * 8 + 2); --'0';
LED_HUB_RX(8) <= not '0';
- LED_SFP_GREEN(0) <= not status_raw(12 * 8 + 6); --'0'; -- D0
- LED_SFP_RED(0) <= not status_raw(12 * 8 + 5); --'0';
+ LED_SFP_GREEN(0) <= not status_raw(12 * 8 + 7); --'0'; -- D0
+ LED_SFP_RED(0) <= not status_raw(12 * 8 + 2); --'0';
- LED_SFP_GREEN(1) <= not status_raw(13 * 8 + 6); --'0'; -- D1
- LED_SFP_RED(1) <= not status_raw(13 * 8 + 5); --'0';
+ LED_SFP_GREEN(1) <= not status_raw(13 * 8 + 7); --'0'; -- D1
+ LED_SFP_RED(1) <= not status_raw(13 * 8 + 2); --'0';
LED_WHITE(1) <= not additional_reg(31); --'0';
LED_WHITE(0) <= not status(0); --'0';
- LED_RJ_GREEN(0) <= not status_raw(0 * 8 + 6); -- A0
- LED_RJ_RED(0) <= not status_raw(0 * 8 + 5);
+ LED_RJ_GREEN(0) <= not status_raw(0 * 8 + 7); -- A0
+ LED_RJ_RED(0) <= not status_raw(0 * 8 + 2);
end architecture;
jspc29 / trb3sc.git / commitdiff