Let's try with this ADC phase determination

diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd
index 6e875b2867dea3d6ee198ea78e96a1f47af6c169..2de252c4ab14c4fdc768f72a5414eef9277b6a27 100644 (file)
--- a/ADC/source/adc_handler.vhd
+++ b/ADC/source/adc_handler.vhd
@@ -404,15 +404,15 @@ begin
         );
     end generate;
     
-    ADC_CLK_TDC_OUT <= epoch_counter(10);
-    
     PROC_EPOCH_COUNTER : process is
     begin
       wait until rising_edge(adc_clk_left);
       epoch_counter <= epoch_counter + 1;
       trigger_in_i <= TRIGGER_IN;
+      ADC_CLK_TDC_OUT <= '0';
       if trigger_in_i = '1' then
         epoch_counter_save <= epoch_counter;
+        ADC_CLK_TDC_OUT <= '1';
       end if;
     end process PROC_EPOCH_COUNTER;