]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Tue, 6 Apr 2010 13:47:02 +0000 (13:47 +0000)
committerhadeshyp <hadeshyp>
Tue, 6 Apr 2010 13:47:02 +0000 (13:47 +0000)
special/handler_data.vhd
special/handler_ipu.vhd
special/handler_trigger_and_data.vhd
trb_net16_endpoint_hades_full.vhd
trb_net16_endpoint_hades_full_handler.vhd

index 140686bb49ebe88b07d316cc13b4005090c85127..1807848d7126aa151004c937e6501983f08e46c9 100644 (file)
@@ -13,7 +13,7 @@ entity handler_data is
   generic(
     DATA_INTERFACE_NUMBER        : integer range 1 to 16         := 1;
     DATA_BUFFER_DEPTH            : integer range 8 to 15         := 9;
-    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 31;
+    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 32;
     DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**15-1    := 2**8;
     TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
     HEADER_BUFFER_DEPTH          : integer range 8 to 15         := 9;
@@ -114,7 +114,7 @@ architecture handler_data_arch of handler_data is
   signal header_buffer_full        : std_logic;
   signal header_buffer_empty       : std_logic;
   signal header_buffer_almost_full : std_logic;
-  signal header_buffer_write       : std_logic;
+  signal header_buffer_write       : std_logic := '0';
 
   signal lvl1_busy_release_i       : std_logic;
   signal lvl1_statusbits_i         : std_logic_vector(31 downto 0);
@@ -129,7 +129,7 @@ architecture handler_data_arch of handler_data is
 
   signal length_buffer_data_in     : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0);
   signal length_buffer_data_out    : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0);
-  signal length_buffer_write       : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+  signal length_buffer_write       : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0) := (others => '0');
   signal length_buffer_empty       : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
   signal length_buffer_full        : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
   signal length_buffer_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
@@ -149,6 +149,8 @@ begin
   IPU_HDR_DATA_OUT               <= header_buffer_data_out(31 downto 0);
   IPU_DATA_EMPTY_OUT             <= data_buffer_empty;
 
+  LVL1_TRG_RELEASE_OUT           <= lvl1_busy_release_i;
+
 
 ---------------------------------------------------------------------------
 -- Generate Fifo I/O
@@ -220,7 +222,7 @@ begin
 ---------------------------------------------------------------------------
 -- Length FIFO
 ---------------------------------------------------------------------------
-  gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
+  gen_length_fifo : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
     THE_LENGTH_FIFO : fifo_var_oreg
       generic map(
         FIFO_WIDTH               => 18,
@@ -239,6 +241,9 @@ begin
         Full                     => length_buffer_full(i),
         AlmostFull               => length_buffer_almost_full(i)
         );
+
+    IPU_DATA_LENGTH_OUT(i*16+15 downto i*16)  <= length_buffer_data_out(i*18+15 downto i*18);
+
   end generate;
 
 
@@ -253,6 +258,7 @@ begin
             current_buffer_state(i)        <= IDLE;
           else
             length_buffer_write(i)         <= '0';
+            length_buffer_data_in(i*18+17 downto i*18) <= LVL1_TRG_NUMBER_IN(1 downto 0) & std_logic_vector(data_counter(i));
 
             case current_buffer_state(i) is
               when IDLE =>
@@ -290,22 +296,30 @@ begin
     begin
       if rising_edge(CLOCK) then
         if RESET = '1' then
-          current_lvl1_state <= IDLE;
+          current_lvl1_state   <= IDLE;
+          header_buffer_write  <= '0';
+          lvl1_busy_release_i  <= '0';
         else
-          LVL1_TRG_RELEASE_OUT             <= '0';
+          lvl1_busy_release_i              <= '0';
+          header_buffer_write              <= '0';
           case current_lvl1_state is
             when IDLE =>
               lvl1_state_bits              <= "001";
+              if LVL1_VALID_TRIGGER_IN = '1' then
+                current_lvl1_state         <= WAIT_BUSY;
+              end if;
 
             when WAIT_BUSY =>
               lvl1_state_bits              <= "010";
+              if LVL1_TRG_DATA_VALID_IN = '1' and or_all(got_busy_release) = '1' then
+                current_lvl1_state         <= BUSY_RELEASE;
+              end if;
 
             when BUSY_RELEASE =>
               lvl1_state_bits              <= "100";
-              if or_all(got_busy_release) = '1'  then
-                LVL1_TRG_RELEASE_OUT       <= '1';
-                current_lvl1_state         <= IDLE;
-              end if;
+              lvl1_busy_release_i          <= '1';
+              header_buffer_write          <= '1';
+              current_lvl1_state           <= IDLE;
 
           end case;
         end if;
@@ -322,7 +336,9 @@ begin
           got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)
                                  <= got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0) or FEE_DATA_FINISHED_IN;
           if TRG_RELEASE_AFTER_DATA = c_NO then
-            got_busy_release(DATA_INTERFACE_NUMBER) <= '1';
+            got_busy_release(DATA_INTERFACE_NUMBER)
+                                 <= not (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full)
+                                                                         or header_buffer_almost_full);
           elsif or_all(got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)) = '1' and
                 (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' then
             got_busy_release(DATA_INTERFACE_NUMBER) <= '1';
index 36ef167c22efadefc4aabe70a07684aa8b6c97af..c7abb64ffa5f3baefe62a84c23b9ae45031511cf 100644 (file)
@@ -114,8 +114,8 @@ begin
 
   THE_FSM : process(current_state, error_not_found, IPU_START_READOUT_IN, DAT_HDR_DATA_EMPTY_IN,
                     DAT_HDR_DATA_IN, last_hdr_fifo_valid_read, ipu_dataready_i, IPU_READ_IN,
-                    DAT_HDR_DATA_EMPTY_IN, error_missing, dat_fifo_valid_read, next_dat_fifo_number,
-                    dat_fifo_finished, dat_fifo_number, ipu_dataready_i)
+                    error_missing, dat_fifo_valid_read, next_dat_fifo_number,
+                    dat_fifo_finished, dat_fifo_number, DAT_DATA_IN)
     begin
       next_state                 <= current_state;
       next_error_not_found       <= error_not_found;
index 81b0fe8bd8bf121af071723dbcb0289ccb2b4b89..3cbad87d738b103ec70a3448924596f8db8064cd 100644 (file)
@@ -99,6 +99,7 @@ architecture handler_trigger_and_data_arch of handler_trigger_and_data is
   signal ipu_header_read         : std_logic;
 
   signal fee_trg_release         : std_logic_vector(DATA_INTERFACE_NUMBER downto 0);
+  signal buf_lvl1_trg_release    : std_logic;
 
 
 begin
@@ -111,7 +112,7 @@ begin
     variable tmp_statusbits : std_logic_vector(31 downto 0);
     begin
       if rising_edge(CLOCK) then
-        if RESET = '1' or LVL1_VALID_TRIGGER_IN = '0' then
+        if RESET = '1' or buf_lvl1_trg_release = '1' then
           fee_trg_statusbits     <= (others => '0');
           fee_trg_release        <= (others => '0');
         else
@@ -220,7 +221,8 @@ begin
 -----------------------------------------------------------------------
 -- Connect Outputs
 -----------------------------------------------------------------------
-  LVL1_TRG_RELEASE_OUT           <= and_all(fee_trg_release);
+  LVL1_TRG_RELEASE_OUT           <= buf_lvl1_trg_release;
+  buf_lvl1_trg_release           <= and_all(fee_trg_release);
   LVL1_ERROR_PATTERN_OUT         <= fee_trg_statusbits;
 
 
index 9977063000921d3ae7915caaede96a4ff9e66bd9..e9ee71cd911d34b44578fe9f3c62be207bb6fc5a 100644 (file)
@@ -323,7 +323,8 @@ begin
             CTRL_GEN               => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
             STAT_INIT_OBUF_DEBUG   => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32),
             STAT_REPLY_OBUF_DEBUG  => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32),
-            TIMER_TICKS_IN         => buf_TIMER_TICKS_OUT
+            TIMER_TICKS_IN         => buf_TIMER_TICKS_OUT,
+            CTRL_STAT              => x"0000"
             );
 
       gen_api : if i /= c_TRG_LVL1_CHANNEL generate
index c465a274e103f67cd61dcf7cf251088cafbe1661..12d8926ee40b4cf7e7f0e7cd46894276c867d39a 100644 (file)
@@ -32,7 +32,7 @@ entity trb_net16_endpoint_hades_full_handler is
     --Configure data handler
     DATA_INTERFACE_NUMBER        : integer range 1 to 16         := 1;
     DATA_BUFFER_DEPTH            : integer range 9 to 14         := 9;
-    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 31;
+    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 32;
     DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
     TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
     HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
@@ -195,6 +195,8 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha
   signal tbuf_dataready          : std_logic;
   signal tbuf_read_enable        : std_logic;
 
+  signal dummy                   : std_logic_vector(95 downto 0);
+
 begin
 ---------------------------------------------------------------------------
 -- TrbNet Endpoint
@@ -329,38 +331,71 @@ begin
       DAT_NO_MORE_DATA_OUT       => regio_nomoredata_i,
       DAT_UNKNOWN_ADDR_OUT       => regio_unknown_addr_i,
 
+--       BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
+--       BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
+--       BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
+--       BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
+--       BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
+--       BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
+--       BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
+--       BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
+--       BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
+--       BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
+--
+--       BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
+--       BUS_WRITE_ENABLE_OUT(1)    => open,
+--       BUS_DATA_OUT(63 downto 32) => open,
+--       BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+--       BUS_ADDR_OUT(31 downto 20) => open,
+--       BUS_TIMEOUT_OUT(1)         => open,
+--       BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
+--       BUS_DATAREADY_IN(1)        => dbuf_dataready,
+--       BUS_WRITE_ACK_IN(1)        => '0',
+--       BUS_NO_MORE_DATA_IN(1)     => '0',
+--       BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
+--
+--       BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
+--       BUS_WRITE_ENABLE_OUT(2)    => open,
+--       BUS_DATA_OUT(95 downto 64) => open,
+--       BUS_ADDR_OUT(47 downto 32) => open,
+--       BUS_TIMEOUT_OUT(1)         => open,
+--       BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
+--       BUS_DATAREADY_IN(2)        => tbuf_dataready,
+--       BUS_WRITE_ACK_IN(2)        => '0',
+--       BUS_NO_MORE_DATA_IN(2)     => '0',
+--       BUS_UNKNOWN_ADDR_IN(2)     => '0'
+
+--Fucking Modelsim wants it like this...
       BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
+      BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
+      BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
       BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
+      BUS_WRITE_ENABLE_OUT(1)    => dummy(0),
+      BUS_WRITE_ENABLE_OUT(2)    => dummy(1),
       BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
+      BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),
+      BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),
       BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
+      BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+      BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),
+      BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),
       BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
+      BUS_TIMEOUT_OUT(1)         => dummy(94),
+      BUS_TIMEOUT_OUT(2)         => dummy(95),
       BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
-      BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
-      BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
-      BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
-      BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
-
-      BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
-      BUS_WRITE_ENABLE_OUT(1)    => open,
-      BUS_DATA_OUT(63 downto 32) => open,
-      BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
-      BUS_ADDR_OUT(31 downto 20) => open,
-      BUS_TIMEOUT_OUT(1)         => open,
       BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
-      BUS_DATAREADY_IN(1)        => dbuf_dataready,
-      BUS_WRITE_ACK_IN(1)        => '0',
-      BUS_NO_MORE_DATA_IN(1)     => '0',
-      BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
-
-      BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
-      BUS_WRITE_ENABLE_OUT(2)    => open,
-      BUS_DATA_OUT(95 downto 64) => open,
-      BUS_ADDR_OUT(47 downto 32) => open,
-      BUS_TIMEOUT_OUT(1)         => open,
       BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
+      BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
+      BUS_DATAREADY_IN(1)        => dbuf_dataready,
       BUS_DATAREADY_IN(2)        => tbuf_dataready,
+      BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
+      BUS_WRITE_ACK_IN(1)        => '0',
       BUS_WRITE_ACK_IN(2)        => '0',
+      BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
+      BUS_NO_MORE_DATA_IN(1)     => '0',
       BUS_NO_MORE_DATA_IN(2)     => '0',
+      BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
+      BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
       BUS_UNKNOWN_ADDR_IN(2)     => '0'
       );
 
@@ -431,7 +466,7 @@ begin
 -- Connect Status Registers
 ---------------------------------------------------------------------------
   proc_buf_status : process(CLK)
-    variable tmp : integer range 0 to DATA_INTERFACE_NUMBER-1;
+    variable tmp : integer range 0 to 15;
     begin
       if rising_edge(CLK) then
         dbuf_unknown_addr        <= '0';