generic(
DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
DATA_BUFFER_DEPTH : integer range 8 to 15 := 9;
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;
DATA_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**8;
TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;
HEADER_BUFFER_DEPTH : integer range 8 to 15 := 9;
signal header_buffer_full : std_logic;
signal header_buffer_empty : std_logic;
signal header_buffer_almost_full : std_logic;
- signal header_buffer_write : std_logic;
+ signal header_buffer_write : std_logic := '0';
signal lvl1_busy_release_i : std_logic;
signal lvl1_statusbits_i : std_logic_vector(31 downto 0);
signal length_buffer_data_in : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0);
signal length_buffer_data_out : std_logic_vector(DATA_INTERFACE_NUMBER*18-1 downto 0);
- signal length_buffer_write : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
+ signal length_buffer_write : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0) := (others => '0');
signal length_buffer_empty : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
signal length_buffer_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
signal length_buffer_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
IPU_HDR_DATA_OUT <= header_buffer_data_out(31 downto 0);
IPU_DATA_EMPTY_OUT <= data_buffer_empty;
+ LVL1_TRG_RELEASE_OUT <= lvl1_busy_release_i;
+
---------------------------------------------------------------------------
-- Generate Fifo I/O
---------------------------------------------------------------------------
-- Length FIFO
---------------------------------------------------------------------------
- gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
+ gen_length_fifo : for i in 0 to DATA_INTERFACE_NUMBER-1 generate
THE_LENGTH_FIFO : fifo_var_oreg
generic map(
FIFO_WIDTH => 18,
Full => length_buffer_full(i),
AlmostFull => length_buffer_almost_full(i)
);
+
+ IPU_DATA_LENGTH_OUT(i*16+15 downto i*16) <= length_buffer_data_out(i*18+15 downto i*18);
+
end generate;
current_buffer_state(i) <= IDLE;
else
length_buffer_write(i) <= '0';
+ length_buffer_data_in(i*18+17 downto i*18) <= LVL1_TRG_NUMBER_IN(1 downto 0) & std_logic_vector(data_counter(i));
case current_buffer_state(i) is
when IDLE =>
begin
if rising_edge(CLOCK) then
if RESET = '1' then
- current_lvl1_state <= IDLE;
+ current_lvl1_state <= IDLE;
+ header_buffer_write <= '0';
+ lvl1_busy_release_i <= '0';
else
- LVL1_TRG_RELEASE_OUT <= '0';
+ lvl1_busy_release_i <= '0';
+ header_buffer_write <= '0';
case current_lvl1_state is
when IDLE =>
lvl1_state_bits <= "001";
+ if LVL1_VALID_TRIGGER_IN = '1' then
+ current_lvl1_state <= WAIT_BUSY;
+ end if;
when WAIT_BUSY =>
lvl1_state_bits <= "010";
+ if LVL1_TRG_DATA_VALID_IN = '1' and or_all(got_busy_release) = '1' then
+ current_lvl1_state <= BUSY_RELEASE;
+ end if;
when BUSY_RELEASE =>
lvl1_state_bits <= "100";
- if or_all(got_busy_release) = '1' then
- LVL1_TRG_RELEASE_OUT <= '1';
- current_lvl1_state <= IDLE;
- end if;
+ lvl1_busy_release_i <= '1';
+ header_buffer_write <= '1';
+ current_lvl1_state <= IDLE;
end case;
end if;
got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)
<= got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0) or FEE_DATA_FINISHED_IN;
if TRG_RELEASE_AFTER_DATA = c_NO then
- got_busy_release(DATA_INTERFACE_NUMBER) <= '1';
+ got_busy_release(DATA_INTERFACE_NUMBER)
+ <= not (or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full)
+ or header_buffer_almost_full);
elsif or_all(got_busy_release(DATA_INTERFACE_NUMBER-1 downto 0)) = '1' and
(or_all(data_buffer_almost_full) or or_all(length_buffer_almost_full) or header_buffer_almost_full) = '0' then
got_busy_release(DATA_INTERFACE_NUMBER) <= '1';
--Configure data handler
DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1;
DATA_BUFFER_DEPTH : integer range 9 to 14 := 9;
- DATA_BUFFER_WIDTH : integer range 1 to 32 := 31;
+ DATA_BUFFER_WIDTH : integer range 1 to 32 := 32;
DATA_BUFFER_FULL_THRESH : integer range 0 to 2**14-2 := 2**8;
TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES;
HEADER_BUFFER_DEPTH : integer range 9 to 14 := 9;
signal tbuf_dataready : std_logic;
signal tbuf_read_enable : std_logic;
+ signal dummy : std_logic_vector(95 downto 0);
+
begin
---------------------------------------------------------------------------
-- TrbNet Endpoint
DAT_NO_MORE_DATA_OUT => regio_nomoredata_i,
DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_i,
+-- BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,
+-- BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,
+-- BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,
+-- BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,
+-- BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,
+-- BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,
+-- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,
+-- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,
+-- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,
+-- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,
+--
+-- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,
+-- BUS_WRITE_ENABLE_OUT(1) => open,
+-- BUS_DATA_OUT(63 downto 32) => open,
+-- BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+-- BUS_ADDR_OUT(31 downto 20) => open,
+-- BUS_TIMEOUT_OUT(1) => open,
+-- BUS_DATA_IN(63 downto 32) => dbuf_data_in,
+-- BUS_DATAREADY_IN(1) => dbuf_dataready,
+-- BUS_WRITE_ACK_IN(1) => '0',
+-- BUS_NO_MORE_DATA_IN(1) => '0',
+-- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,
+--
+-- BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,
+-- BUS_WRITE_ENABLE_OUT(2) => open,
+-- BUS_DATA_OUT(95 downto 64) => open,
+-- BUS_ADDR_OUT(47 downto 32) => open,
+-- BUS_TIMEOUT_OUT(1) => open,
+-- BUS_DATA_IN(95 downto 64) => stat_header_buffer_level,
+-- BUS_DATAREADY_IN(2) => tbuf_dataready,
+-- BUS_WRITE_ACK_IN(2) => '0',
+-- BUS_NO_MORE_DATA_IN(2) => '0',
+-- BUS_UNKNOWN_ADDR_IN(2) => '0'
+
+--Fucking Modelsim wants it like this...
BUS_READ_ENABLE_OUT(0) => BUS_READ_ENABLE_OUT,
+ BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,
+ BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,
BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT(1) => dummy(0),
+ BUS_WRITE_ENABLE_OUT(2) => dummy(1),
BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT,
+ BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),
+ BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),
BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT,
+ BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
+ BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),
+ BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),
BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT,
+ BUS_TIMEOUT_OUT(1) => dummy(94),
+ BUS_TIMEOUT_OUT(2) => dummy(95),
BUS_DATA_IN(31 downto 0) => BUS_DATA_IN,
- BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,
- BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,
- BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,
- BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,
-
- BUS_READ_ENABLE_OUT(1) => dbuf_read_enable,
- BUS_WRITE_ENABLE_OUT(1) => open,
- BUS_DATA_OUT(63 downto 32) => open,
- BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
- BUS_ADDR_OUT(31 downto 20) => open,
- BUS_TIMEOUT_OUT(1) => open,
BUS_DATA_IN(63 downto 32) => dbuf_data_in,
- BUS_DATAREADY_IN(1) => dbuf_dataready,
- BUS_WRITE_ACK_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,
-
- BUS_READ_ENABLE_OUT(2) => tbuf_read_enable,
- BUS_WRITE_ENABLE_OUT(2) => open,
- BUS_DATA_OUT(95 downto 64) => open,
- BUS_ADDR_OUT(47 downto 32) => open,
- BUS_TIMEOUT_OUT(1) => open,
BUS_DATA_IN(95 downto 64) => stat_header_buffer_level,
+ BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN,
+ BUS_DATAREADY_IN(1) => dbuf_dataready,
BUS_DATAREADY_IN(2) => tbuf_dataready,
+ BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN,
+ BUS_WRITE_ACK_IN(1) => '0',
BUS_WRITE_ACK_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN,
+ BUS_NO_MORE_DATA_IN(1) => '0',
BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN,
+ BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr,
BUS_UNKNOWN_ADDR_IN(2) => '0'
);
-- Connect Status Registers
---------------------------------------------------------------------------
proc_buf_status : process(CLK)
- variable tmp : integer range 0 to DATA_INTERFACE_NUMBER-1;
+ variable tmp : integer range 0 to 15;
begin
if rising_edge(CLK) then
dbuf_unknown_addr <= '0';