--- /dev/null
+<?xml version="1.0" encoding="utf-8" ?>
+<TrbNetEntity xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ xsi:noNamespaceSchemaLocation="../schema/TrbNetEntity.xsd"
+ name="TDCv4"
+ address="c000"
+ >
+ <description>An FPGA-based tapped-delay line time-to-digital converter (TDC) version 4.0 for DiRICH </description>
+
+ <!--===========================================-->
+ <!-- TDC Status registers -->
+ <!--===========================================-->
+
+ <group name="Status" purpose="status" address="0e00" mode="r" continuous="false" size="18" >
+
+ <register name="InputSignal0" address="0001" purpose="status">
+ <description>Level of input signals. Rightmost box is channel 0.</description>
+ <field name="InputSignals_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="InputSignal1" address="0011" purpose="status">
+ <description>Level of input signals. Rightmost box is channel 16. Bit31 is Reference Channel.</description>
+ <field name="InputSignals_R_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="GeneralStatus" address="0000" purpose="status">
+ <description>Status information about the TDC-Core</description>
+ <field name="LOCK" start="0" bits="1" invertflag="true" format="enum" purpose="status">
+ <description>Lock signal for all PLLs, 1: not locked 0: locked</description>
+ <enumItem value="0">Locked</enumItem>
+ <enumItem value="1">Not Locked</enumItem>
+ </field>
+ <field name="SLOCK" start="1" bits="1" format="enum" purpose="status">
+ <description>Lock signal of the Sampling-PLL</description>
+ <enumItem value="0">Not Locked</enumItem>
+ <enumItem value="1">Locked</enumItem>
+ </field>
+ <field name="HLOCK" start="2" bits="1" format="enum" purpose="status">
+ <description>Lock signal of the Halfclock-PLL</description>
+ <enumItem value="0">Not Locked</enumItem>
+ <enumItem value="1">Locked</enumItem>
+ </field>
+ <field name="RESET" start="3" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>State of Reset-Signal for TDC-Core</description>
+ <enumItem value="0">TDC active</enumItem>
+ <enumItem value="1">TDC in Reset</enumItem>
+ </field>
+ <field name="ISTRES" start="4" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>TDC was reset because of illegal FSM-State (SEU)</description>
+ <enumItem value="0">No SEU</enumItem>
+ <enumItem value="1">SEU detected</enumItem>
+ </field>
+ <field name="DOVF" start="5" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>DAQ-FIFO full detected, possible Data Loss</description>
+ <enumItem value="0">No Overflow</enumItem>
+ <enumItem value="1">Overflow occurred</enumItem>
+ </field>
+ <field name="DLEND" start="6" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>Delay-Line min/max has been reached</description>
+ <enumItem value="0">In-band</enumItem>
+ <enumItem value="1">End reached</enumItem>
+ </field>
+ <field name="TBTDET" start="7" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>Trace Buffer Trigger Flag</description>
+ <enumItem value="0">Idle/Recording</enumItem>
+ <enumItem value="1">Trigger Found</enumItem>
+ </field>
+ <field name="HSTDET" start="8" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>High-Rate Sampler Trigger Flag</description>
+ <enumItem value="0">Idle/Recording</enumItem>
+ <enumItem value="1">Trigger Found</enumItem>
+ </field>
+ <field name="DLAIP" start="9" bits="1" format="enum" purpose="status" invertflag="true">
+ <description>Delay-Line Adjustment in Progress</description>
+ <enumItem value="0">Done</enumItem>
+ <enumItem value="1">Adjusting</enumItem>
+ </field>
+ </register>
+
+ <register name="TriggerCommandReturn" address="0010" purpose="status" rate="1">
+ <description>Type and ID of last finished Trigger Command, for both DAQ FIFO and Data Container.</description>
+ <field name="LastID_FIFO" start="0" bits="14" format="unsigned" purpose="status" />
+ <field name="LastType_FIFO" start="14" bits="4" format="unsigned" purpose="status" />
+ <field name="LastID_Container" start="18" bits="10" format="unsigned" purpose="status" />
+ <field name="LastType_Container" start="28" bits="4" format="unsigned" purpose="status" />
+ </register>
+
+ <register name="CaptureBlockTimeout0" address="0002" purpose="status">
+ <description>Timeout occurred in Capture Block. Rightmost box is channel 0.</description>
+ <field name="CaptureBlockTimeout_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="CaptureBlockTimeout1" address="0012" purpose="status">
+ <description>Timeout occurred in Capture Block. Rightmost box is channel 16. Bit31 is Reference Channel.</description>
+ <field name="CaptureBlockTimeout_R_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="StretcherDelayTooShort0" address="0003" purpose="status">
+ <description>Programmable Stretcher Delay is too short. Rightmost box is channel 0.</description>
+ <field name="StretcherDelayTooShort_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="StretcherDelayTooShort1" address="0013" purpose="status">
+ <description>Programmable Stretcher Delay is too short. Rightmost box is channel 16.</description>
+ <field name="StretcherDelayTooShort_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="DeadtimeViolationDetected0" address="0004" purpose="status">
+ <description>A second rising edge occurred during the deadtime. Rightmost box is channel 0.</description>
+ <field name="DeadtimeViolationDetected_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="DeadtimeViolationDetected1" address="0014" purpose="status">
+ <description>A second rising edge occurred during the deadtime. Rightmost box is channel 16.</description>
+ <field name="DeadtimeViolationDetected_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="SolitaryFallingEdgeDetected0" address="0005" purpose="status">
+ <description>A solitary falling edge occurred after the deadtime. Rightmost box is channel 0.</description>
+ <field name="SolitaryFallingEdgeDetected_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="SolitaryFallingEdgeDetected1" address="0015" purpose="status">
+ <description>A solitary falling edge occurred after the deadtime. Rightmost box is channel 16.</description>
+ <field name="SolitaryFallingEdgeDetected_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="HitFifoDataLoss0" address="0006" purpose="status">
+ <description>Data was discarded from the Hit FIFO. Rightmost box is channel 0.</description>
+ <field name="HitFifoDataLoss_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="HitFifoDataLoss1" address="0016" purpose="status">
+ <description>Data was discarded from the Hit FIFO. Rightmost box is channel 16. Bit31 is Reference Channel.</description>
+ <field name="HitFifoDataLoss_R_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="EventFifoDataLoss0" address="0007" purpose="status">
+ <description>Data was discarded from the Event FIFO. Rightmost box is channel 0.</description>
+ <field name="EventFifoDataLoss_15_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="EventFifoDataLoss1" address="0017" purpose="status">
+ <description>Data was discarded from the Event FIFO. Rightmost box is channel 16. Bit31 is Reference Channel.</description>
+ <field name="EventFifoDataLoss_R_31_16" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="IllegalChannelConfiguration0" address="0008" purpose="status">
+ <description>Illegal Combination of Channel Control Signals. One bit per channel pair. Rightmost box is channel pair 0.</description>
+ <field name="IllegalChannelConfiguration_7_0" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ <register name="IllegalChannelConfiguration1" address="0018" purpose="status">
+ <description>Illegal Combination of Channel Control Signals. One bit per channel pair. Rightmost box is channel pair 8.</description>
+ <field name="IllegalChannelConfiguration_15_8" start="0" bits="32" format="bitmask" purpose="status" rate="1" />
+ </register>
+
+ </group>
+
+ <!--===========================================-->
+ <!-- TDC control registers -->
+ <!--===========================================-->
+ <group name="Control" address="0d00" purpose="config" mode="rw" continuous="false" size="64">
+ <register name="ControlReg0" address="0000">
+ <description>Control Bits for all Channels</description>
+ <field name="PTDCRES" start="0" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Programmable TDC Reset. When 1, keeps TDC but not Control Subsystem in Reset.</description>
+ <enumItem value="0">Released</enumItem>
+ <enumItem value="1">Reset</enumItem>
+ </field>
+ <field name="PLLCTL0" start="1" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Reset-Signal for Sampling Clock PLL.</description>
+ <enumItem value="0">Released</enumItem>
+ <enumItem value="1">Reset</enumItem>
+ </field>
+ <field name="PLLCTL1" start="2" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Reset-Signal for Half-Frequency Clock PLL.</description>
+ <enumItem value="0">Released</enumItem>
+ <enumItem value="1">Reset</enumItem>
+ </field>
+ <field name="PLLCTL3_2" start="3" bits="2" mode="rw" format="enum">
+ <description>Dynamic Clock Selection Control.</description>
+ <enumItem value="0">Illegal</enumItem>
+ <enumItem value="1">Clock from Pin</enumItem>
+ <enumItem value="2">Clock from PLL</enumItem>
+ <enumItem value="3">Illegal</enumItem>
+ </field>
+ <field name="PLLCTL4" start="5" bits="1" mode="rw" format="enum">
+ <description>DCS Switching Mode.</description>
+ <enumItem value="0">Glitchless</enumItem>
+ <enumItem value="1">Non-glitchless</enumItem>
+ </field>
+ <field name="PLLCTL5" start="6" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Standby-Signal (power-down) for all TDC-PLLs.</description>
+ <enumItem value="0">Powered-up</enumItem>
+ <enumItem value="1">Standby</enumItem>
+ </field>
+ <field name="PLLCTL6" start="7" bits="1" mode="rw" format="enum">
+ <description>Reference Clock Select for Sampling Clock PLL. Not used on DiRICH.</description>
+ <enumItem value="0">Clock 0</enumItem>
+ <enumItem value="1">Clock 1</enumItem>
+ </field>
+ <field name="PHCRES" start="8" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Programmable Hit Counter Reset. When 1, keeps all Hit Counters at 0.</description>
+ <enumItem value="0">Released</enumItem>
+ <enumItem value="1">Reset</enumItem>
+ </field>
+ <field name="PHCGATE" start="9" bits="1" mode="rw" format="enum">
+ <description>Programmable Hit Counter Gate. When 0, no Hit Counter can count, instead keeps its value.</description>
+ <enumItem value="0">Stopped</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="PRCRES" start="10" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Programmable Reference Counter Reset.</description>
+ <enumItem value="0">Released</enumItem>
+ <enumItem value="1">Reset</enumItem>
+ </field>
+ <field name="ENDVD" start="11" bits="1" mode="rw" format="enum">
+ <description>Enable Deadtime Violation Detection.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="DTO" start="12" bits="5" format="unsigned" unit="us" scale="1.8">
+ <description>Deadman Timeout for Capture Block. When Timeout occurs, Capture Block will be reset. Disabled when bit 4 is set.</description>
+ </field>
+ <field name="SRCD" start="17" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Suppress Reference Channel Data in Event Data Packet.</description>
+ <enumItem value="0">Include</enumItem>
+ <enumItem value="1">Suppress</enumItem>
+ </field>
+ <field name="SEW" start="18" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Suppress Epoch Words in Event Data Packet.</description>
+ <enumItem value="0">Include</enumItem>
+ <enumItem value="1">Suppress</enumItem>
+ </field>
+ <field name="ATTS" start="19" bits="1" mode="rw" format="enum">
+ <description>Append Trigger Timestamps to Event Data Packet.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="MHPE" start="20" bits="5" format="unsigned">
+ <description>Maximum Number of Hits per Event. If bit 4 is set, all hits are included.</description>
+ </field>
+ <field name="RBLCKIN" start="25" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Block Input Buffer of the Reference Channel.</description>
+ <enumItem value="0">Pass</enumItem>
+ <enumItem value="1">Blocked</enumItem>
+ </field>
+ <field name="RINVA" start="26" bits="1" invertflag="true" mode="rw" format="enum">
+ <description>Input Signal Polarity Inversion for Reference Channel.</description>
+ <enumItem value="0">Non-Inverted</enumItem>
+ <enumItem value="1">Inverted</enumItem>
+ </field>
+ <field name="RENT" start="27" bits="1" mode="rw" format="enum">
+ <description>Enable TDL for Reference Channel.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="RINSEL" start="28" bits="1" mode="rw" format="enum">
+ <description>Input Select for Reference Channel. Only applies to TRB5sc.</description>
+ <enumItem value="0">RJ45</enumItem>
+ <enumItem value="1">Backplane</enumItem>
+ </field>
+ <field name="RRESEL" start="29" bits="1" mode="rw" format="enum">
+ <description>Rising Edge Select for Reference Channel.</description>
+ <enumItem value="0">Dual-Edge Mode</enumItem>
+ <enumItem value="1">Only Rising Edge</enumItem>
+ </field>
+ <field name="RSTSEL" start="30" bits="1" mode="rw" format="enum">
+ <description>Stretcher Select for Reference Channel.</description>
+ <enumItem value="0">Bypassed</enumItem>
+ <enumItem value="1">Employed</enumItem>
+ </field>
+ <field name="RENS" start="31" bits="1" mode="rw" format="enum">
+ <description>Enable Sampling-TDC for Reference Channel.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ </register>
+
+ <register name="ControlReg1" address="0001">
+ <description>Control Bits for all Channels</description>
+ <field name="NUMCP" start="0" bits="2" mode="rw" format="unsigned">
+ <description>Number of Calibration Pulses per Calibration Trigger. Actual number of pulses is NUMCP + 1. Program with SETCP.</description>
+ </field>
+ <field name="CALSET" start="2" bits="2" mode="rw" format="unsigned">
+ <description>Calibration Channel Set. 0: no Channels, 1: 1/4 round-robin, 2: 1/2 alternating, 3: all. Program with SETCP.</description>
+ </field>
+ <field name="CCDIV" start="4" bits="4" mode="rw" format="unsigned">
+ <description>Calibration Clock Divider. Pulse Length is (CCDIV + 1) / Fosc. Program with SETCF.</description>
+ </field>
+ <field name="CBDEL" start="8" bits="8" mode="rw" format="unsigned">
+ <description>Capture Block Delay. [7..4]: Stretcher, [3..0]: Unhit. Program with SETDP.</description>
+ </field>
+ <field name="DUID" start="16" bits="9" mode="rw" format="unsigned">
+ <description>Delay Unit ID. Capture Block: (4 * Channel Number). IOBlock Delay: (4 * Channel Number) + 1. Program with SETDP.</description>
+ </field>
+ <field name="DLDIR" start="25" bits="1" mode="rw" format="enum">
+ <description>Delay Line Step Direction. STEP or NSTEP will perform the Delay Adjustment.</description>
+ <enumItem value="0">Increase</enumItem>
+ <enumItem value="1">Decrease</enumItem>
+ </field>
+ <field name="BISTM0" start="26" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 0. 0: INVA is passed to TDL, 1: one-clock Pulse from INVA-edge.</description>
+ <enumItem value="0">INVA to TDL</enumItem>
+ <enumItem value="1">Pulse</enumItem>
+ </field>
+ <field name="BISTM9" start="27" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 9. BISTM[11..9] control INRD State Machine.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="BISTM_6_3" start="28" bits="4" mode="rw" format="unsigned">
+ <description>Used during calibration of the IO-Blocks for the Sampling-TDCs and the High-rate Samplers. See Manual.</description>
+ </field>
+ </register>
+
+ <register name="TriggerWindowControl" address="0002">
+ <description>Configuration of the Trigger Window.</description>
+ <field name="TriggerWindowStartOffset" start="0" bits="15" mode="rw" format="signed" unit="ns" scale="7.14">
+ <description>Defines the Trigger Window Start relative to the clock when the trigger command was received. Negative values are in the past.</description>
+ </field>
+ <field name="TWSE" start="15" bits="1" mode="rw" format="enum">
+ <description>Trigger Window Start Enable. If zero, all hits in the hit FIFO earlier than the Trigger Window End are included in an event.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="TriggerWindowEndOffset" start="16" bits="15" mode="rw" format="signed" unit="ns" scale="7.14">
+ <description>Defines the Trigger Window End relative to the clock when the trigger command was received. Negative values are in the past.</description>
+ </field>
+ <field name="TWEE" start="31" bits="1" mode="rw" format="enum">
+ <description>Trigger Window End Enable. If 0, the Trigger Window End is the clock when the trigger command was received.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ </register>
+
+ <register name="ControlReg3" address="0003">
+ <description>Control Bits for all Channels</description>
+ <field name="WriteMask_12_0" start="0" bits="13" mode="rw" format="bitmask">
+ <description>Write Mask for Calibration Table RAMs 12..0 (12: reference channel, 11..0: regular channels). Only one bit may be set.</description>
+ </field>
+ <field name="CALOVR" start="13" bits="1" mode="rw" format="enum">
+ <description>Calibration Override. If 1, trigger types 1000 are changed into 1001. On-the-fly calibration is switched on for types 1000.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="CTRLEN" start="14" bits="2" mode="rw" format="unsigned">
+ <description>Calibration Table Read-back Length per trigger 0100 command. 00: 16, 01: 32, 10: 64, 11: 128 entries.</description>
+ </field>
+ <field name="BISTM1" start="16" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 1. Overrides IO-Block Reset by BLCKIN.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="BISTM2" start="17" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 2. For the hit counters, selects between the transition indicator pulses and the hit counter test signal.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="BISTM10" start="18" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 10. BISTM[11..9] control INRD State Machine.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="CALCEN" start="19" bits="1" mode="rw" format="enum">
+ <description>Calibration Clock Enable. When 0, blocks signal from on-board calibration clock oscillator. Can be used to reduce noise. Must be 1 for calibration triggers.</description>
+ <enumItem value="0">Blocked</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="TCWT" start="20" bits="12" mode="rw" format="unsigned">
+ <description>Temperature Change Warning Threshold. Format depends on Temperature Sensor on the Board. Used to compute the flag STC in the header.</description>
+ </field>
+ </register>
+
+ <register name="ControlReg4" address="0004">
+ <description>Control Bits for all Channels</description>
+ <field name="ENTB" start="0" bits="1" mode="rw" format="enum">
+ <description>Enable Trace Buffer. If 1, sampled input data will continuously be stored in the trace buffer. Applies also to the Micro Trace Buffer.</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="TBSR" start="1" bits="3" mode="rw" format="unsigned">
+ <description>Trace Buffer Sampling Rate. 1--: 1/1, 011: 1/2, 010: 1/4, 001: 1/8, 000: 1/16 of sampling clock.</description>
+ </field>
+ <field name="TBTLEN" start="4" bits="2" mode="rw" format="unsigned">
+ <description>Trace Buffer Transfer Length. Number of sample vectors to be read per 0110 trigger. Actual number of vectors is 2^(5+TBTLEN). 1 Vector = 4 Words.</description>
+ </field>
+ <field name="TBTSRC" start="6" bits="2" mode="rw" format="unsigned">
+ <description>Trace Buffer Trigger Source. Not yet defined.</description>
+ </field>
+ <field name="TBTP" start="8" bits="8" mode="rw" format="unsigned">
+ <description>Trace Buffer Trigger Position in multiples of 16. Must never be 0. Most recent vector in Trace Buffer has number 0. Number increases with age.</description>
+ </field>
+ <field name="TBSSEL" start="16" bits="1" mode="rw" format="enum" invertflag="true">
+ <description>Trace Buffer Source Select. 0: hit signals. 1: Outputs of first and second level Triglets.</description>
+ <enumItem value="0">Hit Signals</enumItem>
+ <enumItem value="1">Triglets</enumItem>
+ </field>
+ <field name="TBARA" start="17" bits="1" mode="rw" format="enum">
+ <description>Trace Buffer Automatic Re-Arm. If 1, Trace Buffer and Micro Trace Buffer will automatically resume data acquisition after a trigger 0111 command.</description>
+ <enumItem value="0">Explicit</enumItem>
+ <enumItem value="1">Automatic</enumItem>
+ </field>
+ <field name="BISTM7" start="18" bits="1" mode="rw" format="enum" invertflag="true">
+ <description>Built-in Selftest Mode 7. If 1, the Hit Counter test will run. The ring oscillator will operate. During regular operation, BISTM[7] should be 0.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="BISTM8" start="19" bits="1" mode="rw" format="enum" invertflag="true">
+ <description>Built-in Selftest Mode 8. When BISTM[7]=1, with BISTM[8]=1 a different internal signal can be measured.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ <field name="PTSF" start="20" bits="12" mode="rw" format="unsigned">
+ <description>Processing Time Scale Factor. Used to scale the trigger command processing time so that meaningful bits are in positions 19..16 of TRLB.</description>
+ </field>
+ </register>
+
+ <register name="ControlReg5" address="0005">
+ <description>Control Bits for all Channels</description>
+ <field name="PTID" start="0" bits="8" mode="rw" format="unsigned">
+ <description>Programmable Trigger ID. This bit field has an auto-increment feature. Trigger will be launched by PTCMD in Activity Register.</description>
+ </field>
+ <field name="PTTY" start="8" bits="4" mode="rw" format="unsigned">
+ <description>Programmable Trigger Type. All trigger types can be launched internally via PTCMD in Activity Register.</description>
+ </field>
+ <field name="PTDD" start="12" bits="2" mode="rw" format="unsigned">
+ <description>Programmable Trigger Data Destination. 00: discard data. 01: DAQ FIFO. 10: Data Container. 11: Both.</description>
+ </field>
+ <field name="PRATU" start="14" bits="2" mode="rw" format="unsigned">
+ <description>Programmable Re-Arm Trigger Unit. Not yet defined.</description>
+ </field>
+ <field name="MIPE" start="16" bits="6" mode="rw" format="unsigned">
+ <description>Maximum Data Items per Event. Applies to the High-Rate Sampler channels. If bit 5 is set, no limit is applied.</description>
+ </field>
+ <field name="HSTSRC" start="22" bits="2" mode="rw" format="unsigned">
+ <description>High-Rate Sampler Trigger Source. To be defined.</description>
+ </field>
+ <field name="IHSD" start="24" bits="1" mode="rw" format="enum">
+ <description>Include High-Rate Sampler Data in Event Packet of Timing Trigger 1000 or 1001.</description>
+ <enumItem value="0">Exclude</enumItem>
+ <enumItem value="1">Include</enumItem>
+ </field>
+ <field name="HSROO" start="25" bits="1" mode="rw" format="enum">
+ <description>High-Rate Sampler Read-Out Order. 0: FIFO order, 1: LIFO order.</description>
+ <enumItem value="0">FIFO</enumItem>
+ <enumItem value="1">LIFO</enumItem>
+ </field>
+ <field name="ACSR0" start="26" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers CaptureBlockTimeout0 and CaptureBlockTimeout1 after respective read access (CBTO latches).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="ACSR1" start="27" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers StretcherDelayTooShort0 and StretcherDelayTooShort1 after respective read access (SDTS latches).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="ACSR2" start="28" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers DeadtimeViolationDetected0 and DeadtimeViolationDetected1 after respective read access (DTVD latches).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="ACSR3" start="29" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers SolitaryFallingEdgeDetected0 and SolitaryFallingEdgeDetected1 after respective read access (SFED FFs).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="ACSR4" start="30" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers HitFifoDataLoss0 and HitFifoDataLoss1 after respective read access (HFDL latches).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ <field name="ACSR5" start="31" bits="1" mode="rw" format="enum">
+ <description>Automatic Clear of Status Registers EventFifoDataLoss0 and EventFifoDataLoss1 after respective read access (EFDL latches).</description>
+ <enumItem value="0">Disabled</enumItem>
+ <enumItem value="1">Enabled</enumItem>
+ </field>
+ </register>
+
+ <register name="BlockInputBuffer0" address="0010">
+ <description>Blocks the Input Signals from entering the Circuitry. 0: allowed, 1: blocked. Rightmost box is channel 0.</description>
+ <field name="BlockInput_15_0" start="0" bits="16" format="bitmask" invertflag="true" />
+ </register>
+ <register name="BlockInputBuffer1" address="0020">
+ <description>Blocks the Input Signals from entering the Circuitry. 0: allowed, 1: blocked. Rightmost box is channel 16.</description>
+ <field name="BlockInput_31_16" start="0" bits="16" format="bitmask" invertflag="true" />
+ </register>
+
+ <register name="InputPolarityInversion0" address="0011">
+ <description>Invert-Bits for the Input Signals. 0: true value, 1: inverted. Rightmost box is channel 0.</description>
+ <field name="InputInvert_15_0" start="0" bits="16" format="bitmask" invertflag="true" />
+ </register>
+ <register name="InputPolarityInversion1" address="0021">
+ <description>Invert-Bits for the Input Signals. 0: true value, 1: inverted. Rightmost box is channel 16.</description>
+ <field name="InputInvert_31_16" start="0" bits="16" format="bitmask" invertflag="true" />
+ </register>
+
+ <register name="EnableTDL0" address="0012">
+ <description>Enable TDL-TDC. Rightmost box is channel 0.</description>
+ <field name="EnableTDL_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="EnableTDL1" address="0022">
+ <description>Enable TDL-TDC. Rightmost box is channel 16.</description>
+ <field name="EnableTDL_31_16" start="0" bits="16" format="bitmask" />
+ </register>
+
+ <register name="AlternatingChannelMode0" address="0013">
+ <description>Sends Pulses to alternating channels. 0: replicates, 1: alternates. Rightmost box is channel 0.</description>
+ <field name="AlternatingChannelMode_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="AlternatingChannelMode1" address="0023">
+ <description>Sends Pulses to alternating channels. 0: replicates, 1: alternates. Rightmost box is channel 16.</description>
+ <field name="AlternatingChannelMode_31_16" start="0" bits="16" format="bitmask" />
+ </register>
+
+ <register name="InputSelect0" address="0014">
+ <description>Selects input signal for a channel. 0: own input, 1: signal from sibling. Rightmost box is channel 0.</description>
+ <field name="InputSelect_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="InputSelect1" address="0024">
+ <description>Selects input signal for a channel. 0: own input, 1: signal from sibling. Rightmost box is channel 16. Bits 31..24: Sampling Frequency, bits 7..0</description>
+ <field name="InputSelect_31_16" start="0" bits="16" format="bitmask" />
+ <field name="SAMFRQ_7_0" start="24" bits="8" mode="rw" format="unsigned" />
+ </register>
+
+ <register name="ChannelPolarityInversion0" address="0015">
+ <description>Second programmable Inverter. Used for Rising Edge in one Channel, Falling Edge in Sibling. Rightmost box is channel 0.</description>
+ <field name="ChannelPolarityInversion_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="ChannelPolarityInversion1" address="0025">
+ <description>Second programmable Inverter. Used for Rising Edge in one Channel, Falling Edge in Sibling. Rightmost box is channel 16. Bits 31..24: Sampling Frequency, bits 15..8</description>
+ <field name="ChannelPolarityInversion_31_16" start="0" bits="16" format="bitmask" />
+ <field name="SAMFRQ_15_8" start="24" bits="8" mode="rw" format="unsigned" />
+ </register>
+
+ <register name="RisingEdgeSelect0" address="0016">
+ <description>Rising Edge Select. If 1, only rising edges are measured. Rightmost box is channel 0.</description>
+ <field name="RisingEdgeSelect_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="RisingEdgeSelect1" address="0026">
+ <description>Rising Edge Select. If 1, only rising edges are measured. Rightmost box is channel 16. Bits 31..24: Calibration Oscillator Frequency, bits 7..0</description>
+ <field name="RisingEdgeSelect_31_16" start="0" bits="16" format="bitmask" />
+ <field name="CALFRQ_7_0" start="24" bits="8" mode="rw" format="unsigned" />
+ </register>
+
+ <register name="UseStretcher0" address="0017">
+ <description>Stretcher Select. 0: bypassed, 1: employed. Rightmost box is channel 0.</description>
+ <field name="UseStretcher_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="UseStretcher1" address="0027">
+ <description>Stretcher Select. 0: bypassed, 1: employed. Rightmost box is channel 16. Bits 31..24: Calibration Oscillator Frequency, bits 15..8</description>
+ <field name="UseStretcher_31_16" start="0" bits="16" format="bitmask" />
+ <field name="CALFRQ_15_8" start="24" bits="8" mode="rw" format="unsigned" />
+ </register>
+
+ <register name="EnableSamplingTDC0" address="0018">
+ <description>Enable Sampling-TDC using the DDR-FFs in the IO-Blocks. Rightmost box is channel 0.</description>
+ <field name="EnableSamplingTDC_15_0" start="0" bits="16" format="bitmask" />
+ </register>
+ <register name="EnableSamplingTDC1" address="0028">
+ <description>Enable Sampling-TDC using the DDR-FFs in the IO-Blocks. Rightmost box is channel 16.</description>
+ <field name="EnableSamplingTDC_31_16" start="0" bits="16" format="bitmask" />
+ <field name="SFPREC" start="28" bits="1" mode="rw" format="enum">
+ <description>Must be set to 1 if the parameter SAMFRQ is precise, to zero otherwise. This bit appears in bit 28 of Trailer B.</description>
+ <enumItem value="0">Approx</enumItem>
+ <enumItem value="1">Precise</enumItem>
+ </field>
+ <field name="CFPREC" start="29" bits="1" mode="rw" format="enum">
+ <description>Must be set to 1 if the parameter CALFRQ is precise, to zero otherwise. This bit appears in bit 28 of Trailer C.</description>
+ <enumItem value="0">Approx</enumItem>
+ <enumItem value="1">Precise</enumItem>
+ </field>
+ <field name="BISTM11" start="30" bits="1" mode="rw" format="enum">
+ <description>Built-in Selftest Mode 11. BISTM[11..9] control INRD State Machine.</description>
+ <enumItem value="0">See Manual</enumItem>
+ <enumItem value="1">See Manual</enumItem>
+ </field>
+ </register>
+
+ <register name="ActivityRegister" address="0030" mode="w">
+ <description>Write-only bits for triggering Activities on the TDC</description>
+ <field name="CLSR0" start="0" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all latches that can be read via Register GeneralStatus.</description>
+ </field>
+ <field name="CCBTO" start="1" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Capture-Block-TimeOut latches.</description>
+ </field>
+ <field name="CSDTS" start="2" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Stretcher-Delay-Too-Short latches.</description>
+ </field>
+ <field name="CDTVD" start="3" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Deadtime-Violation-Detected latches.</description>
+ </field>
+ <field name="CSFED" start="4" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Solitary-Falling-Edge-Detected latches.</description>
+ </field>
+ <field name="CHFDL" start="5" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Hit-FIFO-Data-Loss latches.</description>
+ </field>
+ <field name="CEFDL" start="6" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Clears all Event-FIFO-Data-Loss latches.</description>
+ </field>
+ <field name="CLSR9" start="7" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Initializes the TriggerCommandReturn Register to a trigger type of 1111 and an ID of 0.</description>
+ </field>
+ <field name="PHCCAP" start="8" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Captures momentary state of all hit counters, the reference counter and the slow control timer.</description>
+ </field>
+ <field name="PTCMD" start="9" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Launch programmable trigger command. Programmable trigger ID will be incremented afterwards.</description>
+ </field>
+ <field name="STCA" start="10" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Set Trigger Command Attributes PTDD and PRATU for trigger type PTTY from the DAQ. All parameters in ControlReg5.</description>
+ </field>
+ <field name="SETCP" start="11" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Set Calibration Parameters. Programs NUMCP and CALSET into the corresponding hardware units.</description>
+ </field>
+ <field name="SETCF" start="12" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Set Calibration Clock Divider. Programs CCDIV into the corresponding hardware units.</description>
+ </field>
+ <field name="SETDP" start="13" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Set programmed Delay Parameters. Will program CBDEL (CR1[15..8]) into the selected Capture Block.</description>
+ </field>
+ <field name="STEP" start="14" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Will increment or decrement the delay of the delay line (DELAYF) selected by DUID.</description>
+ </field>
+ <field name="NSTEP" start="15" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Performs N increment or decrement steps on the delay line (DELAYF) selected by DUID. N = CBDEL[6..0].</description>
+ </field>
+ <field name="DEFDEL" start="16" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Resets the delay line (DELAYF) selected by DUID to the default (configured) delay value.</description>
+ </field>
+ <field name="ATDC" start="17" bits="1" purpose="trigger" mode="w" format="boolean">
+ <description>Arms Trigger Data Container. Resets the write address to 0, and enables data storage again.</description>
+ </field>
+ </register>
+
+ </group>
+
+ <!--===========================================-->
+ <!-- TDC Channels -->
+ <!--===========================================-->
+ <group name="ChannelCounter" purpose="statistics" address="0c00" mode="r" continuous="false" size="8" >
+ <register name="Channel_0" address="0000" mode="r" rate="1">
+ <description>Hit Counter for Channel 0</description>
+ <field name="Current0" start="0" bits="32" format="unsigned" purpose="statistics" />
+ </register>
+ <register name="Channel_1" address="0001" mode="r" rate="1">
+ <description>Hit Counter for Channel 1</description>
+ <field name="Current1" start="0" bits="32" format="unsigned" purpose="statistics" />
+ </register>
+ <register name="Channel_2" address="0002" mode="r" rate="1">
+ <description>Hit Counter for Channel 2</description>
+ <field name="Current2" start="0" bits="32" format="unsigned" purpose="statistics" />
+ </register>
+ <register name="Channel_3" address="0003" mode="r" rate="1">
+ <description>Hit Counter for Channel 3</description>
+ <field name="Current3" start="0" bits="32" format="unsigned" purpose="statistics" />
+ </register>
+ </group>
+
+
+</TrbNetEntity>
jspc29 / daqtools.git / commitdiff