--- /dev/null
+
+
+
+--synopsys translate_off
+
+library pcsd_work;
+use pcsd_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSD is
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+-- CONFIG_FILE : String := "mupix_serdes.txt";
+-- QUAD_MODE : String := "SINGLE";
+-- CH0_CDR_SRC : String := "REFCLK_CORE";
+-- CH1_CDR_SRC : String := "REFCLK_CORE";
+-- CH2_CDR_SRC : String := "REFCLK_CORE";
+-- CH3_CDR_SRC : String := "REFCLK_CORE";
+-- PLL_SRC : String := "REFCLK_CORE"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+
+end PCSD;
+
+architecture PCSD_arch of PCSD is
+
+
+component PCSD_sim
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String;
+ CH1_CDR_SRC : String;
+ CH2_CDR_SRC : String;
+ CH3_CDR_SRC : String;
+ PLL_SRC : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+
+begin
+
+PCSD_sim_inst : PCSD_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE,
+ QUAD_MODE => QUAD_MODE,
+ CH0_CDR_SRC => CH0_CDR_SRC,
+ CH1_CDR_SRC => CH1_CDR_SRC,
+ CH2_CDR_SRC => CH2_CDR_SRC,
+ CH3_CDR_SRC => CH3_CDR_SRC,
+ PLL_SRC => PLL_SRC
+ )
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
+ FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
+ FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
+ FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
+ FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
+ FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
+ FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
+ FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
+ FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
+ FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
+ FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
+ FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
+ FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
+ FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
+ FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
+ FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
+ FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
+ FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
+ FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
+ LDR_CORE2TX_0 => LDR_CORE2TX_0,
+ LDR_CORE2TX_1 => LDR_CORE2TX_1,
+ LDR_CORE2TX_2 => LDR_CORE2TX_2,
+ LDR_CORE2TX_3 => LDR_CORE2TX_3,
+ FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
+ FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
+ FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
+ FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
+ PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
+ PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
+ PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
+ PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
+ PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
+ PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
+ PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
+ PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
+ PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
+ PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
+ PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
+ PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
+ PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
+ PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
+ PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
+ PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
+ PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
+ PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
+ PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
+ PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
+ FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
+ FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
+ FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
+ FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
+ FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
+ FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
+ FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
+ FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
+ FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
+ FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
+ FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
+ FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
+ FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
+ PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
+ PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
+ PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
+ PCIE_RXVALID_0 => PCIE_RXVALID_0,
+ PCIE_RXVALID_1 => PCIE_RXVALID_1,
+ PCIE_RXVALID_2 => PCIE_RXVALID_2,
+ PCIE_RXVALID_3 => PCIE_RXVALID_3,
+ FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
+ FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
+ FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
+ FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
+ FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
+ FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
+ FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
+ FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
+ LDR_RX2CORE_0 => LDR_RX2CORE_0,
+ LDR_RX2CORE_1 => LDR_RX2CORE_1,
+ LDR_RX2CORE_2 => LDR_RX2CORE_2,
+ LDR_RX2CORE_3 => LDR_RX2CORE_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7,
+ REFCLK_FROM_NQ => REFCLK_FROM_NQ,
+ REFCLK_TO_NQ => REFCLK_TO_NQ
+ );
+
+end PCSD_arch;
+
+--synopsys translate_on
+
+--THIS MODULE IS INSTANTIATED PER RX CHANNEL
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity mupix_serdesrx_reset_sm is
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end mupix_serdesrx_reset_sm ;
+
+architecture rx_reset_sm_arch of mupix_serdesrx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal cs: statetype; -- current state of lsm
+signal ns: statetype; -- next state of lsm
+attribute syn_encoding : string;
+attribute syn_encoding of cs : signal is "safe";
+attribute syn_encoding of ns : signal is "safe";
+
+signal tx_pll_lol_qd_s_int: std_logic;
+signal rx_los_low_int: std_logic;
+signal plol_los_int: std_logic;
+signal rx_lol_los : std_logic;
+signal rx_lol_los_int: std_logic;
+signal rx_lol_los_del: std_logic;
+signal rx_pcs_rst_ch_c_int: std_logic;
+signal rx_serdes_rst_ch_c_int: std_logic;
+
+signal reset_timer1: std_logic;
+signal reset_timer2: std_logic;
+
+signal counter1: std_logic_vector(1 downto 0);
+signal TIMER1: std_logic;
+
+signal counter2: std_logic_vector(18 downto 0);
+signal TIMER2 : std_logic;
+signal rstn_m1: std_logic;
+signal rstn_m2: std_logic;
+signal sync_rst_n: std_logic;
+begin
+
+process (refclkdiv2, rst_n)
+begin
+ if rst_n = '0' then
+ rstn_m1 <= '0';
+ rstn_m2 <= '0';
+ else if rising_edge(refclkdiv2) then
+ rstn_m1 <= '1';
+ rstn_m2 <= rstn_m1;
+ end if;
+ end if;
+end process;
+
+ sync_rst_n <= rstn_m2;
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2, sync_rst_n)
+begin
+ if sync_rst_n = '0' then
+ cs <= WAIT_FOR_PLOL;
+ rx_lol_los_int <= '1';
+ rx_lol_los_del <= '1';
+ tx_pll_lol_qd_s_int <= '1';
+ rx_pcs_rst_ch_c <= '1';
+ rx_serdes_rst_ch_c <= '0';
+ rx_los_low_int <= '1';
+ else if rising_edge(refclkdiv2) then
+ cs <= ns;
+ rx_lol_los_del <= rx_lol_los;
+ rx_lol_los_int <= rx_lol_los_del;
+ tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+ rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+ rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+ rx_los_low_int <= rx_los_low_ch_s;
+ end if;
+ end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer1 = '1' then
+ counter1 <= "00";
+ TIMER1 <= '0';
+ else
+ if counter1(1) = '1' then
+ TIMER1 <='1';
+ else
+ TIMER1 <='0';
+ counter1 <= counter1 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2)
+begin
+ if rising_edge(refclkdiv2) then
+ if reset_timer2 = '1' then
+ counter2 <= "0000000000000000000";
+ TIMER2 <= '0';
+ else
+ if counter2(count_index) = '1' then
+ TIMER2 <='1';
+ else
+ TIMER2 <='0';
+ counter2 <= counter2 + 1 ;
+ end if;
+ end if;
+ end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+ reset_timer1 <= '0';
+ reset_timer2 <= '0';
+
+ case cs is
+ when WAIT_FOR_PLOL =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then --Also make sure A Signal
+ ns <= WAIT_FOR_PLOL; --is Present prior to moving to the next
+ else
+ ns <= RX_SERDES_RESET;
+ end if;
+
+ when RX_SERDES_RESET =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ reset_timer1 <= '1';
+ ns <= WAIT_FOR_TIMER1;
+
+
+ when WAIT_FOR_TIMER1 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '1';
+ if TIMER1 = '1' then
+ ns <= CHECK_LOL_LOS;
+ else
+ ns <= WAIT_FOR_TIMER1;
+ end if;
+
+ when CHECK_LOL_LOS =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ reset_timer2 <= '1';
+ ns <= WAIT_FOR_TIMER2;
+
+ when WAIT_FOR_TIMER2 =>
+ rx_pcs_rst_ch_c_int <= '1';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES
+ if TIMER2 = '1' then
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+ else
+ ns <= WAIT_FOR_TIMER2;
+ end if;
+ else
+ ns <= CHECK_LOL_LOS; --RESET TIMER2
+ end if;
+
+ when NORMAL =>
+ rx_pcs_rst_ch_c_int <= '0';
+ rx_serdes_rst_ch_c_int <= '0';
+ if rx_lol_los_int = '1' then
+ ns <= WAIT_FOR_PLOL;
+ else
+ ns <= NORMAL;
+ end if;
+
+ when others =>
+ ns <= WAIT_FOR_PLOL;
+
+ end case;
+
+end process;
+
+
+end rx_reset_sm_arch;
+
+
+
+--synopsys translate_off
+library ECP3;
+use ECP3.components.all;
+--synopsys translate_on
+
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity mupix_serdes is
+ GENERIC (USER_CONFIG_FILE : String := "mupix_serdes.txt");
+ port (
+------------------
+-- CH0 --
+ hdinp_ch0, hdinn_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
+ rx_full_clk_ch0 : out std_logic;
+ rx_half_clk_ch0 : out std_logic;
+ fpga_rxrefclk_ch0 : in std_logic;
+ rxdata_ch0 : out std_logic_vector (7 downto 0);
+ rx_k_ch0 : out std_logic;
+ rx_disp_err_ch0 : out std_logic;
+ rx_cv_err_ch0 : out std_logic;
+ rx_pwrup_ch0_c : in std_logic;
+ rx_los_low_ch0_s : out std_logic;
+ lsm_status_ch0_s : out std_logic;
+ rx_cdr_lol_ch0_s : out std_logic;
+ rx_div2_mode_ch0_c : in std_logic;
+-- CH1 --
+ hdinp_ch1, hdinn_ch1 : in std_logic;
+ rxiclk_ch1 : in std_logic;
+ rx_full_clk_ch1 : out std_logic;
+ rx_half_clk_ch1 : out std_logic;
+ fpga_rxrefclk_ch1 : in std_logic;
+ rxdata_ch1 : out std_logic_vector (7 downto 0);
+ rx_k_ch1 : out std_logic;
+ rx_disp_err_ch1 : out std_logic;
+ rx_cv_err_ch1 : out std_logic;
+ rx_pwrup_ch1_c : in std_logic;
+ rx_los_low_ch1_s : out std_logic;
+ lsm_status_ch1_s : out std_logic;
+ rx_cdr_lol_ch1_s : out std_logic;
+ rx_div2_mode_ch1_c : in std_logic;
+-- CH2 --
+ hdinp_ch2, hdinn_ch2 : in std_logic;
+ rxiclk_ch2 : in std_logic;
+ rx_full_clk_ch2 : out std_logic;
+ rx_half_clk_ch2 : out std_logic;
+ fpga_rxrefclk_ch2 : in std_logic;
+ rxdata_ch2 : out std_logic_vector (7 downto 0);
+ rx_k_ch2 : out std_logic;
+ rx_disp_err_ch2 : out std_logic;
+ rx_cv_err_ch2 : out std_logic;
+ rx_pwrup_ch2_c : in std_logic;
+ rx_los_low_ch2_s : out std_logic;
+ lsm_status_ch2_s : out std_logic;
+ rx_cdr_lol_ch2_s : out std_logic;
+ rx_div2_mode_ch2_c : in std_logic;
+-- CH3 --
+ hdinp_ch3, hdinn_ch3 : in std_logic;
+ rxiclk_ch3 : in std_logic;
+ rx_full_clk_ch3 : out std_logic;
+ rx_half_clk_ch3 : out std_logic;
+ fpga_rxrefclk_ch3 : in std_logic;
+ rxdata_ch3 : out std_logic_vector (7 downto 0);
+ rx_k_ch3 : out std_logic;
+ rx_disp_err_ch3 : out std_logic;
+ rx_cv_err_ch3 : out std_logic;
+ rx_pwrup_ch3_c : in std_logic;
+ rx_los_low_ch3_s : out std_logic;
+ lsm_status_ch3_s : out std_logic;
+ rx_cdr_lol_ch3_s : out std_logic;
+ rx_div2_mode_ch3_c : in std_logic;
+---- Miscillaneous ports
+ fpga_txrefclk : in std_logic;
+ tx_sync_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
+ rst_n : in std_logic;
+ serdes_rst_qd_c : in std_logic);
+
+end mupix_serdes;
+
+
+architecture mupix_serdes_arch of mupix_serdes is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+
+component mupix_serdesrx_reset_sm
+generic (count_index: integer :=18);
+port (
+ rst_n : in std_logic;
+ refclkdiv2 : in std_logic;
+ tx_pll_lol_qd_s : in std_logic;
+ rx_serdes_rst_ch_c: out std_logic;
+ rx_cdr_lol_ch_s : in std_logic;
+ rx_los_low_ch_s : in std_logic;
+ rx_pcs_rst_ch_c : out std_logic
+);
+end component ;
+
+
+component PCSD
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String;
+ QUAD_MODE : String;
+ CH0_CDR_SRC : String := "REFCLK_EXT";
+ CH1_CDR_SRC : String := "REFCLK_EXT";
+ CH2_CDR_SRC : String := "REFCLK_EXT";
+ CH3_CDR_SRC : String := "REFCLK_EXT";
+ PLL_SRC : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX_0 : in std_logic;
+ FFC_CK_CORE_RX_1 : in std_logic;
+ FFC_CK_CORE_RX_2 : in std_logic;
+ FFC_CK_CORE_RX_3 : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_SYNC_TOGGLE : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ FFC_RATE_MODE_RX_0 : in std_logic;
+ FFC_RATE_MODE_RX_1 : in std_logic;
+ FFC_RATE_MODE_RX_2 : in std_logic;
+ FFC_RATE_MODE_RX_3 : in std_logic;
+ FFC_RATE_MODE_TX_0 : in std_logic;
+ FFC_RATE_MODE_TX_1 : in std_logic;
+ FFC_RATE_MODE_TX_2 : in std_logic;
+ FFC_RATE_MODE_TX_3 : in std_logic;
+ FFC_DIV11_MODE_RX_0 : in std_logic;
+ FFC_DIV11_MODE_RX_1 : in std_logic;
+ FFC_DIV11_MODE_RX_2 : in std_logic;
+ FFC_DIV11_MODE_RX_3 : in std_logic;
+ FFC_DIV11_MODE_TX_0 : in std_logic;
+ FFC_DIV11_MODE_TX_1 : in std_logic;
+ FFC_DIV11_MODE_TX_2 : in std_logic;
+ FFC_DIV11_MODE_TX_3 : in std_logic;
+ LDR_CORE2TX_0 : in std_logic;
+ LDR_CORE2TX_1 : in std_logic;
+ LDR_CORE2TX_2 : in std_logic;
+ LDR_CORE2TX_3 : in std_logic;
+ FFC_LDR_CORE2TX_EN_0 : in std_logic;
+ FFC_LDR_CORE2TX_EN_1 : in std_logic;
+ FFC_LDR_CORE2TX_EN_2 : in std_logic;
+ FFC_LDR_CORE2TX_EN_3 : in std_logic;
+ PCIE_POWERDOWN_0_0 : in std_logic;
+ PCIE_POWERDOWN_0_1 : in std_logic;
+ PCIE_POWERDOWN_1_0 : in std_logic;
+ PCIE_POWERDOWN_1_1 : in std_logic;
+ PCIE_POWERDOWN_2_0 : in std_logic;
+ PCIE_POWERDOWN_2_1 : in std_logic;
+ PCIE_POWERDOWN_3_0 : in std_logic;
+ PCIE_POWERDOWN_3_1 : in std_logic;
+ PCIE_RXPOLARITY_0 : in std_logic;
+ PCIE_RXPOLARITY_1 : in std_logic;
+ PCIE_RXPOLARITY_2 : in std_logic;
+ PCIE_RXPOLARITY_3 : in std_logic;
+ PCIE_TXCOMPLIANCE_0 : in std_logic;
+ PCIE_TXCOMPLIANCE_1 : in std_logic;
+ PCIE_TXCOMPLIANCE_2 : in std_logic;
+ PCIE_TXCOMPLIANCE_3 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_0 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_1 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_2 : in std_logic;
+ PCIE_TXDETRX_PR2TLB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ REFCLK_FROM_NQ : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_TX_F_CLK_0 : out std_logic;
+ FF_TX_F_CLK_1 : out std_logic;
+ FF_TX_F_CLK_2 : out std_logic;
+ FF_TX_F_CLK_3 : out std_logic;
+ FF_TX_H_CLK_0 : out std_logic;
+ FF_TX_H_CLK_1 : out std_logic;
+ FF_TX_H_CLK_2 : out std_logic;
+ FF_TX_H_CLK_3 : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_CDR_TRAIN_DONE_0 : out std_logic;
+ FFS_CDR_TRAIN_DONE_1 : out std_logic;
+ FFS_CDR_TRAIN_DONE_2 : out std_logic;
+ FFS_CDR_TRAIN_DONE_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RLOS_HI_0 : out std_logic;
+ FFS_RLOS_HI_1 : out std_logic;
+ FFS_RLOS_HI_2 : out std_logic;
+ FFS_RLOS_HI_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic;
+ PCIE_PHYSTATUS_0 : out std_logic;
+ PCIE_PHYSTATUS_1 : out std_logic;
+ PCIE_PHYSTATUS_2 : out std_logic;
+ PCIE_PHYSTATUS_3 : out std_logic;
+ PCIE_RXVALID_0 : out std_logic;
+ PCIE_RXVALID_1 : out std_logic;
+ PCIE_RXVALID_2 : out std_logic;
+ PCIE_RXVALID_3 : out std_logic;
+ FFS_SKP_ADDED_0 : out std_logic;
+ FFS_SKP_ADDED_1 : out std_logic;
+ FFS_SKP_ADDED_2 : out std_logic;
+ FFS_SKP_ADDED_3 : out std_logic;
+ FFS_SKP_DELETED_0 : out std_logic;
+ FFS_SKP_DELETED_1 : out std_logic;
+ FFS_SKP_DELETED_2 : out std_logic;
+ FFS_SKP_DELETED_3 : out std_logic;
+ LDR_RX2CORE_0 : out std_logic;
+ LDR_RX2CORE_1 : out std_logic;
+ LDR_RX2CORE_2 : out std_logic;
+ LDR_RX2CORE_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ REFCLK_TO_NQ : out std_logic
+);
+end component;
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
+ attribute QUAD_MODE: string;
+ attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
+ attribute PLL_SRC: string;
+ attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH0_CDR_SRC: string;
+ attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH1_CDR_SRC: string;
+ attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH2_CDR_SRC: string;
+ attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute CH3_CDR_SRC: string;
+ attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "125.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "62.5000";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal refclk_from_nq : std_logic := '0';
+signal fpsc_vlo : std_logic := '0';
+signal fpsc_vhi : std_logic := '1';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+
+signal refclk2fpga_sig : std_logic;
+signal tx_pll_lol_qd_sig : std_logic;
+signal rx_los_low_ch0_sig : std_logic;
+signal rx_los_low_ch1_sig : std_logic;
+signal rx_los_low_ch2_sig : std_logic;
+signal rx_los_low_ch3_sig : std_logic;
+signal rx_cdr_lol_ch0_sig : std_logic;
+signal rx_cdr_lol_ch1_sig : std_logic;
+signal rx_cdr_lol_ch2_sig : std_logic;
+signal rx_cdr_lol_ch3_sig : std_logic;
+
+signal rx_serdes_rst_ch0_c : std_logic;
+signal rx_serdes_rst_ch1_c : std_logic;
+signal rx_serdes_rst_ch2_c : std_logic;
+signal rx_serdes_rst_ch3_c : std_logic;
+signal rx_pcs_rst_ch0_c : std_logic;
+signal rx_pcs_rst_ch1_c : std_logic;
+signal rx_pcs_rst_ch2_c : std_logic;
+signal rx_pcs_rst_ch3_c : std_logic;
+
+-- reset sequence for rx
+signal refclkdiv2_rx_ch0 : std_logic;
+signal refclkdiv2_rx_ch1 : std_logic;
+signal refclkdiv2_rx_ch2 : std_logic;
+signal refclkdiv2_rx_ch3 : std_logic;
+
+
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+vhi_inst : VHI port map(Z => fpsc_vhi);
+
+ refclk2fpga <= refclk2fpga_sig;
+ rx_los_low_ch0_s <= rx_los_low_ch0_sig;
+ rx_los_low_ch1_s <= rx_los_low_ch1_sig;
+ rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+ rx_los_low_ch3_s <= rx_los_low_ch3_sig;
+ rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
+ rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
+ rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
+ rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+
+-- pcs_quad instance
+PCSD_INST : PCSD
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE,
+ QUAD_MODE => "SINGLE",
+ CH0_CDR_SRC => "REFCLK_CORE",
+ CH1_CDR_SRC => "REFCLK_CORE",
+ CH2_CDR_SRC => "REFCLK_CORE",
+ CH3_CDR_SRC => "REFCLK_CORE",
+ PLL_SRC => "REFCLK_CORE"
+ )
+--synopsys translate_on
+port map (
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+
+----- CH0 -----
+ HDOUTP0 => open,
+ HDOUTN0 => open,
+ HDINP0 => hdinp_ch0,
+ HDINN0 => hdinn_ch0,
+ PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
+ PCIE_RXPOLARITY_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_0 => fpsc_vlo,
+ PCIE_POWERDOWN_0_1 => fpsc_vlo,
+ PCIE_RXVALID_0 => open,
+ PCIE_PHYSTATUS_0 => open,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => rxiclk_ch0,
+ FF_TXI_CLK_0 => fpsc_vlo,
+ FF_EBRD_CLK_0 => fpsc_vlo,
+ FF_RX_F_CLK_0 => rx_full_clk_ch0,
+ FF_RX_H_CLK_0 => rx_half_clk_ch0,
+ FF_TX_F_CLK_0 => open,
+ FF_TX_H_CLK_0 => open,
+ FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
+ FF_TX_D_0_0 => fpsc_vlo,
+ FF_TX_D_0_1 => fpsc_vlo,
+ FF_TX_D_0_2 => fpsc_vlo,
+ FF_TX_D_0_3 => fpsc_vlo,
+ FF_TX_D_0_4 => fpsc_vlo,
+ FF_TX_D_0_5 => fpsc_vlo,
+ FF_TX_D_0_6 => fpsc_vlo,
+ FF_TX_D_0_7 => fpsc_vlo,
+ FF_TX_D_0_8 => fpsc_vlo,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => fpsc_vlo,
+ FF_TX_D_0_11 => fpsc_vlo,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => rxdata_ch0(0),
+ FF_RX_D_0_1 => rxdata_ch0(1),
+ FF_RX_D_0_2 => rxdata_ch0(2),
+ FF_RX_D_0_3 => rxdata_ch0(3),
+ FF_RX_D_0_4 => rxdata_ch0(4),
+ FF_RX_D_0_5 => rxdata_ch0(5),
+ FF_RX_D_0_6 => rxdata_ch0(6),
+ FF_RX_D_0_7 => rxdata_ch0(7),
+ FF_RX_D_0_8 => rx_k_ch0,
+ FF_RX_D_0_9 => rx_disp_err_ch0,
+ FF_RX_D_0_10 => rx_cv_err_ch0,
+ FF_RX_D_0_11 => open,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+
+ FFC_RRST_0 => rx_serdes_rst_ch0_c,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => fpsc_vlo,
+ FFC_TXPWDNB_0 => fpsc_vlo,
+ FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
+ FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
+ FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
+ FFS_RLOS_HI_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFS_PCIE_DONE_0 => open,
+ FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
+ FFS_CC_OVERRUN_0 => open,
+ FFS_CC_UNDERRUN_0 => open,
+ FFS_SKP_ADDED_0 => open,
+ FFS_SKP_DELETED_0 => open,
+ FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
+ FFS_RXFBFIFO_ERROR_0 => open,
+ FFS_TXFBFIFO_ERROR_0 => open,
+ LDR_CORE2TX_0 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
+ LDR_RX2CORE_0 => open,
+ FFS_CDR_TRAIN_DONE_0 => open,
+ FFC_DIV11_MODE_TX_0 => fpsc_vlo,
+ FFC_RATE_MODE_TX_0 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_0 => fpsc_vlo,
+ FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
+
+----- CH1 -----
+ HDOUTP1 => open,
+ HDOUTN1 => open,
+ HDINP1 => hdinp_ch1,
+ HDINN1 => hdinn_ch1,
+ PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
+ PCIE_RXPOLARITY_1 => fpsc_vlo,
+ PCIE_POWERDOWN_1_0 => fpsc_vlo,
+ PCIE_POWERDOWN_1_1 => fpsc_vlo,
+ PCIE_RXVALID_1 => open,
+ PCIE_PHYSTATUS_1 => open,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => rxiclk_ch1,
+ FF_TXI_CLK_1 => fpsc_vlo,
+ FF_EBRD_CLK_1 => fpsc_vlo,
+ FF_RX_F_CLK_1 => rx_full_clk_ch1,
+ FF_RX_H_CLK_1 => rx_half_clk_ch1,
+ FF_TX_F_CLK_1 => open,
+ FF_TX_H_CLK_1 => open,
+ FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
+ FF_TX_D_1_0 => fpsc_vlo,
+ FF_TX_D_1_1 => fpsc_vlo,
+ FF_TX_D_1_2 => fpsc_vlo,
+ FF_TX_D_1_3 => fpsc_vlo,
+ FF_TX_D_1_4 => fpsc_vlo,
+ FF_TX_D_1_5 => fpsc_vlo,
+ FF_TX_D_1_6 => fpsc_vlo,
+ FF_TX_D_1_7 => fpsc_vlo,
+ FF_TX_D_1_8 => fpsc_vlo,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => fpsc_vlo,
+ FF_TX_D_1_11 => fpsc_vlo,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => rxdata_ch1(0),
+ FF_RX_D_1_1 => rxdata_ch1(1),
+ FF_RX_D_1_2 => rxdata_ch1(2),
+ FF_RX_D_1_3 => rxdata_ch1(3),
+ FF_RX_D_1_4 => rxdata_ch1(4),
+ FF_RX_D_1_5 => rxdata_ch1(5),
+ FF_RX_D_1_6 => rxdata_ch1(6),
+ FF_RX_D_1_7 => rxdata_ch1(7),
+ FF_RX_D_1_8 => rx_k_ch1,
+ FF_RX_D_1_9 => rx_disp_err_ch1,
+ FF_RX_D_1_10 => rx_cv_err_ch1,
+ FF_RX_D_1_11 => open,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+
+ FFC_RRST_1 => rx_serdes_rst_ch1_c,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => fpsc_vlo,
+ FFC_TXPWDNB_1 => fpsc_vlo,
+ FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
+ FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
+ FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
+ FFS_RLOS_HI_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFS_PCIE_DONE_1 => open,
+ FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
+ FFS_CC_OVERRUN_1 => open,
+ FFS_CC_UNDERRUN_1 => open,
+ FFS_SKP_ADDED_1 => open,
+ FFS_SKP_DELETED_1 => open,
+ FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
+ FFS_RXFBFIFO_ERROR_1 => open,
+ FFS_TXFBFIFO_ERROR_1 => open,
+ LDR_CORE2TX_1 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
+ LDR_RX2CORE_1 => open,
+ FFS_CDR_TRAIN_DONE_1 => open,
+ FFC_DIV11_MODE_TX_1 => fpsc_vlo,
+ FFC_RATE_MODE_TX_1 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_1 => fpsc_vlo,
+ FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
+
+----- CH2 -----
+ HDOUTP2 => open,
+ HDOUTN2 => open,
+ HDINP2 => hdinp_ch2,
+ HDINN2 => hdinn_ch2,
+ PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
+ PCIE_RXPOLARITY_2 => fpsc_vlo,
+ PCIE_POWERDOWN_2_0 => fpsc_vlo,
+ PCIE_POWERDOWN_2_1 => fpsc_vlo,
+ PCIE_RXVALID_2 => open,
+ PCIE_PHYSTATUS_2 => open,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => rxiclk_ch2,
+ FF_TXI_CLK_2 => fpsc_vlo,
+ FF_EBRD_CLK_2 => fpsc_vlo,
+ FF_RX_F_CLK_2 => rx_full_clk_ch2,
+ FF_RX_H_CLK_2 => rx_half_clk_ch2,
+ FF_TX_F_CLK_2 => open,
+ FF_TX_H_CLK_2 => open,
+ FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+ FF_TX_D_2_0 => fpsc_vlo,
+ FF_TX_D_2_1 => fpsc_vlo,
+ FF_TX_D_2_2 => fpsc_vlo,
+ FF_TX_D_2_3 => fpsc_vlo,
+ FF_TX_D_2_4 => fpsc_vlo,
+ FF_TX_D_2_5 => fpsc_vlo,
+ FF_TX_D_2_6 => fpsc_vlo,
+ FF_TX_D_2_7 => fpsc_vlo,
+ FF_TX_D_2_8 => fpsc_vlo,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => fpsc_vlo,
+ FF_TX_D_2_11 => fpsc_vlo,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => rxdata_ch2(0),
+ FF_RX_D_2_1 => rxdata_ch2(1),
+ FF_RX_D_2_2 => rxdata_ch2(2),
+ FF_RX_D_2_3 => rxdata_ch2(3),
+ FF_RX_D_2_4 => rxdata_ch2(4),
+ FF_RX_D_2_5 => rxdata_ch2(5),
+ FF_RX_D_2_6 => rxdata_ch2(6),
+ FF_RX_D_2_7 => rxdata_ch2(7),
+ FF_RX_D_2_8 => rx_k_ch2,
+ FF_RX_D_2_9 => rx_disp_err_ch2,
+ FF_RX_D_2_10 => rx_cv_err_ch2,
+ FF_RX_D_2_11 => open,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+
+ FFC_RRST_2 => rx_serdes_rst_ch2_c,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => fpsc_vlo,
+ FFC_TXPWDNB_2 => fpsc_vlo,
+ FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+ FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+ FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
+ FFS_RLOS_HI_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFS_PCIE_DONE_2 => open,
+ FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
+ FFS_CC_OVERRUN_2 => open,
+ FFS_CC_UNDERRUN_2 => open,
+ FFS_SKP_ADDED_2 => open,
+ FFS_SKP_DELETED_2 => open,
+ FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
+ FFS_RXFBFIFO_ERROR_2 => open,
+ FFS_TXFBFIFO_ERROR_2 => open,
+ LDR_CORE2TX_2 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
+ LDR_RX2CORE_2 => open,
+ FFS_CDR_TRAIN_DONE_2 => open,
+ FFC_DIV11_MODE_TX_2 => fpsc_vlo,
+ FFC_RATE_MODE_TX_2 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_2 => fpsc_vlo,
+ FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
+
+----- CH3 -----
+ HDOUTP3 => open,
+ HDOUTN3 => open,
+ HDINP3 => hdinp_ch3,
+ HDINN3 => hdinn_ch3,
+ PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
+ PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
+ PCIE_RXPOLARITY_3 => fpsc_vlo,
+ PCIE_POWERDOWN_3_0 => fpsc_vlo,
+ PCIE_POWERDOWN_3_1 => fpsc_vlo,
+ PCIE_RXVALID_3 => open,
+ PCIE_PHYSTATUS_3 => open,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => rxiclk_ch3,
+ FF_TXI_CLK_3 => fpsc_vlo,
+ FF_EBRD_CLK_3 => fpsc_vlo,
+ FF_RX_F_CLK_3 => rx_full_clk_ch3,
+ FF_RX_H_CLK_3 => rx_half_clk_ch3,
+ FF_TX_F_CLK_3 => open,
+ FF_TX_H_CLK_3 => open,
+ FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
+ FF_TX_D_3_0 => fpsc_vlo,
+ FF_TX_D_3_1 => fpsc_vlo,
+ FF_TX_D_3_2 => fpsc_vlo,
+ FF_TX_D_3_3 => fpsc_vlo,
+ FF_TX_D_3_4 => fpsc_vlo,
+ FF_TX_D_3_5 => fpsc_vlo,
+ FF_TX_D_3_6 => fpsc_vlo,
+ FF_TX_D_3_7 => fpsc_vlo,
+ FF_TX_D_3_8 => fpsc_vlo,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => fpsc_vlo,
+ FF_TX_D_3_11 => fpsc_vlo,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => rxdata_ch3(0),
+ FF_RX_D_3_1 => rxdata_ch3(1),
+ FF_RX_D_3_2 => rxdata_ch3(2),
+ FF_RX_D_3_3 => rxdata_ch3(3),
+ FF_RX_D_3_4 => rxdata_ch3(4),
+ FF_RX_D_3_5 => rxdata_ch3(5),
+ FF_RX_D_3_6 => rxdata_ch3(6),
+ FF_RX_D_3_7 => rxdata_ch3(7),
+ FF_RX_D_3_8 => rx_k_ch3,
+ FF_RX_D_3_9 => rx_disp_err_ch3,
+ FF_RX_D_3_10 => rx_cv_err_ch3,
+ FF_RX_D_3_11 => open,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+
+ FFC_RRST_3 => rx_serdes_rst_ch3_c,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => fpsc_vlo,
+ FFC_TXPWDNB_3 => fpsc_vlo,
+ FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
+ FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
+ FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+ FFS_RLOS_HI_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFS_PCIE_DONE_3 => open,
+ FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+ FFS_CC_OVERRUN_3 => open,
+ FFS_CC_UNDERRUN_3 => open,
+ FFS_SKP_ADDED_3 => open,
+ FFS_SKP_DELETED_3 => open,
+ FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+ FFS_RXFBFIFO_ERROR_3 => open,
+ FFS_TXFBFIFO_ERROR_3 => open,
+ LDR_CORE2TX_3 => fpsc_vlo,
+ FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
+ LDR_RX2CORE_3 => open,
+ FFS_CDR_TRAIN_DONE_3 => open,
+ FFC_DIV11_MODE_TX_3 => fpsc_vlo,
+ FFC_RATE_MODE_TX_3 => fpsc_vlo,
+ FFC_DIV11_MODE_RX_3 => fpsc_vlo,
+ FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+
+----- Auxilliary ----
+ SCIWDATA7 => fpsc_vlo,
+ SCIWDATA6 => fpsc_vlo,
+ SCIWDATA5 => fpsc_vlo,
+ SCIWDATA4 => fpsc_vlo,
+ SCIWDATA3 => fpsc_vlo,
+ SCIWDATA2 => fpsc_vlo,
+ SCIWDATA1 => fpsc_vlo,
+ SCIWDATA0 => fpsc_vlo,
+ SCIADDR5 => fpsc_vlo,
+ SCIADDR4 => fpsc_vlo,
+ SCIADDR3 => fpsc_vlo,
+ SCIADDR2 => fpsc_vlo,
+ SCIADDR1 => fpsc_vlo,
+ SCIADDR0 => fpsc_vlo,
+ SCIRDATA7 => open,
+ SCIRDATA6 => open,
+ SCIRDATA5 => open,
+ SCIRDATA4 => open,
+ SCIRDATA3 => open,
+ SCIRDATA2 => open,
+ SCIRDATA1 => open,
+ SCIRDATA0 => open,
+ SCIENAUX => fpsc_vlo,
+ SCISELAUX => fpsc_vlo,
+ SCIRD => fpsc_vlo,
+ SCIWSTN => fpsc_vlo,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_CK_CORE_TX => fpga_txrefclk,
+ FFC_MACRO_RST => serdes_rst_qd_c,
+ FFC_QUAD_RST => fpsc_vlo,
+ FFC_TRST => fpsc_vlo,
+ FFS_PLOL => open,
+ FFC_SYNC_TOGGLE => tx_sync_qd_c,
+ REFCK2CORE => refclk2fpga_sig,
+ CIN0 => fpsc_vlo,
+ CIN1 => fpsc_vlo,
+ CIN2 => fpsc_vlo,
+ CIN3 => fpsc_vlo,
+ CIN4 => fpsc_vlo,
+ CIN5 => fpsc_vlo,
+ CIN6 => fpsc_vlo,
+ CIN7 => fpsc_vlo,
+ CIN8 => fpsc_vlo,
+ CIN9 => fpsc_vlo,
+ CIN10 => fpsc_vlo,
+ CIN11 => fpsc_vlo,
+ COUT0 => open,
+ COUT1 => open,
+ COUT2 => open,
+ COUT3 => open,
+ COUT4 => open,
+ COUT5 => open,
+ COUT6 => open,
+ COUT7 => open,
+ COUT8 => open,
+ COUT9 => open,
+ COUT10 => open,
+ COUT11 => open,
+ COUT12 => open,
+ COUT13 => open,
+ COUT14 => open,
+ COUT15 => open,
+ COUT16 => open,
+ COUT17 => open,
+ COUT18 => open,
+ COUT19 => open,
+ REFCLK_FROM_NQ => refclk_from_nq,
+ REFCLK_TO_NQ => open);
+
+-- reset sequence for rx
+
+ P1 : PROCESS(fpga_rxrefclk_ch0, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch0 <= '0';
+ ELSIF (fpga_rxrefclk_ch0'event and fpga_rxrefclk_ch0 = '1') THEN
+ refclkdiv2_rx_ch0 <= not refclkdiv2_rx_ch0;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch0 : mupix_serdesrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch0,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch0_sig,
+ rx_los_low_ch_s => rx_los_low_ch0_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch0_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch0_c);
+
+ P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch1 <= '0';
+ ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
+ refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch1 : mupix_serdesrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch1,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
+ rx_los_low_ch_s => rx_los_low_ch1_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
+
+ P3 : PROCESS(fpga_rxrefclk_ch2, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch2 <= '0';
+ ELSIF (fpga_rxrefclk_ch2'event and fpga_rxrefclk_ch2 = '1') THEN
+ refclkdiv2_rx_ch2 <= not refclkdiv2_rx_ch2;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch2 : mupix_serdesrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch2,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch2_sig,
+ rx_los_low_ch_s => rx_los_low_ch2_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch2_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch2_c);
+
+ P4 : PROCESS(fpga_rxrefclk_ch3, rst_n)
+ BEGIN
+ IF (rst_n = '0') THEN
+ refclkdiv2_rx_ch3 <= '0';
+ ELSIF (fpga_rxrefclk_ch3'event and fpga_rxrefclk_ch3 = '1') THEN
+ refclkdiv2_rx_ch3 <= not refclkdiv2_rx_ch3;
+ END IF;
+ END PROCESS;
+
+rx_reset_sm_ch3 : mupix_serdesrx_reset_sm
+--synopsys translate_off
+ generic map (count_index => 4)
+--synopsys translate_on
+port map (
+ refclkdiv2 => refclkdiv2_rx_ch3,
+ rst_n => rst_n,
+ rx_cdr_lol_ch_s => rx_cdr_lol_ch3_sig,
+ rx_los_low_ch_s => rx_los_low_ch3_sig,
+ tx_pll_lol_qd_s => fpsc_vlo,
+ rx_pcs_rst_ch_c => rx_pcs_rst_ch3_c,
+ rx_serdes_rst_ch_c => rx_serdes_rst_ch3_c);
+
+
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+end mupix_serdes_arch ;
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n serdes_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill
+
+-- Thu Jan 11 13:46:45 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity serdes_fifo is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end serdes_fifo;
+
+architecture Structure of serdes_fifo is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r1: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5: std_logic;
+ signal co4: std_logic;
+ signal wcount_11: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal co3_1: std_logic;
+ signal rcount_9: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal precin: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r9: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r10: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w7: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal rcount_w8: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_10: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "serdes_fifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t23: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t22: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t21: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_27: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>w_gcount_r211,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_26: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>w_gcount_r27,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_25: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_24: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r10);
+
+ LUT4_23: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
+
+ LUT4_22: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+ LUT4_21: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
+
+ LUT4_20: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
+
+ LUT4_19: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_18: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_17: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
+
+ LUT4_16: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_15: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r211, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 9)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2,
+ ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6,
+ ADB12=>rptr_7, ADB13=>rptr_8, CEB=>rden_i, CLKB=>RdClock,
+ OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0),
+ DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5),
+ DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>Q(8), DOA10=>Q(9),
+ DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12), DOA14=>Q(13),
+ DOA15=>Q(14), DOA16=>Q(15), DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>open,
+ DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26), DOB12=>Q(27),
+ DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31),
+ DOB17=>open);
+
+ FF_121: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_120: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_119: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_118: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_117: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_116: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_115: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_114: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_113: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_112: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_111: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_110: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_109: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_108: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_107: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_106: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_105: FD1P3DX
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_104: FD1P3DX
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_103: FD1P3DX
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_102: FD1P3DX
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_101: FD1P3DX
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_100: FD1P3DX
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_99: FD1P3DX
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_98: FD1P3DX
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_97: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_96: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_95: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_94: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_93: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_92: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_91: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_90: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_89: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_88: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_87: FD1P3DX
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_86: FD1P3DX
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_85: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_84: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_83: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_82: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_81: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_80: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_79: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_78: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_77: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_76: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_75: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_74: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_73: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_72: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_71: FD1P3DX
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_70: FD1P3DX
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_69: FD1P3DX
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_68: FD1P3DX
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_67: FD1P3DX
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_66: FD1P3DX
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_65: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_64: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_63: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_62: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_61: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_60: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_59: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_58: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_57: FD1P3DX
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_56: FD1P3DX
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_55: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_54: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_53: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_52: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_51: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_50: FD1S3DX
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_49: FD1S3DX
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_48: FD1S3DX
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_47: FD1S3DX
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_46: FD1S3DX
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_45: FD1S3DX
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_44: FD1S3DX
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_43: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_42: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_41: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_40: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_39: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_38: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_37: FD1S3DX
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_36: FD1S3DX
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_35: FD1S3DX
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_34: FD1S3DX
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_33: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_32: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_31: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_30: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_29: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_28: FD1S3DX
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_24: FD1S3DX
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_23: FD1S3DX
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_22: FD1S3DX
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ precin_inst276: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open,
+ S1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>precin, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r7, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r9, A1=>wcount_r10, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r9, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r10,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w7, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w8,
+ B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of serdes_fifo is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:OR2 use entity ecp3.OR2(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
+-- Module Version: 5.8
+--/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n serdes_fifo_large -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 8 -depth 4096 -rdata_width 32 -no_enable -pe -1 -pf -1 -rfill
+
+-- Thu Jan 11 13:50:20 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity serdes_fifo_large is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(10 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end serdes_fifo_large;
+
+architecture Structure of serdes_fifo_large is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_2: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal r_gdata_9: std_logic;
+ signal rptr_10: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal r_gcount_10: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal r_gcount_w210: std_logic;
+ signal r_gcount_w10: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal co6: std_logic;
+ signal co5: std_logic;
+ signal wcount_12: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co3_1: std_logic;
+ signal ircount_10: std_logic;
+ signal co5_1: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_10: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal precin: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal rfill_sub_10: std_logic;
+ signal co4_2: std_logic;
+ signal rptr_9: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal co5_2d: std_logic;
+ signal co5_2: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal wcount_r8: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r10: std_logic;
+ signal wcount_r11: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_w6: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_4: std_logic;
+ signal rcount_w8: std_logic;
+ signal rcount_w9: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1A
+ generic (INITVAL : in std_logic_vector(15 downto 0));
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KC
+ generic (GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String; CSDECODE_B : in String;
+ CSDECODE_A : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
+ WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
+ WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute RESETMODE : string;
+ attribute GSR : string;
+ attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "serdes_fifo_large.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is "";
+ attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC";
+ attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "serdes_fifo_large.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
+ attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_132 : label is "ENABLED";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ AND2_t25: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t24: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t23: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t22: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t21: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t10: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_9, B=>rcount_10, Z=>r_gdata_9);
+
+ LUT4_30: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>w_gcount_r212,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_29: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_28: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_27: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r11);
+
+ LUT4_26: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
+
+ LUT4_25: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
+
+ LUT4_24: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+ LUT4_23: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
+
+ LUT4_22: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_21: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_20: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
+
+ LUT4_19: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_18: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_17: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_16: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
+
+ LUT4_15: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>r_gcount_w210,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_14: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_gcount_w26,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_13: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w29, AD2=>r_gcount_w210, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w9);
+
+ LUT4_12: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29,
+ AD1=>r_gcount_w210, AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_11: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>rcount_w9, DO0=>rcount_w6);
+
+ LUT4_10: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_9: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w4);
+
+ LUT4_8: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w3);
+
+ LUT4_7: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_6: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>r_gcount_w22, DO0=>rcount_w1);
+
+ LUT4_5: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
+ AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>r_g2b_xor_cluster_2);
+
+ LUT4_4: ROM16X1A
+ generic map (initval=> X"6996")
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r212, B=>rptr_10, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1A
+ generic map (initval=> X"0410")
+ port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r212,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1A
+ generic map (initval=> X"1004")
+ port map (AD3=>rptr_10, AD2=>rcount_10, AD1=>w_gcount_r212,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1A
+ generic map (initval=> X"0140")
+ port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w210,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1A
+ generic map (initval=> X"4001")
+ port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w210,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_1: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
+ ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
+ ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2,
+ ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6,
+ ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i,
+ CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0),
+ DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(8), DOB5=>Q(9),
+ DOB6=>Q(10), DOB7=>Q(11), DOB8=>open, DOB9=>Q(16),
+ DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19), DOB13=>Q(24),
+ DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27), DOB17=>open);
+
+ pdp_ram_0_1_0: DP16KC
+ generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
+ WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
+ REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 4)
+ port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6),
+ DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
+ ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
+ ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
+ OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, ADB6=>rptr_2,
+ ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, ADB10=>rptr_6,
+ ADB11=>rptr_7, ADB12=>rptr_8, ADB13=>rptr_9, CEB=>rden_i,
+ CLKB=>RdClock, OCEB=>rden_i, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open,
+ DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open,
+ DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open,
+ DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open,
+ DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4),
+ DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(12), DOB5=>Q(13),
+ DOB6=>Q(14), DOB7=>Q(15), DOB8=>open, DOB9=>Q(20),
+ DOB10=>Q(21), DOB11=>Q(22), DOB12=>Q(23), DOB13=>Q(28),
+ DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31), DOB17=>open);
+
+ FF_132: FD1P3BX
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_131: FD1P3DX
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_130: FD1P3DX
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_129: FD1P3DX
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_128: FD1P3DX
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_127: FD1P3DX
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_126: FD1P3DX
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_125: FD1P3DX
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_124: FD1P3DX
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_123: FD1P3DX
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_122: FD1P3DX
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_121: FD1P3DX
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_120: FD1P3DX
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_119: FD1P3DX
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_118: FD1P3DX
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_117: FD1P3DX
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_116: FD1P3DX
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_115: FD1P3DX
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_114: FD1P3DX
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_113: FD1P3DX
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_112: FD1P3DX
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_111: FD1P3DX
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_110: FD1P3DX
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_109: FD1P3DX
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_108: FD1P3DX
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_107: FD1P3DX
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_106: FD1P3DX
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_105: FD1P3DX
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_104: FD1P3DX
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_103: FD1P3DX
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_102: FD1P3DX
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_101: FD1P3DX
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_100: FD1P3DX
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_99: FD1P3DX
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_98: FD1P3DX
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_97: FD1P3DX
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_96: FD1P3DX
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_95: FD1P3DX
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_94: FD1P3DX
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_93: FD1P3BX
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_92: FD1P3DX
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_91: FD1P3DX
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_90: FD1P3DX
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_89: FD1P3DX
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_88: FD1P3DX
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_87: FD1P3DX
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_86: FD1P3DX
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_85: FD1P3DX
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_84: FD1P3DX
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_83: FD1P3DX
+ port map (D=>ircount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_10);
+
+ FF_82: FD1P3DX
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_81: FD1P3DX
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_80: FD1P3DX
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_79: FD1P3DX
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_78: FD1P3DX
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_77: FD1P3DX
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_76: FD1P3DX
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_75: FD1P3DX
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_74: FD1P3DX
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_73: FD1P3DX
+ port map (D=>r_gdata_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_72: FD1P3DX
+ port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_10);
+
+ FF_71: FD1P3DX
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_70: FD1P3DX
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_69: FD1P3DX
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_68: FD1P3DX
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_67: FD1P3DX
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_66: FD1P3DX
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_65: FD1P3DX
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_64: FD1P3DX
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_63: FD1P3DX
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_62: FD1P3DX
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_61: FD1P3DX
+ port map (D=>rcount_10, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_10);
+
+ FF_60: FD1S3DX
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_59: FD1S3DX
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_58: FD1S3DX
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_57: FD1S3DX
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_56: FD1S3DX
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_55: FD1S3DX
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_54: FD1S3DX
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_53: FD1S3DX
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_52: FD1S3DX
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_51: FD1S3DX
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_50: FD1S3DX
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_49: FD1S3DX
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_48: FD1S3DX
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_47: FD1S3DX
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_46: FD1S3DX
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_45: FD1S3DX
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_44: FD1S3DX
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_43: FD1S3DX
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_42: FD1S3DX
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_41: FD1S3DX
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_40: FD1S3DX
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_39: FD1S3DX
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_38: FD1S3DX
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_37: FD1S3DX
+ port map (D=>r_gcount_10, CK=>WrClock, CD=>rRst, Q=>r_gcount_w10);
+
+ FF_36: FD1S3DX
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_35: FD1S3DX
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_34: FD1S3DX
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_33: FD1S3DX
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_32: FD1S3DX
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_31: FD1S3DX
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_30: FD1S3DX
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_29: FD1S3DX
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_28: FD1S3DX
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_27: FD1S3DX
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_26: FD1S3DX
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_25: FD1S3DX
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_24: FD1S3DX
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_23: FD1S3DX
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_22: FD1S3DX
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_21: FD1S3DX
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_20: FD1S3DX
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_19: FD1S3DX
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_18: FD1S3DX
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_17: FD1S3DX
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_16: FD1S3DX
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_15: FD1S3DX
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_14: FD1S3DX
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_13: FD1S3DX
+ port map (D=>r_gcount_w10, CK=>WrClock, CD=>rRst,
+ Q=>r_gcount_w210);
+
+ FF_12: FD1S3DX
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_11: FD1S3DX
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_10: FD1S3DX
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_9: FD1S3DX
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_8: FD1S3DX
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_7: FD1S3DX
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_6: FD1S3DX
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_5: FD1S3DX
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_4: FD1S3DX
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_3: FD1S3DX
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_2: FD1S3DX
+ port map (D=>rfill_sub_10, CK=>RdClock, CD=>rRst, Q=>RCNT(10));
+
+ FF_1: FD1S3BX
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
+ NC0=>iwcount_12, NC1=>open);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ r_gctr_5: CU2
+ port map (CI=>co4_1, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_1,
+ NC0=>ircount_10, NC1=>open);
+
+ precin_inst297: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open,
+ S1=>open);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>precin, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_5, B1=>rptr_6,
+ BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5, S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r10, B0=>rptr_7,
+ B1=>rptr_8, BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7,
+ S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>wcount_r11, A1=>rfill_sub_msb, B0=>rptr_9,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>co5_2, S0=>rfill_sub_9,
+ S1=>rfill_sub_10);
+
+ rfilld: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co5_2, COUT=>open, S0=>co5_2d, S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>wcount_r8,
+ B1=>w_g2b_xor_cluster_0, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>rcount_9, B0=>wcount_r10,
+ B1=>wcount_r11, CI=>co3_3, GE=>co4_3);
+
+ empty_cmp_5: AGEB2
+ port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
+ B1=>scuba_vlo, CI=>co4_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w6,
+ B1=>r_g2b_xor_cluster_0, CI=>co3_4, GE=>co4_4);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w8,
+ B1=>rcount_w9, CI=>co4_4, GE=>co5_3);
+
+ full_cmp_6: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co5_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of serdes_fifo_large is
+ for Structure
+ for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+ for all:AND2 use entity ecp3.AND2(V); end for;
+ for all:CU2 use entity ecp3.CU2(V); end for;
+ for all:FADD2B use entity ecp3.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp3.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+ for all:INV use entity ecp3.INV(V); end for;
+ for all:OR2 use entity ecp3.OR2(V); end for;
+ for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+ for all:VHI use entity ecp3.VHI(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ for all:XOR2 use entity ecp3.XOR2(V); end for;
+ for all:DP16KC use entity ecp3.DP16KC(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trb3.git / commitdiff