+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
---USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-USE IEEE.numeric_std.ALL;
-library work;
-use work.trb_net_std.all;
-
-
-entity cri_data_sender is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- ENABLE_TRANSPORT : in std_logic;
-
- -- Port to API
- API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_DATAREADY_OUT : out std_logic;
- API_READ_IN : in std_logic;
- API_SHORT_TRANSFER_OUT : out std_logic;
- API_DTYPE_OUT : out std_logic_vector (3 downto 0);
- API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0);
- API_SEND_OUT : out std_logic;
- -- Receiver port
- API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- API_TYP_IN : in std_logic_vector (2 downto 0);
- API_DATAREADY_IN : in std_logic;
- API_READ_OUT : out std_logic;
- -- APL Control port
- API_RUN_IN : in std_logic;
- API_SEQNR_IN : in std_logic_vector (7 downto 0);
- API_LENGTH_OUT : out std_logic_vector (15 downto 0);
- MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
-
- --data from event packer
- CTS_NUMBER_IN : in std_logic_vector(15 downto 0); --not used; got it from FEE
- CTS_CODE_IN : in std_logic_vector( 7 downto 0); --not used; got it from FEE
- CTS_INFORMATION_IN : in std_logic_vector( 7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector( 3 downto 0); --not used; got it from FEE
- CTS_START_READOUT_IN : in std_logic;
- CTS_READ_IN : in std_logic;
- CTS_DATA_OUT : out std_logic_vector(31 downto 0);
- CTS_DATAREADY_OUT : out std_logic;
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); -- 0 terminated
- CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- 0 terminated
- -- Data from Frontends
- FEE_DATA_IN : in std_logic_vector(15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic;
- FEE_BUSY_IN : in std_logic;
- FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0);
-
- DEBUG_OUT : out std_logic_vector(191 downto 0)
- );
-end entity;
-
-architecture cri_data_sender_arch of cri_data_sender is
-
- type save_states_t is (IDLE, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SEND_TERM_PULSE, CLOSE, CLEANUP);
- signal save_current_state, save_next_state : save_states_t;
-
- type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP);
- signal send_state_current, send_state_next : data_sender_states_t;
-
- constant loc_buff_depth : integer := 4;
- type loc_buffer_t is array (0 to loc_buff_depth) of std_logic_vector(16 downto 0);
- signal local_buffer : loc_buffer_t := (others => (others=> '0'));
-
- signal rec_state, send_state_bits : std_logic_vector(3 downto 0);
-
- signal df_wr_en_qq, df_wr_en_q, df_wr_en,df_rd_en : std_logic;
- signal df_data : std_logic_vector(15 downto 0);
- signal df_eos_q, df_eos : std_logic;
- signal fifo_almFull : std_logic;
- signal df_afull, df_full_real : std_logic;
- signal df_empty : std_logic;
- signal df_wcnt : std_logic_vector(11 downto 0);
- signal df_rdy_q, df_rdy : std_logic;
- signal data_out, df_q : std_logic_vector(15 downto 0);
- signal load_eod : std_logic;
- signal fifo_rd_en : std_logic;
- signal eod_out : std_logic;
- signal local_buf_empty : std_logic;
-
- -- saving
- signal cts_rnd, cts_trg : std_logic_vector(15 downto 0);
- signal length_cnt : std_logic_vector(15 downto 0) := x"0000";
-
- -- sending
- signal cri_apl_reading : std_logic;
- signal cri_apl_data : std_logic_vector(15 downto 0);
- signal cri_apl_packet_num : std_logic_vector(2 downto 0);
- signal cri_apl_dataready : std_logic;
- signal cri_apl_read : std_logic;
- signal data_trans_finished : std_logic;
- signal load_data : std_logic;
- signal tmp_data : std_logic_vector( 7 downto 0);
- signal cri_apl_send : std_logic;
- signal received_answer : std_logic;
- signal cri_apl_run : std_logic;
-
- signal cri_event_cnt : std_logic_vector(15 downto 0) := x"0000";
-
- signal cri_apl_answer_data : std_logic_vector(15 downto 0);
- signal cri_apl_answer_packet_num : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal cri_apl_answer_typ : std_logic_vector( 2 downto 0);
- signal cri_apl_answer_dataready : std_logic;
- signal loaded_bytes : std_logic_vector(15 downto 0) := x"0000";
- signal cri_packet_num_cnt : std_logic_vector( 1 downto 0) := "00";
-
- signal data_save_cnt : std_logic_vector(15 downto 0);
- signal fee_read_loc : std_logic;
-
- signal data_open : std_logic; -- for modelsim
-
- type loc_buffer_dbg_t is array (0 to 7) of std_logic_vector(15 downto 0);
- signal local_buffer_dbg : loc_buffer_dbg_t := (others => (others=> '0'));
-begin
-
- CTS_LENGTH_OUT <= (others => '0');
- CTS_ERROR_PATTERN_OUT <= (others => '0');
-
- SAVE_MACHINE_PROC : process(RESET, CLK)
- begin
- if RESET = '1' then
- save_current_state <= IDLE;
- elsif rising_edge(CLK) then
- save_current_state <= save_next_state;
- end if;
- end process;
-
- SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN)
- begin
- rec_state <= x"0";
- case (save_current_state) is
- when IDLE =>
- rec_state <= x"1";
- if (CTS_START_READOUT_IN = '1') then
- save_next_state <= WAIT_FOR_DATA;
- else
- save_next_state <= IDLE;
- end if;
-
- when WAIT_FOR_DATA =>
- rec_state <= x"2";
- if (FEE_BUSY_IN = '1') then
- save_next_state <= SAVE_DATA;
- else
- save_next_state <= WAIT_FOR_DATA;
- end if;
-
- when SAVE_DATA =>
- rec_state <= x"3";
- if (FEE_BUSY_IN = '0') then
- save_next_state <= TERMINATE;
- else
- save_next_state <= SAVE_DATA;
- end if;
-
- when TERMINATE =>
- rec_state <= x"5";
- if (CTS_READ_IN = '1') then
- save_next_state <= SEND_TERM_PULSE; --CLOSE;
- else
- save_next_state <= TERMINATE;
- end if;
-
- when SEND_TERM_PULSE =>
- rec_state <= x"6";
- save_next_state <= CLOSE;
-
- when CLOSE =>
- rec_state <= x"6";
- save_next_state <= ADD_SUBSUB1;
-
- when ADD_SUBSUB1 =>
- rec_state <= x"7";
- save_next_state <= ADD_SUBSUB2;
-
- when ADD_SUBSUB2 =>
- rec_state <= x"8";
- save_next_state <= ADD_SUBSUB3;
-
- when ADD_SUBSUB3 =>
- rec_state <= x"9";
- save_next_state <= ADD_SUBSUB4;
-
- when ADD_SUBSUB4 =>
- rec_state <= x"a";
- save_next_state <= CLEANUP;
-
- when CLEANUP =>
- rec_state <= x"c";
- if (CTS_START_READOUT_IN = '0') then
- save_next_state <= IDLE;
- else
- save_next_state <= CLEANUP;
- end if;
-
- when others => save_next_state <= IDLE;
-
- end case;
- end process;
-
- CTS_DATAREADY_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then
- CTS_DATAREADY_OUT <= '1';
- elsif (save_current_state = TERMINATE) then
- CTS_DATAREADY_OUT <= '1';
- else
- CTS_DATAREADY_OUT <= '0';
- end if;
- end if;
- end process;
-
- CTS_READOUT_FINISHED_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if (save_current_state = CLEANUP) then
- CTS_READOUT_FINISHED_OUT <= '1';
- else
- CTS_READOUT_FINISHED_OUT <= '0';
- end if;
- end if;
- end process;
-
- CTS_DATA_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg;
- end if;
- end process;
-
- CTS_RND_TRG_PROC : process(CLK)
- begin
- if rising_edge(CLK) then
- if ((save_current_state = SAVE_DATA) and
- (FEE_DATAREADY_IN = '1') and
- (fee_read_loc = '1'))
- then
- if (length_cnt = x"0000") then
- cts_rnd <= FEE_DATA_IN;
- end if;
-
- if (length_cnt = x"0001") then
- cts_trg <= FEE_DATA_IN;
- end if;
- else
- cts_rnd <= cts_rnd;
- cts_trg <= cts_trg;
- end if;
- end if;
- end process;
-
- CTS_WORD_CNT : process(CLK)
- begin
- if rising_edge(CLK) then
- if (save_current_state = IDLE) then
- length_cnt <= (others => '0');
- elsif ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then
- length_cnt <= length_cnt + 1;
- else
- length_cnt <= length_cnt;
- end if;
- end if;
- end process;
-
-
- DATA_WRITE_PROC : process begin
- wait until rising_edge(CLK);
- if ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then
- df_wr_en <= '1';
- elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then
- df_wr_en <= '1';
- else
- df_wr_en <= '0';
- end if;
- end process;
-
--- FEE_READ_PROC : process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if (save_current_state = SAVE_DATA) then
--- if (df_afull = '0') then
--- local_read <= '1';
--- else
--- local_read <= '0';
--- end if;
--- else
--- local_read <= '1';
--- end if;
--- end if;
--- end process FEE_READ_PROC;
-
- SF_DATA_EOD_PROC : process begin
- wait until rising_edge(CLK);
- case (save_current_state) is
- when SAVE_DATA =>
- df_data <= FEE_DATA_IN;
- df_eos_q <= '0';
-
- when ADD_SUBSUB1 =>
- df_data <= x"0001";
- df_eos_q <= '0';
-
- when ADD_SUBSUB2 =>
- df_data <= x"5555";
- df_eos_q <= '0';
-
- when ADD_SUBSUB3 =>
- df_data <= FEE_STATUS_BITS_IN(31 downto 16);
- df_eos_q <= '0';
-
- when ADD_SUBSUB4 =>
- df_data <= FEE_STATUS_BITS_IN(15 downto 0);
- df_eos_q <= '1';
-
- when others =>
- df_data <= df_data;
- df_eos_q <= '0';
-
- end case;
- end process;
-
- FEE_READ_OUT <= fee_read_loc;
- fee_read_loc <= not df_afull;--local_read;
-
--- DATA_FIFO : entity work.fifo_64kx9_af_cnt
--- port map(
--- Data(15 downto 0) => df_data,
--- Data(16) => df_eos_q,
--- WrClock => CLK,
--- RdClock => CLK,
--- WrEn => df_wr_en,
--- RdEn => df_rd_en,
--- Reset => RESET,
--- RPReset => RESET,
--- Q(15 downto 0) => df_q,
--- Q(16) => load_eod,
--- Empty => df_empty,
--- Full => df_full_real,
--- AlmostFull => df_afull,
--- WCNT => df_wcnt
--- );
-
- DATA_FIFO : entity work.fifo_18x2k_oreg
- port map (
- Data(15 downto 0) => df_data,
- Data(16) => df_eos_q,
- Data(17) => '0',
- Clock => CLK,
- WrEn => df_wr_en,
- RdEn => df_rd_en,
- Reset => RESET,
- AmFullThresh => b"11111111000",
- Q(15 downto 0) => data_out,--df_q, --df_q if fifo is without outreg
- Q(16) => eod_out,--load_eod, --load_eod if fifo is without outreg
- Q(17) => data_open,
- WCNT => df_wcnt,
- Empty => df_empty,
- Full => df_full_real,
- AlmostFull => df_afull
- );
-
- --READ from FIFO to TrbNet API
-
- df_rd_en <= load_data and not df_empty and local_buf_empty;
-
- load_data <= '1' when send_state_current = LOAD else '0';
-
- DATA_FIFO_CONTRL_PROC : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- df_rdy_q <= '0';
- df_rdy <= '0';
- --data_out <= x"0000";
- --eod_out <= '0';
- else
- df_rdy_q <= df_rd_en;
- df_rdy <= df_rdy_q; -- delay from readout reg of fifo
-
- --data_out <= df_q; -- readout reg for fifo
- --eod_out <= load_eod;
- end if;
- end process;
-
-
- LOCAL_BUFF_PROC : process
- variable buff_cnt : integer range 0 to loc_buff_depth := 0;
- begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- buff_cnt := 0;
- else
-
- -- Data from sub is loaded; first data from following sub is (partialy) loaded
- if (send_state_current /= LOAD) and (df_rdy = '1') then
- local_buffer(buff_cnt) <= eod_out & data_out;
- buff_cnt := buff_cnt + 1;
- end if;
-
- -- first word in buffer is always in 0; is loaded in sending process.
- if (send_state_current = LOAD) and (local_buf_empty = '0') then
- local_buffer(0) <= local_buffer(1);
- local_buffer(1) <= local_buffer(2);
- local_buffer(2) <= local_buffer(3);
- local_buffer(3) <= local_buffer(4);
- local_buffer(4) <= (others => '0');
- buff_cnt := buff_cnt - 1;
- end if;
-
- -- has to be atthis position, to garantee that buff_cnt won't be negative
- if buff_cnt = 0 then
- local_buf_empty <= '1';
- else
- local_buf_empty <= '0';
- end if;
-
- end if;
- end process;
-
-
- SEND_STATE_PROC : process(RESET, CLK)
- begin
- if RESET = '1' then
- send_state_current <= IDLE;
- else
- if rising_edge(CLK) then
- send_state_current <= send_state_next;
- end if;
- end if;
- end process;
-
-
- SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(8),data_trans_finished,received_answer,cri_apl_run)
- begin
- send_state_bits <= x"0";
- case send_state_current is
- when IDLE =>
- send_state_bits <= x"1";
- send_state_next <= PREPARE_SEND;
-
- when PREPARE_SEND =>
- send_state_bits <= x"2";
- if cri_apl_reading = '1' and ENABLE_TRANSPORT = '1' then
- send_state_next <= LOAD;
- else
- send_state_next <= PREPARE_SEND;
- end if;
-
- when LOAD =>
- send_state_bits <= x"3";
- if ((eod_out = '1' and df_rdy = '1') or ( local_buf_empty = '0' and local_buffer(0)(8) = '1' )) then --last word of subevent is currently in data_out
- send_state_next <= FINISH_SEND;
- else
- send_state_next <= LOAD;
- end if;
-
- when FINISH_SEND =>
- send_state_bits <= x"4";
- if data_trans_finished = '1' then
- send_state_next <= STOP_SEND;
- else
- send_state_next <= FINISH_SEND;
- end if;
-
- when STOP_SEND =>
- send_state_bits <= x"5";
- send_state_next <= READ_ANSWER;
-
- when READ_ANSWER =>
- send_state_bits <= x"6";
- if received_answer = '1' then
- send_state_next <= FINISH_ACTION;
- else
- send_state_next <= READ_ANSWER;
- end if;
-
- when FINISH_ACTION =>
- send_state_bits <= x"7";
- if cri_apl_run = '0' then
- send_state_next <= PREPARE_SEND;
- else
- send_state_next <= FINISH_ACTION;
- end if;
-
- when others =>
- send_state_bits <= x"8";
- send_state_next <= IDLE;
-
- end case;
- end process;
-
-
-
- DATA_TRANSPORT_PROC : process
- variable loc_tmp_data : std_logic_vector(15 downto 0);
- variable loc_data_rdy : std_logic;
- --variable pos_cnt : std_logic := '0';
- begin
- wait until rising_edge(CLK);
-
- cri_apl_dataready <= '0';
- data_trans_finished <= '0';
-
- if RESET = '1' then
- loc_tmp_data := x"0000";
- loc_data_rdy := '0';
- loaded_bytes <= (others => '0');
- else
- --prepare data
- loc_data_rdy := '0';
- if (send_state_current = LOAD) then -- load state data
- -- get data from correct source
- if (local_buf_empty = '0') then
- loc_tmp_data := local_buffer(0)(15 downto 0);
- loc_data_rdy := '1';
- else
- loc_tmp_data := data_out;
- loc_data_rdy := df_rdy;
- end if;
- end if;
-
- if (send_state_current = LOAD) then -- or (send_state_current = FINISH_SEND)) then
- if loc_data_rdy = '1' then -- only process if data is valid/rdy
- cri_apl_dataready <= '1';
- cri_packet_num_cnt <= cri_packet_num_cnt + 1;
- loaded_bytes <= loaded_bytes + 1;
- cri_apl_data <= loc_tmp_data;-- & tmp_data; --maybe wrong order!
- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
- end if; -- end data rdy
- end if;-- load state
-
-
- -- finish the send process:
- -- packet if last word in LOAD was not send, send it now.
- if (send_state_current = FINISH_SEND) then
- if (cri_packet_num_cnt = "00") then
- data_trans_finished <= '1';
- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
- else
- cri_packet_num_cnt <= cri_packet_num_cnt + 1;
- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt);
- cri_apl_dataready <= '1';
- cri_apl_data <= x"AAAA";
- end if;
- end if; -- FINISH_SEND
-
- -- to be sure that cntr is null in next data sending process.
- if (data_trans_finished = '1') then
- cri_packet_num_cnt <= "00";
- loaded_bytes <= (others => '0');
- end if;
-
- if ((loaded_bytes > x"0000") and (loaded_bytes < x"0009") and (cri_apl_dataready = '1')) then
- local_buffer_dbg(to_integer( unsigned( loaded_bytes )-1) ) <= cri_apl_data;
- end if;
-
- end if;
- end process;
-
-
-
- -- handle the data sending flag to the trbnet APL
- DATA_SEND_OUT_PROC : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- cri_apl_send <= '0';
- else
- if ((send_state_current = PREPARE_SEND) or
- (send_state_current = LOAD) or
- (send_state_current = FINISH_SEND) or
- (send_state_current = STOP_SEND))
- then
- cri_apl_send <= '1';
- else
- cri_apl_send <= '0';
- end if;
- end if;
- end process;
-
-
-
- -- handle the read flag to the trbnet APL
- DATA_READ_OUT_PROC : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- cri_apl_read <= '0';
- else
- --if ((send_state_current /= IDLE) then
- if (( send_state_current = READ_ANSWER ) or
- ( send_state_current = STOP_SEND ))
- then
- cri_apl_read <= '1';
- else
- cri_apl_read <= '0';
- end if;
- end if;
- end process;
-
-
-
- -- handle the answer from CRI over trbnet
- EVENT_CNT_PROC : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- received_answer <= '0';
- cri_event_cnt <= (others => '0');
- else
- received_answer <= '0';
- if ((cri_apl_answer_dataready = '1') and (cri_apl_answer_typ = TYPE_TRM) and (cri_apl_answer_packet_num = c_F3)) then
- --cri_data_send_cnt <= 0;
- cri_event_cnt <= cri_event_cnt + 1;
- received_answer <= '1';
- end if;
- end if;
- end process;
-
-
--- DEBUG_OUT
- DATA_SAVE_CNT_PROC : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- data_save_cnt <= (others => '0');
- else
- if ((save_current_state = CLEANUP) and (CTS_START_READOUT_IN = '0')) then
- data_save_cnt <= data_save_cnt + 1;
- end if;
- end if;
- end process;
-
-
- -- Data to CRI board
- API_DATA_OUT <= cri_apl_data;
- API_PACKET_NUM_OUT <= cri_apl_packet_num;
- API_DATAREADY_OUT <= cri_apl_dataready;
- cri_apl_reading <= API_READ_IN;
-
- API_SHORT_TRANSFER_OUT <= '0';
- API_DTYPE_OUT <= (others => '0');
- API_ERROR_PATTERN_OUT <= (others => '0');
- API_SEND_OUT <= cri_apl_send;
-
- cri_apl_answer_data <= API_DATA_IN;
- cri_apl_answer_packet_num <= API_PACKET_NUM_IN;
- cri_apl_answer_typ <= API_TYP_IN;
- cri_apl_answer_dataready <= API_DATAREADY_IN;
-
- API_READ_OUT <= cri_apl_read;
- -- APL Control port
- cri_apl_run <= API_RUN_IN;
- API_LENGTH_OUT <= (others => '0');
-
- DEBUG_OUT(3 downto 0) <= rec_state;
- DEBUG_OUT(7 downto 4) <= send_state_bits;
- DEBUG_OUT( 8) <= df_empty;
- DEBUG_OUT( 9) <= df_full_real;
- DEBUG_OUT(10) <= df_afull;
- DEBUG_OUT(11) <= '0';
- DEBUG_OUT(14 downto 12) <= cri_apl_packet_num;
- DEBUG_OUT(15) <= '0';
- DEBUG_OUT(31 downto 16) <= cri_event_cnt;
-
- DEBUG_OUT( 47 downto 32) <= local_buffer_dbg(0);
- DEBUG_OUT( 63 downto 48) <= local_buffer_dbg(1);
- DEBUG_OUT( 79 downto 64) <= local_buffer_dbg(2);
- DEBUG_OUT( 95 downto 80) <= local_buffer_dbg(3);
- DEBUG_OUT(111 downto 96) <= local_buffer_dbg(4);
- DEBUG_OUT(127 downto 112) <= local_buffer_dbg(5);
- DEBUG_OUT(143 downto 128) <= local_buffer_dbg(6);
- DEBUG_OUT(159 downto 144) <= local_buffer_dbg(7);
-
- DEBUG_OUT(175 downto 160) <= data_save_cnt;
- DEBUG_OUT(176) <= local_buf_empty;
- DEBUG_OUT(177) <= local_buffer(0)(8);
- DEBUG_OUT(178) <= df_rdy;
- DEBUG_OUT(179) <= eod_out;
- DEBUG_OUT(180) <= data_trans_finished;
- DEBUG_OUT(181) <= cri_apl_run;
- DEBUG_OUT(182) <= cri_apl_dataready;
- DEBUG_OUT(183) <= cri_apl_send;
- DEBUG_OUT(184) <= cri_apl_read;
- DEBUG_OUT(191 downto 185) <= cri_apl_data( 6 downto 0);
-
-end architecture;
+++ /dev/null
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-
---take care of USE_INPUT_SBUF for multiplexer!
-
-entity trb_net16_cri_hub_base is
- generic (
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
- HUB_CTRL_ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
- HUB_CTRL_BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FE";
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES);
- USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES);
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- IBUF_SECURE_MODE : integer range 0 to 1 := c_YES; --not used any more
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
- INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0');
- INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) :=
- x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_000050FF_00000000" &
- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF";
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0');
- INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
- USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- CLOCK_FREQUENCY : integer range 1 to 200 := 100;
- USE_ONEWIRE : integer range 0 to 2 := c_YES;
- BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
- --media interfaces
- MII_NUMBER : integer range 0 to 32 := 4; --TODO increase to 48; will be a problem due to reg sizes
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
- MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO);
- -- settings for external api connections
- INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
- INT_CHANNELS : hub_api_config_t := (others => 3);
- INT_IBUF_DEPTH : hub_api_config_t := (others => 6);
- RESET_IOBUF_AT_TIMEOUT : integer range 0 to 1 := c_NO
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media interfacces
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
- --INT: interfaces to connect APIs
- INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0);
- INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0);
- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0);
- INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0');
- INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0');
- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0');
- INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0);
- ONEWIRE : inout std_logic;
- ONEWIRE_MONITOR_IN : in std_logic := '0';
- ONEWIRE_MONITOR_OUT : out std_logic;
- COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs
- COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
- COMMON_STAT_REG_STROBE : out std_logic_vector (std_COMSTATREG-1 downto 0);
- COMMON_CTRL_REG_STROBE : out std_logic_vector (std_COMCTRLREG-1 downto 0);
- MY_ADDRESS_OUT : out std_logic_vector (15 downto 0);
- TEMPERATURE_OUT : out std_logic_vector (11 downto 0);
- --REGIO INTERFACE
- REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0);
- REGIO_READ_ENABLE_OUT : out std_logic;
- REGIO_WRITE_ENABLE_OUT : out std_logic;
- REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0);
- REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0');
- REGIO_DATAREADY_IN : in std_logic := '0';
- REGIO_NO_MORE_DATA_IN : in std_logic := '0';
- REGIO_WRITE_ACK_IN : in std_logic := '0';
- REGIO_UNKNOWN_ADDR_IN : in std_logic := '0';
- REGIO_TIMEOUT_OUT : out std_logic;
- REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0');
- TIMER_TICKS_OUT : out std_logic_vector(1 downto 0);
- HUB_LED_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- UNIQUE_ID_OUT : out std_logic_vector (63 downto 0);
- --Fixed status and control ports
- HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- HUB_STAT_GEN : out std_logic_vector (31 downto 0);
- MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (16*32-1 downto 0); --Status of custom STAT regs
- STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
- IOBUF_STAT_INIT_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
- IOBUF_STAT_REPLY_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
-
- --Debugging registers
- STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
- CTRL_DEBUG : in std_logic_vector (31 downto 0); --free control regs for debugging
- -- bits 0-2 are NOT (inverted) error of streaming port
-
- BUS_HUB_DBG_RX : in CTRLBUS_RX;
- BUS_HUB_DBG_TX : out CTRLBUS_TX
- );
-end entity;
-
-architecture trb_net16_cri_hub_base_arch of trb_net16_cri_hub_base is
-
-
-
- constant total_point_num : integer := MII_NUMBER*2**(c_MUX_WIDTH-1) + INT_NUMBER + 1;
- signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0) := (others => '0');
- signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0) := (others => '0');
- signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0) := (others => '0');
- signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0) := (others => '0');
- signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0) := (others => '0');
-
- signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0) := (others => '0');
- signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal hub_to_buf_INIT_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
-
- signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
- signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal buf_to_hub_INIT_PACKET_NUM: std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
-
- signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
- signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal hub_to_buf_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
-
- signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
- signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal buf_to_hub_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
-
- signal HUB_INIT_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_INIT_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal HUB_INIT_PACKET_NUM_OUT : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal HUB_INIT_READ_IN : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_INIT_DATAREADY_IN : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_INIT_DATA_IN : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal HUB_INIT_PACKET_NUM_IN : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal HUB_INIT_READ_OUT : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_REPLY_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_REPLY_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal HUB_REPLY_PACKET_NUM_OUT : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal HUB_REPLY_READ_IN : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_REPLY_DATAREADY_IN : std_logic_vector (total_point_num-1 downto 0);
- signal HUB_REPLY_DATA_IN : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal HUB_REPLY_PACKET_NUM_IN : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal HUB_REPLY_READ_OUT : std_logic_vector (total_point_num-1 downto 0);
-
- signal HUB_STAT_ERRORBITS : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
- signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
- signal buf_STAT_POINTS_locked : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
- signal buf_STAT_DEBUG : std_logic_vector (31 downto 0);
- signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0);
- signal buf_MED_DATAREADY_OUT : std_logic_vector (MII_NUMBER-1 downto 0);
- signal buf_MED_PACKET_NUM_OUT : std_logic_vector(MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- signal buf_MED_DATA_OUT : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
-
- signal HUB_locked : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
-
-
- signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0) := (others => '0');
- signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0) := (others => '0');
- signal HC_DATAREADY_IN : std_logic;
- signal HC_READ_OUT : std_logic;
- signal HC_SHORT_TRANSFER_IN : std_logic;
- signal HC_DTYPE_IN : std_logic_vector (3 downto 0);
- signal HC_ERROR_PATTERN_IN : std_logic_vector (31 downto 0);
- signal HC_SEND_IN : std_logic;
- signal HC_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal HC_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH-1 downto 0);
- signal HC_TYP_OUT : std_logic_vector (2 downto 0);
- signal HC_DATAREADY_OUT : std_logic;
- signal HC_READ_IN : std_logic;
- signal HC_RUN_OUT : std_logic;
- signal HC_SEQNR_OUT : std_logic_vector (7 downto 0);
- signal HC_STAT_REGS : std_logic_vector (64*32-1 downto 0) := (others => '0');
- signal HUB_SCTRL_ERROR : std_logic_vector (MII_NUMBER-1 downto 0);
- signal STAT_REG_STROBE : std_logic_vector (2**6-1 downto 0);
- signal reg_STROBES : std_logic_vector (2**6-1 downto 0);
- signal CTRL_REG_STROBE : std_logic_vector (2**4-1 downto 0);
- signal HC_CTRL_REGS : std_logic_vector (2**4*32-1 downto 0);
- signal HC_COMMON_STAT_REGS : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal HC_COMMON_CTRL_REGS : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal HC_COMMON_STAT_REG_STROBE : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal HC_COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal buf_HC_STAT_REGS : std_logic_vector (64*32-1 downto 0);
- signal HC_STAT_ack_waiting : std_logic_vector(127 downto 0) := (others => '0');
- signal HUB_CTRL_LOCAL_NETWORK_RESET : std_logic_vector(MII_NUMBER-1 downto 0);
- signal ctrl_local_net_reset_changed : std_logic_vector(3 downto 0);
-
- signal HUB_MED_CONNECTED : std_logic_vector (31 downto 0);
- signal HUB_CTRL_final_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
- signal HUB_CTRL_activepoints : std_logic_vector (2**(c_MUX_WIDTH-1)*32-1 downto 0);
- signal HUB_CTRL_media_interfaces_off: std_logic_vector (31 downto 0);
- signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (31 downto 0);
- signal HUB_ADDRESS : std_logic_vector (15 downto 0);
- signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0);
- signal HUB_ERROR_BITS : std_logic_vector (16*32-1 downto 0);
- signal buf_HUB_ALL_ERROR_BITS : std_logic_vector ((16*2**(c_MUX_WIDTH-1))*32-1 downto 0);
-
- signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
- signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
- signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
- signal IOBUF_STAT_DATA_COUNTER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
-
- signal resync : std_logic_vector(MII_NUMBER-1 downto 0);
- signal reset_i : std_logic;
- signal reset_i_mux_io : std_logic_vector((MII_NUMBER*2**(c_MUX_WIDTH-1))-1 downto 0);
-
-
- signal combined_resync : std_logic;
- signal IDRAM_DATA_IN, IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
- signal IDRAM_WR_IN : std_logic;
- signal IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
- signal TEMP_OUT : std_logic_vector(11 downto 0);
- signal ONEWIRE_DATA : std_logic_vector(15 downto 0);
- signal ONEWIRE_ADDR : std_logic_vector(2 downto 0);
- signal ONEWIRE_WRITE : std_logic;
-
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal timer_ms_tick : std_logic;
- signal timer_us_tick : std_logic;
- signal stat_ipu_fsm : std_logic_vector(31 downto 0);
-
- signal DAT_ADDR_OUT : std_logic_vector(16-1 downto 0) := (others => '0');
- signal DAT_READ_ENABLE_OUT : std_logic;
- signal DAT_WRITE_ENABLE_OUT : std_logic;
- signal DAT_DATA_OUT : std_logic_vector(32-1 downto 0) := (others => '0');
- signal DAT_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
- signal DAT_DATAREADY_IN : std_logic := '0';
- signal DAT_NO_MORE_DATA_IN : std_logic := '0';
- signal DAT_WRITE_ACK_IN : std_logic := '0';
- signal DAT_UNKNOWN_ADDR_IN : std_logic := '0';
- signal DAT_TIMEOUT_OUT : std_logic;
-
- signal STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0);
- signal last_STAT_TIMEOUT : std_logic_vector(4*32-1 downto 0);
-
- signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0);
- signal local_reset_med : std_logic_vector(MII_NUMBER-1 downto 0);
- signal network_reset_counter : std_logic_vector(11 downto 0) := (others => '0');
-
- signal stream_port_connected : std_logic;
-
- signal stat_packets_addr : std_logic_vector(4 downto 0);
- signal stat_packets_read : std_logic;
- signal stat_packets_write : std_logic;
- signal stat_packets_data : std_logic_vector(31 downto 0);
- signal stat_packets_ready : std_logic;
- signal stat_packets_unknown : std_logic;
- signal stat_packets_ack : std_logic;
- signal stat_packets_all : std_logic_vector(32*32-1 downto 0);
-
- signal stat_errorbits_addr : std_logic_vector(3 downto 0);
- signal stat_errorbits_read : std_logic;
- signal stat_errorbits_write : std_logic;
- signal stat_errorbits_data : std_logic_vector(31 downto 0);
- signal stat_errorbits_ready : std_logic;
- signal stat_errorbits_unknown : std_logic;
-
- signal stat_busycntincl_addr : std_logic_vector(3 downto 0);
- signal stat_busycntincl_read : std_logic;
- signal stat_busycntincl_write : std_logic;
- signal stat_busycntincl_data : std_logic_vector(31 downto 0);
- signal stat_busycntincl_ready : std_logic;
- signal stat_busycntincl_ack : std_logic;
- signal stat_busycntincl_unknown : std_logic;
-
- signal stat_busycntexcl_addr : std_logic_vector(3 downto 0);
- signal stat_busycntexcl_read : std_logic;
- signal stat_busycntexcl_write : std_logic;
- signal stat_busycntexcl_data : std_logic_vector(31 downto 0);
- signal stat_busycntexcl_ready : std_logic;
- signal stat_busycntexcl_ack : std_logic;
- signal stat_busycntexcl_unknown : std_logic;
-
- signal stat_globaltime_read : std_logic;
- signal stat_globaltime_write : std_logic;
- signal last_stat_globaltime_read : std_logic;
- signal last_stat_globaltime_write: std_logic;
-
- signal iobuf_ctrl_stat : std_logic_vector(63 downto 0);
- signal iobuf_reset_ipu_counter : std_logic;
- signal iobuf_reset_sctrl_counter : std_logic;
-
- type tv_t is array (2**(c_MUX_WIDTH-1)-1 downto 0) of std_logic_vector(15 downto 0);
- signal current_timeout_value : tv_t := (others => (others => '0'));
- signal hub_level : std_logic_vector(7 downto 0);
-
- type cnt_t is array (MII_NUMBER+2 downto 0) of unsigned(31 downto 0);
- signal busy_counter_excl : cnt_t := (others => (others => '0'));
- signal busy_counter_incl : cnt_t := (others => (others => '0'));
- signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER+2 downto 0);
- signal reg_excl_enable : std_logic_vector(MII_NUMBER+2 downto 0);
- signal delay1_media_reset_me : std_logic_vector(MII_NUMBER-1 downto 0);
- signal delay2_media_reset_me : std_logic_vector(MII_NUMBER-1 downto 0);
-
- signal mii_error : std_logic_vector(31 downto 0);
-
- signal iobuf_stat_init_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal iobuf_stat_reply_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
-
- signal led_counter : unsigned(9 downto 0) := (others => '0');
- signal hub_led_i : std_logic_vector(MII_NUMBER-1 downto 0);
- signal hub_show_port : std_logic_vector(MII_NUMBER-1 downto 0);
-
- signal lsm_addr : std_logic_vector(3 downto 0);
- signal lsm_read : std_logic;
- signal lsm_write : std_logic;
- signal lsm_data : std_logic_vector(31 downto 0);
- signal next_lsm_data : std_logic_vector(31 downto 0);
- signal last_lsm_read : std_logic;
- signal next_last_lsm_read : std_logic;
-
- signal hub_ctrl_disabled_ports : std_logic_vector(31 downto 0);
- signal buf_HUB_MISMATCH_PATTERN : std_logic_vector(31 downto 0);
-
- type counter8b_t is array (0 to 15) of unsigned(7 downto 0);
- signal received_retransmit_requests : counter8b_t := (others => (others => '0'));
- signal sent_retransmit_requests : counter8b_t := (others => (others => '0'));
- signal received_resets : counter8b_t := (others => (others => '0'));
- signal make_trbnet_reset, last_make_trbnet_reset : std_logic_vector(MII_NUMBER-1 downto 0);
-
- signal dummy : std_logic_vector(270 downto 0);
- signal tmp_buf_to_hub_REPLY_DATA_ctrl : std_logic_vector(15 downto 0);
-
-
- signal buf_apl_to_cri_data : std_logic_vector(MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- signal buf_apl_to_cri_packnum : std_logic_vector(MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- signal buf_apl_to_cri_dataready : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_cri_to_apl_read : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_apl_to_cri_short_transfer : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_apl_to_cri_send : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_cri_to_apl_data : std_logic_vector(MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- signal buf_cri_to_apl_packnum : std_logic_vector(MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- signal buf_cri_to_apl_dataready : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_apl_to_cri_read : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_cri_to_apl_run : std_logic_vector(MII_NUMBER-1 downto 0);
- signal buf_cri_to_apl_seqnr : std_logic_vector(MII_NUMBER*8-1 downto 0);
- signal buf_cri_to_apl_type : std_logic_vector(MII_NUMBER*3-1 downto 0);
-
- signal bus_cri_data_rec_rx : ctrlbus_rx_array_t(0 to MII_NUMBER-1);
- signal bus_cri_data_rec_tx : ctrlbus_tx_array_t(0 to MII_NUMBER-1);
-
- type point_array_t is array (0 to 15) of unsigned(15 downto 0);
- signal dbg_cnt : point_array_t := (others => (others=> '0'));
-
-
- attribute syn_preserve : boolean;
- attribute syn_keep : boolean;
- attribute syn_preserve of m_DATA_IN : signal is true;
- attribute syn_keep of m_DATA_IN : signal is true;
- attribute syn_preserve of m_DATAREADY_IN : signal is true;
- attribute syn_keep of m_DATAREADY_IN : signal is true;
- attribute syn_preserve of m_PACKET_NUM_IN : signal is true;
- attribute syn_keep of m_PACKET_NUM_IN : signal is true;
-
- attribute syn_preserve of m_PACKET_NUM_OUT : signal is true;
- attribute syn_keep of m_PACKET_NUM_OUT : signal is true;
- attribute syn_preserve of m_DATA_OUT : signal is true;
- attribute syn_keep of m_DATA_OUT : signal is true;
- attribute syn_preserve of m_DATAREADY_OUT : signal is true;
- attribute syn_keep of m_DATAREADY_OUT : signal is true;
-
- attribute syn_preserve of m_READ_OUT : signal is true;
- attribute syn_keep of m_READ_OUT : signal is true;
- attribute syn_preserve of m_READ_IN : signal is true;
- attribute syn_keep of m_READ_IN : signal is true;
-
- attribute syn_keep of reset_i : signal is true;
-
- attribute syn_keep of reset_i_mux_io : signal is true;
- attribute syn_preserve of reset_i_mux_io : signal is true;
-
- attribute syn_hier : string;
- attribute syn_hier of trb_net16_cri_hub_base_arch : architecture is "firm";
-
-begin
-
-
----------------------------------------------------------------------
---Generate various reset signals
----------------------------------------------------------------------
- proc_SYNC_RESET : process(CLK)
- begin
- if rising_edge(CLK) then
- reset_i <= RESET;
- last_STAT_TIMEOUT <= STAT_TIMEOUT;
- end if;
- end process;
-
--- STAT_TIMEOUT
-
- gen_iobuf_noreset : if RESET_IOBUF_AT_TIMEOUT = c_NO generate
- gen_internal_reset : for i in 0 to MII_NUMBER-1 generate
- gen_int_reset_2 : for j in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- SYNC_RESET_MUX_IO : process(CLK)
- begin
- if rising_edge(CLK) then
- reset_i_mux_io(i+j*MII_NUMBER) <= MED_STAT_OP(i*16+14) or RESET;
- end if;
- end process;
- end generate;
- end generate;
- end generate;
-
- gen_iobuf_reset : if RESET_IOBUF_AT_TIMEOUT = c_YES generate
- gen_int_reset_3 : for i in 0 to MII_NUMBER-1 generate
- gen_int_reset_4 : for j in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- SYNC_RESET_MUX_IO : process begin
- wait until rising_edge(CLK);
- if j /= 2 then
- if HUB_locked(j) = '1' then
- reset_i_mux_io(i+j*MII_NUMBER) <= RESET or (STAT_TIMEOUT(j*32+i) and not last_STAT_TIMEOUT(j*32+i))
- or reset_i_mux_io(i+j*MII_NUMBER) or delay2_media_reset_me(i);
- else
- reset_i_mux_io(i+j*MII_NUMBER) <= MED_STAT_OP(i*16+14) or RESET;
- end if;
- else
- reset_i_mux_io(i+j*MII_NUMBER) <= (MED_STAT_OP(i*16+14) and (not or_all(HUB_locked) or reset_i_mux_io(i+j*MII_NUMBER)))
- or RESET;
- end if;
- end process;
- end generate;
- end generate;
- end generate;
-
-
---generate media resync
- gen_resync : for i in 0 to MII_NUMBER-1 generate
- resync(i) <= MED_STAT_OP(i*16+15) when MII_IS_UPLINK(i) = c_YES else '0';
- proc_SYNC_CTRL_OP : process(CLK)
- begin
- if rising_edge(CLK) then
- MED_CTRL_OP(7+i*16 downto i*16) <= (others => '0');
- MED_CTRL_OP(8+i*16) <= HC_COMMON_CTRL_REGS(64+27);
- MED_CTRL_OP(12+i*16 downto 9+i*16) <= (others => '0');
- MED_CTRL_OP(13+i*16) <= local_reset_med(i);
- MED_CTRL_OP(14+i*16) <= HUB_CTRL_media_interfaces_off(i);
- if MII_IS_UPLINK(i) = 0 then
- MED_CTRL_OP(15+i*16) <= combined_resync or local_network_reset(i);
- else
- MED_CTRL_OP(15+i*16) <= combined_resync;
- end if;
- end if;
- end process;
- end generate;
- combined_resync <= or_all(resync);
-
- gen_local_network_reset : process(CLK)
- begin
- if rising_edge(CLK) then
- if reset_i = '1' then
- local_network_reset <= (others => '0');
- local_reset_med <= (others => '0');
- network_reset_counter <= (others => '0');
- elsif ctrl_local_net_reset_changed(3) = '1' then
- local_network_reset <= HUB_CTRL_LOCAL_NETWORK_RESET;
- local_reset_med <= (others => '0');
- network_reset_counter <= x"001";
-
- elsif network_reset_counter(10) = '1' then
- network_reset_counter <= (others => '0');
- local_network_reset <= (others => '0');
- local_reset_med <= (others => '0');
- elsif and_all(network_reset_counter(9 downto 0)) = '1' then
- local_reset_med <= local_network_reset;
- local_network_reset <= (others => '0');
- end if;
- if network_reset_counter(9 downto 0) /= 0 then
- network_reset_counter <= network_reset_counter + 1;
- end if;
- end if;
- end process;
-
- gen_delayed_link_off : for i in 0 to MII_NUMBER-1 generate
- process begin
- wait until rising_edge(CLK);
- if timer_us_tick = '1' then
- delay1_media_reset_me(i) <= MED_STAT_OP(i*16+14);
- delay2_media_reset_me(i) <= delay1_media_reset_me(i);
- end if;
- end process;
- end generate;
-
- gen_local_net_reset_ctrl_reg : process begin
- wait until rising_edge(CLK);
- ctrl_local_net_reset_changed(0) <= (CTRL_REG_STROBE(6) or ctrl_local_net_reset_changed(0))
- and not ctrl_local_net_reset_changed(1);
- if timer_us_tick = '1' then
- ctrl_local_net_reset_changed(3 downto 1) <= ctrl_local_net_reset_changed(2 downto 0);
- end if;
- end process;
-
----------------------------------------------------------------------
---Multiplexer
----------------------------------------------------------------------
-
- gen_muxes: for i in 0 to MII_NUMBER-1 generate
- constant t : integer := 0;
- begin
- MPLEX: trb_net16_io_multiplexer
- generic map(
- USE_INPUT_SBUF => (c_NO,c_NO,
- c_NO, c_YES,--MII_IS_DOWNLINK(i),MII_IS_UPLINK(i),
- c_NO, c_NO,
- MII_IS_DOWNLINK(i),MII_IS_UPLINK(i))
- )
- port map (
- CLK => CLK,
- RESET => reset_i_mux_io(i+2*MII_NUMBER), --use reset from ch.2 here (not influenced by timeouts)
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MED_DATAREADY_IN(i),
- MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- MED_READ_OUT => MED_READ_OUT(i),
- MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT(i),
- MED_DATA_OUT => buf_MED_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- MED_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- MED_READ_IN => MED_READ_IN(i),
- INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)),
- INT_DATA_OUT => m_DATA_IN((i+1)*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH*2**(c_MUX_WIDTH-1)),
- INT_PACKET_NUM_OUT => m_PACKET_NUM_IN((i+1)*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH*2**(c_MUX_WIDTH-1)),
- INT_READ_IN => m_READ_OUT((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)),
- INT_DATAREADY_IN => m_DATAREADY_OUT((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH),
- INT_DATA_IN => m_DATA_OUT((i+1)*c_DATA_WIDTH*2**c_MUX_WIDTH-1 downto i*c_DATA_WIDTH*2**c_MUX_WIDTH),
- INT_PACKET_NUM_IN => m_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH*2**c_MUX_WIDTH-1 downto i*c_NUM_WIDTH*2**c_MUX_WIDTH),
- INT_READ_OUT => m_READ_IN((i+1)*2**c_MUX_WIDTH-1 downto i*2**c_MUX_WIDTH),
- CTRL => MPLEX_CTRL((i+1)*32-1 downto i*32),
- STAT => MPLEX_STAT((i+1)*32-1 downto i*32)
- );
- m_ERROR_IN((i+1)*3-1 downto i*3) <=MED_STAT_OP(i*16+2 downto i*16);
- end generate;
-MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT;
-MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT;
-MED_DATA_OUT <= buf_MED_DATA_OUT;
-
-
----------------------------------------------------------------------
---IOBufs
----------------------------------------------------------------------
- gen_bufs : for j in 0 to MII_NUMBER-1 generate
- gen_iobufs: for k in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- constant i : integer := j*2**(c_MUX_WIDTH-1)+k;
- begin
- -- data channel
- gen_iobuf: if (k = c_DATA_CHANNEL) generate --and ( j < MII_NUMBER-1)
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
- USE_CHECKSUM => USE_CHECKSUM(k),
- SBUF_VERSION => 0,
- SBUF_VERSION_OBUF => 6,
- OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(k),
- USE_VENDOR_CORES => USE_VENDOR_CORES,
- INIT_CAN_RECEIVE_DATA => 1,
- REPLY_CAN_RECEIVE_DATA=> 0,
- INIT_CAN_SEND_DATA => 0,
- REPLY_CAN_SEND_DATA => 1
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => reset_i_mux_io(j+k*MII_NUMBER),
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => m_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1),
- MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- MED_READ_OUT => m_READ_OUT(i),
- MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3),
-
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_hub_INIT_READ(i),
- INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i),
- INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i),
- INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i),
- -- Status and control port
- STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
- STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32),
- STAT_DATA_COUNTER => IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32),
- CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
- CTRL_OBUF_settings(15 downto 0) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
- CTRL_OBUF_settings(31 downto 16) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
- STAT_INIT_OBUF_DEBUG => iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32),
- STAT_REPLY_OBUF_DEBUG => iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32),
- TIMER_TICKS_IN(0) => timer_us_tick,
- TIMER_TICKS_IN(1) => timer_ms_tick,
- CTRL_STAT => iobuf_ctrl_stat(k*16+15 downto k*16)
- );
- end generate;
-
- -- slow control channel
- gen_iobuf: if k = c_SLOW_CTRL_CHANNEL generate
- IOBUF: trb_net16_iobuf
- generic map (
- IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
- USE_CHECKSUM => USE_CHECKSUM(k),
- SBUF_VERSION => 0,
- SBUF_VERSION_OBUF => 6,
- OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(k),
- USE_VENDOR_CORES => USE_VENDOR_CORES,
- INIT_CAN_RECEIVE_DATA => MII_IS_UPLINK(j),
- REPLY_CAN_RECEIVE_DATA=> MII_IS_DOWNLINK(j),
- INIT_CAN_SEND_DATA => MII_IS_DOWNLINK(j),
- REPLY_CAN_SEND_DATA => MII_IS_UPLINK(j)
- )
- port map (
- -- Misc
- CLK => CLK ,
- RESET => reset_i_mux_io(j+k*MII_NUMBER),
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => m_DATAREADY_OUT(i*2),
- MED_INIT_DATA_OUT => m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
- MED_INIT_PACKET_NUM_OUT => m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
- MED_INIT_READ_IN => m_READ_IN(i*2),
- MED_REPLY_DATAREADY_OUT => m_DATAREADY_OUT(i*2+1),
- MED_REPLY_DATA_OUT => m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
- MED_REPLY_PACKET_NUM_OUT=> m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
- MED_REPLY_READ_IN => m_READ_IN(i*2+1),
- MED_DATAREADY_IN => m_DATAREADY_IN(i),
- MED_DATA_IN => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- MED_PACKET_NUM_IN => m_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- MED_READ_OUT => m_READ_OUT(i),
- MED_ERROR_IN => m_ERROR_IN((j+1)*3-1 downto j*3),
-
- -- Internal direction port
- INT_INIT_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),
- INT_INIT_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_OUT=> buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_IN => buf_to_hub_INIT_READ(i),
- INT_INIT_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),
- INT_INIT_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_INIT_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_INIT_READ_OUT => hub_to_buf_INIT_READ(i),
- INT_REPLY_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
- INT_REPLY_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_OUT=> buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_IN => buf_to_hub_REPLY_READ(i),
- INT_REPLY_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i),
- INT_REPLY_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_REPLY_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_REPLY_READ_OUT => hub_to_buf_REPLY_READ(i),
- -- Status and control port
- STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32),
- STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32),
- STAT_DATA_COUNTER => IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32),
- CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32),
- CTRL_OBUF_settings(15 downto 0) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
- CTRL_OBUF_settings(31 downto 16) => (others => '0'), -- current_timeout_value(k),--HUB_CTRL_TIMEOUT_TIME(k*4+19 downto k*4+16),
- STAT_INIT_OBUF_DEBUG => iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32),
- STAT_REPLY_OBUF_DEBUG => iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32),
- TIMER_TICKS_IN(0) => timer_us_tick,
- TIMER_TICKS_IN(1) => timer_ms_tick,
- CTRL_STAT => iobuf_ctrl_stat(k*16+15 downto k*16)
- );
- end generate;
-
- gen_trmbuf: if (k = 0) or (k = 2) generate -- or ((k = c_DATA_CHANNEL) and ( j = MII_NUMBER-1)) : terminate trigger channel and chnl 2 and data uplink channel
- hub_to_buf_init_read(i) <= '0';
- buf_to_hub_init_dataready(i) <= '0';
- buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
- buf_to_hub_init_packet_num((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
- hub_to_buf_reply_read(i) <= '0';
- buf_to_hub_reply_dataready(i) <= '0';
- buf_to_hub_reply_data((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
- buf_to_hub_reply_packet_num((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
- iobuf_stat_gen((i+1)*32-1 downto i*32) <= (others => '0');
- IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
- IOBUF_CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0');
- iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0');
- iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0');
- IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32) <= (others => '0');
-
- m_DATAREADY_OUT(i*2) <= '0';
- m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH) <= (others => '0');
- m_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH) <= (others => '0');
- m_DATAREADY_OUT(i*2+1) <= '0';
- m_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH) <= (others => '0');
- m_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH) <= (others => '0');
- m_READ_OUT(i) <= '1';
-
- end generate;
- end generate;
- end generate;
-
-
----------------------------------------------------------------------
---API for control interface
----------------------------------------------------------------------
- gen_ctrl_api : if 1 = 1 generate --just a dummy now
- constant i : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER;
- begin
- CTRL_API : trb_net16_api_base
- generic map(
- API_TYPE => 0,
- FIFO_TO_INT_DEPTH => HUB_CTRL_DEPTH,
- FIFO_TO_APL_DEPTH => HUB_CTRL_DEPTH,
- ADDRESS_MASK => HUB_CTRL_ADDRESS_MASK,
- BROADCAST_BITMASK => HUB_CTRL_BROADCAST_BITMASK,
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => CLK_EN,
- -- APL Transmitter port
- APL_DATA_IN => HC_DATA_IN(c_DATA_WIDTH-1 downto 0),
- APL_PACKET_NUM_IN => HC_PACKET_NUM_IN(c_NUM_WIDTH-1 downto 0),
- APL_DATAREADY_IN => HC_DATAREADY_IN,
- APL_READ_OUT => HC_READ_OUT,
- APL_SHORT_TRANSFER_IN => HC_SHORT_TRANSFER_IN,
- APL_DTYPE_IN => HC_DTYPE_IN(3 downto 0),
- APL_ERROR_PATTERN_IN => HC_ERROR_PATTERN_IN(31 downto 0),
- APL_SEND_IN => HC_SEND_IN,
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => HC_DATA_OUT(c_DATA_WIDTH-1 downto 0),
- APL_PACKET_NUM_OUT => HC_PACKET_NUM_OUT(c_NUM_WIDTH-1 downto 0),
- APL_TYP_OUT => HC_TYP_OUT(2 downto 0),
- APL_DATAREADY_OUT => HC_DATAREADY_OUT,
- APL_READ_IN => HC_READ_IN,
- -- APL Control port
- APL_RUN_OUT => HC_RUN_OUT,
- APL_MY_ADDRESS_IN => HUB_ADDRESS,
- APL_SEQNR_OUT => HC_SEQNR_OUT(7 downto 0),
- APL_LENGTH_IN => (others => '1'),
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => tmp_buf_to_hub_REPLY_DATA_ctrl,
- INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_IN => buf_to_hub_REPLY_READ(i),
- INT_MASTER_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i),
- INT_MASTER_DATA_IN => hub_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => hub_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => hub_to_buf_REPLY_READ(i),
- INT_SLAVE_DATAREADY_OUT => buf_to_hub_INIT_DATAREADY(i),
- INT_SLAVE_DATA_OUT => buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => buf_to_hub_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => buf_to_hub_INIT_READ(i),
- INT_SLAVE_DATAREADY_IN => hub_to_buf_INIT_DATAREADY(i),
- INT_SLAVE_DATA_IN => hub_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN => hub_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => hub_to_buf_INIT_READ(i),
- CTRL_SEQNR_RESET => HC_COMMON_CTRL_REGS(10),
- -- Status and control port
- STAT_FIFO_TO_INT => open,
- STAT_FIFO_TO_APL => open
- );
-
---Workaround to get channel number right in local hub in pcie bridge
- PROC_CORRECT_CHANNEL : process(tmp_buf_to_hub_REPLY_DATA_ctrl, buf_to_hub_REPLY_PACKET_NUM)
- begin
- if buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
- buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= tmp_buf_to_hub_REPLY_DATA_ctrl or x"0038";
- else
- buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= tmp_buf_to_hub_REPLY_DATA_ctrl;
- end if;
- end process;
-
-end generate;
-
-
----------------------------------------------------------------------
---Connection for additional internal interfaces
----------------------------------------------------------------------
- gen_int : if INT_NUMBER /= 0 generate
- gen_int1 : for i in 0 to INT_NUMBER-1 generate
- constant j : integer := i + 2**(c_MUX_WIDTH-1)*MII_NUMBER+1;
- begin
- buf_to_hub_REPLY_DATAREADY(j) <= INT_REPLY_DATAREADY_IN(i);
- buf_to_hub_REPLY_DATA((j+1)*16-1 downto j*16) <= INT_REPLY_DATA_IN((i+1)*16-1 downto i*16);
- buf_to_hub_REPLY_PACKET_NUM((j+1)*3-1 downto j*3) <= INT_REPLY_PACKET_NUM_IN((i+1)*3-1 downto i*3);
- INT_REPLY_READ_OUT(i) <= buf_to_hub_REPLY_READ(j);
-
- INT_REPLY_DATAREADY_OUT(i) <= hub_to_buf_REPLY_DATAREADY(j);
- INT_REPLY_DATA_OUT((i+1)*16-1 downto i*16) <= hub_to_buf_REPLY_DATA((j+1)*16-1 downto j*16);
- INT_REPLY_PACKET_NUM_OUT((i+1)*3-1 downto i*3) <= hub_to_buf_REPLY_PACKET_NUM((j+1)*3-1 downto j*3);
- hub_to_buf_REPLY_READ(j) <= INT_REPLY_READ_IN(i);
-
- buf_to_hub_INIT_DATAREADY(j) <= INT_INIT_DATAREADY_IN(i);
- buf_to_hub_INIT_DATA((j+1)*16-1 downto j*16) <= INT_INIT_DATA_IN((i+1)*16-1 downto i*16);
- buf_to_hub_INIT_PACKET_NUM((j+1)*3-1 downto j*3) <= INT_INIT_PACKET_NUM_IN((i+1)*3-1 downto i*3);
- INT_INIT_READ_OUT(i) <= buf_to_hub_INIT_READ(j);
-
- INT_INIT_DATAREADY_OUT(i) <= hub_to_buf_INIT_DATAREADY(j);
- INT_INIT_DATA_OUT((i+1)*16-1 downto i*16) <= hub_to_buf_INIT_DATA((j+1)*16-1 downto j*16);
- INT_INIT_PACKET_NUM_OUT((i+1)*3-1 downto i*3) <= hub_to_buf_INIT_PACKET_NUM((j+1)*3-1 downto j*3);
- hub_to_buf_INIT_READ(j) <= INT_INIT_READ_IN(i);
- end generate;
- end generate;
- INT_INIT_DATAREADY_OUT(INT_NUMBER) <= '0';
- INT_INIT_DATA_OUT(INT_NUMBER*c_DATA_WIDTH) <= '0';
- INT_INIT_PACKET_NUM_OUT(INT_NUMBER*c_NUM_WIDTH) <= '0';
- INT_INIT_READ_OUT(INT_NUMBER) <= '0';
- INT_REPLY_DATAREADY_OUT(INT_NUMBER) <= '0';
- INT_REPLY_DATA_OUT(INT_NUMBER*c_DATA_WIDTH) <= '0';
- INT_REPLY_PACKET_NUM_OUT(INT_NUMBER*c_NUM_WIDTH) <= '0';
- INT_REPLY_READ_OUT(INT_NUMBER) <= '0';
-
-
----------------------------------------------------------------------
---Connections between IOBuf and Hublogic
----------------------------------------------------------------------
- gen_rearrange : for CHANNEL in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- constant int_num : integer := calc_special_number(CHANNEL, INT_NUMBER, INT_CHANNELS);
- constant first_point_num : integer := calc_first_point_number(MII_NUMBER, CHANNEL, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS);
- constant is_ctrl_channel : integer := calc_is_ctrl_channel(CHANNEL, HUB_CTRL_CHANNELNUM);
- begin
- gen_hublogicsignals1 : for mii in 0 to MII_NUMBER-1 generate
- constant buf_to_hub_num : integer := mii*2**(c_MUX_WIDTH-1)+CHANNEL;
- constant hublogic_num : integer := first_point_num + mii;
- begin
- HUB_INIT_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num);
- HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_INIT_READ(buf_to_hub_num)
- <= HUB_INIT_READ_OUT(hublogic_num);
-
- hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
- <= HUB_INIT_DATAREADY_OUT(hublogic_num);
- hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_INIT_READ_IN (hublogic_num)
- <= hub_to_buf_INIT_READ(buf_to_hub_num);
-
- HUB_REPLY_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
- HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_REPLY_READ(buf_to_hub_num)
- <= HUB_REPLY_READ_OUT(hublogic_num);
-
- hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
- <= HUB_REPLY_DATAREADY_OUT(hublogic_num);
- hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_REPLY_READ_IN (hublogic_num)
- <= hub_to_buf_REPLY_READ(buf_to_hub_num);
- end generate;
- gen_hublogicsignal_ctrl: if is_ctrl_channel = 1 generate
- constant hublogic_num : integer := first_point_num + MII_NUMBER; --!num of mii not num of channels!
- constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER;
- begin
- HUB_INIT_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num);
- HUB_INIT_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_INIT_READ(buf_to_hub_num)
- <= HUB_INIT_READ_OUT(hublogic_num);
-
- hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
- <= HUB_INIT_DATAREADY_OUT(hublogic_num);
- hub_to_buf_INIT_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_INIT_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_INIT_READ_IN (hublogic_num)
- <= hub_to_buf_INIT_READ(buf_to_hub_num);
-
- HUB_REPLY_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
- HUB_REPLY_DATA_IN ((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH)
- <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH);
- HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH)
- <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH);
- buf_to_hub_REPLY_READ(buf_to_hub_num)
- <= HUB_REPLY_READ_OUT(hublogic_num);
-
- hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
- <= HUB_REPLY_DATAREADY_OUT(hublogic_num);
- hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*c_DATA_WIDTH-1 downto buf_to_hub_num*c_DATA_WIDTH)
- <= HUB_REPLY_DATA_OUT((hublogic_num+1)*c_DATA_WIDTH-1 downto hublogic_num*c_DATA_WIDTH);
- hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*c_NUM_WIDTH-1 downto buf_to_hub_num*c_NUM_WIDTH)
- <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*c_NUM_WIDTH-1 downto hublogic_num*c_NUM_WIDTH);
- HUB_REPLY_READ_IN (hublogic_num)
- <= hub_to_buf_REPLY_READ(buf_to_hub_num);
- end generate;
- g5: if int_num /= 0 generate
- gen_hublogicsignals2 : for int in 0 to INT_NUMBER-1 generate
- constant hublogic_num : integer := first_point_num + MII_NUMBER + is_ctrl_channel + calc_special_number(CHANNEL, int, INT_CHANNELS);
- constant buf_to_hub_num : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER + 1 + int;
- --calc_special_number(CHANNEL, api, API_CHANNELS)
- begin
- h1: if INT_CHANNELS(int) = CHANNEL generate
- HUB_INIT_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_INIT_DATAREADY(buf_to_hub_num);
- HUB_INIT_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16)
- <= buf_to_hub_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16);
- HUB_INIT_PACKET_NUM_IN ((hublogic_num+1)*3-1 downto hublogic_num*3)
- <= buf_to_hub_INIT_PACKET_NUM((buf_to_hub_num+1)*3-1 downto buf_to_hub_num*3);
- buf_to_hub_INIT_READ(buf_to_hub_num)
- <= HUB_INIT_READ_OUT(hublogic_num);
-
- hub_to_buf_INIT_DATAREADY(buf_to_hub_num)
- <= HUB_INIT_DATAREADY_OUT(hublogic_num);
- hub_to_buf_INIT_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16)
- <= HUB_INIT_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16);
- hub_to_buf_INIT_PACKET_NUM((buf_to_hub_num+1)*3-1 downto buf_to_hub_num*3)
- <= HUB_INIT_PACKET_NUM_OUT((hublogic_num+1)*3-1 downto hublogic_num*3);
- HUB_INIT_READ_IN (hublogic_num)
- <= hub_to_buf_INIT_READ(buf_to_hub_num);
-
- HUB_REPLY_DATAREADY_IN (hublogic_num)
- <= buf_to_hub_REPLY_DATAREADY(buf_to_hub_num);
- HUB_REPLY_DATA_IN ((hublogic_num+1)*16-1 downto hublogic_num*16)
- <= buf_to_hub_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16);
- HUB_REPLY_PACKET_NUM_IN ((hublogic_num+1)*3-1 downto hublogic_num*3)
- <= buf_to_hub_REPLY_PACKET_NUM((buf_to_hub_num+1)*3-1 downto buf_to_hub_num*3);
- buf_to_hub_REPLY_READ(buf_to_hub_num)
- <= HUB_REPLY_READ_OUT(hublogic_num);
-
- hub_to_buf_REPLY_DATAREADY(buf_to_hub_num)
- <= HUB_REPLY_DATAREADY_OUT(hublogic_num);
- hub_to_buf_REPLY_DATA((buf_to_hub_num+1)*16-1 downto buf_to_hub_num*16)
- <= HUB_REPLY_DATA_OUT((hublogic_num+1)*16-1 downto hublogic_num*16);
- hub_to_buf_REPLY_PACKET_NUM((buf_to_hub_num+1)*3-1 downto buf_to_hub_num*3)
- <= HUB_REPLY_PACKET_NUM_OUT((hublogic_num+1)*3-1 downto hublogic_num*3);
- HUB_REPLY_READ_IN (hublogic_num)
- <= hub_to_buf_REPLY_READ(buf_to_hub_num);
- end generate;
- end generate;
- end generate;
- end generate;
-
-
-
----------------------------------------------------------------------
---Hub Logic
----------------------------------------------------------------------
- gen_hub_logic: for i in 0 to 2**(c_MUX_WIDTH-1)-1 generate
- constant point_num : integer := calc_point_number (MII_NUMBER, i, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS);
- constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS);
- constant next_point_num : integer := first_point_num + point_num;
- begin
- gen_logic : if (i = c_DATA_CHANNEL) or (i = c_SLOW_CTRL_CHANNEL) generate
- HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= HUB_CTRL_activepoints((i+1)*32-1 downto i*32) and HUB_MED_CONNECTED;
- gen_select_logic1 : if i = c_SLOW_CTRL_CHANNEL generate
- HUBLOGIC : trb_net16_hub_logic
- generic map (
- --media interfaces
- POINT_NUMBER => point_num,
- MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY
- )
- port map(
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => CLK_EN,
- INIT_DATAREADY_IN => HUB_INIT_DATAREADY_IN(next_point_num-1 downto first_point_num),
- INIT_DATA_IN => HUB_INIT_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
- INIT_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
- INIT_READ_OUT => HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num),
- INIT_DATAREADY_OUT => HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num),
- INIT_DATA_OUT => HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
- INIT_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
- INIT_READ_IN => HUB_INIT_READ_IN(next_point_num-1 downto first_point_num),
- REPLY_DATAREADY_IN => HUB_REPLY_DATAREADY_IN(next_point_num-1 downto first_point_num),
- REPLY_DATA_IN => HUB_REPLY_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
- REPLY_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
- REPLY_READ_OUT => HUB_REPLY_READ_OUT(next_point_num-1 downto first_point_num),
- REPLY_DATAREADY_OUT => HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num),
- REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
- REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
- REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
- STAT => buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16),
- STAT_locked => HUB_locked(i),
- STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
- STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
- STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32),
- STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16),
- CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
- CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
- CTRL_DISABLED_PORTS => hub_ctrl_disabled_ports,
- CTRL_TIMER_TICK(0) => timer_us_tick,
- CTRL_TIMER_TICK(1) => timer_ms_tick
- );
- end generate;
- gen_select_logic2 : if (i = c_DATA_CHANNEL) generate -- TODO: think about the last channel: data uplink to nowhere
- gen_data_chnl_api : for j in 0 to point_num-1 generate
- constant local_position : integer := first_point_num+j;
- begin
- --API for data channel
- DATA_CHANNEL_API: trb_net16_api_base
- generic map (
- API_TYPE => c_API_PASSIVE,
- FIFO_TO_INT_DEPTH => 6,
- FIFO_TO_APL_DEPTH => 1,
- FORCE_REPLY => 1,
- SBUF_VERSION => 0,
- USE_VENDOR_CORES => c_YES,
- SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS=> c_NO
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => '1',
- -- APL Transmitter port
- APL_DATA_IN => (others => '0'),--buf_apl_to_cri_data((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => (others => '0'),--buf_apl_to_cri_packnum((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_DATAREADY_IN => '0',--buf_apl_to_cri_dataready(j), -- almostfullflag ; daten in fifo von 8 auf 16 bit packen
- APL_READ_OUT => open,--buf_cri_to_apl_read(j),
- APL_SHORT_TRANSFER_IN => buf_apl_to_cri_short_transfer(j),
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
- APL_SEND_IN => buf_apl_to_cri_send(j), -- 1 till end of Datastream
- APL_TARGET_ADDRESS_IN => (others => '0'),
- -- Receiver port
- APL_DATA_OUT => buf_cri_to_apl_data((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_OUT => buf_cri_to_apl_packnum((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_TYP_OUT => buf_cri_to_apl_type((j+1)*3-1 downto j*3),
- APL_DATAREADY_OUT => buf_cri_to_apl_dataready(j),
- APL_READ_IN => buf_apl_to_cri_read(j),
- -- APL Control port
- APL_RUN_OUT => buf_cri_to_apl_run(j),
- APL_MY_ADDRESS_IN => HUB_ADDRESS,
- APL_SEQNR_OUT => buf_cri_to_apl_seqnr((j+1)*8-1 downto j*8),
- APL_LENGTH_IN => (others => '0'),
- APL_FIFO_COUNT_OUT => open,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => HUB_REPLY_DATAREADY_OUT(local_position),
- INT_MASTER_DATA_OUT => HUB_REPLY_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_OUT=> HUB_REPLY_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_MASTER_READ_IN => HUB_REPLY_READ_IN(local_position),
-
- INT_MASTER_DATAREADY_IN => HUB_REPLY_DATAREADY_IN(local_position),
- INT_MASTER_DATA_IN => HUB_REPLY_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_MASTER_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_MASTER_READ_OUT => HUB_REPLY_READ_OUT(local_position),
-
- INT_SLAVE_DATAREADY_OUT => HUB_INIT_DATAREADY_OUT(local_position),
- INT_SLAVE_DATA_OUT => HUB_INIT_DATA_OUT((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_SLAVE_READ_IN => HUB_INIT_READ_IN(local_position),
-
- INT_SLAVE_DATAREADY_IN => HUB_INIT_DATAREADY_IN(local_position),
- INT_SLAVE_DATA_IN => HUB_INIT_DATA_IN((local_position+1)*c_DATA_WIDTH-1 downto local_position*c_DATA_WIDTH),
- INT_SLAVE_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN((local_position+1)*c_NUM_WIDTH-1 downto local_position*c_NUM_WIDTH),
- INT_SLAVE_READ_OUT => HUB_INIT_READ_OUT(local_position),
-
- -- Status and control port
- CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
- STAT_FIFO_TO_INT => open,
- STAT_FIFO_TO_APL => open
- );
-
-
- DBG_INPUT2API : process (CLK)
- begin
- if rising_edge(CLK) then
- if reset_i = '1' then
- dbg_cnt(j) <= 0;
- else
- if HUB_INIT_DATAREADY_IN(local_position) = '1' or HUB_REPLY_DATAREADY_IN(local_position) = '1' then
- dbg_cnt(j) <= dbg_cnt(j) + 1;
- end if;
- end if;
- end if;
- end process;
-
-
- CRI_DATA_RECEIVER: entity work.cri_data_receiver
- port map (
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => '1',
-
- APL_SHORT_TRANSFER_OUT => buf_apl_to_cri_short_transfer(j),
- APL_SEND_OUT => buf_apl_to_cri_send(j),
-
- APL_DATA_IN => buf_cri_to_apl_data((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
- APL_PACKET_NUM_IN => buf_cri_to_apl_packnum((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
- APL_TYP_IN => buf_cri_to_apl_type((j+1)*3-1 downto j*3),
- APL_DATAREADY_IN => buf_cri_to_apl_dataready(j),
- APL_READ_OUT => buf_apl_to_cri_read(j),
-
- APL_RUN_IN => buf_cri_to_apl_run(j),
-
- BUS_DBG_RX => bus_cri_data_rec_rx(j),
- BUS_DBG_TX => bus_cri_data_rec_tx(j),
-
- dbg_cnt_rdy => dbg_cnt(j)
- );
-
- end generate;
-
--- HUBLOGIC : trb_net16_hub_ipu_logic
--- generic map (
--- --media interfaces
--- POINT_NUMBER => point_num
--- )
--- port map(
--- CLK => CLK,
--- RESET => reset_i,
--- CLK_EN => CLK_EN,
--- INIT_DATAREADY_IN => HUB_INIT_DATAREADY_IN(next_point_num-1 downto first_point_num),
--- INIT_DATA_IN => ,
--- INIT_PACKET_NUM_IN => HUB_INIT_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
--- INIT_READ_OUT => HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num),
--- INIT_DATAREADY_OUT => HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num),
--- INIT_DATA_OUT => HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
--- INIT_PACKET_NUM_OUT => HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
--- INIT_READ_IN => HUB_INIT_READ_IN(next_point_num-1 downto first_point_num),
--- REPLY_DATAREADY_IN => HUB_REPLY_DATAREADY_IN(next_point_num-1 downto first_point_num),
--- REPLY_DATA_IN => HUB_REPLY_DATA_IN(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
--- REPLY_PACKET_NUM_IN => HUB_REPLY_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
--- REPLY_READ_OUT => HUB_REPLY_READ_OUT(next_point_num-1 downto first_point_num),
--- REPLY_DATAREADY_OUT => HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num),
--- REPLY_DATA_OUT => HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH),
--- REPLY_PACKET_NUM_OUT => HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH),
--- REPLY_READ_IN => HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num),
--- MY_ADDRESS_IN => HUB_ADDRESS,
--- STAT_DEBUG => HUBLOGIC_IPU_STAT_DEBUG(31 downto 0),
--- STAT_locked => HUB_locked(i),
--- STAT_POINTS_locked => buf_STAT_POINTS_locked((i+1)*32-1 downto i*32),
--- STAT_TIMEOUT => STAT_TIMEOUT((i+1)*32-1 downto i*32),
--- STAT_ERRORBITS => HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32),
--- STAT_ALL_ERRORBITS => buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16),
--- STAT_FSM => stat_ipu_fsm,
--- STAT_MISMATCH => buf_HUB_MISMATCH_PATTERN(31 downto 0),
--- CTRL_TIMEOUT_TIME => current_timeout_value(i),--HUB_CTRL_TIMEOUT_TIME(i*4+3 downto i*4),
--- CTRL_activepoints => HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32),
--- CTRL_DISABLED_PORTS => hub_ctrl_disabled_ports,
--- CTRL_TIMER_TICK(0) => timer_us_tick,
--- CTRL_TIMER_TICK(1) => timer_ms_tick
--- );
- buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
- end generate;
- end generate;
- gen_select_no_logic : if (i = c_TRG_LVL1_CHANNEL) or (i = c_UNUSED_CHANNEL) generate
- HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
- HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
- HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
- HUB_REPLY_READ_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
- HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
- HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
- HUB_INIT_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
- end generate;
- end generate;
-
- gen_unused_signals : for i in 0 to 2**(c_MUX_WIDTH-1)-2 generate
- begin
- buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
- buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
- HUB_locked(i) <= '0';
- HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
- HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32) <= (others => '0');
- hub_ctrl_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
- buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16) <= (others => '0');
- iobuf_stat_data_counter((i+1)*32-1 downto i*32) <= (others => '0');
- stat_timeout((i+1)*32-1 downto i*32) <= (others => '0');
- end generate;
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_CRI_DATA_REC_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
- generic map(
- PORT_NUMBER => 10,
- PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", 3 => x"0300", 4 => x"0400", 5 => x"0500", 6 => x"0600", 7 => x"0700",
- 8 => x"0800", 9 => x"0900", others => x"0000"),
- PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 8, 3 => 8, 4 => 8, 5 => 8, 6 => 8, 7 => 8,
- 8 => 8, 9 => 8, others => 0),
- PORT_MASK_ENABLE => 1
- )
- port map(
- CLK => CLK,
- RESET => reset_i,
-
- REGIO_RX => BUS_HUB_DBG_RX,
- REGIO_TX => BUS_HUB_DBG_TX,
-
- BUS_RX(0) => bus_cri_data_rec_rx(0), --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bus_cri_data_rec_rx(1),
- BUS_RX(2) => bus_cri_data_rec_rx(2),
- BUS_RX(3) => bus_cri_data_rec_rx(3),
- BUS_RX(4) => bus_cri_data_rec_rx(4),
- BUS_RX(5) => bus_cri_data_rec_rx(5),
- BUS_RX(6) => bus_cri_data_rec_rx(6),
- BUS_RX(7) => bus_cri_data_rec_rx(7),
- BUS_RX(8) => bus_cri_data_rec_rx(8),
- BUS_RX(9) => bus_cri_data_rec_rx(9),
-
- BUS_TX(0) => bus_cri_data_rec_tx(0),
- BUS_TX(1) => bus_cri_data_rec_tx(1),
- BUS_TX(2) => bus_cri_data_rec_tx(2),
- BUS_TX(3) => bus_cri_data_rec_tx(3),
- BUS_TX(4) => bus_cri_data_rec_tx(4),
- BUS_TX(5) => bus_cri_data_rec_tx(5),
- BUS_TX(6) => bus_cri_data_rec_tx(6),
- BUS_TX(7) => bus_cri_data_rec_tx(7),
- BUS_TX(8) => bus_cri_data_rec_tx(8),
- BUS_TX(9) => bus_cri_data_rec_tx(9),
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------
---Control RegIO
----------------------------------------------------------------------
- hub_control : trb_net16_regIO
- generic map(
- NUM_STAT_REGS => 6,
- NUM_CTRL_REGS => 4,
- INIT_CTRL_REGS => INIT_CTRL_REGS,
- USED_CTRL_REGS => (others => '1'),
- USED_CTRL_BITMASK => (others => '1'),
- USE_DAT_PORT => c_YES,
- INIT_ADDRESS => INIT_ADDRESS,
- INIT_UNIQUE_ID => INIT_UNIQUE_ID,
- INIT_ENDPOINT_ID => INIT_ENDPOINT_ID,
- COMPILE_TIME => COMPILE_TIME,
- INCLUDED_FEATURES => INCLUDED_FEATURES,
- HARDWARE_VERSION => HARDWARE_VERSION,
- CLOCK_FREQ => CLOCK_FREQUENCY
- )
- port map(
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => CLK_EN,
- -- Port to API
- API_DATA_OUT => HC_DATA_IN,
- API_PACKET_NUM_OUT => HC_PACKET_NUM_IN,
- API_DATAREADY_OUT => HC_DATAREADY_IN,
- API_READ_IN => HC_READ_OUT,
- API_SHORT_TRANSFER_OUT => HC_SHORT_TRANSFER_IN,
- API_DTYPE_OUT => HC_DTYPE_IN,
- API_ERROR_PATTERN_OUT => HC_ERROR_PATTERN_IN,
- API_SEND_OUT => HC_SEND_IN,
- -- Receiver port
- API_DATA_IN => HC_DATA_OUT,
- API_PACKET_NUM_IN => HC_PACKET_NUM_OUT,
- API_TYP_IN => HC_TYP_OUT,
- API_DATAREADY_IN => HC_DATAREADY_OUT,
- API_READ_OUT => HC_READ_IN,
- -- HC Control port
- API_RUN_IN => HC_RUN_OUT,
- API_SEQNR_IN => HC_SEQNR_OUT,
- MY_ADDRESS_OUT => HUB_ADDRESS,
- TRIGGER_MONITOR => '0',
- GLOBAL_TIME => global_time,
- LOCAL_TIME => local_time,
- TIME_SINCE_LAST_TRG => open,
- TIMER_MS_TICK => timer_ms_tick,
- TIMER_US_TICK => timer_us_tick,
- REGISTERS_IN => HC_STAT_REGS,
- REGISTERS_OUT => HC_CTRL_REGS,
- COMMON_STAT_REG_IN => HC_COMMON_STAT_REGS,
- COMMON_CTRL_REG_OUT => HC_COMMON_CTRL_REGS,
- COMMON_STAT_REG_STROBE => HC_COMMON_STAT_REG_STROBE,
- COMMON_CTRL_REG_STROBE => HC_COMMON_CTRL_REG_STROBE,
- STAT_REG_STROBE => STAT_REG_STROBE,
- CTRL_REG_STROBE => CTRL_REG_STROBE,
- --Port to write Unique ID
- IDRAM_DATA_IN => IDRAM_DATA_IN,
- IDRAM_DATA_OUT => open,
- IDRAM_ADDR_IN => IDRAM_ADDR_IN,
- IDRAM_WR_IN => IDRAM_WR_IN,
- DAT_ADDR_OUT => DAT_ADDR_OUT,
- DAT_READ_ENABLE_OUT => DAT_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_OUT=> DAT_WRITE_ENABLE_OUT,
- DAT_DATA_OUT => DAT_DATA_OUT,
- DAT_DATA_IN => DAT_DATA_IN,
- DAT_DATAREADY_IN => DAT_DATAREADY_IN,
- DAT_NO_MORE_DATA_IN => DAT_NO_MORE_DATA_IN,
- DAT_UNKNOWN_ADDR_IN => DAT_UNKNOWN_ADDR_IN,
- DAT_TIMEOUT_OUT => DAT_TIMEOUT_OUT,
- DAT_WRITE_ACK_IN => DAT_WRITE_ACK_IN
- );
-
-
---Fucking Modelsim wants it like this...
-THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 7,
- PORT_ADDRESSES => (0 => x"0000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", others => x"0000"),
- PORT_ADDR_MASK => (0 => 16, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, others => 0),
- PORT_MASK_ENABLE => 0
- )
- port map(
- CLK => CLK,
- RESET => reset_i,
-
- DAT_ADDR_IN => DAT_ADDR_OUT,
- DAT_DATA_IN => DAT_DATA_OUT,
- DAT_DATA_OUT => DAT_DATA_IN,
- DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
- DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
- DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
- DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
- DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
- DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
- DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
-
-
- BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
- BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
- BUS_ADDR_OUT(31 downto 21) => dummy(10 downto 0),
- BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
- BUS_ADDR_OUT(47 downto 36) => dummy(21 downto 10),
- BUS_ADDR_OUT(51 downto 48) => stat_busycntincl_addr,
- BUS_ADDR_OUT(63 downto 52) => dummy(33 downto 22),
- BUS_ADDR_OUT(67 downto 64) => stat_busycntexcl_addr,
- BUS_ADDR_OUT(79 downto 68) => dummy(44 downto 33),
- BUS_ADDR_OUT(95 downto 80) => dummy(60 downto 45),
- BUS_ADDR_OUT(99 downto 96) => lsm_addr,
- BUS_ADDR_OUT(111 downto 100) => dummy(72 downto 61),
- BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
- BUS_DATA_IN(63 downto 32) => stat_packets_data,
- BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
- BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
- BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data,
- BUS_DATA_IN(191 downto 160) => global_time,
- BUS_DATA_IN(223 downto 192) => lsm_data,
- BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
- BUS_DATA_OUT(63 downto 32) => dummy(104 downto 73),
- BUS_DATA_OUT(95 downto 64) => dummy(136 downto 105),
- BUS_DATA_OUT(127 downto 96) => dummy(168 downto 137),
- BUS_DATA_OUT(159 downto 128) => dummy(200 downto 169),
- BUS_DATA_OUT(191 downto 160) => dummy(232 downto 201),
- BUS_DATA_OUT(223 downto 192) => dummy(264 downto 233),
- BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
- BUS_DATAREADY_IN(1) => stat_packets_ready,
- BUS_DATAREADY_IN(2) => stat_errorbits_ready,
- BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
- BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
- BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
- BUS_DATAREADY_IN(6) => last_lsm_read,
- BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_NO_MORE_DATA_IN(5) => '0',
- BUS_NO_MORE_DATA_IN(6) => '0',
- BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
- BUS_READ_ENABLE_OUT(1) => stat_packets_read,
- BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
- BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
- BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
- BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
- BUS_READ_ENABLE_OUT(6) => lsm_read,
- BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
- BUS_TIMEOUT_OUT(1) => dummy(265),
- BUS_TIMEOUT_OUT(2) => dummy(266),
- BUS_TIMEOUT_OUT(3) => dummy(267),
- BUS_TIMEOUT_OUT(4) => dummy(268),
- BUS_TIMEOUT_OUT(5) => dummy(269),
- BUS_TIMEOUT_OUT(6) => dummy(270),
- BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
- BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
- BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
- BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
- BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
- BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
- BUS_UNKNOWN_ADDR_IN(6) => lsm_write,
- BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
- BUS_WRITE_ACK_IN(1) => stat_packets_ack,
- BUS_WRITE_ACK_IN(2) => '0',
- BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
- BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
- BUS_WRITE_ACK_IN(5) => '0',
- BUS_WRITE_ACK_IN(6) => '0',
- BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
- BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
- BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
- BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
- BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
- BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
- BUS_WRITE_ENABLE_OUT(6) => lsm_write,
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------
---1-wire interface
----------------------------------------------------------------------
- gen_1wire : if USE_ONEWIRE = c_YES generate
- onewire_interface : trb_net_onewire
- generic map(
- USE_TEMPERATURE_READOUT => c_YES,
- CLK_PERIOD => 10
- )
- port map(
- CLK => CLK,
- RESET => reset_i,
- --connection to 1-wire interface
- ONEWIRE => ONEWIRE,
- MONITOR_OUT => ONEWIRE_MONITOR_OUT,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => ONEWIRE_DATA,
- ADDR_OUT => ONEWIRE_ADDR,
- WRITE_OUT=> ONEWIRE_WRITE,
- TEMP_OUT => TEMP_OUT,
- ID_OUT => UNIQUE_ID_OUT,
- STAT => open
- );
- end generate;
-
- gen_1wire_monitor : if USE_ONEWIRE = c_MONITOR generate
- onewire_interface : trb_net_onewire_listener
- port map(
- CLK => CLK,
- CLK_EN => CLK_EN,
- RESET => reset_i,
- --connection to 1-wire interface
- MONITOR_IN => ONEWIRE_MONITOR_IN,
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT => ONEWIRE_DATA,
- ADDR_OUT => ONEWIRE_ADDR,
- WRITE_OUT=> ONEWIRE_WRITE,
- TEMP_OUT => TEMP_OUT,
- ID_OUT => UNIQUE_ID_OUT,
- STAT => open
- );
- end generate;
-
--------------------------------------------------
--- Include variable Endpoint ID
--------------------------------------------------
- gen_var_endpoint_id : if USE_VAR_ENDPOINT_ID = c_YES generate
- IDRAM_DATA_IN <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
- IDRAM_ADDR_IN <= "100" when RESET = '1' else ONEWIRE_ADDR;
- IDRAM_WR_IN <= '1' when RESET = '1' else ONEWIRE_WRITE;
- end generate;
-
- gen_no_var_endpoint_id : if USE_VAR_ENDPOINT_ID = c_NO generate
- IDRAM_DATA_IN <= ONEWIRE_DATA;
- IDRAM_ADDR_IN <= ONEWIRE_ADDR;
- IDRAM_WR_IN <= ONEWIRE_WRITE;
- end generate;
-
----------------------------------------------------------------------
---Status of media interfaces
----------------------------------------------------------------------
- gen_MED_CON : for i in 0 to MII_NUMBER-1 generate
- process(CLK)
- begin
- if rising_edge(CLK) then
- if m_ERROR_IN((i+1)*3-1 downto i*3) /= ERROR_OK then
- HUB_MED_CONNECTED(i) <= '0';
- else
- HUB_MED_CONNECTED(i) <= '1';
- end if;
- end if;
- end process;
- end generate;
-
-
-HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1');
-
----------------------------------------------------------------------
---Status and Control Registers
----------------------------------------------------------------------
-
- gen_timeout_values : for k in 0 to 3 generate
- proc_get_timeout_value : process(CLK)
- begin
- if rising_edge(CLK) then
- case to_integer(unsigned(HUB_CTRL_TIMEOUT_TIME(k*4+3 downto k*4))) is
- when 0 => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16));
- when 1 => current_timeout_value(k) <= std_logic_vector(to_unsigned(128,16) - unsigned(hub_level&'0'));
- when 2 => current_timeout_value(k) <= std_logic_vector(to_unsigned(256,16) - unsigned(hub_level&'0'));
- when 3 => current_timeout_value(k) <= std_logic_vector(to_unsigned(512,16) - unsigned(hub_level&'0'));
- when 4 => current_timeout_value(k) <= std_logic_vector(to_unsigned(1024,16) - unsigned(hub_level&'0'));
- when 5 => current_timeout_value(k) <= std_logic_vector(to_unsigned(2048,16) - unsigned(hub_level&'0'));
- when 6 => current_timeout_value(k) <= std_logic_vector(to_unsigned(4096,16) - unsigned(hub_level&'0'));
- when 7 => current_timeout_value(k) <= std_logic_vector(to_unsigned(8192,16) - unsigned(hub_level&'0'));
- when others => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16));
- end case;
- end if;
- end process;
- end generate;
-
-
---Usual common stat reg, trigger counters are not in use here
- HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0);
- HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT;
- HC_COMMON_STAT_REGS(287 downto 32) <= COMMON_STAT_REGS(287 downto 32);
-
---Status Registers
- buf_HC_STAT_REGS(3*32+31 downto 0) <= buf_STAT_POINTS_locked;
- buf_HC_STAT_REGS(4*32+MII_NUMBER-1 downto 4*32) <= HUB_MED_CONNECTED(MII_NUMBER-1 downto 0);
- buf_HC_STAT_REGS(4*32+31 downto 4*32+MII_NUMBER) <= (others => '0');
- buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0');
- buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0');
- buf_HC_STAT_REGS(7*32+31 downto 7*32) <= stat_ipu_fsm;
- buf_HC_STAT_REGS(15*32+31 downto 8*32) <= (others => '0');
- buf_HC_STAT_REGS(16*32+MII_NUMBER-1 downto 16*32) <= mii_error(MII_NUMBER-1 downto 0);
- buf_HC_STAT_REGS(30*32+31 downto 16*32+MII_NUMBER) <= (others => '0');
- buf_HC_STAT_REGS(31*32+31 downto 31*32) <= buf_HUB_MISMATCH_PATTERN;
- buf_HC_STAT_REGS(35*32+31 downto 32*32) <= HUB_STAT_ERRORBITS;
- buf_HC_STAT_REGS(63*32+31 downto 36*32) <= (others => '0');
-
- loop_links : for i in 0 to 16 generate
- buf_HC_STAT_REGS(5*32+i) <= '1' when MII_IS_UPLINK(i) = 1 else '0'; --(i < MII_NUMBER or (i = MII_NUMBER and INT_NUMBER > 0)) and
- buf_HC_STAT_REGS(6*32+i) <= '1' when MII_IS_DOWNLINK(i) = 1 else '0'; --(i < MII_NUMBER or (i = MII_NUMBER and INT_NUMBER > 0)) and;
- end generate;
-
- PROC_MED_ERROR : process(CLK)
- begin
- if rising_edge(CLK) then
- gen_bits : for i in 0 to MII_NUMBER-1 loop
- if MED_STAT_OP(i*16+15 downto i*16+13) = "000" and MED_STAT_OP(i*16+12) = '1' and RESET = '0' then
- mii_error(i) <= '1';
- elsif STAT_REG_STROBE(16) = '1' then
- mii_error(i) <= '0';
- end if;
- end loop;
- end if;
- end process;
- mii_error(31 downto MII_NUMBER) <= (others => '0');
-
- PROC_TIMEOUT : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_STROBES <= STAT_REG_STROBE;
---Timeouts 88-8B
- if reg_STROBES(8) = '1' then
- HC_STAT_REGS(8*32+31 downto 8*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then
- HC_STAT_REGS(8*32+31 downto 8*32) <= STAT_TIMEOUT(0*32+31 downto 0*32) or HC_STAT_REGS(8*32+31 downto 8*32);
- end if;
- if reg_STROBES(9) = '1' then
- HC_STAT_REGS(9*32+31 downto 9*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then
- HC_STAT_REGS(9*32+31 downto 9*32) <= STAT_TIMEOUT(1*32+31 downto 1*32) or HC_STAT_REGS(9*32+31 downto 9*32);
- end if;
- HC_STAT_REGS(10*32+31 downto 10*32) <= (others => '0');
- if reg_STROBES(11) = '1' then
- HC_STAT_REGS(11*32+31 downto 11*32) <= (others => '0');
- elsif combined_resync = '0' and reset_i = '0' and timer_us_tick = '1' then
- HC_STAT_REGS(11*32+31 downto 11*32) <= STAT_TIMEOUT(3*32+31 downto 3*32) or HC_STAT_REGS(11*32+31 downto 11*32);
- end if;
-
---Waiting for ACK timeout 8C-8F
- if reg_STROBES(12) = '1' then
- HC_STAT_REGS(12*32+31 downto 12*32) <= (others => '0');
- else
- HC_STAT_REGS(12*32+31 downto 12*32) <= HC_STAT_ack_waiting(0*32+31 downto 0*32) or HC_STAT_REGS(12*32+31 downto 12*32);
- end if;
- if reg_STROBES(13) = '1' then
- HC_STAT_REGS(13*32+31 downto 13*32) <= (others => '0');
- else
- HC_STAT_REGS(13*32+31 downto 13*32) <= HC_STAT_ack_waiting(1*32+31 downto 1*32) or HC_STAT_REGS(13*32+31 downto 13*32);
- end if;
--- if reg_STROBES(14) = '1' then
- HC_STAT_REGS(14*32+31 downto 14*32) <= (others => '0');
--- else
--- HC_STAT_REGS(14*32+31 downto 14*32) <= HC_STAT_ack_waiting(2*32+31 downto 2*32) or HC_STAT_REGS(14*32+31 downto 14*32);
--- end if;
- if reg_STROBES(15) = '1' then
- HC_STAT_REGS(15*32+31 downto 15*32) <= (others => '0');
- else
- HC_STAT_REGS(15*32+31 downto 15*32) <= HC_STAT_ack_waiting(3*32+31 downto 3*32) or HC_STAT_REGS(15*32+31 downto 15*32);
- end if;
-
---Error on slowcontrol A4
- if reg_STROBES(36) = '1' then
- HC_STAT_REGS(36*32+31 downto 36*32) <= (others => '0');
- else
- for i in 0 to MII_NUMBER-1 loop
- HC_STAT_REGS(36*32+i) <= HC_STAT_REGS(36*32+i) or buf_HUB_ALL_ERROR_BITS(i*32+48*32+1) or buf_HUB_ALL_ERROR_BITS(i*32+48*32+3) or
- buf_HUB_ALL_ERROR_BITS(i*32+48*32+6);
- end loop;
- end if;
-
---Track boards A5
- if reg_STROBES(37) = '1' then
- HC_STAT_REGS(37*32+31 downto 37*32) <= (others => '0');
- else
- for i in 0 to MII_NUMBER-1 loop
- HC_STAT_REGS(37*32+i) <= HC_STAT_REGS(37*32+i)
- or (buf_HUB_ALL_ERROR_BITS(i*32+48*32+0) and buf_HUB_ALL_ERROR_BITS(i*32+48*32+4));
- end loop;
- end if;
-
---LSM packet timeout A6
- if reg_STROBES(38) = '1' then
- HC_STAT_REGS(38*32+31 downto 38*32) <= (others => '0');
- elsif reset_i = '0' then
- for i in 0 to MII_NUMBER-1 loop
- HC_STAT_REGS(38*32+i) <= HC_STAT_REGS(38*32+i) or (MED_STAT_OP(i*16+12));
- end loop;
- end if;
-
- HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0);
- HC_STAT_REGS(36*32-1 downto 16*32) <= buf_HC_STAT_REGS(36*32-1 downto 16*32);
- end if;
- end process;
- HC_STAT_REGS(64*32-1 downto 39*32) <= buf_HC_STAT_REGS(64*32-1 downto 39*32);
-
-------------------------------------
---STAT error bits
-------------------------------------
- loop_links_2 : for i in 0 to 15 generate
- HUB_ERROR_BITS(i*32+7 downto i*32+0) <= buf_HUB_ALL_ERROR_BITS(i*32+7 downto i*32+0);
- HUB_ERROR_BITS(i*32+15 downto i*32+8) <= buf_HUB_ALL_ERROR_BITS(i*32+23 downto i*32+16);
- HUB_ERROR_BITS(i*32+23 downto i*32+16) <= buf_HUB_ALL_ERROR_BITS(i*32+32*16+7 downto i*32+32*16+0);
- HUB_ERROR_BITS(i*32+31 downto i*32+24) <= buf_HUB_ALL_ERROR_BITS(i*32+32*16+23 downto i*32+32*16+16);
- end generate;
-
- PROC_ERROR_BITS : process(CLK, stat_errorbits_addr)
- variable tmp : integer;
- begin
- tmp := to_integer(unsigned(stat_errorbits_addr));
- if rising_edge(CLK) then
- stat_errorbits_unknown <= stat_errorbits_write;
- stat_errorbits_ready <= stat_errorbits_read;
- stat_errorbits_data <= HUB_ERROR_BITS(tmp*32+31 downto tmp*32);
- end if;
- end process;
-
-------------------------------------
---STAT packet counters
-------------------------------------
- gen_packet_cnt : for i in 0 to MII_NUMBER-1 generate
- stat_packets_all(i*32+31 downto i*32) <= IOBUF_STAT_DATA_COUNTER(i*128+63 downto i*128+32);
- stat_packets_all((i+16)*32+31 downto (i+16)*32) <= IOBUF_STAT_DATA_COUNTER(i*128+127 downto i*128+96);
- end generate;
- stat_packets_all(16*32-1 downto MII_NUMBER*32) <= (others => '0');
- stat_packets_all(32*32-1 downto (MII_NUMBER+16)*32) <= (others => '0');
-
-
- PROC_PACKET_COUNTERS : process(CLK, stat_packets_addr)
- variable tmp : integer;
- begin
- tmp := to_integer(unsigned(stat_packets_addr));
- if rising_edge(CLK) then
- iobuf_reset_ipu_counter <= '0';
- iobuf_reset_sctrl_counter <= '0';
- stat_packets_unknown <= '0';
- stat_packets_ack <= '0';
- stat_packets_ready <= stat_packets_read;
- stat_packets_data <= stat_packets_all(tmp*32+31 downto tmp*32);
- if stat_packets_addr = "00000" and stat_packets_write = '1' then
- stat_packets_ack <= '1';
- iobuf_reset_ipu_counter <= '1';
- elsif stat_packets_addr = "10000" and stat_packets_write = '1' then
- stat_packets_ack <= '1';
- iobuf_reset_sctrl_counter <= '1';
- elsif stat_packets_write = '1' then
- stat_packets_unknown <= stat_packets_write;
- end if;
- end if;
- end process;
-
-------------------------------------
---LSM status
-------------------------------------
- PROC_LSM_STAT : process(CLK, lsm_addr)
- variable tmp : integer range 0 to 15;
- begin
- tmp := to_integer(unsigned(lsm_addr));
- if rising_edge(CLK) then
- next_last_lsm_read <= lsm_read;
- last_lsm_read <= next_last_lsm_read;
- next_lsm_data(7 downto 0) <= MED_STAT_OP(tmp*16+7 downto tmp*16+0);
- next_lsm_data(15 downto 8) <= std_logic_vector(received_resets(tmp));
- next_lsm_data(23 downto 16) <= std_logic_vector(received_retransmit_requests(tmp));
- next_lsm_data(31 downto 24) <= std_logic_vector(sent_retransmit_requests(tmp));
- lsm_data <= next_lsm_data;
- end if;
- end process;
-
- gen_retransmit_counters : for i in 0 to MII_NUMBER-1 generate
- proc_retransmit_counters : process(CLK)
- begin
- if rising_edge(CLK) then
- if HC_COMMON_CTRL_REGS(5) = '1' then
- sent_retransmit_requests(i) <= (others => '0');
- elsif MED_STAT_OP(i*16+12) = '1' then
- sent_retransmit_requests(i) <= sent_retransmit_requests(i) + to_unsigned(1,1);
- end if;
- if HC_COMMON_CTRL_REGS(5) = '1' then
- received_retransmit_requests(i) <= (others => '0');
- elsif MED_STAT_OP(i*16+8) = '1' then
- received_retransmit_requests(i) <= received_retransmit_requests(i) + to_unsigned(1,1);
- end if;
- if HC_COMMON_CTRL_REGS(5) = '1' then
- received_resets(i) <= (others => '0');
- elsif make_trbnet_reset(i) = '1' then
- received_resets(i) <= received_resets(i) + to_unsigned(1,1);
- end if;
- last_make_trbnet_reset(i) <= MED_STAT_OP(i*16+13);
- make_trbnet_reset(i) <= MED_STAT_OP(i*16+13) and not last_make_trbnet_reset(i);
- end if;
- end process;
- end generate;
-
- gen_0s : for i in MII_NUMBER to 15 generate
- received_retransmit_requests(i) <= (others => '0');
- sent_retransmit_requests(i) <= (others => '0');
- received_resets(i) <= (others => '0');
- end generate;
-
-------------------------------------
---STAT busy counters
-------------------------------------
- gen_busy_counters : for i in 0 to MII_NUMBER+2 generate
- proc_busy_counters : process(CLK)
- begin
- if rising_edge(CLK) then
- reg_STAT_POINTS_locked(i) <= buf_STAT_POINTS_locked(i);
- if reg_STAT_POINTS_locked(i) = '1' and
- or_all(reg_STAT_POINTS_locked(MII_NUMBER-1 downto 0) and not (std_logic_vector(to_unsigned(2**i,MII_NUMBER)))) = '0' then
- reg_excl_enable(i) <= '1';
- else
- reg_excl_enable(i) <= '0';
- end if;
-
- if stat_busycntincl_ack = '1' then
- busy_counter_incl(i) <= (others => '0');
- elsif reg_STAT_POINTS_locked(i) = '1' then
- busy_counter_incl(i) <= busy_counter_incl(i) + to_unsigned(1,1);
- end if;
-
- if stat_busycntexcl_ack = '1' then
- busy_counter_excl(i) <= (others => '0');
- elsif reg_excl_enable(i) = '1' then
- busy_counter_excl(i) <= busy_counter_excl(i) + to_unsigned(1,1);
- end if;
-
- end if;
- end process;
- end generate;
-
- proc_busy_counter_incl_register : process(CLK)
- variable tmp : integer range 0 to 15;
- begin
- if rising_edge(CLK) then
- last_stat_globaltime_read <= stat_globaltime_read;
- last_stat_globaltime_write <= stat_globaltime_write;
-
- stat_busycntincl_unknown <= '0';
- stat_busycntincl_ready <= '0';
- if stat_busycntincl_read = '1' then
- tmp := to_integer(unsigned(stat_busycntincl_addr));
- if tmp < MII_NUMBER then
- stat_busycntincl_data <= std_logic_vector(busy_counter_incl(tmp));
- stat_busycntincl_ready <= '1';
- else
- stat_busycntincl_data <= (others => '0');
- stat_busycntincl_ready <= '1';
- end if;
- end if;
- if stat_busycntincl_write = '1' then
- stat_busycntincl_ack <= '1';
- else
- stat_busycntincl_ack <= '0';
- end if;
- end if;
- end process;
-
- proc_busy_counter_excl_register : process(CLK)
- variable tmp : integer range 0 to 15;
- begin
- if rising_edge(CLK) then
- stat_busycntexcl_unknown <= '0';
- stat_busycntexcl_ready <= '0';
- if stat_busycntexcl_read = '1' then
- tmp := to_integer(unsigned(stat_busycntexcl_addr));
- if tmp < MII_NUMBER then
- stat_busycntexcl_data <= std_logic_vector(busy_counter_excl(tmp));
- stat_busycntexcl_ready <= '1';
- else
- stat_busycntexcl_data <= (others => '0');
- stat_busycntexcl_ready <= '1';
- end if;
- end if;
- if stat_busycntexcl_write = '1' then
- stat_busycntexcl_ack <= '1';
- else
- stat_busycntexcl_ack <= '0';
- end if;
- end if;
- end process;
-
-------------------------------------
---Control Registers
-------------------------------------
- HUB_CTRL_media_interfaces_off <= HC_CTRL_REGS(2**2*32+31 downto 2**2*32);
- HUB_CTRL_LOCAL_NETWORK_RESET <= HC_CTRL_REGS(6*32+MII_NUMBER-1 downto 6*32);
-
- PROC_active_points : process (CLK)
- begin
- if rising_edge(CLK) then
- for i in 0 to 2**(c_MUX_WIDTH-1)-1 loop
- if HUB_locked(i) = '0' then
- HUB_CTRL_activepoints(i*32+31 downto i*32) <= HC_CTRL_REGS(i*32+31 downto i*32);
- if i < 2 and INT_NUMBER >= 3 then
- HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HC_CTRL_REGS(i*32+MII_NUMBER) and stream_port_connected;
- else
- HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HC_CTRL_REGS(i*32+MII_NUMBER+1) and stream_port_connected;
- end if;
- else
- HUB_CTRL_activepoints(i*32+31 downto i*32) <= HUB_CTRL_activepoints(i*32+31 downto i*32); -- and not HC_STAT_ack_waiting(i*32+31 downto i*32)
- if i < 2 and INT_NUMBER >= 3 then
- HUB_CTRL_activepoints(i*32+MII_NUMBER) <= HUB_CTRL_activepoints(i*32+MII_NUMBER) and stream_port_connected; -- and not HC_STAT_ack_waiting(i*32+31 downto i*32)
- else
- HUB_CTRL_activepoints(i*32+MII_NUMBER+1) <= HUB_CTRL_activepoints(i*32+MII_NUMBER+1) and stream_port_connected; -- and not HC_STAT_ack_waiting(i*32+31 downto i*32)
- end if;
- end if;
- end loop;
- end if;
- end process;
-
- PROC_ports_disable_after_timeout: process begin
- wait until rising_edge(CLK);
- if HUB_CTRL_TIMEOUT_TIME(31) = '0' or reset_i = '1' then
- hub_ctrl_disabled_ports <= not HUB_MED_CONNECTED; --(others => '0');
- else
- hub_ctrl_disabled_ports(31 downto MII_NUMBER) <= (others => '0');
- hub_ctrl_disabled_ports(MII_NUMBER-1 downto 0) <= STAT_TIMEOUT(3*32+MII_NUMBER-1+16 downto 3*32+16) or not HUB_MED_CONNECTED(MII_NUMBER-1 downto 0);
- end if;
- end process;
-
- PROC_timeout_settings : process (CLK)
- begin
- if rising_edge(CLK) then
--- if CTRL_REG_STROBE(5) = '1' then
- HUB_CTRL_TIMEOUT_TIME <= HC_CTRL_REGS(5*32+31 downto 5*32);
- hub_level <= HC_CTRL_REGS(5*32+23 downto 5*32+16);
--- end if;
- end if;
- end process;
-
-
- gen_ack_waiting : for i in 0 to MII_NUMBER-1 generate
- HC_STAT_ack_waiting(i) <= iobuf_stat_init_obuf_debug_i((i*4+0)*32+20);
- HC_STAT_ack_waiting(32+i) <= iobuf_stat_init_obuf_debug_i((i*4+1)*32+20);
- HC_STAT_ack_waiting(64+i) <= iobuf_stat_init_obuf_debug_i((i*4+2)*32+20);
- HC_STAT_ack_waiting(96+i) <= iobuf_stat_init_obuf_debug_i((i*4+3)*32+20);
- end generate;
-
- HC_STAT_ack_waiting( 0+31 downto 0+MII_NUMBER) <= (others => '0');
- HC_STAT_ack_waiting(32+31 downto 32+MII_NUMBER) <= (others => '0');
- HC_STAT_ack_waiting(64+31 downto 64+MII_NUMBER) <= (others => '0');
- HC_STAT_ack_waiting(96+31 downto 96+MII_NUMBER) <= (others => '0');
-
- stream_port_connected <= '1' when CTRL_DEBUG(2 downto 0) = (not ERROR_OK) else '0';
----------------------------------------------------------------------
--- Counter reset signals
----------------------------------------------------------------------
- iobuf_ctrl_stat(15 downto 0) <= (others => '0');
- iobuf_ctrl_stat(16) <= iobuf_reset_ipu_counter;
- iobuf_ctrl_stat(47 downto 17) <= (others => '0');
- iobuf_ctrl_stat(48) <= iobuf_reset_sctrl_counter;
- iobuf_ctrl_stat(63 downto 49) <= (others => '0');
-
----------------------------------------------------------------------
---LED signals
----------------------------------------------------------------------
- proc_led_count: process(CLK)
- begin
- if rising_edge(CLK) then
- if timer_ms_tick = '1' then
- led_counter <= led_counter + to_unsigned(1,1);
- end if;
- end if;
- end process;
-
- proc_led : process(CLK)
- begin
- if rising_edge(CLK) then
- for i in 0 to MII_NUMBER-1 loop
- hub_led_i(i) <= '0';
- if hub_show_port(i) = '1' then
- if led_counter(6 downto 0) < to_unsigned(32,7) then
- hub_led_i(i) <= '1';
- end if;
- elsif HC_STAT_REGS(8*32+i) = '1' or HC_STAT_REGS(9*32+i) = '1' or HC_STAT_REGS(10*32+i) = '1' or HC_STAT_REGS(11*32+i) = '1' then
- if led_counter(8 downto 0) < to_unsigned(128,10) then
- hub_led_i(i) <= '1';
- end if;
- end if;
- end loop;
- end if;
- end process;
-
- hub_show_port <= HC_CTRL_REGS(7*32+MII_NUMBER-1 downto 7*32);
- HUB_LED_OUT <= hub_led_i;
-
----------------------------------------------------------------------
---Debugging Signals
----------------------------------------------------------------------
--- buf_STAT_DEBUG(0) <= hub_to_buf_INIT_DATAREADY(2**(c_MUX_WIDTH-1)*MII_NUMBER);
--- buf_STAT_DEBUG(1) <= hub_to_buf_INIT_READ(2**(c_MUX_WIDTH-1)*MII_NUMBER);
--- buf_STAT_DEBUG(2) <= hub_to_buf_REPLY_DATAREADY(2**(c_MUX_WIDTH-1)*MII_NUMBER);
--- buf_STAT_DEBUG(3) <= hub_to_buf_REPLY_READ(2**(c_MUX_WIDTH-1)*MII_NUMBER);
--- buf_STAT_DEBUG(6 downto 4) <= hub_to_buf_INIT_DATA(2**(c_MUX_WIDTH-1)*MII_NUMBER*16+2 downto 2**(c_MUX_WIDTH-1)*MII_NUMBER*16);
--- buf_STAT_DEBUG(7) <= buf_HUB_STAT_CHANNEL(3*16+1);
---
--- buf_STAT_DEBUG(8) <= reset_i_mux_io(2*MII_NUMBER+6);
--- buf_STAT_DEBUG(9) <= reset_i_mux_io(3*MII_NUMBER+6);
--- buf_STAT_DEBUG(10) <= HUB_CTRL_final_activepoints(3*32+6);
--- buf_STAT_DEBUG(11) <= STAT_TIMEOUT(3*32+6);
--- buf_STAT_DEBUG(12) <= buf_to_hub_REPLY_DATAREADY(6*4+3);
--- buf_STAT_DEBUG(13) <= buf_to_hub_REPLY_READ(6*4+3);
--- buf_STAT_DEBUG(14) <= buf_HUB_STAT_CHANNEL(3*16+2);
---
--- buf_STAT_DEBUG(15) <= buf_to_hub_INIT_DATAREADY(0*4+3);
-
-
- buf_STAT_DEBUG( 3 downto 0 ) <= STAT_TIMEOUT(3*32+3 downto 3*32);
- buf_STAT_DEBUG( 7 downto 4 ) <= HUB_CTRL_final_activepoints(3*32+3 downto 3*32);
-
-
- IOBUF_STAT_INIT_OBUF_DEBUG <= iobuf_stat_init_obuf_debug_i;
- IOBUF_STAT_REPLY_OBUF_DEBUG <= iobuf_stat_reply_obuf_debug_i;
- IOBUF_CTRL_GEN <= (others => '0');
- --map regio registers to stat & ctrl outputs
- COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS;
- COMMON_CTRL_REG_STROBE <= HC_COMMON_CTRL_REG_STROBE;
- COMMON_STAT_REG_STROBE <= HC_COMMON_STAT_REG_STROBE;
- MY_ADDRESS_OUT <= HUB_ADDRESS;
- STAT_REGS <= HC_STAT_REGS(16*32-1 downto 0);
- STAT_CTRL_REGS <= HC_CTRL_REGS(255 downto 0);
- HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL;
- STAT_DEBUG <= buf_STAT_DEBUG;
-
- HUB_STAT_GEN(3 downto 0) <= HUB_locked;
- HUB_STAT_GEN(31 downto 4) <= (others => '0');
-
- TIMER_TICKS_OUT(0) <= timer_us_tick;
- TIMER_TICKS_OUT(1) <= timer_ms_tick;
- TEMPERATURE_OUT <= TEMP_OUT;
-end architecture;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.version.all;
-use work.config.all;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb_net_gbe_components.all;
-use work.trb_net_gbe_protocols.all;
-use work.med_sync_define.all;
-
-entity trb_net16_cri_interface is
- generic(
- INCLUDE_READOUT : integer range 0 to 1 := 1;
- INCLUDE_SLOWCTRL : integer range 0 to 1 := 1;
- READOUT_BUFFER_SIZE : integer range 1 to 4 := 1
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- --Media Interface
- MEDIA_MED2INT : in med2int_array_t(0 to 0);
- MEDIA_INT2MED : out int2med_array_t(0 to 0);
-
- MY_ADDRESS_IN : in std_logic_vector(15 downto 0);
-
- --Event information coming from CTS for CRI
- CTS_NUMBER_IN : in std_logic_vector (15 downto 0);
- CTS_CODE_IN : in std_logic_vector (7 downto 0);
- CTS_INFORMATION_IN : in std_logic_vector (7 downto 0);
- CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0);
- CTS_START_READOUT_IN : in std_logic;
-
- --Information sent to CTS
- CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM
- CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0);
-
- --Data from Frontends
- FEE_DATA_IN : in std_logic_vector (15 downto 0);
- FEE_DATAREADY_IN : in std_logic;
- FEE_READ_OUT : out std_logic; --must be high when idle, otherwise you will never get a dataready
- FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0);
- FEE_BUSY_IN : in std_logic;
-
- --Gbe Sctrl Input
- GSC_INIT_DATAREADY_OUT : out std_logic;
- GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0);
- GSC_INIT_PACKET_NUM_OUT : out std_logic_vector( 2 downto 0);
- GSC_INIT_READ_IN : in std_logic;
- GSC_REPLY_DATAREADY_IN : in std_logic;
- GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0);
- GSC_REPLY_PACKET_NUM_IN : in std_logic_vector( 2 downto 0);
- GSC_REPLY_READ_OUT : out std_logic;
- GSC_BUSY_IN : in std_logic;
-
- -- Registers config
- BUS_REG_RX : in CTRLBUS_RX;
- BUS_REG_TX : out CTRLBUS_TX;
-
- BUS_DBG_RX : in CTRLBUS_RX;
- BUS_DBG_TX : out CTRLBUS_TX;
-
- TIMER_TICKS_IN : in std_logic_vector( 1 downto 0)
- );
-end entity;
-
-architecture arch of trb_net16_cri_interface is
-
- signal reset_i, reset_i_mux_io : std_logic;
-
- signal gbe_cts_number : std_logic_vector(15 downto 0);
- signal gbe_cts_code : std_logic_vector(7 downto 0);
- signal gbe_cts_information : std_logic_vector(7 downto 0);
- signal gbe_cts_start_readout : std_logic;
- signal gbe_cts_readout_type : std_logic_vector(3 downto 0);
- signal gbe_cts_readout_finished : std_logic;
- signal gbe_cts_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_data : std_logic_vector(15 downto 0);
- signal gbe_fee_dataready : std_logic;
- signal gbe_fee_read : std_logic;
- signal gbe_fee_status_bits : std_logic_vector(31 downto 0);
- signal gbe_fee_busy : std_logic;
-
- signal io_dataready_out : std_logic_vector(7 downto 0);
- signal io_data_out : std_logic_vector(127 downto 0);
- signal io_packet_num_out : std_logic_vector(23 downto 0);
- signal io_read_in : std_logic_vector(7 downto 0);
-
- signal io_dataready_in : std_logic_vector(3 downto 0);
- signal io_read_out : std_logic_vector(3 downto 0);
- signal io_data_in : std_logic_vector(4*16-1 downto 0);
- signal io_packet_num_in : std_logic_vector(4*3-1 downto 0);
- signal io_error_in : std_logic_vector(2 downto 0);
-
- signal cfg_gbe_enable : std_logic;
- signal cfg_ipu_enable : std_logic;
- signal cfg_mult_enable : std_logic;
- signal cfg_subevent_id : std_logic_vector(31 downto 0);
- signal cfg_subevent_dec : std_logic_vector(31 downto 0);
- signal cfg_queue_dec : std_logic_vector(31 downto 0);
- signal cfg_readout_ctr : std_logic_vector(23 downto 0);
- signal cfg_readout_ctr_valid : std_logic;
- signal cfg_insert_ttype : std_logic;
- signal cfg_max_sub : std_logic_vector(15 downto 0);
- signal cfg_max_queue : std_logic_vector(15 downto 0);
- signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0);
- signal cfg_max_single_sub : std_logic_vector(15 downto 0);
- signal cfg_additional_hdr : std_logic;
- signal cfg_soft_rst : std_logic;
- signal cfg_allow_rx : std_logic;
- signal cfg_max_frame : std_logic_vector(15 downto 0);
-
- signal tc_rd_en : std_logic := '0';
- signal tc_data : std_logic_vector( 8 downto 0);
- signal tc_size : std_logic_vector(15 downto 0);
- signal resp_ready : std_logic := '0';
- signal resp_busy : std_logic := '0';
- signal cri_readout_finished_in : std_logic;
-
- signal cri_init_dataready_out : std_logic;
- signal cri_init_data_out : std_logic_vector(15 downto 0);
- signal cri_init_packet_num_out : std_logic_vector( 2 downto 0);
- signal cri_init_read_in : std_logic;
-
- signal cri_reply_dataready_in : std_logic;
- signal cri_reply_data_in : std_logic_vector(15 downto 0);
- signal cri_reply_packet_num_in : std_logic_vector( 2 downto 0);
- signal cri_reply_read_out : std_logic;
-
- --API data Transmitter to CRI
- signal cri_apl_data_in : std_logic_vector(15 downto 0);
- signal cri_apl_packet_num_in : std_logic_vector( 2 downto 0);
- signal cri_apl_dataready_in : std_logic;
- signal cri_apl_read_out : std_logic;
- signal cri_apl_send_in : std_logic;
-
- --API data Receiver from CRI
- signal cri_apl_data_out : std_logic_vector(15 downto 0);
- signal cri_apl_packet_num_out : std_logic_vector( 2 downto 0);
- signal cri_apl_typ_out : std_logic_vector( 2 downto 0);
- signal cri_apl_dataready_out : std_logic;
- signal cri_apl_read_in : std_logic;
-
- --API data controller
- signal cri_apl_run_out : std_logic;
- signal cri_packet_num_cnt : unsigned( 1 downto 0) := 0;
- signal cri_data_send_cnt : unsigned(15 downto 0) := 0;
- signal cri_send : std_logic;
-
- signal cri_event_cnt : unsigned(15 downto 0) := 0;
-
- --DEBUG SIGNALS:
- signal debug_resp_control : std_logic_vector(63 downto 0);
- signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0);
- signal last_cts_readout_finished, last_cts_readout_start : std_logic;
-
- signal dbg_pc_wr_en : std_logic;
- signal dbg_pc_data : std_logic_vector( 7 downto 0);
- signal dbg_pc_sos : std_logic;
- signal dbg_pc_eos : std_logic;
- signal dbg_pc_eoq : std_logic;
- signal dbg_pc_sub_size : std_logic_vector(31 downto 0);
- signal dbg_pc_trig_nr : std_logic_vector(31 downto 0);
- signal dbg_pc_trig_type : std_logic_vector( 3 downto 0);
-
- signal last_dbg_pc_wr_en : std_logic;
- signal last_dbg_pc_sos : std_logic;
- signal last_dbg_pc_eos : std_logic;
- signal last_dbg_pc_eoq : std_logic;
-
- signal dbg_pc_wr_en_cnt : unsigned(15 downto 0);
- signal dbg_pc_sos_cnt : unsigned(15 downto 0);
- signal dbg_pc_eos_cnt : unsigned(15 downto 0);
- signal dbg_pc_eoq_cnt : unsigned(15 downto 0);
-
- signal dbg_api_fifo_to_int : std_logic_vector(31 downto 0);
- signal dbg_api_fifo_to_api : std_logic_vector(31 downto 0);
-
- signal dbg_start_data_send : std_logic := '0';
-
- signal dbg_io_dataready_cnt_2 : unsigned(15 downto 0);
- signal dbg_io_dataready_cnt_3 : unsigned(15 downto 0);
- signal dbg_io_dataready_cnt_6 : unsigned(15 downto 0);
- signal dbg_io_dataready_cnt_7 : unsigned(15 downto 0);
-
- signal resp_ready_q : std_logic := '0';
- signal resp_ready_qq : std_logic := '0';
- signal resp_ready_3q : std_logic := '0';
- signal resp_ready_4q : std_logic := '0';
- signal resp_ready_5q : std_logic := '0';
- signal resp_ready_6q : std_logic := '0';
-
- signal tc_data_rdy : std_logic;
-
- signal tmp_data, ipu_data : std_logic_vector( 7 downto 0);
-
- signal ipu_wr_en, ipu_wr_en_q, ipu_wr_en_qq, ipu_wr_en_qqq : std_logic;
- signal ipu_sos_out_q, ipu_sos_out_qq, ipu_sos_out_qqq : std_logic;
- signal ipu_eod_out_q, ipu_eod_out_qq, ipu_eod_out_qqq : std_logic;
- signal ipu_data_start, ipu_data_end : std_logic;
- signal ipu_sub_size : std_logic_vector(31 downto 0);
-
- signal ipu_ready_in : std_logic;
- signal ipu_start_rdy : std_logic;
- signal loaded_bytes : std_logic_vector(15 downto 0);
-
- signal debug_sender :std_logic_vector(191 downto 0);
-begin
-
----------------------------------------------------------------------
--- Reset
----------------------------------------------------------------------
---13: reset sequence received
---14: not connected
---15: send reset sequence
-
- SYNC_RESET_MUX_IO : process(CLK)
- begin
- if rising_edge(CLK) then
- reset_i <= RESET;
- reset_i_mux_io <= MEDIA_MED2INT(0).stat_op(14) or reset_i;
- end if;
- end process;
-
-
-
-
-
----------------------------------------------------------------------
--- I/O Buffers
----------------------------------------------------------------------
--- iobuf of Trigger channel -> As CTS is part of Combiner, this channel is
--- not used anymore in this place
-
--- channel 0
- THE_IOBUF_0 : trb_net16_term_buf
- port map (
- -- Misc
- CLK => CLK ,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(0),
- MED_INIT_DATA_OUT => io_data_out(15 downto 0),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0),
- MED_INIT_READ_IN => io_read_in(0),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(1),
- MED_REPLY_DATA_OUT => io_data_out(31 downto 16),
- MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(5 downto 3),
- MED_REPLY_READ_IN => io_read_in(1),
-
- MED_DATAREADY_IN => io_dataready_in(0),
- MED_DATA_IN => io_data_in(15 downto 0),
- MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0),
- MED_READ_OUT => io_read_out(0)
- );
-
----------------------------------------------------------------------
--- TrbNet Data Readout
----------------------------------------------------------------------
- trbnet_gen : if INCLUDE_READOUT = 1 generate
-
- THE_CRI_DATA_SENDER : entity work.cri_data_sender
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => '1',
-
- ENABLE_TRANSPORT => '1',--dbg_start_data_send,
-
- -- Port to API
- API_DATA_OUT => cri_apl_data_in,
- API_PACKET_NUM_OUT => cri_apl_packet_num_in,
- API_DATAREADY_OUT => cri_apl_dataready_in,
- API_READ_IN => cri_apl_read_out,
- API_SHORT_TRANSFER_OUT => open,
- API_DTYPE_OUT => open,
- API_ERROR_PATTERN_OUT => open,
- API_SEND_OUT => cri_apl_send_in,
- -- Receiver port
- API_DATA_IN => cri_apl_data_out,
- API_PACKET_NUM_IN => cri_apl_packet_num_out,
- API_TYP_IN => cri_apl_typ_out,
- API_DATAREADY_IN => cri_apl_dataready_out,
- API_READ_OUT => cri_apl_read_in,
- -- APL Control port
- API_RUN_IN => cri_apl_run_out,
- API_SEQNR_IN => (others => '0'),
- API_LENGTH_OUT => open,
- MY_ADDRESS_IN => MY_ADDRESS_IN,
-
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_READ_IN => '1',
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_BUSY_IN => FEE_BUSY_IN,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
-
- DEBUG_OUT => debug_sender
- );
-
- THE_CRI_DATARDY_DBG : process begin
- wait until rising_edge(CLK);
- if RESET = '1' then
- dbg_io_dataready_cnt_2 <= 0;
- dbg_io_dataready_cnt_3 <= 0;
- dbg_io_dataready_cnt_6 <= 0;
- dbg_io_dataready_cnt_7 <= 0;
- else
- if io_dataready_out(2) = '1' then
- dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1;
- end if;
-
- if io_dataready_out(3) = '1' then
- dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1;
- end if;
-
- if io_dataready_out(6) = '1' then
- dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1;
- end if;
-
- if io_dataready_out(7) = '1' then
- dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------
--- active API for Data Channel
----------------------------------------------------------------------
- TRG_CHANNEL_API: trb_net16_api_base
- generic map (
- API_TYPE => c_API_ACTIVE,
- FIFO_TO_INT_DEPTH => 6,
- FIFO_TO_APL_DEPTH => 6,
- FORCE_REPLY => 1,
- SBUF_VERSION => 0,
- USE_VENDOR_CORES => c_YES,
- SECURE_MODE_TO_APL => c_YES,
- SECURE_MODE_TO_INT => c_YES,
- APL_WRITE_ALL_WORDS=> c_YES
- )
- port map (
- -- Misc
- CLK => CLK,
- RESET => reset_i,
- CLK_EN => '1',
- -- APL Transmitter port
- APL_DATA_IN => cri_apl_data_in,
- APL_PACKET_NUM_IN => cri_apl_packet_num_in,
- APL_DATAREADY_IN => cri_apl_dataready_in, -- almostfullflag ; daten in fifo von 8 auf 16 bit packen
- APL_READ_OUT => cri_apl_read_out,
- APL_SHORT_TRANSFER_IN => '0',
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
- APL_SEND_IN => cri_apl_send_in, -- 1 till end of Datastream
- APL_TARGET_ADDRESS_IN => (others => '1'),
- -- Receiver port
- APL_DATA_OUT => cri_apl_data_out,
- APL_PACKET_NUM_OUT => cri_apl_packet_num_out,
- APL_TYP_OUT => cri_apl_typ_out,
- APL_DATAREADY_OUT => cri_apl_dataready_out,
- APL_READ_IN => cri_apl_read_in,
- -- APL Control port
- APL_RUN_OUT => cri_apl_run_out,
- APL_MY_ADDRESS_IN => MY_ADDRESS_IN,
- APL_SEQNR_OUT => open,
- APL_LENGTH_IN => (others => '0'),
- APL_FIFO_COUNT_OUT => open,
-
- -- Internal direction port
- INT_MASTER_DATAREADY_OUT => cri_init_dataready_out,
- INT_MASTER_DATA_OUT => cri_init_data_out,
- INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out,
- INT_MASTER_READ_IN => cri_init_read_in,
- INT_MASTER_DATAREADY_IN => '0',
- INT_MASTER_DATA_IN => (others => '0'),
- INT_MASTER_PACKET_NUM_IN => "000",
- INT_MASTER_READ_OUT => open,
- INT_SLAVE_DATAREADY_OUT => open,
- INT_SLAVE_DATA_OUT => open,
- INT_SLAVE_PACKET_NUM_OUT => open,
- INT_SLAVE_READ_IN => '1',
- INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in,
- INT_SLAVE_DATA_IN => cri_reply_data_in,
- INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in,
- INT_SLAVE_READ_OUT => cri_reply_read_out,
- -- Status and control port
- CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED
- STAT_FIFO_TO_INT => dbg_api_fifo_to_int,
- STAT_FIFO_TO_APL => dbg_api_fifo_to_api
- );
-
- --iobuf on streaming api, towards CRI, data channel
- THE_IOBUF_1 : trb_net16_iobuf
- generic map(
- IBUF_DEPTH => 6,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1),
- USE_CHECKSUM => cfg_USE_CHECKSUM(1),
- INIT_CAN_SEND_DATA => c_YES,
- INIT_CAN_RECEIVE_DATA => c_NO,
- REPLY_CAN_SEND_DATA => c_NO,
- REPLY_CAN_RECEIVE_DATA => c_YES
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(2),
- MED_INIT_DATA_OUT => io_data_out(47 downto 32),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
- MED_INIT_READ_IN => io_read_in(2),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
- MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9),
- MED_REPLY_READ_IN => io_read_in(3),
-
- MED_DATAREADY_IN => io_dataready_in(1),
- MED_DATA_IN => io_data_in(31 downto 16),
- MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
- MED_READ_OUT => io_read_out(1),
- MED_ERROR_IN => io_error_in,
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => open,
- INT_INIT_DATA_OUT => open,
- INT_INIT_PACKET_NUM_OUT => open,
- INT_INIT_READ_IN => '1',
-
- INT_INIT_DATAREADY_IN => cri_init_dataready_out,
- INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI
- INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out,
- INT_INIT_READ_OUT => cri_init_read_in,
-
- INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in,
- INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI
- INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in,
- INT_REPLY_READ_IN => cri_reply_read_out,
-
- INT_REPLY_DATAREADY_IN => '0',
- INT_REPLY_DATA_IN => (others => '0'),
- INT_REPLY_PACKET_NUM_IN => (others => '0'),
- INT_REPLY_READ_OUT => open,
-
- -- Status and control port
- STAT_GEN => open,
- STAT_IBUF_BUFFER => open,
- CTRL_GEN => (others => '0'),
- STAT_INIT_OBUF_DEBUG => open,
- STAT_REPLY_OBUF_DEBUG => open,
- TIMER_TICKS_IN => TIMER_TICKS_IN
- );
- end generate trbnet_gen;
-
-
-
-
- no_readout_gen : if INCLUDE_READOUT = 0 generate
- -- terminate data channel if no readout
- THE_IOBUF_1 : trb_net16_term_buf
- port map (
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(2),
- MED_INIT_DATA_OUT => io_data_out(47 downto 32),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6),
- MED_INIT_READ_IN => io_read_in(2),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(3),
- MED_REPLY_DATA_OUT => io_data_out(63 downto 48),
- MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(11 downto 9),
- MED_REPLY_READ_IN => io_read_in(3),
-
- MED_DATAREADY_IN => io_dataready_in(1),
- MED_DATA_IN => io_data_in(31 downto 16),
- MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3),
- MED_READ_OUT => io_read_out(1)
- );
-
- --Terminate Data
- THE_TrbNetData : entity work.trb_net16_gbe_ipu_interface
- generic map(
- DO_SIMULATION => 0
- )
- port map (
- CLK_IPU => CLK,
- CLK_GBE => CLK,
- RESET => reset_i_mux_io,
-
- CTS_NUMBER_IN => CTS_NUMBER_IN,
- CTS_CODE_IN => CTS_CODE_IN,
- CTS_INFORMATION_IN => CTS_INFORMATION_IN,
- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
- CTS_START_READOUT_IN => CTS_START_READOUT_IN,
- CTS_READ_IN => '1',
- CTS_DATA_OUT => open,
- CTS_DATAREADY_OUT => open,
- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
- CTS_LENGTH_OUT => open,
- CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT,
- -- Data from Frontends
- FEE_DATA_IN => FEE_DATA_IN,
- FEE_DATAREADY_IN => FEE_DATAREADY_IN,
- FEE_READ_OUT => FEE_READ_OUT,
- FEE_BUSY_IN => FEE_BUSY_IN,
- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
- -- slow control interface
- START_CONFIG_OUT => open,
- BANK_SELECT_OUT => open,
- CONFIG_DONE_IN => '1',
- DATA_GBE_ENABLE_IN => cfg_gbe_enable,
- DATA_IPU_ENABLE_IN => cfg_ipu_enable, -- never used in code
- MULT_EVT_ENABLE_IN => cfg_mult_enable,
- MAX_SUBEVENT_SIZE_IN => cfg_max_sub,
- MAX_QUEUE_SIZE_IN => cfg_max_queue,
- MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
- MAX_SINGLE_SUB_SIZE_IN => cfg_max_single_sub,
- READOUT_CTR_IN => cfg_readout_ctr,
- READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
- CFG_AUTO_THROTTLE_IN => '0',
- CFG_THROTTLE_PAUSE_IN => (others => '0'),
- -- PacketConstructor interface
- PC_WR_EN_OUT => dbg_pc_wr_en,
- PC_DATA_OUT => dbg_pc_data,
- PC_READY_IN => '1',
- PC_SOS_OUT => dbg_pc_sos,
- PC_EOS_OUT => dbg_pc_eos,
- PC_EOQ_OUT => dbg_pc_eoq,
- PC_SUB_SIZE_OUT => dbg_pc_sub_size,
- PC_TRIG_NR_OUT => dbg_pc_trig_nr,
- PC_TRIGGER_TYPE_OUT => dbg_pc_trig_type,
- MONITOR_OUT => open,
- DEBUG_OUT => open
- );
-
- end generate no_readout_gen;
-
-
---who cares about an unused channel?
- THE_IOBUF_2 : trb_net16_term_buf
- port map (
- -- Misc
- CLK => CLK ,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(4),
- MED_INIT_DATA_OUT => io_data_out(79 downto 64),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12),
- MED_INIT_READ_IN => io_read_in(4),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(5),
- MED_REPLY_DATA_OUT => io_data_out(95 downto 80),
- MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15),
- MED_REPLY_READ_IN => io_read_in(5),
-
- MED_DATAREADY_IN => io_dataready_in(2),
- MED_DATA_IN => io_data_in(47 downto 32),
- MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6),
- MED_READ_OUT => io_read_out(2)
- );
-
---iobuf towards slow control channel
- THE_IOBUF_3 : trb_net16_iobuf
- generic map(
- IBUF_DEPTH => 6,
- USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3),
- USE_CHECKSUM => cfg_USE_CHECKSUM(3),
- INIT_CAN_SEND_DATA => c_NO,--MII_IS_DOWNLINK(mii),
- INIT_CAN_RECEIVE_DATA => c_YES,--MII_IS_UPLINK(mii),
- REPLY_CAN_SEND_DATA => c_YES,--MII_IS_UPLINK(mii),
- REPLY_CAN_RECEIVE_DATA => c_NO--MII_IS_DOWNLINK(mii)
- )
- port map(
- -- Misc
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- -- Media direction port
- MED_INIT_DATAREADY_OUT => io_dataready_out(6),
- MED_INIT_DATA_OUT => io_data_out(111 downto 96),
- MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18),
- MED_INIT_READ_IN => io_read_in(6),
-
- MED_REPLY_DATAREADY_OUT => io_dataready_out(7),
- MED_REPLY_DATA_OUT => io_data_out(127 downto 112),
- MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21),
- MED_REPLY_READ_IN => io_read_in(7),
-
- MED_DATAREADY_IN => io_dataready_in(3),
- MED_DATA_IN => io_data_in(63 downto 48),
- MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9),
- MED_READ_OUT => io_read_out(3),
- MED_ERROR_IN => io_error_in,
-
- -- Internal direction port
-
- INT_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT,
- INT_INIT_DATA_OUT => GSC_INIT_DATA_OUT,
- INT_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT,
- INT_INIT_READ_IN => GSC_INIT_READ_IN,
-
- INT_INIT_DATAREADY_IN => '0',
- INT_INIT_DATA_IN => (others => '0'),
- INT_INIT_PACKET_NUM_IN => (others => '0'),
- INT_INIT_READ_OUT => open,
-
- INT_REPLY_DATAREADY_OUT => open,
- INT_REPLY_DATA_OUT => open,
- INT_REPLY_PACKET_NUM_OUT => open,
- INT_REPLY_READ_IN => '1',
-
- INT_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN,
- INT_REPLY_DATA_IN => GSC_REPLY_DATA_IN,
- INT_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN,
- INT_REPLY_READ_OUT => GSC_REPLY_READ_OUT,
-
- -- Status and control port
- STAT_GEN => open,
- STAT_IBUF_BUFFER => open,
- CTRL_GEN => (others => '0'),
- STAT_INIT_OBUF_DEBUG => open,
- STAT_REPLY_OBUF_DEBUG => open,
- TIMER_TICKS_IN => TIMER_TICKS_IN
- );
-
-
----------------------------------------------------------------------
--- Multiplexer
----------------------------------------------------------------------
- MPLEX: trb_net16_io_multiplexer
- port map (
- CLK => CLK,
- RESET => reset_i_mux_io,
- CLK_EN => CLK_EN,
- MED_DATAREADY_IN => MEDIA_MED2INT(0).dataready,
- MED_DATA_IN => MEDIA_MED2INT(0).data,
- MED_PACKET_NUM_IN => MEDIA_MED2INT(0).packet_num,
- MED_READ_OUT => open,
- MED_DATAREADY_OUT => MEDIA_INT2MED(0).dataready,
- MED_DATA_OUT => MEDIA_INT2MED(0).data,
- MED_PACKET_NUM_OUT => MEDIA_INT2MED(0).packet_num,
- MED_READ_IN => MEDIA_MED2INT(0).tx_read,
- INT_DATAREADY_OUT => io_dataready_in,
- INT_DATA_OUT => io_data_in,
- INT_PACKET_NUM_OUT => io_packet_num_in,
- INT_READ_IN => io_read_out,
- INT_DATAREADY_IN => io_dataready_out,
- INT_DATA_IN => io_data_out,
- INT_PACKET_NUM_IN => io_packet_num_out,
- INT_READ_OUT => io_read_in,
- CTRL => (others => '0'),
- STAT => open
- );
- io_error_in <= MEDIA_MED2INT(0).stat_op(2 downto 0);
-
-
- SETUP : gbe_setup
- port map(
- CLK => CLK,
- RESET => reset_i_mux_io,
-
- -- interface to regio bus
- BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0),
- BUS_DATA_IN => BUS_REG_RX.data,
- BUS_DATA_OUT => BUS_REG_TX.data,
- BUS_WRITE_EN_IN => BUS_REG_RX.write,
- BUS_READ_EN_IN => BUS_REG_RX.read,
- BUS_ACK_OUT => BUS_REG_TX.ack,
-
- -- output to gbe_buf
- GBE_SUBEVENT_ID_OUT => cfg_subevent_id,
- GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec,
- GBE_QUEUE_DEC_OUT => cfg_queue_dec,
- GBE_MAX_FRAME_OUT => cfg_max_frame,
- GBE_USE_GBE_OUT => cfg_gbe_enable,
- GBE_USE_TRBNET_OUT => cfg_ipu_enable,
- GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable,
- GBE_READOUT_CTR_OUT => cfg_readout_ctr,
- GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid,
- GBE_ALLOW_RX_OUT => cfg_allow_rx,
- GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr,
- GBE_INSERT_TTYPE_OUT => cfg_insert_ttype,
- GBE_SOFT_RESET_OUT => cfg_soft_rst,
- GBE_MAX_REPLY_OUT => open, -- is for SLWCNTR
- GBE_MAX_SUB_OUT => cfg_max_sub,
- GBE_MAX_QUEUE_OUT => cfg_max_queue,
- GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue,
- GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
- GBE_AUTOTHROTTLE_OUT => open,
- GBE_THROTTLE_PAUSE_OUT => open,
- MONITOR_RX_BYTES_IN => (others => '0'), --sum_rx_bytes,
- MONITOR_RX_FRAMES_IN => (others => '0'), --sum_rx_frames,
- MONITOR_TX_BYTES_IN => (others => '0'), --sum_tx_bytes,
- MONITOR_TX_FRAMES_IN => (others => '0'), --sum_tx_frames,
- MONITOR_TX_PACKETS_IN => (others => '0'), --sum_tx_packets,
- MONITOR_DROPPED_IN => (others => '0'), --sum_dropped,
- MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec,
- MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes,
- MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes,
- MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent,
- MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in,
- MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out,
- MONITOR_SELECT_GEN_DBG_IN => (others => '0'), --monitor_gen_dbg, --dbg_select_gen,
-
- DUMMY_EVENT_SIZE_OUT => open,--dummy_event,
- DUMMY_TRIGGERED_MODE_OUT => open,
- DATA_HIST_IN => (others => (others => '0')), --dbg_hist,
- SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2
- );
-
-
- debug_gen : if INCLUDE_READOUT = 0 generate
-
- THE_CTS_READOUT_FINISHED_CNT : process begin
- wait until rising_edge(CLK);
-
- if RESET = '1' then
- last_cts_readout_finished <= '0';
- last_cts_readout_start <= '0';
-
- last_dbg_pc_wr_en <= '0';
- last_dbg_pc_sos <= '0';
- last_dbg_pc_eos <= '0';
- last_dbg_pc_eoq <= '0';
-
- readout_finished_cnt <= 0;
- readout_start_cnt <= 0;
-
- dbg_pc_wr_en_cnt <= 0;
- dbg_pc_sos_cnt <= 0;
- dbg_pc_eos_cnt <= 0;
- dbg_pc_eoq_cnt <= 0;
- else
- last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT;
- last_cts_readout_start <= CTS_START_READOUT_IN;
- if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then
- readout_finished_cnt <= readout_finished_cnt + 1;
- end if;
-
- if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then
- readout_start_cnt <= readout_start_cnt + 1;
- end if;
-
- -------------------
-
- last_dbg_pc_wr_en <= dbg_pc_wr_en;
- if ((dbg_pc_wr_en and (not last_dbg_pc_wr_en)) = '1') then
- dbg_pc_wr_en_cnt <= dbg_pc_wr_en_cnt + 1;
- end if;
-
- last_dbg_pc_sos <= dbg_pc_sos;
- if ((dbg_pc_sos and (not last_dbg_pc_sos)) = '1') then
- dbg_pc_sos_cnt <= dbg_pc_sos_cnt + 1;
- end if;
-
- last_dbg_pc_eos <= dbg_pc_eos;
- if ((dbg_pc_eos and (not last_dbg_pc_eos)) = '1') then
- dbg_pc_eos_cnt <= dbg_pc_eos_cnt + 1;
- end if;
-
- last_dbg_pc_eoq <= dbg_pc_eoq;
- if ((dbg_pc_eoq and (not last_dbg_pc_eoq)) = '1') then
- dbg_pc_eoq_cnt <= dbg_pc_eoq_cnt + 1;
- end if;
-
- -------------------
- end if;
- end process;
-
-
- THE_CRI_READOUT_DEBUG : process begin
- wait until rising_edge(CLK);
- BUS_DBG_TX.ack <= '0';
- BUS_DBG_TX.nack <= '0';
- BUS_DBG_TX.unknown <= '0';
-
- if BUS_DBG_RX.read = '1' then
- if BUS_DBG_RX.addr(7 downto 0) = x"00" then
- BUS_DBG_TX.data <= debug_resp_control(31 downto 0);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"01" then
- BUS_DBG_TX.data <= debug_resp_control(63 downto 32);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"02" then
- BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN;
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"03" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt);
- BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable;
- BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable;
- BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable;
- BUS_DBG_TX.data(31 downto 28) <= "0000";
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"04" then
- BUS_DBG_TX.data(7 downto 0) <= dbg_pc_data;
- BUS_DBG_TX.data(15 downto 8) <= x"00";
- BUS_DBG_TX.data(19 downto 16) <= dbg_pc_trig_type;
- BUS_DBG_TX.data(23 downto 20) <= x"0";
- BUS_DBG_TX.data(24) <= dbg_pc_wr_en;
- BUS_DBG_TX.data(25) <= dbg_pc_sos;
- BUS_DBG_TX.data(26) <= dbg_pc_eos;
- BUS_DBG_TX.data(27) <= dbg_pc_eoq;
- BUS_DBG_TX.data(31 downto 28) <= x"0";
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"05" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_wr_en_cnt);
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_sos_cnt);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"06" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_eos_cnt);
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_eoq_cnt);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- elsif BUS_DBG_RX.write = '1' then
-
--- if BUS_DBG_RX.addr( 7 downto 0) = x"00" then
--- dbg_start_data_send <= BUS_DBG_RX.data(0);
--- end if;
---
--- BUS_DBG_TX.ack <= '1';
- end if;
- end process;
- end generate debug_gen;
-
-debug_gen : if INCLUDE_READOUT = 1 generate
-
-
- THE_CRI_READOUT_DEBUG : process begin
- wait until rising_edge(CLK);
- BUS_DBG_TX.ack <= '0';
- BUS_DBG_TX.nack <= '0';
- BUS_DBG_TX.unknown <= '0';
-
- if BUS_DBG_RX.read = '1' then
- if BUS_DBG_RX.addr(7 downto 0) = x"00" then
- BUS_DBG_TX.data <= debug_sender(31 downto 0);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"01" then
- BUS_DBG_TX.data(0) <= dbg_start_data_send;
- BUS_DBG_tX.data(31 downto 1) <= (others => '0');
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"02" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_2);
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_3);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"03" then
- BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_6);
- BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_7);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"04" then
- BUS_DBG_TX.data <= debug_sender(63 downto 32);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"05" then
- BUS_DBG_TX.data <= debug_sender(95 downto 64);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"06" then
- BUS_DBG_TX.data <= debug_sender(127 downto 96);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"07" then
- BUS_DBG_TX.data <= debug_sender(159 downto 128);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- if BUS_DBG_RX.addr(7 downto 0) = x"08" then
- BUS_DBG_TX.data <= debug_sender(191 downto 160);
- BUS_DBG_TX.ack <= '1';
- end if;
-
- elsif BUS_DBG_RX.write = '1' then
-
- if BUS_DBG_RX.addr( 7 downto 0) = x"01" then
- dbg_start_data_send <= BUS_DBG_RX.data(0);
- BUS_DBG_TX.ack <= '1';
- end if;
-
-
- end if;
- end process;
- end generate debug_gen;
-
-end architecture;
-
-
-
jspc29 / dirich.git / commitdiff