--- /dev/null
+
+--
+-- Verific VHDL Description of module DCUA
+--
+
+-- DCUA is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_0rsl_core
+--
+
+-- serdes_sync_0rsl_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_0sll_core
+--
+
+-- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it
+
+--
+-- Verific VHDL Description of module serdes_sync_0
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+library ecp5um ;
+use ecp5um.components.all ;
+
+entity serdes_sync_0 is
+ port (hdoutp: out std_logic;
+ hdoutn: out std_logic;
+ hdinp: in std_logic;
+ hdinn: in std_logic;
+ rxrefclk: in std_logic;
+ rx_pclk: out std_logic;
+ tx_pclk: out std_logic;
+ txdata: in std_logic_vector(7 downto 0);
+ tx_k: in std_logic_vector(0 downto 0);
+ tx_force_disp: in std_logic_vector(0 downto 0);
+ tx_disp_sel: in std_logic_vector(0 downto 0);
+ rxdata: out std_logic_vector(7 downto 0);
+ rx_k: out std_logic_vector(0 downto 0);
+ rx_disp_err: out std_logic_vector(0 downto 0);
+ rx_cv_err: out std_logic_vector(0 downto 0);
+ tx_idle_c: in std_logic;
+ signal_detect_c: in std_logic;
+ rx_los_low_s: out std_logic;
+ lsm_status_s: out std_logic;
+ rx_cdr_lol_s: out std_logic;
+ sli_rst: in std_logic;
+ tx_pwrup_c: in std_logic;
+ rx_pwrup_c: in std_logic;
+ sci_wrdata: in std_logic_vector(7 downto 0);
+ sci_addr: in std_logic_vector(5 downto 0);
+ sci_rddata: out std_logic_vector(7 downto 0);
+ sci_en_dual: in std_logic;
+ sci_sel_dual: in std_logic;
+ sci_en: in std_logic;
+ sci_sel: in std_logic;
+ sci_rd: in std_logic;
+ sci_wrn: in std_logic;
+ sci_int: out std_logic;
+ cyawstn: in std_logic;
+ serdes_pdb: in std_logic;
+ pll_refclki: in std_logic;
+ rsl_disable: in std_logic;
+ rsl_rst: in std_logic;
+ serdes_rst_dual_c: in std_logic;
+ rst_dual_c: in std_logic;
+ tx_serdes_rst_c: in std_logic;
+ tx_pcs_rst_c: in std_logic;
+ pll_lol: out std_logic;
+ rsl_tx_rdy: out std_logic;
+ rx_serdes_rst_c: in std_logic;
+ rx_pcs_rst_c: in std_logic;
+ rsl_rx_rdy: out std_logic
+ );
+
+end entity serdes_sync_0;
+
+architecture v1 of serdes_sync_0 is
+ component serdes_sync_0rsl_core is
+ generic (pnum_channels: integer := 1;
+ pprotocol: string := "G8B10B";
+ pserdes_mode: string := "RX AND TX";
+ pport_tx_rdy: string := "ENABLED";
+ pwait_tx_rdy: integer := 3000;
+ pport_rx_rdy: string := "ENABLED";
+ pwait_rx_rdy: integer := 3000);
+ port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132)
+ rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133)
+ rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134)
+ rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135)
+ rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137)
+ rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138)
+ rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139)
+ rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140)
+ rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142)
+ rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143)
+ rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144)
+ rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145)
+ rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146)
+ rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149)
+ rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150)
+ ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152)
+ rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153)
+ rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154)
+ ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156)
+ rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157)
+ rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158)
+ );
+
+ end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88)
+ component serdes_sync_0sll_core is
+ generic (PPROTOCOL: string := "G8B10B";
+ PLOL_SETTING: integer := 1;
+ PDYN_RATE_CTRL: string := "DISABLED";
+ PPCIE_MAX_RATE: string := "2.5";
+ PDIFF_VAL_LOCK: integer := 20;
+ PDIFF_VAL_UNLOCK: integer := 132;
+ PPCLK_TC: integer := 65536;
+ PDIFF_DIV11_VAL_LOCK: integer := 0;
+ PDIFF_DIV11_VAL_UNLOCK: integer := 0;
+ PPCLK_DIV11_TC: integer := 0);
+ port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(125)
+ sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(126)
+ sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(127)
+ sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(128)
+ sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(129)
+ sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(130)
+ sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(131)
+ sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(132)
+ slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(135)
+ );
+
+ end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.11_x64/ispfpga/sa5p00/data/sll_core_template.v(107)
+ signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
+ n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17,
+ n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c,
+ rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23,
+ n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
+ n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51,
+ n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,
+ n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,
+ n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,
+ n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114,
+ n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122,
+ n123,\_Z\,n127,n126,gnd,pwr : std_logic;
+ attribute LOC : string;
+ attribute LOC of DCU0_inst : label is "DCU0";
+ attribute CHAN : string;
+ attribute CHAN of DCU0_inst : label is "CH1";
+begin
+ rx_pclk <= rx_pclk_c;
+ tx_pclk <= tx_pclk_c;
+ rx_los_low_s <= rx_los_low_s_c;
+ rx_cdr_lol_s <= rx_cdr_lol_s_c;
+ pll_lol <= pll_lol_c;
+ DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
+ D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
+ D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+ D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
+ D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0",
+ CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0",
+ CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0",
+ CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0",
+ CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0",
+ CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0",
+ CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1",
+ CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0",
+ CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC",
+ CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C",
+ CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C",
+ CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1",
+ CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00",
+ CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00",
+ CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01",
+ CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000",
+ CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01",
+ CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0",
+ CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0",
+ CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0",
+ CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0",
+ CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00",
+ CH1_REQ_EN=>"0b0",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1",
+ CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000",
+ CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b000",CH1_RX_LOS_CEQ=>"0b11",
+ CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0",
+ CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2",
+ CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED",
+ CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01",
+ D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001",
+ D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00",
+ CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00",
+ CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b000",CH1_DCOCTLGI=>"0b011",
+ CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b00",CH1_DCOFTNRG=>"0b001",
+ CH1_DCOIOSTUNE=>"0b010",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b010",
+ CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b100",CH1_DCOSCALEI=>"0b01",
+ CH1_DCOSTARTVAL=>"0b010",CH1_DCOSTEP=>"0b11",CH1_BAND_THRESHOLD=>"0d0",
+ CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0",
+ CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0",
+ CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00",
+ D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000",
+ D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101",
+ D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10",
+ D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01",
+ D_RG_EN=>"0b0",D_RG_SET=>"0b00")
+ port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn,
+ D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47,
+ CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c,
+ CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105,
+ CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106,
+ CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2),
+ CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4),
+ CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6),
+ CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0),
+ CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106,
+ CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47,
+ CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106,
+ CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106,
+ CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106,
+ CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106,
+ CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106,
+ CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47,
+ CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106,
+ CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106,
+ CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106,
+ CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106,
+ CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47,
+ CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106,
+ CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106,
+ CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106,
+ CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47,
+ CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106,
+ CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c,
+ CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106,
+ CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c,
+ CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106,
+ CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1),
+ D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4),
+ D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7),
+ D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2),
+ D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5),
+ D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en,
+ CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn,
+ D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c,
+ D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c,
+ CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47,
+ D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47,
+ D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47,
+ D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47,
+ D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47,
+ D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp,
+ CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2,
+ D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5,
+ CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7,
+ CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c,
+ CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0),
+ CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2),
+ CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4),
+ CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6),
+ CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0),
+ CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68,
+ CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70,
+ CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74,
+ CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78,
+ CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82,
+ CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86,
+ CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90,
+ CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93,
+ CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95,
+ CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s,
+ CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98,
+ CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15,
+ CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101,
+ CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17,
+ CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104,
+ CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1),
+ D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4),
+ D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7),
+ D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21,
+ D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25,
+ D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30,
+ D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36,
+ D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41,
+ D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46,
+ D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49);
+ n48 <= '1' ;
+ n47 <= '0' ;
+ n1 <= 'Z' ;
+ n2 <= 'Z' ;
+ n3 <= 'Z' ;
+ n4 <= 'Z' ;
+ n5 <= 'Z' ;
+ n6 <= 'Z' ;
+ n7 <= 'Z' ;
+ n8 <= 'Z' ;
+ n9 <= 'Z' ;
+ n10 <= 'Z' ;
+ n11 <= 'Z' ;
+ n12 <= 'Z' ;
+ n13 <= 'Z' ;
+ n14 <= 'Z' ;
+ n15 <= 'Z' ;
+ n16 <= 'Z' ;
+ n17 <= 'Z' ;
+ n18 <= 'Z' ;
+ n19 <= 'Z' ;
+ n20 <= 'Z' ;
+ n21 <= 'Z' ;
+ n22 <= 'Z' ;
+ n23 <= 'Z' ;
+ n24 <= 'Z' ;
+ n25 <= 'Z' ;
+ n26 <= 'Z' ;
+ n27 <= 'Z' ;
+ n28 <= 'Z' ;
+ n29 <= 'Z' ;
+ n30 <= 'Z' ;
+ n31 <= 'Z' ;
+ n32 <= 'Z' ;
+ n33 <= 'Z' ;
+ n34 <= 'Z' ;
+ n35 <= 'Z' ;
+ n36 <= 'Z' ;
+ n37 <= 'Z' ;
+ n38 <= 'Z' ;
+ n39 <= 'Z' ;
+ n40 <= 'Z' ;
+ n41 <= 'Z' ;
+ n42 <= 'Z' ;
+ n43 <= 'Z' ;
+ n44 <= 'Z' ;
+ n45 <= 'Z' ;
+ n46 <= 'Z' ;
+ n49 <= 'Z' ;
+ n106 <= '0' ;
+ n105 <= '1' ;
+ n50 <= 'Z' ;
+ n51 <= 'Z' ;
+ n52 <= 'Z' ;
+ n53 <= 'Z' ;
+ n54 <= 'Z' ;
+ n55 <= 'Z' ;
+ n56 <= 'Z' ;
+ n57 <= 'Z' ;
+ n58 <= 'Z' ;
+ n59 <= 'Z' ;
+ n60 <= 'Z' ;
+ n61 <= 'Z' ;
+ n62 <= 'Z' ;
+ n63 <= 'Z' ;
+ n64 <= 'Z' ;
+ n65 <= 'Z' ;
+ n66 <= 'Z' ;
+ n67 <= 'Z' ;
+ n68 <= 'Z' ;
+ n69 <= 'Z' ;
+ n70 <= 'Z' ;
+ n71 <= 'Z' ;
+ n72 <= 'Z' ;
+ n73 <= 'Z' ;
+ n74 <= 'Z' ;
+ n75 <= 'Z' ;
+ n76 <= 'Z' ;
+ n77 <= 'Z' ;
+ n78 <= 'Z' ;
+ n79 <= 'Z' ;
+ n80 <= 'Z' ;
+ n81 <= 'Z' ;
+ n82 <= 'Z' ;
+ n83 <= 'Z' ;
+ n84 <= 'Z' ;
+ n85 <= 'Z' ;
+ n86 <= 'Z' ;
+ n87 <= 'Z' ;
+ n88 <= 'Z' ;
+ n89 <= 'Z' ;
+ n90 <= 'Z' ;
+ n91 <= 'Z' ;
+ n92 <= 'Z' ;
+ n93 <= 'Z' ;
+ n94 <= 'Z' ;
+ n95 <= 'Z' ;
+ n96 <= 'Z' ;
+ n97 <= 'Z' ;
+ n98 <= 'Z' ;
+ n99 <= 'Z' ;
+ n100 <= 'Z' ;
+ n101 <= 'Z' ;
+ n102 <= 'Z' ;
+ n103 <= 'Z' ;
+ n104 <= 'Z' ;
+ n115 <= 'Z' ;
+ rsl_inst: component serdes_sync_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c,
+ rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki,
+ rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125,
+ rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c,
+ rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125,
+ rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c,
+ rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125,
+ rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125,
+ rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c,
+ rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125,
+ rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c,
+ rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c,
+ rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118,
+ rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119,
+ rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c,
+ rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\,
+ rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c);
+ n114 <= '1' ;
+ n113 <= '0' ;
+ n125 <= '0' ;
+ n124 <= '1' ;
+ n116 <= 'Z' ;
+ n117 <= 'Z' ;
+ n118 <= 'Z' ;
+ n119 <= 'Z' ;
+ n120 <= 'Z' ;
+ n121 <= 'Z' ;
+ n122 <= 'Z' ;
+ n123 <= 'Z' ;
+ \_Z\ <= 'Z' ;
+ sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki,
+ sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd,
+ sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd,
+ sli_pcie_mode=>gnd,slo_plol=>pll_lol_c);
+ n127 <= '1' ;
+ n126 <= '0' ;
+ gnd <= '0' ;
+ pwr <= '1' ;
+
+end architecture v1;
+
--- /dev/null
+
+
+--
+-- Verific VHDL Description of module pcs
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity pcs is
+ port (serdes_sync_0_rx_cv_err: out std_logic_vector(0 downto 0);
+ serdes_sync_0_rx_disp_err: out std_logic_vector(0 downto 0);
+ serdes_sync_0_rx_k: out std_logic_vector(0 downto 0);
+ serdes_sync_0_rxdata: out std_logic_vector(7 downto 0);
+ serdes_sync_0_sci_addr: in std_logic_vector(5 downto 0);
+ serdes_sync_0_sci_rddata: out std_logic_vector(7 downto 0);
+ serdes_sync_0_sci_wrdata: in std_logic_vector(7 downto 0);
+ serdes_sync_0_tx_disp_sel: in std_logic_vector(0 downto 0);
+ serdes_sync_0_tx_force_disp: in std_logic_vector(0 downto 0);
+ serdes_sync_0_tx_k: in std_logic_vector(0 downto 0);
+ serdes_sync_0_txdata: in std_logic_vector(7 downto 0);
+ serdes_sync_0_cyawstn: in std_logic;
+ serdes_sync_0_hdinn: in std_logic;
+ serdes_sync_0_hdinp: in std_logic;
+ serdes_sync_0_hdoutn: out std_logic;
+ serdes_sync_0_hdoutp: out std_logic;
+ serdes_sync_0_lsm_status_s: out std_logic;
+ serdes_sync_0_pll_lol: out std_logic;
+ serdes_sync_0_pll_refclki: in std_logic;
+ serdes_sync_0_rsl_disable: in std_logic;
+ serdes_sync_0_rsl_rst: in std_logic;
+ serdes_sync_0_rsl_rx_rdy: out std_logic;
+ serdes_sync_0_rsl_tx_rdy: out std_logic;
+ serdes_sync_0_rst_dual_c: in std_logic;
+ serdes_sync_0_rx_cdr_lol_s: out std_logic;
+ serdes_sync_0_rx_los_low_s: out std_logic;
+ serdes_sync_0_rx_pclk: out std_logic;
+ serdes_sync_0_rx_pcs_rst_c: in std_logic;
+ serdes_sync_0_rx_pwrup_c: in std_logic;
+ serdes_sync_0_rx_serdes_rst_c: in std_logic;
+ serdes_sync_0_rxrefclk: in std_logic;
+ serdes_sync_0_sci_en: in std_logic;
+ serdes_sync_0_sci_en_dual: in std_logic;
+ serdes_sync_0_sci_int: out std_logic;
+ serdes_sync_0_sci_rd: in std_logic;
+ serdes_sync_0_sci_sel: in std_logic;
+ serdes_sync_0_sci_sel_dual: in std_logic;
+ serdes_sync_0_sci_wrn: in std_logic;
+ serdes_sync_0_serdes_pdb: in std_logic;
+ serdes_sync_0_serdes_rst_dual_c: in std_logic;
+ serdes_sync_0_signal_detect_c: in std_logic;
+ serdes_sync_0_tx_idle_c: in std_logic;
+ serdes_sync_0_tx_pclk: out std_logic;
+ serdes_sync_0_tx_pcs_rst_c: in std_logic;
+ serdes_sync_0_tx_pwrup_c: in std_logic;
+ serdes_sync_0_tx_serdes_rst_c: in std_logic
+ );
+
+end entity pcs; -- sbp_module=true
+
+architecture pcs of pcs is
+ component serdes_sync_0 is
+ port (rx_cv_err: out std_logic_vector(0 downto 0);
+ rx_disp_err: out std_logic_vector(0 downto 0);
+ rx_k: out std_logic_vector(0 downto 0);
+ rxdata: out std_logic_vector(7 downto 0);
+ sci_addr: in std_logic_vector(5 downto 0);
+ sci_rddata: out std_logic_vector(7 downto 0);
+ sci_wrdata: in std_logic_vector(7 downto 0);
+ tx_disp_sel: in std_logic_vector(0 downto 0);
+ tx_force_disp: in std_logic_vector(0 downto 0);
+ tx_k: in std_logic_vector(0 downto 0);
+ txdata: in std_logic_vector(7 downto 0);
+ cyawstn: in std_logic;
+ hdinn: in std_logic;
+ hdinp: in std_logic;
+ hdoutn: out std_logic;
+ hdoutp: out std_logic;
+ lsm_status_s: out std_logic;
+ pll_lol: out std_logic;
+ pll_refclki: in std_logic;
+ rsl_disable: in std_logic;
+ rsl_rst: in std_logic;
+ rsl_rx_rdy: out std_logic;
+ rsl_tx_rdy: out std_logic;
+ rst_dual_c: in std_logic;
+ rx_cdr_lol_s: out std_logic;
+ rx_los_low_s: out std_logic;
+ rx_pclk: out std_logic;
+ rx_pcs_rst_c: in std_logic;
+ rx_pwrup_c: in std_logic;
+ rx_serdes_rst_c: in std_logic;
+ rxrefclk: in std_logic;
+ sci_en: in std_logic;
+ sci_en_dual: in std_logic;
+ sci_int: out std_logic;
+ sci_rd: in std_logic;
+ sci_sel: in std_logic;
+ sci_sel_dual: in std_logic;
+ sci_wrn: in std_logic;
+ serdes_pdb: in std_logic;
+ serdes_rst_dual_c: in std_logic;
+ signal_detect_c: in std_logic;
+ sli_rst: in std_logic;
+ tx_idle_c: in std_logic;
+ tx_pclk: out std_logic;
+ tx_pcs_rst_c: in std_logic;
+ tx_pwrup_c: in std_logic;
+ tx_serdes_rst_c: in std_logic
+ );
+
+ end component serdes_sync_0; -- not_need_bbox=true
+
+
+ signal sli_rst_wire0,gnd : std_logic;
+begin
+ sli_rst_wire0 <= serdes_sync_0_serdes_rst_dual_c OR serdes_sync_0_tx_serdes_rst_c OR (NOT serdes_sync_0_serdes_pdb) OR (NOT serdes_sync_0_tx_pwrup_c);
+ serdes_sync_0_inst: component serdes_sync_0 port map (rx_cv_err(0)=>serdes_sync_0_rx_cv_err(0),
+ rx_disp_err(0)=>serdes_sync_0_rx_disp_err(0),rx_k(0)=>serdes_sync_0_rx_k(0),
+ rxdata(7)=>serdes_sync_0_rxdata(7),rxdata(6)=>serdes_sync_0_rxdata(6),
+ rxdata(5)=>serdes_sync_0_rxdata(5),rxdata(4)=>serdes_sync_0_rxdata(4),
+ rxdata(3)=>serdes_sync_0_rxdata(3),rxdata(2)=>serdes_sync_0_rxdata(2),
+ rxdata(1)=>serdes_sync_0_rxdata(1),rxdata(0)=>serdes_sync_0_rxdata(0),
+ sci_addr(5)=>serdes_sync_0_sci_addr(5),sci_addr(4)=>serdes_sync_0_sci_addr(4),
+ sci_addr(3)=>serdes_sync_0_sci_addr(3),sci_addr(2)=>serdes_sync_0_sci_addr(2),
+ sci_addr(1)=>serdes_sync_0_sci_addr(1),sci_addr(0)=>serdes_sync_0_sci_addr(0),
+ sci_rddata(7)=>serdes_sync_0_sci_rddata(7),sci_rddata(6)=>serdes_sync_0_sci_rddata(6),
+ sci_rddata(5)=>serdes_sync_0_sci_rddata(5),sci_rddata(4)=>serdes_sync_0_sci_rddata(4),
+ sci_rddata(3)=>serdes_sync_0_sci_rddata(3),sci_rddata(2)=>serdes_sync_0_sci_rddata(2),
+ sci_rddata(1)=>serdes_sync_0_sci_rddata(1),sci_rddata(0)=>serdes_sync_0_sci_rddata(0),
+ sci_wrdata(7)=>serdes_sync_0_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_0_sci_wrdata(6),
+ sci_wrdata(5)=>serdes_sync_0_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_0_sci_wrdata(4),
+ sci_wrdata(3)=>serdes_sync_0_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_0_sci_wrdata(2),
+ sci_wrdata(1)=>serdes_sync_0_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_0_sci_wrdata(0),
+ tx_disp_sel(0)=>serdes_sync_0_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_0_tx_force_disp(0),
+ tx_k(0)=>serdes_sync_0_tx_k(0),txdata(7)=>serdes_sync_0_txdata(7),
+ txdata(6)=>serdes_sync_0_txdata(6),txdata(5)=>serdes_sync_0_txdata(5),
+ txdata(4)=>serdes_sync_0_txdata(4),txdata(3)=>serdes_sync_0_txdata(3),
+ txdata(2)=>serdes_sync_0_txdata(2),txdata(1)=>serdes_sync_0_txdata(1),
+ txdata(0)=>serdes_sync_0_txdata(0),cyawstn=>serdes_sync_0_cyawstn,
+ hdinn=>serdes_sync_0_hdinn,hdinp=>serdes_sync_0_hdinp,hdoutn=>serdes_sync_0_hdoutn,
+ hdoutp=>serdes_sync_0_hdoutp,lsm_status_s=>serdes_sync_0_lsm_status_s,
+ pll_lol=>serdes_sync_0_pll_lol,pll_refclki=>serdes_sync_0_pll_refclki,
+ rsl_disable=>serdes_sync_0_rsl_disable,rsl_rst=>serdes_sync_0_rsl_rst,
+ rsl_rx_rdy=>serdes_sync_0_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_0_rsl_tx_rdy,
+ rst_dual_c=>serdes_sync_0_rst_dual_c,rx_cdr_lol_s=>serdes_sync_0_rx_cdr_lol_s,
+ rx_los_low_s=>serdes_sync_0_rx_los_low_s,rx_pclk=>serdes_sync_0_rx_pclk,
+ rx_pcs_rst_c=>serdes_sync_0_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_0_rx_pwrup_c,
+ rx_serdes_rst_c=>serdes_sync_0_rx_serdes_rst_c,rxrefclk=>serdes_sync_0_rxrefclk,
+ sci_en=>serdes_sync_0_sci_en,sci_en_dual=>serdes_sync_0_sci_en_dual,
+ sci_int=>serdes_sync_0_sci_int,sci_rd=>serdes_sync_0_sci_rd,sci_sel=>serdes_sync_0_sci_sel,
+ sci_sel_dual=>serdes_sync_0_sci_sel_dual,sci_wrn=>serdes_sync_0_sci_wrn,
+ serdes_pdb=>serdes_sync_0_serdes_pdb,serdes_rst_dual_c=>serdes_sync_0_serdes_rst_dual_c,
+ signal_detect_c=>serdes_sync_0_signal_detect_c,sli_rst=>sli_rst_wire0,
+ tx_idle_c=>serdes_sync_0_tx_idle_c,tx_pclk=>serdes_sync_0_tx_pclk,
+ tx_pcs_rst_c=>serdes_sync_0_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_0_tx_pwrup_c,
+ tx_serdes_rst_c=>serdes_sync_0_tx_serdes_rst_c);
+ gnd <= '0' ;
+
+end architecture pcs; -- sbp_module=true
+
+++ /dev/null
-<!DOCTYPE serdes_sync_0>
-<lattice:project mode="SingleComponent">
- <spirit:component>
- <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
- <spirit:library>LEGACY</spirit:library>
- <spirit:name>PCS</spirit:name>
- <spirit:version>8.2</spirit:version>
- <spirit:fileSets>
- <spirit:fileset>
- <spirit:name>Diamond_Simulation</spirit:name>
- <spirit:group>simulation</spirit:group>
- <spirit:file>
- <spirit:name>./serdes_sync_0_softlogic.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>./serdes_sync_0.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileset>
- <spirit:fileset>
- <spirit:name>Diamond_Synthesis</spirit:name>
- <spirit:group>synthesis</spirit:group>
- <spirit:file>
- <spirit:name>./serdes_sync_0_softlogic.v</spirit:name>
- <spirit:fileType>verilogSource</spirit:fileType>
- </spirit:file>
- <spirit:file>
- <spirit:name>./serdes_sync_0.vhd</spirit:name>
- <spirit:fileType>vhdlSource</spirit:fileType>
- </spirit:file>
- </spirit:fileset>
- </spirit:fileSets>
- <spirit:componentGenerators>
- <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
- <spirit:name>Configuration</spirit:name>
- <spirit:apiType>none</spirit:apiType>
- <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
- <spirit:group>CONFIG</spirit:group>
- </spirit:componentGenerator>
- <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
- <spirit:name>Generation</spirit:name>
- <spirit:apiType>none</spirit:apiType>
- <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
- <spirit:group>GENERATE</spirit:group>
- </spirit:componentGenerator>
- </spirit:componentGenerators>
- <spirit:model>
- <spirit:views/>
- <spirit:ports/>
- </spirit:model>
- <spirit:vendorExtensions>
- <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
- <lattice:synthesis>synplify</lattice:synthesis>
- <lattice:date>2016-01-04.02:14:28 PM</lattice:date>
- <lattice:modified>2019-04-24.16:52:40</lattice:modified>
- <lattice:diamond>3.10.3.144</lattice:diamond>
- <lattice:language>VHDL</lattice:language>
- <lattice:attributes>
- <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
- <lattice:attribute lattice:name="BBox">false</lattice:attribute>
- <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangePack">true</lattice:attribute>
- <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
- <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
- <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
- <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
- <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
- <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
- <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
- </lattice:attributes>
- <lattice:elements>
- <lattice:element>
- <lattice:name>Lane0</lattice:name>
- <lattice:type>DCUCHANNEL</lattice:type>
- <lattice:attributes>
- <lattice:attribute lattice:name="ElementDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="ElementHide">false</lattice:attribute>
- <lattice:attribute lattice:name="ElementType">DCUCHANNEL</lattice:attribute>
- </lattice:attributes>
- </lattice:element>
- </lattice:elements>
- <lattice:lpc>
- <lattice:lpcsection lattice:name="Device"/>
- <lattice:lpcentry>
- <lattice:lpckey>Family</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>OperatingCondition</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Package</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PartName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PartType</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SpeedGrade</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Status</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="IP"/>
- <lattice:lpcentry>
- <lattice:lpckey>CoreName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">PCS</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreRevision</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8.2</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreStatus</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CoreType</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Date</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">04/24/2019</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ModuleName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">serdes_sync_0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SourceFormat</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Time</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">16:52:37</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>VendorName</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="Parameters"/>
- <lattice:lpcentry>
- <lattice:lpckey>;ACHARA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>;ACHARB</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>;ACHARM</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>;RXMCAENABLE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CDRLOLACTION</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Full Recalibration</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CDR_MULT</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CDR_REF_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>CH_MODE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Rx and Tx</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Destination</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>EDIF</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Expression</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>IO</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>IO_TYPE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>LEQ</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>LOOPBACK</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>LOSPORT</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>NUM_CHS</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Order</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PPORT_RX_RDY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PPORT_TX_RDY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PROTOCOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">G8B10B</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PWAIT_RX_RDY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>PWAIT_TX_RDY</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">3000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RCSRC</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>REFCLK_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RSTSEQSEL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RX8B10B</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCOMMAA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1100000100</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCOMMAB</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0011111000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCOMMAM</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1111111100</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCOUPLING</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTC</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTCBYTEN</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTCBYTEN1</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTCBYTEN2</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTCBYTEN3</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0 00H</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXCTCMATCHPATTERN</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">M4-S4</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXDIFFTERM</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXFIFO_ENABLE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXINVPOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXLDR</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXLOSTHRESHOLD</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXLSM</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXSC</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">K28P157</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RXWA</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Barrel Shift</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RX_DATA_WIDTH</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RX_FICLK_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RX_LINE_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>RX_RATE_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SCIPORT</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>SOFTLOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX8B10B</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXAMPLITUDE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">800</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXDEPOST</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXDEPRE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Disabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXDIFFTERM</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">50 ohms</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXFIFO_ENABLE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Enabled</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXINVPOL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Non-invert</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXLDR</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Off</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXPLLLOLTHRESHOLD</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TXPLLMULT</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">10X</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX_DATA_WIDTH</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">8/10-Bit</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX_FICLK_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">200.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX_LINE_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">2.0000</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX_MAX_RATE</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>TX_RATE_DIV</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">Full Rate</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>VHDL</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>Verilog</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcsection lattice:name="FilesGenerated"/>
- <lattice:lpcentry>
- <lattice:lpckey>serdes_sync_0.pp</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">pp</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>serdes_sync_0.sym</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">sym</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>serdes_sync_0.tft</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">tft</lattice:lpcvalue>
- </lattice:lpcentry>
- <lattice:lpcentry>
- <lattice:lpckey>serdes_sync_0.txt</lattice:lpckey>
- <lattice:lpcvalue lattice:resolve="constant">pcs_module</lattice:lpcvalue>
- </lattice:lpcentry>
- </lattice:lpc>
- <lattice:groups>
- <lattice:group>
- <lattice:name>DCUCHANNEL</lattice:name>
- <lattice:category>1</lattice:category>
- <lattice:attributes>
- <lattice:attribute lattice:name="GroupDrag">true</lattice:attribute>
- <lattice:attribute lattice:name="GroupHide">false</lattice:attribute>
- <lattice:attribute lattice:name="GroupType">DCUCHANNEL</lattice:attribute>
- </lattice:attributes>
- <lattice:elementref>Lane0</lattice:elementref>
- </lattice:group>
- </lattice:groups>
- </spirit:vendorExtensions>
- </spirit:component>
- <spirit:design>
- <spirit:vendor>LATTICE</spirit:vendor>
- <spirit:library>LOCAL</spirit:library>
- <spirit:name>serdes_sync_0</spirit:name>
- <spirit:version>1.0</spirit:version>
- <spirit:componentInstances/>
- <spirit:adHocConnections/>
- </spirit:design>
-</lattice:project>
jspc29 / trbnet.git / commitdiff