delay of data for more relaxed timing and preparaion for syn_keep

diff --git a/src/cri_cbm_rich_calib.vhd b/src/cri_cbm_rich_calib.vhd
index 3038ac441fe701e07c58b3e568dc0f35e8b6d2c4..90ecb7ad4037adda14d6839d409457525c2f7a4d 100644 (file)
--- a/src/cri_cbm_rich_calib.vhd
+++ b/src/cri_cbm_rich_calib.vhd
@@ -58,6 +58,12 @@ architecture cbm_rich_calib_arch of cbm_rich_calib is
   signal cri_apl_caldrdy_out                : std_logic;
   signal cri_apl_caleod_out                 : std_logic;
   
+  signal cri_cal_active_in                  : std_logic;    
+  signal cri_apl_caldata_in                 : std_logic_vector(15 downto 0);
+  signal cri_apl_calpacknum_in              : std_logic_vector( 2 downto 0);
+  signal cri_apl_caldrdy_in                 : std_logic;
+  signal cri_apl_caleod_in                  : std_logic;  
+  
   signal cri_apl_caldata_out_l              : std_logic_vector(15 downto 0);
   signal cri_apl_calpacknum_out_l           : std_logic_vector( 2 downto 0);
   signal cri_apl_caldrdy_out_l              : std_logic;
@@ -65,6 +71,48 @@ architecture cbm_rich_calib_arch of cbm_rich_calib is
   
   signal rec_state, cal_out_state_flg       : std_logic_vector( 3 downto 0);
   signal data_open_modelsim                 : std_logic_vector(23 downto 0); 
+  
+  attribute syn_keep                             : boolean; 
+  
+  attribute syn_keep of cri_apl_caldata_out      : signal is true;
+  attribute syn_keep of cri_apl_calpacknum_out   : signal is true;
+  attribute syn_keep of cri_apl_caldrdy_out      : signal is true;
+  attribute syn_keep of cri_apl_caleod_out       : signal is true;
+  
+  
+  attribute syn_keep of cri_cal_active_in        : signal is true;
+  attribute syn_keep of cri_apl_caldata_in       : signal is true;
+  attribute syn_keep of cri_apl_calpacknum_in    : signal is true;
+  attribute syn_keep of cri_apl_caldrdy_in       : signal is true;
+  attribute syn_keep of cri_apl_caleod_in        : signal is true;
+  
+  attribute syn_preserve                             : boolean; 
+  
+  attribute syn_preserve of cri_apl_caldata_out      : signal is true;
+  attribute syn_preserve of cri_apl_calpacknum_out   : signal is true;
+  attribute syn_preserve of cri_apl_caldrdy_out      : signal is true;
+  attribute syn_preserve of cri_apl_caleod_out       : signal is true;
+  
+  
+  attribute syn_preserve of cri_cal_active_in        : signal is true;
+  attribute syn_preserve of cri_apl_caldata_in       : signal is true;
+  attribute syn_preserve of cri_apl_calpacknum_in    : signal is true;
+  attribute syn_preserve of cri_apl_caldrdy_in       : signal is true;
+  attribute syn_preserve of cri_apl_caleod_in        : signal is true;
+  
+  attribute nomerge                              : string;
+  
+  attribute nomerge of cri_apl_caldata_out      : signal is "true";
+  attribute nomerge of cri_apl_calpacknum_out   : signal is "true";
+  attribute nomerge of cri_apl_caldrdy_out      : signal is "true";
+  attribute nomerge of cri_apl_caleod_out       : signal is "true";
+  
+  
+  attribute nomerge of cri_cal_active_in        : signal is "true";
+  attribute nomerge of cri_apl_caldata_in       : signal is "true";
+  attribute nomerge of cri_apl_calpacknum_in    : signal is "true";
+  attribute nomerge of cri_apl_caldrdy_in       : signal is "true";
+  attribute nomerge of cri_apl_caleod_in        : signal is "true";
 
 begin
 
@@ -83,6 +131,14 @@ begin
 --     end if;
 --   end process;
 
+
+  cri_cal_active_in      <= CRI_CAL_ACTIVE;
+  cri_apl_caldata_in     <= CRI_APL_DATA_IN;      
+  cri_apl_calpacknum_in  <= CRI_APL_PACKET_NUM_IN;
+  cri_apl_caldrdy_in     <= CRI_APL_DATAREADY_IN; 
+  cri_apl_caleod_in      <= CRI_CALIB_EOD_IN;     
+
+
   THE_CALIB_CHECK_MACHINE : process--(calib_current_state, CRI_CAL_ACTIVE, CRI_APL_DATAREADY_IN)
   begin
    wait until rising_edge(CLK);
@@ -97,7 +153,7 @@ begin
     case (calib_next_state) is
       when IDLE =>
           rec_state <= x"1";
-          if (CRI_CAL_ACTIVE = '1') then
+          if (cri_cal_active_in = '1') then
             calib_next_state <= TRIGGER_CODE;
           else
             calib_next_state <= IDLE;
@@ -105,11 +161,11 @@ begin
       
       when TRIGGER_CODE =>
           rec_state <= x"2";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_h           <= CRI_APL_DATA_IN;
-            pack_num_h       <= CRI_APL_PACKET_NUM_IN;
-            cal_eod_h        <= CRI_CALIB_EOD_IN;
-            trigger_code_i   <= CRI_APL_DATA_IN;
+          if (cri_apl_caldrdy_in = '1') then
+            data_h           <= cri_apl_caldata_in;
+            pack_num_h       <= cri_apl_calpacknum_in;
+            cal_eod_h        <= cri_apl_caleod_in;
+            trigger_code_i   <= cri_apl_caldata_in;
             calib_next_state <= TRIGGER_NUM;
           else
             calib_next_state <= TRIGGER_CODE;
@@ -117,12 +173,12 @@ begin
           
       when TRIGGER_NUM =>
           rec_state <= x"3";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_full        <= data_h & CRI_APL_DATA_IN;
-            pack_num_full    <= pack_num_h & CRI_APL_PACKET_NUM_IN;
-            cal_eod_full     <= cal_eod_h & CRI_CALIB_EOD_IN;
+          if (cri_apl_caldrdy_in = '1') then
+            data_full        <= data_h & cri_apl_caldata_in;
+            pack_num_full    <= pack_num_h & cri_apl_calpacknum_in;
+            cal_eod_full     <= cal_eod_h & cri_apl_caleod_in;
             data_rdy         <= '1';          
-            trigger_num_i    <= CRI_APL_DATA_IN;
+            trigger_num_i    <= cri_apl_caldata_in;
             calib_next_state <= COMBINER_LENGTH;
           else
             calib_next_state <= TRIGGER_NUM;
@@ -130,11 +186,11 @@ begin
           
       when COMBINER_LENGTH =>
           rec_state <= x"4";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_h            <= CRI_APL_DATA_IN;
-            pack_num_h        <= CRI_APL_PACKET_NUM_IN;
-            cal_eod_h         <= CRI_CALIB_EOD_IN;
-            combiner_length_i <= CRI_APL_DATA_IN;
+          if (cri_apl_caldrdy_in = '1') then
+            data_h            <= cri_apl_caldata_in;
+            pack_num_h        <= cri_apl_calpacknum_in;
+            cal_eod_h         <= cri_apl_caleod_in;
+            combiner_length_i <= cri_apl_caldata_in;
             calib_next_state  <= COMBINER_ADDRESS;
           else
             calib_next_state  <= COMBINER_LENGTH;
@@ -142,12 +198,12 @@ begin
           
       when COMBINER_ADDRESS =>
           rec_state <= x"5";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_full        <= data_h & CRI_APL_DATA_IN;
-            pack_num_full    <= pack_num_h & CRI_APL_PACKET_NUM_IN;
-            cal_eod_full     <= cal_eod_h & CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_full        <= data_h & cri_apl_caldata_in;
+            pack_num_full    <= pack_num_h & cri_apl_calpacknum_in;
+            cal_eod_full     <= cal_eod_h & cri_apl_caleod_in;            
             data_rdy         <= '1';          
-            combiner_addr_i  <= CRI_APL_DATA_IN;
+            combiner_addr_i  <= cri_apl_caldata_in;
             calib_next_state <= DIRICH_LENGTH;
           else
             calib_next_state <= COMBINER_ADDRESS;
@@ -155,31 +211,31 @@ begin
 
       when DIRICH_LENGTH =>
           rec_state <= x"6";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_h                <= CRI_APL_DATA_IN;
-            pack_num_h            <= CRI_APL_PACKET_NUM_IN;
-            cal_eod_h             <= CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_h                <= cri_apl_caldata_in;
+            pack_num_h            <= cri_apl_calpacknum_in;
+            cal_eod_h             <= cri_apl_caleod_in;            
             calib_next_state      <= DIRICH_ADDRESS;
-            dirich_length_i       <= CRI_APL_DATA_IN;
-            dirich_length_input_i <= CRI_APL_DATA_IN;
+            dirich_length_i       <= cri_apl_caldata_in;
+            dirich_length_input_i <= cri_apl_caldata_in;
           else
             calib_next_state <= DIRICH_LENGTH;
           end if;          
           
       when DIRICH_ADDRESS =>
           rec_state <= x"7";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_full     <= data_h & CRI_APL_DATA_IN;
-            pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
-            cal_eod_full  <= cal_eod_h & CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_full     <= data_h & cri_apl_caldata_in;
+            pack_num_full <= pack_num_h & cri_apl_calpacknum_in;
+            cal_eod_full  <= cal_eod_h & cri_apl_caleod_in;            
             data_rdy      <= '1';
             --combiner_length_i <= std_logic_vector(unsigned(combiner_length_i) - 1);
-            if (CRI_APL_DATA_IN = combiner_addr_i) then  -- CTS
+            if (cri_apl_caldata_in = combiner_addr_i) then  -- CTS
               calib_next_state <= CTS_H;
-              dirich_addr_i    <= CRI_APL_DATA_IN; -- include CTS to calibration
+              dirich_addr_i    <= cri_apl_caldata_in; -- include CTS to calibration
             else
               calib_next_state <= TDC_DATA_H;
-              dirich_addr_i    <= CRI_APL_DATA_IN;
+              dirich_addr_i    <= cri_apl_caldata_in;
             end if;
           else
             calib_next_state <= DIRICH_ADDRESS;
@@ -187,10 +243,10 @@ begin
           
       when TDC_DATA_H =>
           rec_state <= x"8";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_h           <= CRI_APL_DATA_IN;
-            pack_num_h       <= CRI_APL_PACKET_NUM_IN;
-            cal_eod_h        <= CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_h           <= cri_apl_caldata_in;
+            pack_num_h       <= cri_apl_calpacknum_in;
+            cal_eod_h        <= cri_apl_caleod_in;            
             calib_next_state <= TDC_DATA_L;
           else
             calib_next_state <= TDC_DATA_H;
@@ -198,10 +254,10 @@ begin
           
       when TDC_DATA_L =>
           rec_state <= x"9";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_full     <= data_h & CRI_APL_DATA_IN;
-            pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
-            cal_eod_full  <= cal_eod_h & CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_full     <= data_h & cri_apl_caldata_in;
+            pack_num_full <= pack_num_h & cri_apl_calpacknum_in;
+            cal_eod_full  <= cal_eod_h & cri_apl_caleod_in;            
             data_rdy      <= '1';
             dtype         <= x"4";
             if (dirich_length_i = x"0001") then
@@ -222,10 +278,10 @@ begin
           
       when CTS_H =>   
           rec_state <= x"A";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_h           <= CRI_APL_DATA_IN;
-            pack_num_h       <= CRI_APL_PACKET_NUM_IN;
-            cal_eod_h        <= CRI_CALIB_EOD_IN;            
+          if (cri_apl_caldrdy_in = '1') then
+            data_h           <= cri_apl_caldata_in;
+            pack_num_h       <= cri_apl_calpacknum_in;
+            cal_eod_h        <= cri_apl_caleod_in;            
             calib_next_state <= CTS_L;
           else
             calib_next_state <= CTS_H;
@@ -233,10 +289,10 @@ begin
           
       when CTS_L =>   
           rec_state <= x"B";
-          if (CRI_APL_DATAREADY_IN = '1') then
-            data_full     <= data_h & CRI_APL_DATA_IN;
-            pack_num_full <= pack_num_h & CRI_APL_PACKET_NUM_IN;
-            cal_eod_full  <= cal_eod_h & CRI_CALIB_EOD_IN;
+          if (cri_apl_caldrdy_in = '1') then
+            data_full     <= data_h & cri_apl_caldata_in;
+            pack_num_full <= pack_num_h & cri_apl_calpacknum_in;
+            cal_eod_full  <= cal_eod_h & cri_apl_caleod_in;
             data_rdy      <= '1';
             if (dirich_length_i = x"0001") then
               --if (combiner_length_i = x"0001") 
@@ -265,7 +321,7 @@ begin
           
       when CLEANUP =>
           rec_state       <= x"D";
-          if (CRI_CAL_ACTIVE = '0') then
+          if (cri_cal_active_in = '0') then
             calib_next_state <= IDLE;
           else
             calib_next_state <= CLEANUP;

diff --git a/src/cri_data_sender.vhd b/src/cri_data_sender.vhd
index 1897a150f6939871fb77e3a226da39964f731aaf..a9723830c0ccb97851c42db08b5d44626f4f9592 100644 (file)
--- a/src/cri_data_sender.vhd
+++ b/src/cri_data_sender.vhd
@@ -5,6 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL;
 USE IEEE.numeric_std.ALL;
 library work;
 use work.trb_net_std.all;
+use work.config.all;
 
 
 entity cri_data_sender is
@@ -130,6 +131,60 @@ architecture cri_data_sender_arch of cri_data_sender is
   signal cri_apl_packet_num_2api : std_logic_vector(2 downto 0);
   signal cri_apl_dataready_2api  : std_logic;
   
+  
+  signal calib_active_q            : std_logic;
+
+  signal cri_apl_data_q            : std_logic_vector(15 downto 0);
+  signal cri_apl_packet_num_q      : std_logic_vector( 2 downto 0);
+  signal cri_apl_dataready_q       : std_logic;
+  signal cri_calib_eod_q           : std_logic;
+
+  signal cri_apl_data_2api_q       : std_logic_vector(15 downto 0);
+  signal cri_apl_packet_num_2api_q : std_logic_vector( 2 downto 0);
+  signal cri_apl_dataready_2api_q  : std_logic;
+  signal calib_finished_q          : std_logic;
+
+  
+  attribute syn_keep                            : boolean; 
+  attribute syn_keep of calib_active            : signal is true;
+
+  attribute syn_keep of cri_apl_data            : signal is true;
+  attribute syn_keep of cri_apl_packet_num      : signal is true;
+  attribute syn_keep of cri_apl_dataready       : signal is true;
+  attribute syn_keep of cri_calib_eod           : signal is true;
+
+  attribute syn_keep of cri_apl_data_2api       : signal is true;
+  attribute syn_keep of cri_apl_packet_num_2api : signal is true;
+  attribute syn_keep of cri_apl_dataready_2api  : signal is true;
+  attribute syn_keep of calib_finished          : signal is true;
+  
+  attribute syn_preserve                            : boolean; 
+  attribute syn_preserve of calib_active            : signal is true;
+
+  attribute syn_preserve of cri_apl_data            : signal is true;
+  attribute syn_preserve of cri_apl_packet_num      : signal is true;
+  attribute syn_preserve of cri_apl_dataready       : signal is true;
+  attribute syn_preserve of cri_calib_eod           : signal is true;
+
+  attribute syn_preserve of cri_apl_data_2api       : signal is true;
+  attribute syn_preserve of cri_apl_packet_num_2api : signal is true;
+  attribute syn_preserve of cri_apl_dataready_2api  : signal is true;
+  attribute syn_preserve of calib_finished          : signal is true;  
+  
+  attribute nomerge                                 : string; 
+  attribute nomerge of calib_active            : signal is "true";
+
+  attribute nomerge of cri_apl_data            : signal is "true";
+  attribute nomerge of cri_apl_packet_num      : signal is "true";
+  attribute nomerge of cri_apl_dataready       : signal is "true";
+  attribute nomerge of cri_calib_eod           : signal is "true";
+
+  attribute nomerge of cri_apl_data_2api       : signal is "true";
+  attribute nomerge of cri_apl_packet_num_2api : signal is "true";
+  attribute nomerge of cri_apl_dataready_2api  : signal is "true";
+  attribute nomerge of calib_finished          : signal is "true";  
+
+  
 begin
 
   CTS_LENGTH_OUT        <= (others => '0');
@@ -667,38 +722,56 @@ begin
     end if;
   end process;  
   
-  --gen_onlineDataCal: if (INCLUDE_CALIBRATION = c_YES) generate
+  gen_onlineDataCal: if (INCLUDE_CALIBRATION = c_YES) generate
+  
+    THE_CALIB_PIPELINE : process begin
+    wait until rising_edge(CLK);
+       calib_active_q          <= calib_active;
+    
+       cri_apl_data_q          <= cri_apl_data;
+       cri_apl_packet_num_q    <= cri_apl_packet_num;
+       cri_apl_dataready_q     <= cri_apl_dataready;
+       cri_calib_eod_q         <= cri_calib_eod;
+
+       cri_apl_data_2api       <= cri_apl_data_2api_q;
+       cri_apl_packet_num_2api <= cri_apl_packet_num_2api_q;
+       cri_apl_dataready_2api  <= cri_apl_dataready_2api_q;
+       calib_finished          <= calib_finished_q;
+    end process;  
   
     THE_DATA_CALIBRATION : entity work.cbm_rich_calib
     port map(
       CLK                    => CLK,
       RESET                  => RESET,
       
-      CRI_CAL_ACTIVE         => calib_active,
+      CRI_CAL_ACTIVE         => calib_active_q,
       
-      CRI_APL_DATA_IN        => cri_apl_data,
-      CRI_APL_PACKET_NUM_IN  => cri_apl_packet_num,
-      CRI_APL_DATAREADY_IN   => cri_apl_dataready,
-      CRI_CALIB_EOD_IN       => cri_calib_eod,
+      CRI_APL_DATA_IN        => cri_apl_data_q,
+      CRI_APL_PACKET_NUM_IN  => cri_apl_packet_num_q,
+      CRI_APL_DATAREADY_IN   => cri_apl_dataready_q,
+      CRI_CALIB_EOD_IN       => cri_calib_eod_q,
                             
-      CRI_APL_DATA_OUT       => cri_apl_data_2api,
-      CRI_APL_PACKET_NUM_OUT => cri_apl_packet_num_2api,
-      CRI_APL_DATAREADY_OUT  => cri_apl_dataready_2api,
-      CRI_CALIB_EOD_OUT      => calib_finished,
+      CRI_APL_DATA_OUT       => cri_apl_data_2api_q,
+      CRI_APL_PACKET_NUM_OUT => cri_apl_packet_num_2api_q,
+      CRI_APL_DATAREADY_OUT  => cri_apl_dataready_2api_q,
+      CRI_CALIB_EOD_OUT      => calib_finished_q,
       
       BUS_RX                 => BUS_CALIBRATON_RX,
       BUS_TX                 => BUS_CALIBRATON_TX
     );
-  --end generate  
-  
---   gen_no_onlineDataCal: if (INCLUDE_CALIBRATION = c_NO) generate
---   
---     cri_apl_data_2api       <= cri_apl_data;
---     cri_apl_packet_num_2api <= cri_apl_packet_num;
---     cri_apl_dataready_2api  <= cri_apl_dataready;
---     calib_finished          <= '1';
---     
---   end generate  
+  end generate;  
+  
+  gen_no_onlineDataCal: if (INCLUDE_CALIBRATION = c_NO) generate
+  
+    cri_apl_data_2api       <= cri_apl_data;
+    cri_apl_packet_num_2api <= cri_apl_packet_num;
+    cri_apl_dataready_2api  <= cri_apl_dataready;
+    calib_finished          <= '1';
+    
+    BUS_CALIBRATON_TX.ack     <= '0';
+    BUS_CALIBRATON_TX.nack    <= '0';
+    BUS_CALIBRATON_TX.unknown <= '0';
+  end generate;  
     
        
   -- Data to CRI board