relax clock constraints for slowcontrol stuff

diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf
index 3aec3b1cc2a4c809b7660516ad3d7a663160a9cd..6eb73dc654d6bad0ed86029db439c94f604606e5 100644 (file)
--- a/ADC/trb3_periph_adc_constraints.lpf
+++ b/ADC/trb3_periph_adc_constraints.lpf
@@ -83,3 +83,6 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c";
 
 #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0";
 #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1";
+
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X;
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "P_CLOCK_c" 2 X;