add registers to update network address

diff --git a/trb_net16_addresses.vhd b/trb_net16_addresses.vhd
index 348524e739a23ea587358e787214d90000ce5556..7d6650a2ada3461496264fa7129052354b634a8a 100644 (file)
--- a/trb_net16_addresses.vhd
+++ b/trb_net16_addresses.vhd
@@ -33,6 +33,7 @@ entity trb_net16_addresses is
     DONT_UNDERSTAND_OUT : out std_logic;
     API_SEND_OUT        : out std_logic;
     ADDRESS_OUT         : out std_logic_vector(15 downto 0);
+    CONF_ADDRESSES      : in  std_logic_vector(31 downto 0) := x"00000000";
     STAT_DEBUG          : out std_logic_vector(15 downto 0)
     );
 end entity;
@@ -108,6 +109,9 @@ begin
           recv_set_address <= '0';
           sending_state <= sending_idle;
         elsif CLK_EN = '1' then
+          if CONF_ADDRESSES(31) = '1' then
+            buf_ADDRESS_OUT <= CONF_ADDRESSES(15 downto 0);
+          end if;
           buf_API_READ_OUT <= '1';
           ADDRESS_REJECTED <= '0';
           DONT_UNDERSTAND_OUT <= '0';
@@ -307,4 +311,4 @@ STAT_DEBUG(15 downto 12) <= "0000"; --added by regio!
 --   STAT_ADDR_DEBUG(14) <= ADR_SEND_OUT;
 --   STAT_ADDR_DEBUG(15) <= ADR_DATAREADY_OUT;      --dataready out of addresses
 
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd
index f4565facddaa53cb4111cfed4a6e7666e85b6ea7..c4409e71df7f64c0e5e670e5db938b0212f49653 100644 (file)
--- a/trb_net16_api_base.vhd
+++ b/trb_net16_api_base.vhd
@@ -50,6 +50,7 @@ entity trb_net16_api_base is
     -- APL Control port
     APL_RUN_OUT           : out std_logic;
     APL_MY_ADDRESS_IN     : in  std_logic_vector (15 downto 0);
+    APL_MY_BROADCAST_IN   : in  std_logic_vector (7 downto 0) := x"00";
     APL_SEQNR_OUT         : out std_logic_vector (7 downto 0);
     APL_LENGTH_IN         : in  std_logic_vector (15 downto 0);
     APL_FIFO_COUNT_OUT    : out std_logic_vector (10 downto 0) := (others => '0');
@@ -656,7 +657,8 @@ INT_MASTER_DATAREADY_OUT  <= buf_INT_MASTER_DATAREADY_OUT;
               if INT_SLAVE_PACKET_NUM_IN = c_F1 then
                 if ((INT_SLAVE_DATA_IN and ADDRESS_MASK) = (APL_MY_ADDRESS_IN and ADDRESS_MASK))
                    or (and_all(not((not INT_SLAVE_DATA_IN) and (x"FF" & BROADCAST_BITMASK))) = '1')
-                   or (INT_SLAVE_DATA_IN = x"FE" & BROADCAST_SPECIAL_ADDR) then
+                   or (INT_SLAVE_DATA_IN = x"FE" & BROADCAST_SPECIAL_ADDR) 
+                   or (INT_SLAVE_DATA_IN = x"FD" & APL_MY_BROADCAST_IN) then
                   next_state_to_apl <= sa_MY_ADDR;
                   slave_start <= '1';
                 else

diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd
index ac38bc59fcd954b2a89406af92f5eda26eee826b..d028dc2058cf9432e2acde5f39715a2b152317b3 100644 (file)
--- a/trb_net16_endpoint_hades_full_gbe.vhd
+++ b/trb_net16_endpoint_hades_full_gbe.vhd
@@ -145,6 +145,7 @@ entity trb_net16_endpoint_hades_full_gbe is
     REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
     REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
     MY_ADDRESS_OUT            : out std_logic_vector(15 downto 0);
+    CONF_ADDRESSES            : in  std_logic_vector(31 downto 0) := (others => '0');
 
     BUSGBEIP_RX, BUSGBEREG_RX : in CTRLBUS_RX;  --only for GbE
     BUSGBEIP_TX, BUSGBEREG_TX : out CTRLBUS_TX;
@@ -789,6 +790,7 @@ begin
               -- APL Control port
               APL_RUN_OUT       => buf_APL_RUN_OUT(i),
               APL_MY_ADDRESS_IN => MY_ADDRESS,
+              APL_MY_BROADCAST_IN => CONF_ADDRESSES(23 downto 16),
               APL_SEQNR_OUT     => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
               APL_LENGTH_IN     => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16),
               -- Internal direction port
@@ -861,6 +863,7 @@ begin
               IDRAM_ADDR_IN          => buf_IDRAM_ADDR_IN,
               IDRAM_WR_IN            => buf_IDRAM_WR_IN,
               MY_ADDRESS_OUT         => MY_ADDRESS,
+              CONF_ADDRESSES         => CONF_ADDRESSES,
               TRIGGER_MONITOR        => buf_LVL1_VALID_TIMING_TRG_OUT,
               GLOBAL_TIME            => GLOBAL_TIME_OUT,
               LOCAL_TIME             => LOCAL_TIME_OUT,

diff --git a/trb_net16_endpoint_hades_full_handler_record.vhd b/trb_net16_endpoint_hades_full_handler_record.vhd
index a7411ad0f8c40a551f6323bf18eb709f5654dff1..5bd608f6413287c9d4c70a823a9ef6fd9705f01b 100644 (file)
--- a/trb_net16_endpoint_hades_full_handler_record.vhd
+++ b/trb_net16_endpoint_hades_full_handler_record.vhd
@@ -121,15 +121,11 @@ architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endp
   signal common_ctrl_reg_i       : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
   signal common_stat_strobe_i    : std_logic_vector (std_COMSTATREG-1 downto 0);
   signal common_ctrl_strobe_i    : std_logic_vector (std_COMCTRLREG-1 downto 0);
---   signal stat_reg_i              : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
---   signal ctrl_reg_i              : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
---   signal stat_strobe_i           : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
---   signal ctrl_strobe_i           : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
 
   signal regio_rx, dbuf_rx, info_rx, stat_handler_rx, stat_buffer_rx, 
-         handlerbus_rx, busgbeip_rx, busgbereg_rx : CTRLBUS_RX;
+         handlerbus_rx, busgbeip_rx, busgbereg_rx, busaddr_rx : CTRLBUS_RX;
   signal regio_tx, dbuf_tx, info_tx, stat_handler_tx, stat_buffer_tx, 
-         busgbeip_tx, busgbereg_tx : CTRLBUS_TX;
+         busgbeip_tx, busgbereg_tx, busaddr_tx : CTRLBUS_TX;
 
   signal time_global_i           : std_logic_vector (31 downto 0);
   signal time_local_i            : std_logic_vector ( 7 downto 0);
@@ -170,7 +166,9 @@ architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endp
   signal min_event_size            : std_logic_vector( 7 downto 0);
   signal buffer_disable            : std_logic_vector(15 downto 0);  
   signal new_max_size              : std_logic_vector(15 downto 0);
-
+  signal CONF_addresses            : std_logic_vector(31 downto 0) := x"00" & BROADCAST_SPECIAL_ADDR & x"0000";
+  signal CONF_generic              : std_logic_vector( 7 downto 0);
+  
 begin
 ---------------------------------------------------------------------------
 -- TrbNet Endpoint
@@ -279,6 +277,7 @@ begin
       I2C_SDA                    => I2C_SDA,
       REGIO_VAR_ENDPOINT_ID      => REGIO_VAR_ENDPOINT_ID,
       MY_ADDRESS_OUT             => TIMERS_OUT.network_address,
+      CONF_ADDRESSES             => CONF_addresses,
 
       BUSGBEIP_RX                => busgbeip_rx,
       BUSGBEREG_RX               => busgbereg_rx,
@@ -319,9 +318,9 @@ TIMERS_OUT.uid          <= unique_id_i;
 
   THE_INTERNAL_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
-      PORT_NUMBER                => 7,
-      PORT_ADDRESSES             => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7300", 5 => x"8100", 6 => x"8300", others => x"0000"),
-      PORT_ADDR_MASK             => (0 => 15,      1 => 4,       2 => 3,       3 => 2,       4 => 5,       5 => 8,       6 => 8, others => 0)
+      PORT_NUMBER                => 8,
+      PORT_ADDRESSES             => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7300", 5 => x"8100", 6 => x"8300", 7 => x"7000", others => x"0000"),
+      PORT_ADDR_MASK             => (0 => 15,      1 => 4,       2 => 3,       3 => 2,       4 => 5,       5 => 8,       6 => 8,       7 => 1,       others => 0)
       )
     port map(
       CLK         => CLK,
@@ -337,6 +336,7 @@ TIMERS_OUT.uid          <= unique_id_i;
       BUS_RX(4)   => stat_buffer_rx,
       BUS_RX(5)   => busgbeip_rx,
       BUS_RX(6)   => busgbereg_rx,
+      BUS_RX(7)   => busaddr_rx,
       
       BUS_TX(0)   => BUS_TX,
       BUS_TX(1)   => dbuf_tx,
@@ -344,7 +344,8 @@ TIMERS_OUT.uid          <= unique_id_i;
       BUS_TX(3)   => stat_handler_tx,
       BUS_TX(4)   => stat_buffer_tx,
       BUS_TX(5)   => busgbeip_tx,
-      BUS_TX(6)   => busgbereg_tx
+      BUS_TX(6)   => busgbereg_tx,
+      BUS_TX(7)   => busaddr_tx
       );
 
 ---------------------------------------------------------------------------
@@ -400,6 +401,25 @@ info_registers(4) <= x"00" & min_event_size & buffer_disable;
     end if;
   end process;                     
 
+  proc_addresses : process begin
+    wait until rising_edge(CLK);
+    CONF_addresses(31) <= '0';
+    busaddr_tx.ack <= busaddr_rx.write or busaddr_rx.read;
+    if busaddr_rx.write = '1' then
+      if busaddr_rx.addr(0) = '0' then
+        CONF_generic <= busaddr_rx.data(7 downto 0);
+      else
+        CONF_addresses <= busaddr_rx.data;
+      end if;
+    elsif busaddr_rx.read = '1' then
+      if busaddr_rx.addr(0) = '0' then
+        busaddr_tx.data <= X"000000" & CONF_generic;
+      else
+        busaddr_tx.data <= CONF_addresses;      
+      end if;  
+    end if;
+  end process;      
+  
 ---------------------------------------------------------------------------
 --  registers 0x7200 ff.  
 ---------------------------------------------------------------------------  

diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd
index 1655fbd6a75da597cbe6eb00ddde357839bd7348..fd08c495fff65ef823420d7db8ce4b7b5e641398 100644 (file)
--- a/trb_net16_regIO.vhd
+++ b/trb_net16_regIO.vhd
@@ -63,6 +63,7 @@ entity trb_net16_regIO is
 
     --Informations
     MY_ADDRESS_OUT      : out std_logic_vector(15 downto 0);
+    CONF_ADDRESSES      : in  std_logic_vector(31 downto 0);
     TRIGGER_MONITOR     : in  std_logic;  --strobe when timing trigger received
     GLOBAL_TIME         : out std_logic_vector(31 downto 0); --global time, microseconds
     LOCAL_TIME          : out std_logic_vector(7 downto 0);  --local time running with chip frequency
@@ -238,6 +239,7 @@ begin
       ADDRESS_REJECTED  => ADR_REJECTED,
       DONT_UNDERSTAND_OUT => ADR_DONT_UNDERSTAND,
       ADDRESS_OUT       => MY_ADDRESS_OUT,
+      CONF_ADDRESSES    => CONF_ADDRESSES,
       STAT_DEBUG        => buf_STAT_ADDR_DEBUG
       );
 

diff --git a/trb_net_components.vhd b/trb_net_components.vhd
index dc988f2d9d7c280f87feb0492182bc1c9f0da684..3729cef3092aa5b4a40a6feb741669a1c39fdd1b 100644 (file)
--- a/trb_net_components.vhd
+++ b/trb_net_components.vhd
@@ -246,6 +246,7 @@ end component;
       DONT_UNDERSTAND_OUT : out std_logic;\r
       API_SEND_OUT        : out std_logic;\r
       ADDRESS_OUT         : out std_logic_vector(15 downto 0);\r
+      CONF_ADDRESSES      : in  std_logic_vector(31 downto 0);\r
       STAT_DEBUG          : out std_logic_vector(15 downto 0)\r
       );\r
   end component;\r
@@ -296,6 +297,7 @@ end component;
       -- APL Control port\r
       APL_RUN_OUT               : out std_logic;\r
       APL_MY_ADDRESS_IN         : in  std_logic_vector (15 downto 0);\r
+      APL_MY_BROADCAST_IN       : in  std_logic_vector (7 downto 0) := x"00";\r
       APL_SEQNR_OUT             : out std_logic_vector (7 downto 0);\r
       APL_LENGTH_IN             : in  std_logic_vector (15 downto 0);\r
       APL_FIFO_COUNT_OUT        : out std_logic_vector (10 downto 0);\r
@@ -972,7 +974,7 @@ component trb_net16_endpoint_hades_full_gbe is
     REGIO_ONEWIRE_MONITOR_OUT : out std_logic;\r
     REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');\r
     MY_ADDRESS_OUT            : out std_logic_vector(15 downto 0);\r
-\r
+    CONF_ADDRESSES            : in  std_logic_vector(31 downto 0);\r
     BUSGBEIP_RX, BUSGBEREG_RX : in CTRLBUS_RX;  --only for GbE\r
     BUSGBEIP_TX, BUSGBEREG_TX : out CTRLBUS_TX;\r
     GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds\r
@@ -2879,6 +2881,7 @@ end component;
 \r
       --Informations\r
       MY_ADDRESS_OUT      : out std_logic_vector(15 downto 0);\r
+      CONF_ADDRESSES      : out std_logic_vector(31 downto 0);\r
       TRIGGER_MONITOR     : in  std_logic;\r
       GLOBAL_TIME         : out std_logic_vector(31 downto 0);  --global time, microseconds\r
       LOCAL_TIME          : out std_logic_vector(7 downto 0);  --local time running with chip frequency\r