add pinout for hptdc to ADA, change clock source

diff --git a/releases/tdc_v2.3/trb3_periph_ADA.vhd b/releases/tdc_v2.3/trb3_periph_ADA.vhd
index a2d2a43a39a7f739f0ad40ca06e5d0f1dd258373..98442ba10d9cc35c0cfbb62f0b754cc886a99bed 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_ADA.vhd
+++ b/releases/tdc_v2.3/trb3_periph_ADA.vhd
@@ -421,7 +421,7 @@ begin
       SIMULATION     => c_NO)
     port map (
       RESET              => reset_i,
-      CLK_TDC            => CLK_PCLK_LEFT,
+      CLK_TDC            => clk_200_i, --CLK_PCLK_LEFT,
       CLK_READOUT        => clk_100_i,  -- Clock for the readout
       REFERENCE_TIME     => timing_trg_received_i,  -- Reference time input
       HIT_IN             => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),  -- Channel start signals
@@ -437,6 +437,7 @@ begin
       LOGIC_ANALYSER_OUT => logic_analyser_i
       );
 
+gen_normal_pins : if USE_PINOUT = 1 generate      
   -- For single edge measurements
   gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
     hit_in_i <= INP;
@@ -449,5 +450,24 @@ begin
       hit_in_i(i*2)   <= not INP(i-1);
     end generate Gen_Hit_In_Signals;
   end generate;
+end generate;
+
+gen_hptdc_pins : if USE_PINOUT = 3 generate      
+  -- For single edge measurements
+  gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+    gen_pins_hptdc: for i in 0 to 15 generate
+      hit_in_i(i+1) <= INP(i*4);
+    end generate;
+  end generate;
+
+  -- For ToT Measurements
+  gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+    Gen_Hit_In_HPTDC_Signals : for i in 1 to 16 generate
+      hit_in_i(i*2-1) <= INP((i-1)*4);
+      hit_in_i(i*2)   <= not INP((i-1)*4);
+    end generate;
+  end generate;
+end generate;
+
 
 end architecture;