+++ /dev/null
-library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.numeric_std.all;\r
---use ieee.std_logic_unsigned.all;\r
-\r
-library work;\r
-use work.trb_net_std.all;\r
-use work.adcmv3_components.all;\r
-\r
-library ecp2m;\r
-use ecp2m.components.all;\r
-\r
-entity adcmv3 is\r
-port( \r
- CLK100M : in std_logic; -- OK -- 100MHz LVDS clock \r
- -- trigger inputs\r
- EXT_IN : in std_logic_vector(3 downto 0); -- OK -- external triggers\r
- -- APV stuff\r
- APV0A_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0B_CLK : out std_logic; -- OK -- APV bank 0: 40MHz phase adjustable clock \r
- APV0A_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0B_TRG : out std_logic; -- OK -- APV bank 0: trigger pulse out\r
- APV0_RST : out std_logic; -- OK -- APV bank 0: reset signal, low active\r
- APV0_SDA : inout std_logic; -- OK -- APV bank 0: I2C bus SDA\r
- APV0_SCL : inout std_logic; -- OK -- APV bank 0: I2C bus SCL\r
- ENA_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- APV1A_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1B_CLK : out std_logic; -- OK -- APV bank 1: 40MHz phase adjustable clock\r
- APV1A_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1B_TRG : out std_logic; -- OK -- APV bank 1: trigger pulse out\r
- APV1_RST : out std_logic; -- OK -- APV bank 1: reset signal, low active\r
- APV1_SDA : inout std_logic; -- OK -- APV bank 1: I2C bus SDA\r
- APV1_SCL : inout std_logic; -- OK -- APV bank 1: I2C bus SCL\r
- ENB_LVDS : out std_logic_vector(7 downto 0); -- OK -- enable LVDS drivers\r
- -- ADC0 stuff\r
- ADC0_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC0_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC0_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC0_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC0_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC0_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC0_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC0_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC0_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- ADC1 stuff\r
- ADC1_CLK : out std_logic; -- OK -- ADC clock, 40MHz LVTTL\r
- ADC1_RST : out std_logic; -- OK -- ADC reset signal\r
- ADC1_PD : out std_logic; -- OK -- ADC powerdown signal\r
- ADC1_CS : out std_logic; -- OK -- ADC /CS signal\r
- ADC1_SDI : out std_logic; -- OK -- ADC serial data in\r
- ADC1_SCK : out std_logic; -- OK -- ADC serial clock\r
- ADC1_LCLK : in std_logic; -- OK -- ADC 240MHz DDR clock\r
- ADC1_ADCLK : in std_logic; -- OK -- ADC 40MHz frame clock\r
- ADC1_OUT : in std_logic_vector(7 downto 0); -- OK -- serial LVDS data streams\r
- -- uC connections\r
- UC_RESET : in std_logic; -- OK -- uC reset, high active\r
- UC_REBOOT : out std_logic; -- OK -- was UC_FPGA(3), requests FPGA reboot\r
- -- SerDes pins \r
- HDINN2 : in std_logic; -- highspeed INPUT\r
- HDINP2 : in std_logic; --\r
- HDOUTN2 : out std_logic; -- highspeed OUTPUT\r
- HDOUTP2 : out std_logic; -- \r
- SD_PRESENT : in std_logic; -- OK -- Present signal from SFP\r
- SD_LOS : in std_logic; -- OK -- Loss Of Signal from SFP\r
- SD_TXDIS : out std_logic; -- OK -- SFP transmitter disable\r
- ADCM_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on ADCM\r
- -- Backplane sense wires\r
- BP_MODULE : in std_logic_vector(3 downto 0); -- OK -- module number input from backplane\r
- BP_SECTOR : in std_logic_vector(3 downto 0); -- OK -- sector number input from backplane\r
- BP_ONEWIRE : inout std_logic; -- OK -- OneWire ID chip on backplane \r
- BP_LED : out std_logic; -- OK -- backplane LED \r
- -- LEDs\r
- FPGA_LED : out std_logic_vector(6 downto 3); -- OK -- general purpose LEDS\r
- FPGA_LED_RXD : out std_logic; -- OK -- FPGA_LED(2)\r
- FPGA_LED_TXD : out std_logic; -- OK -- FPGA_LED(1)\r
- FPGA_LED_LINK : out std_logic; -- OK -- FPGA_LED(0)\r
- FPGA_LED_PLL : out std_logic; -- OK -- PLL locked \r
- FPGA_LED_ADC : out std_logic_vector(1 downto 0); -- OK -- ADCx OK LED \r
- -- 1Wire chips on APV FEs\r
- APV0_1W : inout std_logic_vector(7 downto 0);\r
- APV1_1W : inout std_logic_vector(7 downto 0);\r
- -- SPI FlashROM connections\r
- U_SPI_CS : out std_logic; -- OK -- chip select for SPI boot FlashROM\r
- U_SPI_SCK : out std_logic; -- OK -- clock\r
- U_SPI_SDI : out std_logic; -- OK -- connects to SI on the FlashROM\r
- U_SPI_SDO : in std_logic -- OK -- connects to SO on the FlashROM\r
- -- Debug connections\r
--- DBG_EXP : out std_logic_vector(43 downto 0) -- OK -- SMC50 debug header\r
-);\r
-end;\r
-\r
-architecture adcmv3 of adcmv3 is\r
-\r
--- Signals\r
--- Clock related signals\r
-signal clk100m_locked : std_logic; -- not needed at the moment\r
-signal sysclk : std_logic; -- clean 100MHz for distribution\r
-\r
-signal adc0_ce : std_logic;\r
-signal adc0_valid : std_logic;\r
-signal adc0_swap : std_logic;\r
-signal adc0_reset : std_logic;\r
-signal adc0_powerdown : std_logic;\r
-signal adc1_ce : std_logic;\r
-signal adc1_valid : std_logic;\r
-signal adc1_swap : std_logic;\r
-signal adc1_reset : std_logic;\r
-signal adc1_powerdown : std_logic;\r
-\r
-signal clk_adc : std_logic; -- 40MHz for ADC operation\r
-signal clk_apv : std_logic; -- 40MHz for APV operation (phase shiftable!)\r
-signal clk40m_locked : std_logic;\r
-signal clk40m_reset : std_logic;\r
-\r
-signal async_reset : std_logic;\r
-\r
--- APV related signals\r
-signal apv_sda_out : std_logic; -- APV SDA\r
-signal apv_sda_in : std_logic;\r
-signal apv_scl_out : std_logic; -- APV SCL\r
-signal apv_scl_in : std_logic;\r
-signal apv_trg : std_logic; -- real APV trigger signal\r
-signal apv_sync : std_logic; -- artificial signal\r
-signal apv_frame_reqd : std_logic; -- one 100MHz pulse per requested frame\r
-signal apv0_reset : std_logic;\r
-signal apv1_reset : std_logic;\r
-signal frontend_reset : std_logic;\r
-signal apv_reset : std_logic;\r
-signal adc_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
-signal lvds_on : std_logic_vector(15 downto 0); -- ordered after ADC0[7:0] and ADC1[15:8]\r
-\r
--- Control signals\r
-signal ctrl_pll : std_logic_vector(15 downto 0); -- PLL control register\r
-signal status_pll : std_logic_vector(15 downto 0); -- PLL status register\r
-signal ctrl_trg : std_logic_vector(31 downto 0); -- TRG control register\r
-signal ctrl_lvl : std_logic_vector(31 downto 0); -- LVL control register\r
- \r
-signal ctrl_bitlow : std_logic_vector(11 downto 0); -- BIT_LOW setting for APV digital header\r
-signal ctrl_bithigh : std_logic_vector(11 downto 0); -- BIT_HIGH setting for APV digital header\r
-signal ctrl_flatlow : std_logic_vector(11 downto 0); -- FLAT_LOW setting\r
-signal ctrl_flathigh : std_logic_vector(11 downto 0); -- FLAT_HIGH setting\r
-\r
-signal maximum_trg : std_logic_vector(3 downto 0);\r
-\r
-signal raw_buf_full : std_logic;\r
-signal eds_buf_full : std_logic;\r
-signal eds_buf_level : std_logic_vector(4 downto 0);\r
-\r
--- regIO data bus\r
-signal regio_addr : std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0);\r
-signal regio_read_enable : std_logic;\r
-signal regio_write_enable : std_logic;\r
-signal regio_data_wr : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
-signal regio_data_rd : std_logic_vector(c_REGIO_REGISTER_WIDTH-1 downto 0);\r
-signal regio_dataready : std_logic;\r
-signal regio_no_more_data : std_logic;\r
-signal regio_write_ack : std_logic;\r
-signal regio_unknown_addr : std_logic;\r
-signal regio_timeout : std_logic;\r
-\r
--- common status / control registers from RegIO\r
-signal common_stat_reg : std_logic_vector(63 downto 0);\r
-signal common_ctrl_reg : std_logic_vector(63 downto 0);\r
-\r
--- user defined "quick'n'dirty" registers\r
-signal simple_status : std_logic_vector(127 downto 0);\r
-signal simple_control : std_logic_vector(63 downto 0);\r
-\r
--- debug signals\r
-signal test_reg : std_logic_vector(31 downto 0);\r
-signal trbrich_debug : std_logic_vector(63 downto 0);\r
-signal trgctrl_debug : std_logic_vector(63 downto 0);\r
-signal slave_debug : std_logic_vector(63 downto 0);\r
-signal fifo_debug : std_logic_vector(63 downto 0);\r
-signal raw_buf_debug : std_logic_vector(63 downto 0);\r
-\r
--- EDS / BUFFER signals (raw buf -> ped corr)\r
-signal eds_data : std_logic_vector(39 downto 0);\r
-signal eds_avail : std_logic;\r
-signal eds_done : std_logic;\r
-signal buf_addr : std_logic_vector(6 downto 0);\r
-signal buf_done : std_logic;\r
-signal buf_tick : std_logic_vector(15 downto 0);\r
-signal buf_start : std_logic_vector(15 downto 0);\r
-signal buf_ready : std_logic_vector(15 downto 0); -- just for debugging!\r
-\r
-type reg_38bit_t is array (0 to 15) of std_logic_vector(37 downto 0);\r
-signal buf_data : reg_38bit_t;\r
-\r
-signal thr_addr : std_logic_vector(6 downto 0);\r
-type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0);\r
-signal thr_data : reg_18bit_t;\r
-signal ped_data : reg_18bit_t;\r
-\r
--- FIFO / DHDR signals (ped corr -> ipu stage)\r
-signal dhdr_data : std_logic_vector(31 downto 0);\r
-signal dhdr_length : std_logic_vector(15 downto 0);\r
-signal dhdr_store : std_logic;\r
-signal dhdr_buf_full : std_logic;\r
-\r
-signal fifo_start : std_logic;\r
-signal fifo_done : std_logic;\r
-signal fifo_we : std_logic_vector(15 downto 0);\r
-signal fifo_space_req : std_logic_vector(11 downto 0);\r
-type reg_40bit_t is array (0 to 15) of std_logic_vector(39 downto 0);\r
-signal fifo_data : reg_40bit_t;\r
-type reg_32bit_t is array (0 to 15) of std_logic_vector(31 downto 0);\r
-signal fifo_status : reg_32bit_t;\r
-\r
-signal ipu_handler_status : std_logic_vector(31 downto 0);\r
-signal lvl1_release_status : std_logic_vector(31 downto 0);\r
-\r
--- APV control / status signals\r
-type reg_16bit_t is array (0 to 15) of std_logic_vector(15 downto 0);\r
-signal adc_ctrl_reg : reg_16bit_t;\r
-signal adc_stat_reg : reg_16bit_t;\r
-\r
-signal debug : std_logic_vector(42 downto 0);\r
-signal debug_q : std_logic_vector(42 downto 0);\r
-signal debug_qq : std_logic_vector(42 downto 0);\r
-signal debug_clk : std_logic;\r
- \r
--- LVL1 application interface\r
-signal lvl1_trg_type : std_logic_vector(3 downto 0);\r
-signal lvl1_trg_received : std_logic;\r
-signal lvl1_trg_number : std_logic_vector(15 downto 0);\r
-signal lvl1_trg_code : std_logic_vector(7 downto 0);\r
-signal lvl1_trg_information : std_logic_vector(23 downto 0);\r
-signal lvl1_error_pattern : std_logic_vector(31 downto 0);\r
-signal lvl1_trg_release : std_logic;\r
-signal lvl1_trg_missing : std_logic;\r
-signal lvl1_int_trg_number : std_logic_vector(15 downto 0);\r
-signal lvl1_int_trg_update : std_logic;\r
-signal timing_trg_found : std_logic;\r
-\r
--- IPU application interface\r
-signal ipu_number : std_logic_vector(15 downto 0);\r
-signal ipu_information : std_logic_vector(7 downto 0);\r
-signal ipu_start_readout : std_logic;\r
-signal ipu_data : std_logic_vector(31 downto 0);\r
-signal ipu_dataready : std_logic;\r
-signal ipu_readout_finished : std_logic;\r
-signal ipu_read : std_logic;\r
-signal ipu_length : std_logic_vector(15 downto 0);\r
-signal ipu_error_pattern : std_logic_vector(31 downto 0);\r
-signal ipu_last_num : std_logic_vector(31 downto 0);\r
-\r
-signal local_lvl1_counter : std_logic_vector(15 downto 0);\r
-signal local_lvl2_counter : std_logic_vector(15 downto 0);\r
-\r
--- ADC signals\r
-type reg_12bit_t is array (0 to 15) of std_logic_vector(11 downto 0);\r
-signal adc_raw_data : reg_12bit_t; -- ADC specific clock domain\r
-signal adc_data : reg_12bit_t; -- common APV clock domain\r
-\r
-signal adc1_testdata : std_logic_vector(11 downto 0);\r
-signal adc0_testdata : std_logic_vector(11 downto 0);\r
-signal adc1_select : std_logic_vector(2 downto 0);\r
-signal adc0_select : std_logic_vector(2 downto 0);\r
-\r
--- input synchronizing\r
-signal bp_sector_q : std_logic_vector(3 downto 0);\r
-signal bp_sector_qq : std_logic_vector(3 downto 0);\r
-signal bp_module_q : std_logic_vector(3 downto 0);\r
-signal bp_module_qq : std_logic_vector(3 downto 0);\r
-\r
-signal lsm_state_bits : std_logic_vector(3 downto 0);\r
-signal reset_by_trb : std_logic;\r
-signal global_sync_reset : std_logic;\r
-\r
-signal adc0_iodelay : std_logic_vector(3 downto 0);\r
-signal adc1_iodelay : std_logic_vector(3 downto 0);\r
-\r
-signal cts_clk40m : std_logic;\r
-signal cts_clk40m_locked : std_logic;\r
-signal test_reg40m : std_logic;\r
-\r
-signal serious_error_flag : std_logic;\r
-signal error_flag : std_logic;\r
-signal warning_flag : std_logic;\r
-signal note_flag : std_logic;\r
-\r
-signal broken_buf : std_logic_vector(15 downto 0);\r
-signal next_not_configured : std_logic;\r
-signal not_configured : std_logic;\r
-\r
-signal apv_error : std_logic_vector(15 downto 0);\r
-signal next_fe_error : std_logic;\r
-signal fe_error : std_logic;\r
-\r
-signal test_data_in : unsigned(17 downto 0);\r
-signal test_data_out : std_logic_vector(17 downto 0);\r
-signal test_data_wren : std_logic;\r
-signal test_data_rden : std_logic;\r
-signal test_data_empty : std_logic;\r
-signal test_data_full : std_logic;\r
-\r
-component lattice_ecp2m_fifo_16bit_dualport is\r
-port(\r
- Data: in std_logic_vector(17 downto 0); \r
- WrClock: in std_logic; \r
- RdClock: in std_logic; \r
- WrEn: in std_logic; \r
- RdEn: in std_logic; \r
- Reset: in std_logic; \r
- RPReset: in std_logic; \r
- Q: out std_logic_vector(17 downto 0); \r
- Empty: out std_logic; \r
- Full: out std_logic\r
-);\r
-end component lattice_ecp2m_fifo_16bit_dualport;\r
-\r
-begin\r
-\r
-\r
-----------------------------------------\r
--- TEST TEST TEST TEST TEST\r
-----------------------------------------\r
-THE_TEST_COUNTER: process( sysclk )\r
-begin\r
- if( rising_edge(sysclk) ) then\r
- if( global_sync_reset = '1' ) then\r
- test_data_in <= (others => '0');\r
- else\r
- test_data_in <= test_data_in + 1;\r
- end if;\r
- end if;\r
-end process THE_TEST_COUNTER;\r
-\r
-THE_TEST_FIFO: lattice_ecp2m_fifo_16bit_dualport\r
-port map(\r
- Data => std_logic_vector(test_data_in),\r
- WrClock => sysclk,\r
- RdClock => sysclk, \r
- WrEn => test_data_wren, \r
- RdEn => test_data_rden, \r
- Reset => global_sync_reset, \r
- RPReset => '0', \r
- Q => test_data_out, \r
- Empty => test_data_empty, \r
- Full => test_data_full\r
-);\r
-\r
-test_data_rden <= not test_data_empty;\r
-test_data_wren <= std_logic(test_data_in(3));\r
-\r
-\r
-simple_status(63 downto 54) <= (others => '0');\r
-simple_status(53) <= test_data_wren;\r
-simple_status(52) <= test_data_rden;\r
-simple_status(51) <= test_data_full;\r
-simple_status(50) <= test_data_empty;\r
-simple_status(49 downto 32) <= test_data_out;\r
-----------------------------------------\r
--- TEST TEST TEST TEST TEST\r
-----------------------------------------\r
-\r
-----------------------------------------\r
--- Async reset assignment --\r
-----------------------------------------\r
-async_reset <= uc_reset; -- uC reset pin\r
-\r
-\r
-----------------------------------------\r
--- Reset handler / spike surpression --\r
-----------------------------------------\r
-THE_RESET_HANDLER: reset_handler \r
-generic map (\r
- RESET_DELAY => x"00ff"\r
-)\r
-port map (\r
- CLEAR_IN => async_reset,\r
- CLEAR_N_IN => '1', -- unused\r
- CLK_IN => clk100m,\r
- SYSCLK_IN => sysclk,\r
- PLL_LOCKED_IN => clk100m_locked,\r
- RESET_IN => common_ctrl_reg(3),\r
- TRB_RESET_IN => reset_by_trb,\r
- CLEAR_OUT => open,\r
- RESET_OUT => global_sync_reset,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- Reboot handler (pulse triggered) --\r
-----------------------------------------\r
-THE_REBOOT_HANDLER: reboot_handler\r
-port map( \r
- RESET_IN => reset_by_trb,\r
- CLK_IN => sysclk,\r
- START_IN => common_ctrl_reg(15),\r
- REBOOT_OUT => uc_reboot,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- 100MHz PLL -> 40MHz / 100MHz --\r
-----------------------------------------\r
--- 100MHz PLL, generating 40MHz and phase shifted 40MHz\r
-THE_40M_PLL: PLL_40M\r
-port map( \r
- CLK => clk100m,\r
- RESET => clk40m_reset,\r
- DPAMODE => '1', -- dynamic control \r
- DPHASE0 => ctrl_pll(0),\r
- DPHASE1 => ctrl_pll(1),\r
- DPHASE2 => ctrl_pll(2),\r
- DPHASE3 => ctrl_pll(3),\r
- CLKOP => clk_apv, -- fixed phase, used for logic \r
- CLKOS => clk_adc, -- phase adjustable, for ODDRXC only\r
- LOCK => clk40m_locked\r
-);\r
-clk40m_reset <= ctrl_pll(7);\r
-\r
--- 100MHz DLL, used for clock injection delay removal\r
-THE_100M_DLL: dll_100m\r
-port map( \r
- CLK => clk100m,\r
- RESETN => '1',\r
- ALUHOLD => '0',\r
- CLKOP => sysclk,\r
- CLKOS => open,\r
- LOCK => clk100m_locked\r
-);\r
-\r
--- 40MHz PLL, takes central clock distributed by CTS\r
-THE_SYNC_PLL: sync_pll_40m\r
-port map(\r
- CLK => ext_in(3),\r
- RESET => ctrl_pll(4),\r
- CLKOP => cts_clk40m,\r
- LOCK => cts_clk40m_locked\r
-);\r
-\r
-THE_TEST_REG: process( cts_clk40m, cts_clk40m_locked )\r
-begin\r
- if( cts_clk40m_locked = '0' ) then\r
- test_reg40m <= '0';\r
- else\r
- if( rising_edge(cts_clk40m) ) then\r
- test_reg40m <= not test_reg40m;\r
- end if;\r
- end if;\r
-end process THE_TEST_REG;\r
-\r
-----------------------------------------\r
--- TRB endpoint --\r
-----------------------------------------\r
-THE_RICH_TRB: rich_trb\r
-port map( \r
- CLK100M_IN => clk100m, -- SerDes exclusive clock\r
- SYSCLK_IN => sysclk, -- fabric clock\r
- RESET_IN => global_sync_reset,\r
- SD_RXD_P_IN => hdinp2,\r
- SD_RXD_N_IN => hdinn2,\r
- SD_TXD_P_OUT => hdoutp2, \r
- SD_TXD_N_OUT => hdoutn2,\r
- SD_PRESENT_IN => sd_present,\r
- SD_TXDIS_OUT => sd_txdis,\r
- SD_LOS_IN => sd_los,\r
- ONEWIRE_INOUT => adcm_onewire,\r
- -- common regIO status / control registers\r
- COMMON_STAT_REG_IN => common_stat_reg,\r
- COMMON_CTRL_REG_OUT => common_ctrl_reg,\r
- -- status register input to regIO / control register output from regIO\r
- CONTROL_OUT => simple_control,\r
- STATUS_IN => simple_status,\r
- -- LVL1 signals\r
- LVL1_TRG_TYPE_OUT => lvl1_trg_type,\r
- LVL1_TRG_RECEIVED_OUT => lvl1_trg_received,\r
- LVL1_TRG_NUMBER_OUT => lvl1_trg_number,\r
- LVL1_TRG_CODE_OUT => lvl1_trg_code,\r
- LVL1_TRG_INFORMATION_OUT => lvl1_trg_information,\r
- LVL1_ERROR_PATTERN_IN => lvl1_error_pattern,\r
- LVL1_TRG_RELEASE_IN => lvl1_trg_release,\r
- LVL1_INT_TRG_NUMBER_OUT => lvl1_int_trg_number, -- internal trigger counter\r
- LVL1_INT_TRG_UPDATE_OUT => lvl1_int_trg_update, -- update on internal trigger counter\r
- TIMING_TRG_FOUND_IN => timing_trg_found,\r
- -- IPU data channel signals (yes, we will use ComputeNodes (tm) (R) (C) one day... :-)\r
- IPU_NUMBER_OUT => ipu_number,\r
- IPU_INFORMATION_OUT => ipu_information,\r
- IPU_START_READOUT_OUT => ipu_start_readout,\r
- IPU_DATA_IN => ipu_data,\r
- IPU_DATAREADY_IN => ipu_dataready,\r
- IPU_READOUT_FINISHED_IN => ipu_readout_finished,\r
- IPU_READ_OUT => ipu_read,\r
- IPU_LENGTH_IN => ipu_length,\r
- IPU_ERROR_PATTERN_IN => ipu_error_pattern,\r
- -- regIO bus\r
- REGIO_ADDR_OUT => regio_addr,\r
- REGIO_READ_ENABLE_OUT => regio_read_enable,\r
- REGIO_WRITE_ENABLE_OUT => regio_write_enable,\r
- REGIO_DATA_OUT => regio_data_wr,\r
- REGIO_DATA_IN => regio_data_rd,\r
- REGIO_DATAREADY_IN => regio_dataready,\r
- REGIO_NO_MORE_DATA_IN => regio_no_more_data,\r
- REGIO_WRITE_ACK_IN => regio_write_ack,\r
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr,\r
- REGIO_TIMEOUT_OUT => regio_timeout,\r
- -- status LEDs\r
- LED_LINK_STAT => fpga_led_link,\r
- LED_LINK_TXD => fpga_led_txd,\r
- LED_LINK_RXD => fpga_led_rxd,\r
- LINK_BSM_OUT => lsm_state_bits, -- LinkStateMachine bits\r
- RESET_OUT => reset_by_trb,\r
- DEBUG => trbrich_debug --open \r
-);\r
-\r
--- common control register bit definitions\r
--- [31:24] ---\r
--- [23:16] fake timing trigger\r
--- [15] reboot FPGA\r
--- [14:11] --- \r
--- [10] reset sequence counter\r
--- [9:4] ---\r
--- [3] master reset, reset the whole endpoint\r
--- [2] empty IPU chain, reset IPU logic\r
--- [1] reset trigger logic\r
--- [0] reset frontends\r
-\r
--- LVL1 error pattern, to be sent back to CTS with each trigger\r
-lvl1_error_pattern(31 downto 24) <= (others => '0'); -- reserved\r
-lvl1_error_pattern(23) <= fe_error; -- frontend error\r
-lvl1_error_pattern(22) <= not_configured; -- not configured\r
-lvl1_error_pattern(21) <= '0'; -- buffers almost full\r
-lvl1_error_pattern(20) <= '0'; -- buffers half full\r
-lvl1_error_pattern(19 downto 18) <= (others => '0'); -- reserved\r
-lvl1_error_pattern(17) <= lvl1_trg_missing; -- missing timing trigger (done by Jan)\r
-lvl1_error_pattern(16) <= '0'; -- LVL1 tag mismatch with local counters (done by Jan)\r
-lvl1_error_pattern(15 downto 0) <= (others => '0'); -- reserved for common status bits\r
-\r
-\r
-----------------------------------------------\r
--- mixed status and control bit definitions --\r
-----------------------------------------------\r
-\r
--- Common status register \r
--- CSR1\r
-common_stat_reg(63 downto 48) <= ipu_last_num(15 downto 0); -- LVL2 counter\r
-common_stat_reg(47 downto 32) <= local_lvl1_counter; -- LVL1 counter\r
--- CSR0\r
-common_stat_reg(31 downto 20) <= x"000"; -- reserved for temp sensor\r
-common_stat_reg(19 downto 13) <= (others => '0');\r
-common_stat_reg(12) <= '0'; -- IPU: single broken event\r
-common_stat_reg(11) <= '0'; -- IPU: severe problem\r
-common_stat_reg(10) <= '0'; -- IPU: partially not found\r
-common_stat_reg(9) <= ipu_error_pattern(20); -- IPU: not found\r
-common_stat_reg(8) <= lvl1_trg_missing; -- LVL1: timing trigger missing\r
-common_stat_reg(7) <= fe_error; -- LVL1: frontend error\r
-common_stat_reg(6) <= not_configured; -- LVL1: not configured\r
-common_stat_reg(5) <= '0'; -- LVL2 counter mismatch (not implemented)\r
-common_stat_reg(4) <= '0'; -- LVL1 trigger counter mismatch (reserved)\r
-common_stat_reg(3) <= note_flag; -- note flag\r
-common_stat_reg(2) <= warning_flag; -- warning flag\r
-common_stat_reg(1) <= error_flag; -- error flag\r
-common_stat_reg(0) <= serious_error_flag; -- serious error flag\r
-\r
-serious_error_flag <= lvl1_trg_missing or fe_error or not_configured;\r
-error_flag <= ipu_error_pattern(20);\r
-warning_flag <= '0';\r
-note_flag <= '0';\r
-\r
--- Control register bit padding\r
-ctrl_bithigh <= ctrl_lvl(31 downto 24) & x"0";\r
-ctrl_bitlow <= ctrl_lvl(23 downto 16) & x"0";\r
-ctrl_flathigh <= ctrl_lvl(15 downto 8) & x"0";\r
-ctrl_flatlow <= ctrl_lvl(7 downto 0) & x"0";\r
-\r
--- LVDS driver enable\r
-ena_lvds(0) <= adc_on(4) or lvds_on(4); \r
-ena_lvds(1) <= adc_on(3) or lvds_on(3);\r
-ena_lvds(2) <= adc_on(5) or lvds_on(5);\r
-ena_lvds(3) <= adc_on(2) or lvds_on(2);\r
-ena_lvds(4) <= adc_on(6) or lvds_on(6);\r
-ena_lvds(5) <= adc_on(1) or lvds_on(1);\r
-ena_lvds(6) <= adc_on(7) or lvds_on(7);\r
-ena_lvds(7) <= adc_on(0) or lvds_on(0);\r
- \r
-enb_lvds(0) <= adc_on(13) or lvds_on(13);\r
-enb_lvds(1) <= adc_on(10) or lvds_on(10);\r
-enb_lvds(2) <= adc_on(12) or lvds_on(12);\r
-enb_lvds(3) <= adc_on(11) or lvds_on(11);\r
-enb_lvds(4) <= adc_on(15) or lvds_on(15);\r
-enb_lvds(5) <= adc_on(8) or lvds_on(8);\r
-enb_lvds(6) <= adc_on(14) or lvds_on(14);\r
-enb_lvds(7) <= adc_on(9) or lvds_on(9);\r
-\r
-bp_led <= cts_clk40m_locked; -- LED is against GND!\r
-\r
-\r
-----------------------------------------\r
--- internal slave bus -> slow control --\r
-----------------------------------------\r
-THE_SLAVE_BUS: slave_bus\r
-port map( \r
- CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- -- RegIO signals\r
- REGIO_ADDR_IN => regio_addr,\r
- REGIO_DATA_IN => regio_data_wr,\r
- REGIO_DATA_OUT => regio_data_rd,\r
- REGIO_READ_ENABLE_IN => regio_read_enable,\r
- REGIO_WRITE_ENABLE_IN => regio_write_enable,\r
- REGIO_TIMEOUT_IN => regio_timeout,\r
- REGIO_DATAREADY_OUT => regio_dataready,\r
- REGIO_WRITE_ACK_OUT => regio_write_ack,\r
- REGIO_NO_MORE_DATA_OUT => regio_no_more_data,\r
- REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr,\r
- -- I2C connections\r
- SDA_IN => apv_sda_in,\r
- SDA_OUT => apv_sda_out,\r
- SCL_IN => apv_scl_in,\r
- SCL_OUT => apv_scl_out,\r
- -- 1Wire connections\r
- ONEWIRE_START_IN => '0', -- not used yet\r
- ONEWIRE_INOUT(15 downto 8) => apv1_1w(7 downto 0),\r
- ONEWIRE_INOUT(7 downto 0) => apv0_1w(7 downto 0),\r
- BP_ONEWIRE_INOUT => bp_onewire,\r
- -- SPI connections\r
- SPI_CS_OUT => u_spi_cs,\r
- SPI_SCK_OUT => u_spi_sck,\r
- SPI_SDI_IN => u_spi_sdo,\r
- SPI_SDO_OUT => u_spi_sdi,\r
- -- ADC 0 SPI connections\r
- SPI_ADC0_CS_OUT => adc0_cs,\r
- SPI_ADC0_SCK_OUT => adc0_sck,\r
- SPI_ADC0_SDO_OUT => adc0_sdi,\r
- ADC0_PLL_LOCKED_IN => adc0_valid,\r
- ADC0_PD_OUT => adc0_powerdown,\r
- ADC0_RST_OUT => adc0_reset,\r
- ADC0_DEL_OUT => adc0_iodelay,\r
- ADC0_CLK_IN => clk_apv,\r
- ADC0_DATA_IN => adc0_testdata,\r
- ADC0_SEL_OUT => adc0_select,\r
- APV0_RST_OUT => apv0_reset,\r
- -- ADC 0 SPI connections\r
- SPI_ADC1_CS_OUT => adc1_cs,\r
- SPI_ADC1_SCK_OUT => adc1_sck,\r
- SPI_ADC1_SDO_OUT => adc1_sdi,\r
- ADC1_PLL_LOCKED_IN => adc1_valid,\r
- ADC1_PD_OUT => adc1_powerdown,\r
- ADC1_RST_OUT => adc1_reset,\r
- ADC1_DEL_OUT => adc1_iodelay,\r
- ADC1_CLK_IN => clk_apv,\r
- ADC1_DATA_IN => adc1_testdata,\r
- ADC1_SEL_OUT => adc1_select,\r
- APV1_RST_OUT => apv1_reset,\r
- -- backplane identifier\r
- BACKPLANE_IN => bp_module_qq(2 downto 0),\r
- -- pedestal interface\r
- PED_ADDR_IN => buf_addr,\r
- PED_DATA_0_OUT => ped_data(0),\r
- PED_DATA_1_OUT => ped_data(1),\r
- PED_DATA_2_OUT => ped_data(2),\r
- PED_DATA_3_OUT => ped_data(3),\r
- PED_DATA_4_OUT => ped_data(4),\r
- PED_DATA_5_OUT => ped_data(5),\r
- PED_DATA_6_OUT => ped_data(6),\r
- PED_DATA_7_OUT => ped_data(7),\r
- PED_DATA_8_OUT => ped_data(8),\r
- PED_DATA_9_OUT => ped_data(9),\r
- PED_DATA_10_OUT => ped_data(10),\r
- PED_DATA_11_OUT => ped_data(11),\r
- PED_DATA_12_OUT => ped_data(12),\r
- PED_DATA_13_OUT => ped_data(13),\r
- PED_DATA_14_OUT => ped_data(14),\r
- PED_DATA_15_OUT => ped_data(15),\r
- -- threshold interface\r
- THR_ADDR_IN => thr_addr,\r
- THR_DATA_0_OUT => thr_data(0),\r
- THR_DATA_1_OUT => thr_data(1),\r
- THR_DATA_2_OUT => thr_data(2),\r
- THR_DATA_3_OUT => thr_data(3),\r
- THR_DATA_4_OUT => thr_data(4),\r
- THR_DATA_5_OUT => thr_data(5),\r
- THR_DATA_6_OUT => thr_data(6),\r
- THR_DATA_7_OUT => thr_data(7),\r
- THR_DATA_8_OUT => thr_data(8),\r
- THR_DATA_9_OUT => thr_data(9),\r
- THR_DATA_10_OUT => thr_data(10),\r
- THR_DATA_11_OUT => thr_data(11),\r
- THR_DATA_12_OUT => thr_data(12),\r
- THR_DATA_13_OUT => thr_data(13),\r
- THR_DATA_14_OUT => thr_data(14),\r
- THR_DATA_15_OUT => thr_data(15),\r
- -- APV control / status\r
- CTRL_0_OUT => adc_ctrl_reg(0),\r
- CTRL_1_OUT => adc_ctrl_reg(1),\r
- CTRL_2_OUT => adc_ctrl_reg(2),\r
- CTRL_3_OUT => adc_ctrl_reg(3),\r
- CTRL_4_OUT => adc_ctrl_reg(4),\r
- CTRL_5_OUT => adc_ctrl_reg(5),\r
- CTRL_6_OUT => adc_ctrl_reg(6),\r
- CTRL_7_OUT => adc_ctrl_reg(7),\r
- CTRL_8_OUT => adc_ctrl_reg(8),\r
- CTRL_9_OUT => adc_ctrl_reg(9),\r
- CTRL_10_OUT => adc_ctrl_reg(10),\r
- CTRL_11_OUT => adc_ctrl_reg(11),\r
- CTRL_12_OUT => adc_ctrl_reg(12),\r
- CTRL_13_OUT => adc_ctrl_reg(13),\r
- CTRL_14_OUT => adc_ctrl_reg(14),\r
- CTRL_15_OUT => adc_ctrl_reg(15),\r
- STAT_0_IN => adc_stat_reg(0),\r
- STAT_1_IN => adc_stat_reg(1),\r
- STAT_2_IN => adc_stat_reg(2),\r
- STAT_3_IN => adc_stat_reg(3),\r
- STAT_4_IN => adc_stat_reg(4),\r
- STAT_5_IN => adc_stat_reg(5),\r
- STAT_6_IN => adc_stat_reg(6),\r
- STAT_7_IN => adc_stat_reg(7),\r
- STAT_8_IN => adc_stat_reg(8),\r
- STAT_9_IN => adc_stat_reg(9),\r
- STAT_10_IN => adc_stat_reg(10),\r
- STAT_11_IN => adc_stat_reg(11),\r
- STAT_12_IN => adc_stat_reg(12),\r
- STAT_13_IN => adc_stat_reg(13),\r
- STAT_14_IN => adc_stat_reg(14),\r
- STAT_15_IN => adc_stat_reg(15),\r
- -- FIFO status\r
- FIFO_STATUS_0_IN => fifo_status(0),\r
- FIFO_STATUS_1_IN => fifo_status(1),\r
- FIFO_STATUS_2_IN => fifo_status(2),\r
- FIFO_STATUS_3_IN => fifo_status(3),\r
- FIFO_STATUS_4_IN => fifo_status(4),\r
- FIFO_STATUS_5_IN => fifo_status(5),\r
- FIFO_STATUS_6_IN => fifo_status(6),\r
- FIFO_STATUS_7_IN => fifo_status(7),\r
- FIFO_STATUS_8_IN => fifo_status(8),\r
- FIFO_STATUS_9_IN => fifo_status(9),\r
- FIFO_STATUS_10_IN => fifo_status(10),\r
- FIFO_STATUS_11_IN => fifo_status(11),\r
- FIFO_STATUS_12_IN => fifo_status(12),\r
- FIFO_STATUS_13_IN => fifo_status(13),\r
- FIFO_STATUS_14_IN => fifo_status(14),\r
- FIFO_STATUS_15_IN => fifo_status(15),\r
- IPU_STATUS_IN => ipu_handler_status,\r
- RELEASE_STATUS_IN => lvl1_release_status,\r
- -- some control signals\r
- CTRL_LVL_OUT => ctrl_lvl,\r
- CTRL_TRG_OUT => ctrl_trg,\r
- CTRL_PLL_OUT => ctrl_pll,\r
- STATUS_PLL_IN => status_pll,\r
- -- temporary stuff \r
- TEST_REG_IN => test_reg, -- short cut \r
- TEST_REG_OUT => test_reg,\r
- -- Debug \r
- DEBUG_OUT => slave_debug, --open\r
- STAT => open\r
-); \r
-\r
--- PLL status register \r
-status_pll(15) <= clk100m_locked;\r
-status_pll(14) <= clk40m_locked;\r
-status_pll(13) <= adc1_valid;\r
-status_pll(12) <= adc0_valid;\r
-status_pll(11) <= adc1_swap;\r
-status_pll(10) <= adc0_swap;\r
-status_pll(9) <= test_reg40m; --'0';\r
-status_pll(8) <= cts_clk40m_locked;\r
-status_pll(7) <= '0'; -- make it human readable\r
-status_pll(6 downto 4) <= bp_sector_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
-status_pll(3) <= '0'; -- make it human readable\r
-status_pll(2 downto 0) <= bp_module_qq(2 downto 0); -- given by backplane DIP switch, for readback only\r
-\r
--- Common status register, do not use.\r
-simple_status(127 downto 104) <= (others => '0');\r
-simple_status(103 downto 96) <= trgctrl_debug(39 downto 32);\r
-simple_status(95 downto 64) <= trgctrl_debug(31 downto 0);\r
---simple_status(63 downto 32) <= (others => '0');\r
-simple_status(31 downto 16) <= local_lvl2_counter;\r
-simple_status(15 downto 0) <= local_lvl1_counter;\r
-\r
--- all APVs are reset together, including the common FE reset\r
-THE_APV_PULSE_STRETCH: pulse_stretch\r
-port map(\r
- CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- START_IN => common_ctrl_reg(0),\r
- PULSE_OUT => frontend_reset,\r
- DEBUG_OUT => open\r
-);\r
-\r
-apv_reset <= apv0_reset or apv1_reset or frontend_reset;\r
-\r
--- APV status registers\r
--- "ADC on" bits\r
--- "LVDS ON" bits \r
-GEN_ADC_LVDS_ON: for i in 0 to 15 generate\r
- adc_on(i) <= adc_ctrl_reg(i)(0);\r
- lvds_on(i) <= adc_ctrl_reg(i)(1);\r
- adc_stat_reg(i) <= buf_data(i)(37 downto 30) & raw_buf_debug(i*4+3 downto i*4+0) & std_logic_vector(to_unsigned(i,4));\r
- broken_buf(i) <= buf_data(i)(36); -- BUF_BROKEN bit\r
- apv_error(i) <= buf_data(i)(26); -- APV error frame bit\r
-end generate GEN_ADC_LVDS_ON;\r
-\r
-next_not_configured <= '1' when (broken_buf /= x"0000") else '0';\r
-next_fe_error <= '1' when (apv_error /= x"0000") else '0';\r
-\r
-----------------------------------------\r
--- IPU endpoint for data transport --\r
-----------------------------------------\r
-THE_IPU_STAGE: ipu_fifo_stage \r
-port map( \r
- CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- -- Slow control signals \r
- SECTOR_IN => bp_sector_qq(2 downto 0), \r
- MODULE_IN => bp_module_qq(2 downto 0), \r
- -- IPU channel connections \r
- IPU_NUMBER_IN => ipu_number,\r
- IPU_INFORMATION_IN => ipu_information,\r
- IPU_START_READOUT_IN => ipu_start_readout,\r
- IPU_DATA_OUT => ipu_data,\r
- IPU_DATAREADY_OUT => ipu_dataready,\r
- IPU_READOUT_FINISHED_OUT => ipu_readout_finished,\r
- IPU_READ_IN => ipu_read,\r
- IPU_LENGTH_OUT => ipu_length,\r
- IPU_ERROR_PATTERN_OUT => ipu_error_pattern,\r
- IPU_LAST_NUM_OUT => ipu_last_num,\r
- LVL2_COUNTER_OUT => local_lvl2_counter,\r
- -- DHDR buffer input \r
- DHDR_DATA_IN => dhdr_data,\r
- DHDR_LENGTH_IN => dhdr_length,\r
- DHDR_STORE_IN => dhdr_store,\r
- DHDR_BUF_FULL_OUT => dhdr_buf_full,\r
- -- processed data input\r
- FIFO_SPACE_REQ_IN => fifo_space_req,\r
- FIFO_START_IN => fifo_start,\r
- FIFO_0_DATA_IN => fifo_data(0),\r
- FIFO_1_DATA_IN => fifo_data(1),\r
- FIFO_2_DATA_IN => fifo_data(2),\r
- FIFO_3_DATA_IN => fifo_data(3),\r
- FIFO_4_DATA_IN => fifo_data(4),\r
- FIFO_5_DATA_IN => fifo_data(5),\r
- FIFO_6_DATA_IN => fifo_data(6),\r
- FIFO_7_DATA_IN => fifo_data(7),\r
- FIFO_8_DATA_IN => fifo_data(8),\r
- FIFO_9_DATA_IN => fifo_data(9),\r
- FIFO_10_DATA_IN => fifo_data(10),\r
- FIFO_11_DATA_IN => fifo_data(11),\r
- FIFO_12_DATA_IN => fifo_data(12),\r
- FIFO_13_DATA_IN => fifo_data(13),\r
- FIFO_14_DATA_IN => fifo_data(14),\r
- FIFO_15_DATA_IN => fifo_data(15),\r
- FIFO_WE_IN => fifo_we,\r
- FIFO_DONE_IN => fifo_done,\r
- FIFO_0_STATUS_OUT => fifo_status(0),\r
- FIFO_1_STATUS_OUT => fifo_status(1),\r
- FIFO_2_STATUS_OUT => fifo_status(2),\r
- FIFO_3_STATUS_OUT => fifo_status(3),\r
- FIFO_4_STATUS_OUT => fifo_status(4),\r
- FIFO_5_STATUS_OUT => fifo_status(5),\r
- FIFO_6_STATUS_OUT => fifo_status(6),\r
- FIFO_7_STATUS_OUT => fifo_status(7),\r
- FIFO_8_STATUS_OUT => fifo_status(8),\r
- FIFO_9_STATUS_OUT => fifo_status(9),\r
- FIFO_10_STATUS_OUT => fifo_status(10),\r
- FIFO_11_STATUS_OUT => fifo_status(11),\r
- FIFO_12_STATUS_OUT => fifo_status(12),\r
- FIFO_13_STATUS_OUT => fifo_status(13),\r
- FIFO_14_STATUS_OUT => fifo_status(14),\r
- FIFO_15_STATUS_OUT => fifo_status(15),\r
- IPU_STATUS_OUT => ipu_handler_status,\r
- RELEASE_STATUS_OUT => lvl1_release_status,\r
- -- Debug signals\r
- DBG_BSM_OUT => open,\r
- DBG_OUT => fifo_debug --open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- Data processing unit --\r
-----------------------------------------\r
-THE_PED_CORR_STAGE: ped_corr_ctrl\r
-port map( \r
- CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- VERBOSE_IN => common_ctrl_reg(31), -- QUICKHACK\r
- EDS_DATA_IN => eds_data,\r
- EDS_AVAIL_IN => eds_avail,\r
- EDS_DONE_OUT => eds_done,\r
- -- DHDR information -- to next stage\r
- DHDR_DATA_OUT => dhdr_data,\r
- DHDR_LENGTH_OUT => dhdr_length,\r
- DHDR_STORE_OUT => dhdr_store,\r
- DHDR_BUF_FULL_IN => dhdr_buf_full,\r
- FIFO_SPACE_REQ_OUT => fifo_space_req, \r
- -- data buffers -- from raw_buf_stage\r
- BUF_ADDR_OUT => buf_addr,\r
- BUF_DONE_OUT => buf_done,\r
- BUF_TICK_IN => buf_tick,\r
- BUF_START_IN => buf_start,\r
- -- raw data\r
- BUF_0_DATA_IN => buf_data(0),\r
- BUF_1_DATA_IN => buf_data(1),\r
- BUF_2_DATA_IN => buf_data(2),\r
- BUF_3_DATA_IN => buf_data(3),\r
- BUF_4_DATA_IN => buf_data(4),\r
- BUF_5_DATA_IN => buf_data(5),\r
- BUF_6_DATA_IN => buf_data(6),\r
- BUF_7_DATA_IN => buf_data(7),\r
- BUF_8_DATA_IN => buf_data(8),\r
- BUF_9_DATA_IN => buf_data(9),\r
- BUF_10_DATA_IN => buf_data(10),\r
- BUF_11_DATA_IN => buf_data(11),\r
- BUF_12_DATA_IN => buf_data(12),\r
- BUF_13_DATA_IN => buf_data(13),\r
- BUF_14_DATA_IN => buf_data(14),\r
- BUF_15_DATA_IN => buf_data(15),\r
- -- Pedestal data \r
- PED_ADDR_OUT => open, -- BUGBUGBUG\r
- PED_0_DATA_IN => ped_data(0),\r
- PED_1_DATA_IN => ped_data(1),\r
- PED_2_DATA_IN => ped_data(2),\r
- PED_3_DATA_IN => ped_data(3),\r
- PED_4_DATA_IN => ped_data(4),\r
- PED_5_DATA_IN => ped_data(5),\r
- PED_6_DATA_IN => ped_data(6),\r
- PED_7_DATA_IN => ped_data(7),\r
- PED_8_DATA_IN => ped_data(8),\r
- PED_9_DATA_IN => ped_data(9),\r
- PED_10_DATA_IN => ped_data(10),\r
- PED_11_DATA_IN => ped_data(11),\r
- PED_12_DATA_IN => ped_data(12),\r
- PED_13_DATA_IN => ped_data(13),\r
- PED_14_DATA_IN => ped_data(14),\r
- PED_15_DATA_IN => ped_data(15),\r
- -- Threshold data\r
- THR_ADDR_OUT => thr_addr,\r
- THR_0_DATA_IN => thr_data(0),\r
- THR_1_DATA_IN => thr_data(1),\r
- THR_2_DATA_IN => thr_data(2),\r
- THR_3_DATA_IN => thr_data(3),\r
- THR_4_DATA_IN => thr_data(4),\r
- THR_5_DATA_IN => thr_data(5),\r
- THR_6_DATA_IN => thr_data(6),\r
- THR_7_DATA_IN => thr_data(7),\r
- THR_8_DATA_IN => thr_data(8),\r
- THR_9_DATA_IN => thr_data(9),\r
- THR_10_DATA_IN => thr_data(10),\r
- THR_11_DATA_IN => thr_data(11),\r
- THR_12_DATA_IN => thr_data(12),\r
- THR_13_DATA_IN => thr_data(13),\r
- THR_14_DATA_IN => thr_data(14),\r
- THR_15_DATA_IN => thr_data(15),\r
- -- processed data\r
- FIFO_START_OUT => fifo_start,\r
- FIFO_0_DATA_OUT => fifo_data(0),\r
- FIFO_1_DATA_OUT => fifo_data(1),\r
- FIFO_2_DATA_OUT => fifo_data(2),\r
- FIFO_3_DATA_OUT => fifo_data(3),\r
- FIFO_4_DATA_OUT => fifo_data(4),\r
- FIFO_5_DATA_OUT => fifo_data(5),\r
- FIFO_6_DATA_OUT => fifo_data(6),\r
- FIFO_7_DATA_OUT => fifo_data(7),\r
- FIFO_8_DATA_OUT => fifo_data(8),\r
- FIFO_9_DATA_OUT => fifo_data(9),\r
- FIFO_10_DATA_OUT => fifo_data(10),\r
- FIFO_11_DATA_OUT => fifo_data(11),\r
- FIFO_12_DATA_OUT => fifo_data(12),\r
- FIFO_13_DATA_OUT => fifo_data(13),\r
- FIFO_14_DATA_OUT => fifo_data(14),\r
- FIFO_15_DATA_OUT => fifo_data(15),\r
- FIFO_WE_OUT => fifo_we,\r
- FIFO_DONE_OUT => fifo_done,\r
- -- Debug signals\r
- DBG_BSM_OUT => open,\r
- DBG_OUT => open\r
-);\r
-\r
-\r
-------------------------------------------\r
--- Raw data processing and storage unit --\r
-------------------------------------------\r
-THE_RAW_BUF_STAGE: raw_buf_stage\r
-port map( \r
- CLK_IN => sysclk,\r
- CLK_APV_IN => clk_apv,\r
- RESET_IN => reset_by_trb,\r
- -- trigger related signals\r
- APV_RESET_IN => apv_reset, -- (100MHz clock)\r
- APV_SYNC_IN => apv_sync, -- (40MHz APV clock)\r
- APV_FRAME_REQD_IN => apv_frame_reqd, -- (100MHz clock)\r
- -- ADC0 signals\r
- ADC0_VALID_IN => adc0_valid,\r
- ADC0_0_DATA_IN => adc_data(0),\r
- ADC0_1_DATA_IN => adc_data(1),\r
- ADC0_2_DATA_IN => adc_data(2),\r
- ADC0_3_DATA_IN => adc_data(3),\r
- ADC0_4_DATA_IN => adc_data(4),\r
- ADC0_5_DATA_IN => adc_data(5),\r
- ADC0_6_DATA_IN => adc_data(6),\r
- ADC0_7_DATA_IN => adc_data(7),\r
- -- ADC1 signals\r
- ADC1_VALID_IN => adc1_valid,\r
- ADC1_0_DATA_IN => adc_data(8),\r
- ADC1_1_DATA_IN => adc_data(9),\r
- ADC1_2_DATA_IN => adc_data(10),\r
- ADC1_3_DATA_IN => adc_data(11),\r
- ADC1_4_DATA_IN => adc_data(12),\r
- ADC1_5_DATA_IN => adc_data(13),\r
- ADC1_6_DATA_IN => adc_data(14),\r
- ADC1_7_DATA_IN => adc_data(15),\r
- -- Slow control registers\r
- MAX_TRG_NUM_IN => maximum_trg, -- automatically determined\r
- BIT_LOW_IN => ctrl_bitlow, -- from slow control\r
- BIT_HIGH_IN => ctrl_bithigh, -- from slow control\r
- FL_LOW_IN => ctrl_flatlow, -- from slow control\r
- FL_HIGH_IN => ctrl_flathigh, -- from slow control\r
- APV_ON_IN => adc_on,\r
- -- 100MHZ synchronous interface\r
- -- APV raw buffers\r
- BUF_FULL_OUT => raw_buf_full, -- NEW NEW NEW\r
- BUF_ADDR_IN => buf_addr, -- from ped_corr_ctrl\r
- BUF_DONE_IN => buf_done, -- from ped_corr_ctrl\r
- BUF_TICK_OUT => buf_tick,\r
- BUF_START_OUT => buf_start,\r
- BUF_READY_OUT => buf_ready,\r
- BUF_0_DATA_OUT => buf_data(0), -- to ped_corr_ctrl \r
- BUF_1_DATA_OUT => buf_data(1), -- to ped_corr_ctrl\r
- BUF_2_DATA_OUT => buf_data(2), -- to ped_corr_ctrl\r
- BUF_3_DATA_OUT => buf_data(3), -- to ped_corr_ctrl\r
- BUF_4_DATA_OUT => buf_data(4), -- to ped_corr_ctrl\r
- BUF_5_DATA_OUT => buf_data(5), -- to ped_corr_ctrl\r
- BUF_6_DATA_OUT => buf_data(6), -- to ped_corr_ctrl\r
- BUF_7_DATA_OUT => buf_data(7), -- to ped_corr_ctrl\r
- BUF_8_DATA_OUT => buf_data(8), -- to ped_corr_ctrl\r
- BUF_9_DATA_OUT => buf_data(9), -- to ped_corr_ctrl\r
- BUF_10_DATA_OUT => buf_data(10), -- to ped_corr_ctrl\r
- BUF_11_DATA_OUT => buf_data(11), -- to ped_corr_ctrl\r
- BUF_12_DATA_OUT => buf_data(12), -- to ped_corr_ctrl\r
- BUF_13_DATA_OUT => buf_data(13), -- to ped_corr_ctrl\r
- BUF_14_DATA_OUT => buf_data(14), -- to ped_corr_ctrl\r
- BUF_15_DATA_OUT => buf_data(15), -- to ped_corr_ctrl\r
- -- Debug signals\r
- DEBUG_OUT => raw_buf_debug --open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC1 data handler --\r
-----------------------------------------\r
-THE_ADC1_HANDLER: adc_data_handler \r
-port map( \r
- RESET_IN => reset_by_trb,\r
- ADC_LCLK_IN => adc1_lclk,\r
- ADC_ADCLK_IN => adc1_adclk,\r
- ADC_CHNL_IN => adc1_out,\r
- PLL_CTRL_IN => adc1_iodelay,\r
- ADC_DATA7_OUT => adc_raw_data(15),\r
- ADC_DATA6_OUT => adc_raw_data(14),\r
- ADC_DATA5_OUT => adc_raw_data(13),\r
- ADC_DATA4_OUT => adc_raw_data(12),\r
- ADC_DATA3_OUT => adc_raw_data(11),\r
- ADC_DATA2_OUT => adc_raw_data(10),\r
- ADC_DATA1_OUT => adc_raw_data(9),\r
- ADC_DATA0_OUT => adc_raw_data(8),\r
- ADC_CE_OUT => adc1_ce,\r
- ADC_VALID_OUT => adc1_valid,\r
- ADC_SWAP_OUT => adc1_swap,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC1 clock domain crossover --\r
-----------------------------------------\r
-THE_ADC1_CROSSOVER: adc_crossover\r
-port map( \r
- CLK_APV_IN => clk_apv,\r
- RESET_IN => global_sync_reset,\r
- -- ADC clock domain signals\r
- ADC_CLK_IN => adc1_lclk,\r
- ADC_CE_IN => adc1_ce,\r
- ADC_DATA_VALID_IN => adc1_valid,\r
- ADC_DATA_7_IN => adc_raw_data(15),\r
- ADC_DATA_6_IN => adc_raw_data(14),\r
- ADC_DATA_5_IN => adc_raw_data(13),\r
- ADC_DATA_4_IN => adc_raw_data(12),\r
- ADC_DATA_3_IN => adc_raw_data(11),\r
- ADC_DATA_2_IN => adc_raw_data(10),\r
- ADC_DATA_1_IN => adc_raw_data(9),\r
- ADC_DATA_0_IN => adc_raw_data(8),\r
- LEVEL_WR_OUT => open,\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT => adc_data(15),\r
- APV_DATA_6_OUT => adc_data(14),\r
- APV_DATA_5_OUT => adc_data(13),\r
- APV_DATA_4_OUT => adc_data(12),\r
- APV_DATA_3_OUT => adc_data(11),\r
- APV_DATA_2_OUT => adc_data(10),\r
- APV_DATA_1_OUT => adc_data(9),\r
- APV_DATA_0_OUT => adc_data(8),\r
- APV_DATA_VALID_OUT => open,\r
- LEVEL_RD_OUT => open,\r
- -- Debug signals\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC1 test data multiplexer --\r
-----------------------------------------\r
-THE_ADC_1_SELECT: adc_channel_select\r
-port map( \r
- RESET_IN => reset_by_trb,\r
- ADC_CLK_IN => clk_apv,\r
- ADC_SEL_IN => adc1_select,\r
- ADC_7_IN => adc_data(15),\r
- ADC_6_IN => adc_data(14),\r
- ADC_5_IN => adc_data(13),\r
- ADC_4_IN => adc_data(12),\r
- ADC_3_IN => adc_data(11),\r
- ADC_2_IN => adc_data(10),\r
- ADC_1_IN => adc_data(9),\r
- ADC_0_IN => adc_data(8),\r
- ADC_CH_OUT => adc1_testdata,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC0 data handler --\r
-----------------------------------------\r
-THE_ADC0_HANDLER: adc_data_handler \r
-port map( \r
- RESET_IN => reset_by_trb,\r
- ADC_LCLK_IN => adc0_lclk,\r
- ADC_ADCLK_IN => adc0_adclk,\r
- ADC_CHNL_IN => adc0_out,\r
- PLL_CTRL_IN => adc0_iodelay,\r
- ADC_DATA7_OUT => adc_raw_data(7),\r
- ADC_DATA6_OUT => adc_raw_data(6),\r
- ADC_DATA5_OUT => adc_raw_data(5),\r
- ADC_DATA4_OUT => adc_raw_data(4),\r
- ADC_DATA3_OUT => adc_raw_data(3),\r
- ADC_DATA2_OUT => adc_raw_data(2),\r
- ADC_DATA1_OUT => adc_raw_data(1),\r
- ADC_DATA0_OUT => adc_raw_data(0),\r
- ADC_CE_OUT => adc0_ce,\r
- ADC_VALID_OUT => adc0_valid,\r
- ADC_SWAP_OUT => adc0_swap,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC0 clock domain crossover --\r
-----------------------------------------\r
-THE_ADC0_CROSSOVER: adc_crossover\r
-port map( \r
- CLK_APV_IN => clk_apv,\r
- RESET_IN => global_sync_reset,\r
- -- ADC clock domain signals\r
- ADC_CLK_IN => adc0_lclk,\r
- ADC_CE_IN => adc0_ce,\r
- ADC_DATA_VALID_IN => adc0_valid,\r
- ADC_DATA_7_IN => adc_raw_data(7),\r
- ADC_DATA_6_IN => adc_raw_data(6),\r
- ADC_DATA_5_IN => adc_raw_data(5),\r
- ADC_DATA_4_IN => adc_raw_data(4),\r
- ADC_DATA_3_IN => adc_raw_data(3),\r
- ADC_DATA_2_IN => adc_raw_data(2),\r
- ADC_DATA_1_IN => adc_raw_data(1),\r
- ADC_DATA_0_IN => adc_raw_data(0),\r
- LEVEL_WR_OUT => open,\r
- -- APV clock domain signals\r
- APV_DATA_7_OUT => adc_data(7),\r
- APV_DATA_6_OUT => adc_data(6),\r
- APV_DATA_5_OUT => adc_data(5),\r
- APV_DATA_4_OUT => adc_data(4),\r
- APV_DATA_3_OUT => adc_data(3),\r
- APV_DATA_2_OUT => adc_data(2),\r
- APV_DATA_1_OUT => adc_data(1),\r
- APV_DATA_0_OUT => adc_data(0),\r
- APV_DATA_VALID_OUT => open,\r
- LEVEL_RD_OUT => open,\r
- -- Debug signals\r
- DEBUG_OUT => open\r
-);\r
-\r
- \r
-----------------------------------------\r
--- ADC0 test data multiplexer --\r
-----------------------------------------\r
-THE_ADC_0_SELECT: adc_channel_select\r
-port map( \r
- RESET_IN => reset_by_trb,\r
- ADC_CLK_IN => clk_apv,\r
- ADC_SEL_IN => adc0_select,\r
- ADC_7_IN => adc_data(7),\r
- ADC_6_IN => adc_data(6),\r
- ADC_5_IN => adc_data(5),\r
- ADC_4_IN => adc_data(4),\r
- ADC_3_IN => adc_data(3),\r
- ADC_2_IN => adc_data(2),\r
- ADC_1_IN => adc_data(1),\r
- ADC_0_IN => adc_data(0),\r
- ADC_CH_OUT => adc0_testdata,\r
- DEBUG_OUT => open\r
-);\r
-\r
-\r
-----------------------------------------\r
--- Trigger handler (APV specific) --\r
-----------------------------------------\r
-THE_APV_TRGCTRL: apv_trgctrl\r
-port map( \r
- CLK_IN => sysclk,\r
- RESET_IN => global_sync_reset,\r
- CLK_APV_IN => clk_apv,\r
- -- Triggers\r
- SYNC_TRG_IN => common_ctrl_reg(31), -- slow control pulse\r
- TIME_TRG_IN => ext_in, -- external trigger inputs\r
- TRB_TRG_IN => common_ctrl_reg(19 downto 16), -- slow control triggers\r
- STILL_BUSY_IN => raw_buf_full, -- if no more frames are free in first stage buffer we must cease triggers.\r
- TRG_FOUND_OUT => timing_trg_found, -- to TRB LVL1 endpoint\r
- SECTOR_IN => bp_sector_qq(2 downto 0), \r
- -- slow control settings\r
- TRG_MAX_OUT => maximum_trg,\r
- TRG_3_TODO_IN => ctrl_trg(31 downto 28), -- from slow control\r
- TRG_3_DELAY_IN => ctrl_trg(27 downto 24), -- from slow control\r
- TRG_2_TODO_IN => ctrl_trg(23 downto 20), -- from slow control\r
- TRG_2_DELAY_IN => ctrl_trg(19 downto 16), -- from slow control\r
- TRG_1_TODO_IN => ctrl_trg(15 downto 12), -- from slow control\r
- TRG_1_DELAY_IN => ctrl_trg(11 downto 8), -- from slow control\r
- TRG_0_TODO_IN => ctrl_trg(7 downto 4), -- from slow control\r
- TRG_0_DELAY_IN => ctrl_trg(3 downto 0), -- from slow control\r
- TRG_SETUP_IN => ctrl_pll(15 downto 8), -- from slow control\r
- -- TRB LVL1 signals\r
- TRB_TTAG_IN => lvl1_trg_number, -- from TRB LVL1 endpoint\r
- TRB_TRND_IN => lvl1_trg_code, -- from TRB LVL1 endpoint\r
- TRB_TTYPE_IN => lvl1_trg_type, -- from TRB LVL1 endpoint\r
- TRB_TINFO_IN => lvl1_trg_information, -- from TRB LVL1 endpoint\r
- TRB_TRGRCVD_IN => lvl1_trg_received, -- from TRB LVL1 endpoint\r
- TRB_MISSING_OUT => lvl1_trg_missing, -- missing timing trigger\r
- TRB_RELEASE_OUT => lvl1_trg_release, -- to TRB LVL1 endpoint\r
- TRB_COUNTER_OUT => local_lvl1_counter, -- own trigger counter\r
- TRB_COUNTER_IN => lvl1_int_trg_number, -- official TRB trigger counter\r
- TRB_LD_COUNTER_IN => lvl1_int_trg_update, -- load TRB counter value\r
- -- EDS signals\r
- EDS_DATA_OUT => eds_data, -- to ped_corr_stage\r
- EDS_AVAIL_OUT => eds_avail, -- to ped_corr_stage\r
- EDS_DONE_IN => eds_done, -- from ped_corr_stage\r
- EDS_FULL_OUT => eds_buf_full,\r
- EDS_LEVEL_OUT => eds_buf_level,\r
- FRM_REQD_OUT => apv_frame_reqd, -- to raw_buf_stage (100MHz clock)\r
- -- APV signals \r
- APV_TRG_OUT => apv_trg, -- to APV frontends (40MHz APV clock)\r
- APV_SYNC_OUT => apv_sync, -- to raw_buf_stage (40MHz APV clock)\r
- DEBUG_OUT => trgctrl_debug\r
-);\r
-\r
-\r
-----------------------------------------\r
--- ADC signals --\r
-----------------------------------------\r
-adc1_rst <= adc1_reset;\r
-adc1_pd <= adc1_powerdown;\r
-\r
-THE_ADC1CLK_OUT: ODDRXC\r
-port map( \r
- DA => '1',\r
- DB => '0',\r
- CLK => clk_adc,\r
- RST => '0',\r
- Q => adc1_clk\r
-);\r
-\r
-adc0_rst <= adc0_reset;\r
-adc0_pd <= adc0_powerdown;\r
-\r
-THE_ADC0CLK_OUT: ODDRXC\r
-port map( \r
- DA => '1',\r
- DB => '0',\r
- CLK => clk_adc,\r
- RST => '0',\r
- Q => adc0_clk\r
-);\r
-\r
-\r
-----------------------------------------\r
--- APV signals --\r
-----------------------------------------\r
--- SDA line output\r
-apv0_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
-apv1_sda <= '0' when (apv_sda_out = '0') else 'Z';\r
--- SDA line input (wired OR negative logic)\r
-apv_sda_in <= apv0_sda and apv1_sda;\r
-\r
--- SCL line output\r
-apv0_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
-apv1_scl <= '0' when (apv_scl_out = '0') else 'Z';\r
--- SCL line input (wired OR negative logic)\r
-apv_scl_in <= apv0_scl and apv1_scl;\r
-\r
--- Reset signal with correct polarity\r
-apv0_rst <= not apv_reset;\r
-apv1_rst <= not apv_reset;\r
-\r
--- CLK and TRG signal\r
--- CLK is shifted to meet timing constraints of APV\r
-THE_APV0ACLK_OUT: ODDRXC\r
-port map( \r
- DA => '0', \r
- DB => '1', \r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0a_clk\r
-);\r
-\r
-THE_APV0BCLK_OUT: ODDRXC\r
-port map( \r
- DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0b_clk\r
-);\r
-\r
-THE_APV1ACLK_OUT: ODDRXC\r
-port map( \r
- DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1a_clk\r
-);\r
-\r
-THE_APV1BCLK_OUT: ODDRXC\r
-port map( \r
- DA => '0',\r
- DB => '1',\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1b_clk\r
-);\r
-\r
-THE_APV0ATRG_OUT: ODDRXC\r
-port map( \r
- DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0a_trg\r
-);\r
-THE_APV0BTRG_OUT: ODDRXC\r
-port map( \r
- DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv0b_trg\r
-);\r
-THE_APV1ATRG_OUT: ODDRXC\r
-port map( \r
- DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1a_trg\r
-);\r
-THE_APV1BTRG_OUT: ODDRXC\r
-port map( \r
- DA => apv_trg,\r
- DB => apv_trg,\r
- CLK => clk_apv,\r
- RST => '0',\r
- Q => apv1b_trg\r
-);\r
-\r
-\r
-----------------------------------------\r
--- DIP switch input registers --\r
-----------------------------------------\r
--- switch "OFF" => '1', switch "ON" => '0'; so invert it\r
-THE_SYNC_PROC: process( sysclk )\r
-begin\r
- if( rising_edge(sysclk) ) then\r
- bp_module_qq <= bp_module_q;\r
- bp_module_q <= not bp_module;\r
- bp_sector_qq <= bp_sector_q;\r
- bp_sector_q <= not bp_sector;\r
- not_configured <= next_not_configured; -- status bit\r
- fe_error <= next_fe_error; -- status bit\r
- end if;\r
-end process THE_SYNC_PROC;\r
-\r
-\r
-----------------------------------------\r
--- LED drivers --\r
-----------------------------------------\r
-fpga_led_adc(1) <= not adc1_valid; \r
-fpga_led_adc(0) <= not adc0_valid;\r
-fpga_led(6) <= not lsm_state_bits(0); -- LED "0"\r
-fpga_led(5) <= not lsm_state_bits(1); -- LED "1"\r
-fpga_led(4) <= not lsm_state_bits(2); -- LED "2"\r
-fpga_led(3) <= not lsm_state_bits(3); -- LED "3"\r
-fpga_led_pll <= not clk40m_locked;\r
-\r
-\r
-----------------------------------------\r
--- FPGA debug header driver --\r
-----------------------------------------\r
-\r
--- NOT USED, USE EPIC EDITOR INSTEAD!\r
-\r
-------------------------------------------------------------------\r
--- ORIGINAL STUFF\r
-------------------------------------------------------------------\r
---debug(42 downto 39) <= (others => '0'); \r
----- IPU signals\r
---debug(38 downto 35) <= ipu_number(3 downto 0);\r
---debug(34) <= ipu_start_readout;\r
---debug(33) <= ipu_dataready;\r
---debug(32) <= ipu_read;\r
---debug(31) <= ipu_readout_finished;\r
----- FIFO signals\r
---debug(30) <= fifo_start; -- ped_corr_ctrl -> ipu_stage => data procession starts (unused in ipu_stage)\r
---debug(29) <= fifo_we(0); -- ped_corr_ctrl -> ipu_stage => transfer processed data into data FIFO (0)\r
---debug(28) <= fifo_done; -- ped_corr_ctrl -> ipu_stage => store length count data in small FIFOs\r
---debug(27) <= dhdr_store; -- ped_corr_ctrl -> ipu_stage => store DHDR information for IPU\r
---debug(26) <= dhdr_buf_full; -- ipu_stage ->\r
----- EventDataSheet / buffer signals\r
---debug(25) <= buf_done; -- ped_corr_ctrl -> raw_buf_stage => raw data has been processed\r
---debug(24) <= buf_tick(0); -- raw_buf_stage -> ped_corr_ctrl => synced tickmarks\r
---debug(23) <= buf_ready(0); -- raw_buf_stage => adc_last\r
---debug(22) <= buf_start(0); -- raw_buf_stage -> ped_corr_ctrl => adc_start\r
---debug(21 downto 17) <= buf_data(0)(34 downto 30);\r
---debug(16) <= raw_buf_full; -- raw_buf_stage -> apv_trgctrl => at least one raw buffer is full\r
---debug(15) <= eds_done; -- ped_corr_ctrl -> apv_trgctrl => EDS data has been transfered, release buffer entry\r
---debug(14) <= eds_avail; -- apv_trgctrl -> ped_corr_ctrl => at least one EDS is available\r
---debug(13) <= eds_buf_full; -- apv_trgctrl => EDS buffer is full\r
---debug(12 downto 8) <= eds_buf_level; \r
----- timing trigger signals\r
---debug(7) <= timing_trg_found; -- apv_trgctrl -> endpoint => timing trigger has arrived\r
---debug(6) <= lvl1_trg_received; -- endpoint -> apv_trgctrl => LVL1 trigger packet has arrived\r
---debug(5) <= lvl1_trg_missing; -- apv_trgctrl -> endpoint => two consecutive timing triggers found\r
---debug(4) <= lvl1_trg_release; -- apv_trgctrl -> endpoint => release LVL1 busy \r
---debug(3 downto 0) <= lvl1_trg_number(3 downto 0);\r
-\r
-\r
-----------------------------------------\r
--- "unused" pins --\r
-----------------------------------------\r
-\r
-end adcmv3;\r
SD_LOS_IN : in std_logic;
ONEWIRE_INOUT : inout std_logic;
-- common regIO status / control registers
- COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common status register, bit definitions like in WIKI
- COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REGISTER_WIDTH-1 downto 0); -- common control register, bit definitions like in WIKI
+ COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG * 32 - 1 downto 0); -- common status register, bit definitions like in WIKI
+ COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG * 32-1 downto 0); -- common control register, bit definitions like in WIKI
-- status register input to regIO / control register output from regIO
CONTROL_OUT : out std_logic_vector(63 downto 0);
STATUS_IN : in std_logic_vector(127 downto 0);
-- Full featured HADES endpoint
------------------------------------------------------------------------------------
THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
-generic map(
- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
- INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
- REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
- REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
- BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts
- REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
- REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
- --standard values for output registers
- REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_00000000_00000000" &
- x"00000000_00000000_00000000_00000000",
- --set to 0 for unused ctrl registers to save resources
- REGIO_USED_CTRL_REGS => "0000000000000001",
- --set to 0 for each unused bit in a register
- REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
- REGIO_USE_DAT_PORT => c_YES,
- REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register!
- REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
- REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
- REGIO_INIT_ENDPOINT_ID => x"0001",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- REGIO_COMPILE_VERSION => x"0003",
- REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
- REGIO_USE_1WIRE_INTERFACE => c_YES,
- TIMING_TRIGGER_RAW => c_YES,
- CLOCK_FREQUENCY => 100
-)
-port map(
- CLK => SYSCLK_IN,
- RESET => RESET_IN,
- CLK_EN => clk_en,
- -- Media direction port
- MED_DATAREADY_OUT => med_dataready_out_int,
- MED_DATA_OUT => med_data_out_int,
- MED_PACKET_NUM_OUT => med_packet_num_out_int,
- MED_READ_IN => med_read_in_int,
- MED_DATAREADY_IN => med_dataready_in_int,
- MED_DATA_IN => med_data_in_int,
- MED_PACKET_NUM_IN => med_packet_num_in_int,
- MED_READ_OUT => med_read_out_int,
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
- -- LVL1 trigger APL
- LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
- LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
- LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
- LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT,
- TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN,
- LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
- LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
- LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
- LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
- LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
- -- IPU Port
- IPU_NUMBER_OUT => IPU_NUMBER_OUT,
- IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
- IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
- IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
- IPU_DATA_IN => IPU_DATA_IN,
- IPU_DATAREADY_IN => IPU_DATAREADY_IN,
- IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
- IPU_READ_OUT => IPU_READ_OUT,
- IPU_LENGTH_IN => IPU_LENGTH_IN,
- IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg,
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
- REGIO_REGISTERS_IN => regio_stat_regs,
- REGIO_REGISTERS_OUT => regio_ctrl_regs,
- COMMON_STAT_REG_STROBE => open,
- COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
- STAT_REG_STROBE => open,
- CTRL_REG_STROBE => open,
- --following ports only used when using internal data port
- REGIO_ADDR_OUT => REGIO_ADDR_OUT,
- REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
- REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
- REGIO_DATA_OUT => REGIO_DATA_OUT,
- REGIO_DATA_IN => REGIO_DATA_IN,
- REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
- REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
- REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
- REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
- REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
- --IDRAM is used if no 1-wire interface, onewire used otherwise
- REGIO_IDRAM_DATA_IN => x"0000", -- not used
- REGIO_IDRAM_DATA_OUT => open, -- not used
- REGIO_IDRAM_ADDR_IN => "000", -- not used
- REGIO_IDRAM_WR_IN => '0', -- not used
- REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
- REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
- REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
- -- New stuff
- GLOBAL_TIME_OUT => open,
- LOCAL_TIME_OUT => open,
- TIME_SINCE_LAST_TRG_OUT => open,
- TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
- TIMER_TICKS_OUT(0) => open, -- us ticks
- -- Status and debug
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => stat_debug_1, --open,
- STAT_DEBUG_2 => open,
- MED_STAT_OP => open,
- CTRL_MPLEX => x"00000000",
- IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open
-);
+ generic map (
+ BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts
+ REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+ REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register!
+ REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
+ REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
+ REGIO_INIT_ENDPOINT_ID => x"0001",
+ REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
+ REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
+ REGIO_USE_1WIRE_INTERFACE => c_YES,
+ TIMING_TRIGGER_RAW => c_YES,
+ CLOCK_FREQUENCY => 100
+ )
+ port map (
+ CLK => SYSCLK_IN,
+ RESET => RESET_IN,
+ CLK_EN => clk_en,
+
+ -- Media direction port
+ MED_DATAREADY_OUT => med_dataready_out_int,
+ MED_DATA_OUT => med_data_out_int,
+ MED_PACKET_NUM_OUT => med_packet_num_out_int,
+ MED_READ_IN => med_read_in_int,
+ MED_DATAREADY_IN => med_dataready_in_int,
+ MED_DATA_IN => med_data_in_int,
+ MED_PACKET_NUM_IN => med_packet_num_in_int,
+ MED_READ_OUT => med_read_out_int,
+ MED_STAT_OP_IN => med_stat_op,
+ MED_CTRL_OP_OUT => med_ctrl_op,
+
+ -- LVL1 trigger APL
+ TRG_TIMING_TRG_RECEIVED_IN => open,
+ LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT,
+ LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
+ LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
+ LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+ LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+ LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+ LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+ LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+ LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+ LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+ LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
+
+ --Information about trigger handler errors
+ TRG_MULTIPLE_TRG_OUT => open,
+ TRG_TIMEOUT_DETECTED_OUT => open,
+ TRG_SPURIOUS_TRG_OUT => open,
+ TRG_MISSING_TMG_TRG_OUT => open,
+ TRG_SPIKE_DETECTED_OUT => open,
+ TRG_LONG_TRG_OUT => open,
+
+ -- IPU Port
+ IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+ IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
+ IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+ IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+ IPU_DATA_IN => IPU_DATA_IN,
+ IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+ IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+ IPU_READ_OUT => IPU_READ_OUT,
+ IPU_LENGTH_IN => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+
+ REGIO_COMMON_STAT_REG_IN => open,
+ REGIO_COMMON_CTRL_REG_OUT => open,
+ REGIO_REGISTERS_IN => open,
+ REGIO_REGISTERS_OUT => open,
+ COMMON_STAT_REG_STROBE => open,
+ COMMON_CTRL_REG_STROBE => open,
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
+
+ --following ports only used when using internal data port
+ REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+ REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+ REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+ REGIO_DATA_OUT => REGIO_DATA_OUT,
+ REGIO_DATA_IN => REGIO_DATA_IN,
+ REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+ REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+ REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+ REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+ REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+
+ --IDRAM is used if no 1-wire interface, onewire used otherwise
+ REGIO_IDRAM_DATA_IN => x"0000", -- not used
+ REGIO_IDRAM_DATA_OUT => open, -- not used
+ REGIO_IDRAM_ADDR_IN => "000", -- not used
+ REGIO_IDRAM_WR_IN => '0', -- not used
+ REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
+ REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
+ REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
+ REGIO_VAR_ENDPOINT_ID => open, -- not used
+ MY_ADDRESS_OUT => open,
+
+ -- New stuff
+ GLOBAL_TIME_OUT => open,
+ LOCAL_TIME_OUT => open,
+ TIME_SINCE_LAST_TRG_OUT => open,
+ TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
+ TIMER_TICKS_OUT(0) => open, -- us ticks
+
+ -- Status and debug
+ STAT_DEBUG_IPU => open,
+ STAT_DEBUG_1 => stat_debug_1,
+ STAT_DEBUG_2 => open,
+ MED_STAT_OP => open,
+ CTRL_MPLEX => x"00000000",
+ IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
+ STAT_ONEWIRE => open,
+ STAT_ADDR_DEBUG => open,
+ STAT_TRIGGER_OUT => open,
+ DEBUG_LVL1_HANDLER_OUT => open
+ );
+
+
+-- THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full
+-- generic map(
+-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES),
+-- INIT_CAN_SEND_DATA => (c_NO,c_NO,c_NO,c_NO), -- was c_YES before?
+-- REPLY_CAN_SEND_DATA => (c_YES,c_YES,c_YES,c_YES),
+-- REPLY_CAN_RECEIVE_DATA => (c_NO,c_NO,c_NO,c_NO),
+-- BROADCAST_BITMASK => x"fb", -- RICH uses 0xfffb as subnet mask for broadcasts
+-- REGIO_NUM_STAT_REGS => 2, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+-- REGIO_NUM_CTRL_REGS => 1, -- minimum number: 32 * 2^0 - 1 = 31 => D[31:0]
+-- --standard values for output registers
+-- REGIO_INIT_CTRL_REGS => x"00000000_00000000_00000000_00000000" &
+-- x"00000000_00000000_00000000_00000000" &
+-- x"00000000_00000000_00000000_00000000" &
+-- x"00000000_00000000_00000000_00000000",
+-- --set to 0 for unused ctrl registers to save resources
+-- REGIO_USED_CTRL_REGS => "0000000000000001",
+-- --set to 0 for each unused bit in a register
+-- REGIO_USED_CTRL_BITMASK => x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF" &
+-- x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF",
+-- REGIO_USE_DAT_PORT => c_YES,
+-- REGIO_INIT_ADDRESS => x"fb00", -- useless, as no preload is done in this register!
+-- REGIO_INIT_UNIQUE_ID => x"dead_beef_affe_d00f",
+-- REGIO_INIT_BOARD_INFO => x"5aa5_3cc3",
+-- REGIO_INIT_ENDPOINT_ID => x"0001",
+-- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
+-- REGIO_COMPILE_VERSION => x"0003",
+-- REGIO_HARDWARE_VERSION => x"3300_0000", -- ADCMv3 signature
+-- REGIO_USE_1WIRE_INTERFACE => c_YES,
+-- TIMING_TRIGGER_RAW => c_YES,
+-- CLOCK_FREQUENCY => 100
+-- )
+-- port map(
+-- CLK => SYSCLK_IN,
+-- RESET => RESET_IN,
+-- CLK_EN => clk_en,
+-- -- Media direction port
+-- MED_DATAREADY_OUT => med_dataready_out_int,
+-- MED_DATA_OUT => med_data_out_int,
+-- MED_PACKET_NUM_OUT => med_packet_num_out_int,
+-- MED_READ_IN => med_read_in_int,
+-- MED_DATAREADY_IN => med_dataready_in_int,
+-- MED_DATA_IN => med_data_in_int,
+-- MED_PACKET_NUM_IN => med_packet_num_in_int,
+-- MED_READ_OUT => med_read_out_int,
+-- MED_STAT_OP_IN => med_stat_op,
+-- MED_CTRL_OP_OUT => med_ctrl_op,
+-- -- LVL1 trigger APL
+-- LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received
+-- LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received
+-- LVL1_TRG_INVALID_OUT => open, --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
+-- LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT,
+-- TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN,
+-- LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT,
+-- LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT,
+-- LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT,
+-- LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT,
+-- LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,
+-- LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,
+-- LVL1_INT_TRG_NUMBER_OUT => open, -- internal trigger number from LVL1 endpoint
+-- -- IPU Port
+-- IPU_NUMBER_OUT => IPU_NUMBER_OUT,
+-- IPU_READOUT_TYPE_OUT => open, -- 4bit readout type
+-- IPU_INFORMATION_OUT => IPU_INFORMATION_OUT,
+-- IPU_START_READOUT_OUT => IPU_START_READOUT_OUT,
+-- IPU_DATA_IN => IPU_DATA_IN,
+-- IPU_DATAREADY_IN => IPU_DATAREADY_IN,
+-- IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN,
+-- IPU_READ_OUT => IPU_READ_OUT,
+-- IPU_LENGTH_IN => IPU_LENGTH_IN,
+-- IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
+-- -- Slow Control Data Port
+-- REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+-- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+-- REGIO_REGISTERS_IN => regio_stat_regs,
+-- REGIO_REGISTERS_OUT => regio_ctrl_regs,
+-- COMMON_STAT_REG_STROBE => open,
+-- COMMON_CTRL_REG_STROBE => common_ctrl_reg_strobe, -- [1] means update on internal trigger number
+-- STAT_REG_STROBE => open,
+-- CTRL_REG_STROBE => open,
+-- --following ports only used when using internal data port
+-- REGIO_ADDR_OUT => REGIO_ADDR_OUT,
+-- REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT,
+-- REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT,
+-- REGIO_DATA_OUT => REGIO_DATA_OUT,
+-- REGIO_DATA_IN => REGIO_DATA_IN,
+-- REGIO_DATAREADY_IN => REGIO_DATAREADY_IN,
+-- REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN,
+-- REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN,
+-- REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN,
+-- REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT,
+-- --IDRAM is used if no 1-wire interface, onewire used otherwise
+-- REGIO_IDRAM_DATA_IN => x"0000", -- not used
+-- REGIO_IDRAM_DATA_OUT => open, -- not used
+-- REGIO_IDRAM_ADDR_IN => "000", -- not used
+-- REGIO_IDRAM_WR_IN => '0', -- not used
+-- REGIO_ONEWIRE_INOUT => ONEWIRE_INOUT,
+-- REGIO_ONEWIRE_MONITOR_IN => '1', -- not used
+-- REGIO_ONEWIRE_MONITOR_OUT => open, -- not used
+-- -- New stuff
+-- GLOBAL_TIME_OUT => open,
+-- LOCAL_TIME_OUT => open,
+-- TIME_SINCE_LAST_TRG_OUT => open,
+-- TIMER_TICKS_OUT(1) => tick_1ms, -- ms ticks
+-- TIMER_TICKS_OUT(0) => open, -- us ticks
+-- -- Status and debug
+-- STAT_DEBUG_IPU => open,
+-- STAT_DEBUG_1 => stat_debug_1, --open,
+-- STAT_DEBUG_2 => open,
+-- MED_STAT_OP => open,
+-- CTRL_MPLEX => x"00000000",
+-- IOBUF_CTRL_GEN => x"00000000_00000000_00000000_00000000",
+-- STAT_ONEWIRE => open,
+-- STAT_ADDR_DEBUG => open
+-- );
------------------------------------------------------------------------------------
-- 10s counter
jspc29 / adcm.git / commitdiff