fix the Hades Rich sensor board vhdl code for a more reliabele magnetic board readout...

diff --git a/richSensors/code/magnetBoardParser.vhd b/richSensors/code/magnetBoardParser.vhd
index 1b8ab47fcf2d8675495cd631c0558a5607f9cc12..fafb530d5a9f99d31d85ec160351fee956b34322 100644 (file)
--- a/richSensors/code/magnetBoardParser.vhd
+++ b/richSensors/code/magnetBoardParser.vhd
@@ -41,11 +41,11 @@ PROC_PARSER : process begin
             -- set all values back to 0
             serialNumber <= (others=>'0');
             sensorNumber <= (others=>'0');
-            axis  <= (others=>'0');
-            valueIntern <= (others=>'0');
-            sign  <= '0';
+            axis         <= (others=>'0');
+            valueIntern  <= (others=>'0');
+            sign         <= '0';
             serialNumber_tmp <= (others=>'0');
-            valueIntern_tmp <= (others=>'0');
+            valueIntern_tmp  <= (others=>'0');
             if INPUT = x"4D" then
                 -- Found char 'M'. Start parsing row and go to next state
                 currentState <= readInitSerialNumber;
@@ -130,6 +130,6 @@ end process;
 SERIAL_NUMBER <= output_ID(26 downto 20);
 SENSOR_NUMBER <= output_ID(9 downto 8);
 AXIS_NUMBER <= output_ID(1 downto 0);
-VALUE(27 downto 0) <= output_value(27 downto 0);
-
+VALUE(27 downto 0) <= output_value(27 downto 0);--b"0000_0000_0000_0000_0000_1000_1010";
+VALUE(30 downto 28) <= (others => '0');
 end architecture behavioral;

diff --git a/richSensors/code/magnetBoardParserHandler.vhd b/richSensors/code/magnetBoardParserHandler.vhd
index d5c2614732323d293f556296a73159395d2472a4..51a01c3286143a265853ad4e6ca0d11397adcf12 100644 (file)
--- a/richSensors/code/magnetBoardParserHandler.vhd
+++ b/richSensors/code/magnetBoardParserHandler.vhd
@@ -94,47 +94,64 @@ PROC_CHECK_ERROR : process begin
   end if;
 end process;
 
---sort THE_MAGBOARD_PARSER values to signals, so they can be used in output
---sensor0
-value_00_00 <= value when sensorNumber = "00" and axis = "00";
-value_00_01 <= value when sensorNumber = "00" and axis = "01";
-value_00_10 <= value when sensorNumber = "00" and axis = "10";
-value_00_11 <= value when sensorNumber = "00" and axis = "11";
---sensor1
-value_01_00 <= value when sensorNumber = "01" and axis = "00";
-value_01_01 <= value when sensorNumber = "01" and axis = "01";
-value_01_10 <= value when sensorNumber = "01" and axis = "10";
-value_01_11 <= value when sensorNumber = "01" and axis = "11";
---sensor2
-value_10_00 <= value when sensorNumber = "10" and axis = "00";
-value_10_01 <= value when sensorNumber = "10" and axis = "01";
-value_10_10 <= value when sensorNumber = "10" and axis = "10";
-value_10_11 <= value when sensorNumber = "10" and axis = "11";
---sensor3
-value_11_00 <= value when sensorNumber = "11" and axis = "00";
-value_11_01 <= value when sensorNumber = "11" and axis = "01";
-value_11_10 <= value when sensorNumber = "11" and axis = "10";
-value_11_11 <= value when sensorNumber = "11" and axis = "11";
 
+PROC_CHECK_ERROR : process begin
+  wait until rising_edge(CLK);
+  --sort THE_MAGBOARD_PARSER values to signals, so they can be used in output
+  --sensor0
+  SERIAL_NUMBER  <= serialNumber;
+  ERROR_NO_DATA  <= error;
+  if    (sensorNumber = "00" and axis = "00") then
+    VALUE_S00_A00 <= std_logic_vector(value);
+  elsif (sensorNumber = "00" and axis = "01") then
+    VALUE_S00_A01 <= std_logic_vector(value);
+  elsif (sensorNumber = "00" and axis = "10") then
+    VALUE_S00_A10 <= std_logic_vector(value);
+  elsif (sensorNumber = "00" and axis = "11") then
+    VALUE_S00_A11 <= std_logic_vector(value);
+  elsif (sensorNumber = "01" and axis = "00") then
+    VALUE_S01_A00 <= std_logic_vector(value);
+  elsif (sensorNumber = "01" and axis = "01") then
+    VALUE_S01_A01 <= std_logic_vector(value);
+  elsif (sensorNumber = "01" and axis = "10") then
+    VALUE_S01_A10 <= std_logic_vector(value);
+  elsif (sensorNumber = "01" and axis = "11") then
+    VALUE_S01_A11 <= std_logic_vector(value);
+  elsif (sensorNumber = "10" and axis = "00") then
+    VALUE_S10_A00 <= std_logic_vector(value);
+  elsif (sensorNumber = "10" and axis = "01") then
+    VALUE_S10_A01 <= std_logic_vector(value);
+  elsif (sensorNumber = "10" and axis = "10") then
+    VALUE_S10_A10 <= std_logic_vector(value);
+  elsif (sensorNumber = "10" and axis = "11") then
+    VALUE_S10_A11 <= std_logic_vector(value);
+  elsif (sensorNumber = "11" and axis = "00") then
+    VALUE_S11_A00 <= std_logic_vector(value);
+  elsif (sensorNumber = "11" and axis = "01") then
+    VALUE_S11_A01 <= std_logic_vector(value);
+  elsif (sensorNumber = "11" and axis = "10") then
+    VALUE_S11_A10 <= std_logic_vector(value);
+  elsif (sensorNumber = "11" and axis = "11") then
+    VALUE_S11_A11 <= std_logic_vector(value);
+  end if;
+end process;
+
+-- VALUE_S00_A00 <= std_logic_vector(value_00_00);
+-- VALUE_S00_A01 <= std_logic_vector(value_00_01);
+-- VALUE_S00_A10 <= std_logic_vector(value_00_10);
+-- VALUE_S00_A11 <= std_logic_vector(value_00_11);
+-- VALUE_S01_A00 <= std_logic_vector(value_01_00);
+-- VALUE_S01_A01 <= std_logic_vector(value_01_01);
+-- VALUE_S01_A10 <= std_logic_vector(value_01_10);
+-- VALUE_S01_A11 <= std_logic_vector(value_01_11);
+-- VALUE_S10_A00 <= std_logic_vector(value_10_00);
+-- VALUE_S10_A01 <= std_logic_vector(value_10_01);
+-- VALUE_S10_A10 <= std_logic_vector(value_10_10);
+-- VALUE_S10_A11 <= std_logic_vector(value_10_11);
+-- VALUE_S11_A00 <= std_logic_vector(value_11_00);
+-- VALUE_S11_A01 <= std_logic_vector(value_11_01);
+-- VALUE_S11_A10 <= std_logic_vector(value_11_10);
+-- VALUE_S11_A11 <= std_logic_vector(value_11_11);
 
--- write signals to output pins.
-SERIAL_NUMBER <= serialNumber;
-VALUE_S00_A00 <= std_logic_vector(value_00_00);
-VALUE_S00_A01 <= std_logic_vector(value_00_01);
-VALUE_S00_A10 <= std_logic_vector(value_00_10);
-VALUE_S00_A11 <= std_logic_vector(value_00_11);
-VALUE_S01_A00 <= std_logic_vector(value_01_00);
-VALUE_S01_A01 <= std_logic_vector(value_01_01);
-VALUE_S01_A10 <= std_logic_vector(value_01_10);
-VALUE_S01_A11 <= std_logic_vector(value_01_11);
-VALUE_S10_A00 <= std_logic_vector(value_10_00);
-VALUE_S10_A01 <= std_logic_vector(value_10_01);
-VALUE_S10_A10 <= std_logic_vector(value_10_10);
-VALUE_S10_A11 <= std_logic_vector(value_10_11);
-VALUE_S11_A00 <= std_logic_vector(value_11_00);
-VALUE_S11_A01 <= std_logic_vector(value_11_01);
-VALUE_S11_A10 <= std_logic_vector(value_11_10);
-VALUE_S11_A11 <= std_logic_vector(value_11_11);
-ERROR_NO_DATA <= error;
 
 end architecture behavioral;

diff --git a/richSensors/code/onewire_record.vhd b/richSensors/code/onewire_record.vhd
index a63c771b027530c6dbd91e5e56726097e476e0be..ed6b7b3af43f46aa064fbaabdf86ec3f4b220254 100644 (file)
--- a/richSensors/code/onewire_record.vhd
+++ b/richSensors/code/onewire_record.vhd
@@ -29,7 +29,7 @@ entity onewire_record is
     ONEWIRE  : inout std_logic;
     --Interlock
     INTERLOCK_FLAG  : out std_logic :='0';
-    INTERLOCK_LIMIT : in  std_logic_vector(31 downto 0) := x"000001F0";
+    INTERLOCK_LIMIT : in  std_logic_vector(31 downto 0) := x"00000250"; -- 37 degree celcius on DS18B20
     -- SLOW CONTROL
     BUS_RX     : in  CTRLBUS_RX;
     BUS_TX     : out CTRLBUS_TX
@@ -253,14 +253,14 @@ end process;
     intlck_flag_i(10) <= '0';
   end if;
   
---   interlock_flag_or_i <= or_all(intlck_flag_i(N_SENSORS-1 downto 0));
-  if (x"000001F0" >= INTERLOCK_LIMIT) then
-    interlock_flag_or_i <= '1';
-  else 
-    interlock_flag_or_i <= '0';
-  end if;
+  interlock_flag_or_i <= or_all(intlck_flag_i(N_SENSORS-1 downto 0));
+--  if (x"000001F0" >= INTERLOCK_LIMIT) then
+--    interlock_flag_or_i <= '1';
+--  else 
+--    interlock_flag_or_i <= '0';
+--  end if;
   
 end process;
 
   INTERLOCK_FLAG <= interlock_flag_or_i;  --high: INTERLOCK Active    low: INTERLOCK Unactive
-end architecture;
\ No newline at end of file
+end architecture;

diff --git a/richSensors/code/uart_mag.vhd b/richSensors/code/uart_mag.vhd
index f5163751ab79cb98ad0138f673a1e82d10841191..608ef377f1274c8229a450276846b5c2ca8eb161 100644 (file)
--- a/richSensors/code/uart_mag.vhd
+++ b/richSensors/code/uart_mag.vhd
@@ -57,28 +57,28 @@ signal tx_debug : std_logic_vector(3 downto 0);
 
 
 -- signals for output result from THE_PARSER_HANDLER
-signal parser_error  : std_logic_vector(OUTPUTS-  1 downto 0);
-signal serialNumbers : serialNumber_array;
+signal parser_error  : std_logic_vector(OUTPUTS-  1 downto 0) := (others => '0');
+signal serialNumbers : serialNumber_array := (others => (others => '0'));
 -- sensor0
-signal values_00_00 : parserValue_array;
-signal values_00_01 : parserValue_array;
-signal values_00_10 : parserValue_array;
-signal values_00_11 : parserValue_array;
+signal values_00_00 : parserValue_array := (others => (others => '0'));
+signal values_00_01 : parserValue_array := (others => (others => '0'));
+signal values_00_10 : parserValue_array := (others => (others => '0'));
+signal values_00_11 : parserValue_array := (others => (others => '0'));
 -- sensor1
-signal values_01_00 : parserValue_array;
-signal values_01_01 : parserValue_array;
-signal values_01_10 : parserValue_array;
-signal values_01_11 : parserValue_array;
+signal values_01_00 : parserValue_array := (others => (others => '0'));
+signal values_01_01 : parserValue_array := (others => (others => '0'));
+signal values_01_10 : parserValue_array := (others => (others => '0'));
+signal values_01_11 : parserValue_array := (others => (others => '0'));
 -- sensor2
-signal values_10_00 : parserValue_array;
-signal values_10_01 : parserValue_array;
-signal values_10_10 : parserValue_array;
-signal values_10_11 : parserValue_array;
+signal values_10_00 : parserValue_array := (others => (others => '0'));
+signal values_10_01 : parserValue_array := (others => (others => '0'));
+signal values_10_10 : parserValue_array := (others => (others => '0'));
+signal values_10_11 : parserValue_array := (others => (others => '0'));
 -- sensor3
-signal values_11_00 : parserValue_array;
-signal values_11_01 : parserValue_array;
-signal values_11_10 : parserValue_array;
-signal values_11_11 : parserValue_array;
+signal values_11_00 : parserValue_array := (others => (others => '0'));
+signal values_11_01 : parserValue_array := (others => (others => '0'));
+signal values_11_10 : parserValue_array := (others => (others => '0'));
+signal values_11_11 : parserValue_array := (others => (others => '0'));
 
 --signal i,j : integer;
 
@@ -203,32 +203,49 @@ begin
         elsif j <= OUTPUTS then
           --serial number of boards and potential error
           BUS_TX.data(6 downto 0) <= serialNumbers(j - 1);
+          BUS_TX.data(7) <= '0';
           BUS_TX.data(8) <= parser_error(j - 1);
+          BUS_TX.data(31 downto 9) <= (others => '0');
         else
           BUS_TX.unknown <= '1'; BUS_TX.ack  <= '0';
         end if;
       else
-        case BUS_RX.addr(3 downto 0) is
+        case j is
           -- sensor0: T, X, Y, Z
-          when x"0" => BUS_TX.data(27 downto 0) <= values_00_00(i-1)(27 downto 0);
-          when x"1" => BUS_TX.data(27 downto 0) <= values_00_01(i-1)(27 downto 0);
-          when x"2" => BUS_TX.data(27 downto 0) <= values_00_10(i-1)(27 downto 0);
-          when x"3" => BUS_TX.data(27 downto 0) <= values_00_11(i-1)(27 downto 0);
+          when 0  => BUS_TX.data(27 downto  0) <= values_00_00(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 1  => BUS_TX.data(27 downto  0) <= values_00_01(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 2  => BUS_TX.data(27 downto  0) <= values_00_10(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 3  => BUS_TX.data(27 downto  0) <= values_00_11(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
           -- sensor1: T, X, Y, Z
-          when x"4" => BUS_TX.data(27 downto 0) <= values_01_00(i-1)(27 downto 0);
-          when x"5" => BUS_TX.data(27 downto 0) <= values_01_01(i-1)(27 downto 0);
-          when x"6" => BUS_TX.data(27 downto 0) <= values_01_10(i-1)(27 downto 0);
-          when x"7" => BUS_TX.data(27 downto 0) <= values_01_11(i-1)(27 downto 0);
+          when 4  => BUS_TX.data(27 downto  0) <= values_01_00(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 5  => BUS_TX.data(27 downto  0) <= values_01_01(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 6  => BUS_TX.data(27 downto  0) <= values_01_10(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 7  => BUS_TX.data(27 downto  0) <= values_01_11(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
           -- sensor2: T, X, Y, Z
-          when x"8" => BUS_TX.data(27 downto 0) <= values_10_00(i-1)(27 downto 0);
-          when x"9" => BUS_TX.data(27 downto 0) <= values_10_01(i-1)(27 downto 0);
-          when x"A" => BUS_TX.data(27 downto 0) <= values_10_10(i-1)(27 downto 0);
-          when x"B" => BUS_TX.data(27 downto 0) <= values_10_11(i-1)(27 downto 0);
+          when 8  => BUS_TX.data(27 downto 0) <= values_10_00(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 9  => BUS_TX.data(27 downto 0) <= values_10_01(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 10 => BUS_TX.data(27 downto 0) <= values_10_10(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 11 => BUS_TX.data(27 downto 0) <= values_10_11(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
           -- sensor3: T, X, Y, Z
-          when x"C" => BUS_TX.data(27 downto 0) <= values_11_00(i-1)(27 downto 0);
-          when x"D" => BUS_TX.data(27 downto 0) <= values_11_01(i-1)(27 downto 0);
-          when x"E" => BUS_TX.data(27 downto 0) <= values_11_10(i-1)(27 downto 0);
-          when x"F" => BUS_TX.data(27 downto 0) <= values_11_11(i-1)(27 downto 0);
+          when 12 => BUS_TX.data(27 downto 0) <= values_11_00(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 13 => BUS_TX.data(27 downto 0) <= values_11_01(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 14 => BUS_TX.data(27 downto 0) <= values_11_10(i-1)(27 downto 0);
+                     BUS_TX.data(31 downto 28) <= (others => '0');
+          when 15 => BUS_TX.data(27 downto 0) <= values_11_11(i-1)(27 downto 0);
         
           when others => BUS_TX.unknown <= '1'; BUS_TX.ack  <= '0';
         end case;

diff --git a/richSensors/config.vhd b/richSensors/config.vhd
index 22cdcd0c86e38833b77846f4e9f334a9976065bf..13dc8592bb8387386392136232aa0838a55710d3 100644 (file)
--- a/richSensors/config.vhd
+++ b/richSensors/config.vhd
@@ -13,6 +13,7 @@ package config is
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
   constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
+  constant FPGA_TYPE : integer  := 3;
 
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 

diff --git a/richSensors/config_compile_giessen.pl b/richSensors/config_compile_giessen.pl
new file mode 100644 (file)
index 0000000..9ca88b6
--- /dev/null
+++ b/richSensors/config_compile_giessen.pl
@@ -0,0 +1,19 @@
+TOPNAME                      => "trb3sc_richSensor",
+lm_license_file_for_synplify => "7788\@fb07pc-u102325",
+lm_license_file_for_par      => "7788\@fb07pc-u102325",
+lattice_path                 => '/usr/local/diamond/3.11_x64/',
+synplify_path                => '/usr/local/diamond/3.11_x64/synpbase',
+synplify_command             => "synpwrap -fg -options",
+#synplify_command             => "ssh  adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"",
+
+nodelist_file                => '../nodes_lxhadeb07.txt',
+#par_options                  => '../par.p2t',
+
+#Include only necessary lpf files
+pinout_file                  => 'trb3sc_richSensor', #name of pin-out file, if not equal TOPNAME
+
+#Report settings
+firefox_open                 => 0,
+#no_ltxt2ptxt                 => 1,  #if there is no serdes being used
+#make_jed                     => 1,
+

diff --git a/richSensors/trb3sc_richSensor.prj b/richSensors/trb3sc_richSensor.prj
index 50a2c493afd9428f170c8fd955ca156f05fba272..ba3b1f9cc74212a1cb573a31c80ffb3f2a0a1c2e 100644 (file)
--- a/richSensors/trb3sc_richSensor.prj
+++ b/richSensors/trb3sc_richSensor.prj
@@ -170,6 +170,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
@@ -182,6 +183,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_rec
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 
 add_file -vhdl -lib work "./code/uart_mag.vhd"
+#add_file -vhdl -lib work "./code/uart_andre.vhd"
 
 add_file -vhdl -lib work "code/uart_relais.vhd"
 add_file -vhdl -lib work "code/magnetBoardParser.vhd"

diff --git a/richSensors/trb3sc_richSensor.vhd b/richSensors/trb3sc_richSensor.vhd
index 4eb5fa9a084dd5f84152c3ee0b49db3d9fb7909b..be21ef24974cfa2536d5f9a1e4f787b07536ce9d 100644 (file)
--- a/richSensors/trb3sc_richSensor.vhd
+++ b/richSensors/trb3sc_richSensor.vhd
@@ -180,7 +180,7 @@ architecture trb3sc_arch of trb3sc_richSensor is
  
   signal interlock_flag_i  : std_logic_vector(1 downto 0) := "00";
   signal interlock_output  : std_logic;
-  signal interlock_limit_i : std_logic_vector(31 downto 0):= x"000001F0";
+  signal interlock_limit_i : std_logic_vector(31 downto 0):= x"00000250";
  
 begin