link establishment works now stable (TM)

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 5eb12981b8b05f6308f1656f2ae9a731a6544a96..e621236e5e5000d6a14675883d8619b22f6314fe 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -220,10 +220,14 @@ begin
 -------------------------------------------------      
 -- byte/word alignment
 -------------------------------------------------      
-  word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
-                   word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
-                   word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
-                   word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+  word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE))  else
+                   word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE))  else
+                   word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE))  else
+                   word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE))  else
+                   word_sync_i(0) when ((quad_mode = 1)  and (IS_MODE(0) = c_IS_MASTER)) else
+                   word_sync_i(1) when ((quad_mode = 1)  and (IS_MODE(1) = c_IS_MASTER)) else
+                   word_sync_i(2) when ((quad_mode = 1)  and (IS_MODE(2) = c_IS_MASTER)) else
+                   word_sync_i(3) when ((quad_mode = 1)  and (IS_MODE(3) = c_IS_MASTER)) else
                    '1';
 
   WORD_SYNC_OUT <= word_sync_sel;

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 8f6eda776d5b99037b1681327ade230d54598490..4569313368923354d4b30447ab9d5fb03378e9fc 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -89,6 +89,9 @@ architecture med_sync_control_arch of med_sync_control_RS is
   signal rx_serdes_rst_i          : std_logic;
   signal rx_pcs_rst_i             : std_logic;
 
+  signal word_sync_rx_i           : std_logic;
+  signal word_sync_tx_i           : std_logic;
+
   signal is_wap_zero_i            : std_logic;
   signal debug_tx_control_i       : std_logic_vector(31 downto 0);
   
@@ -176,7 +179,7 @@ begin
       RX_DATA_IN             => RX_DATA_IN,
       RX_K_IN                => RX_K_IN,
 
-      WORD_SYNC_OUT          => WORD_SYNC_OUT,
+      WORD_SYNC_OUT          => word_sync_rx_i,
 
       RX_DLM_OUT             => RX_DLM_OUT,
       RX_DLM_WORD_OUT        => RX_DLM_WORD_OUT,
@@ -211,7 +214,6 @@ begin
 -------------------------------------------------      
 -- TX Data
 -------------------------------------------------
-
   THE_TX_CONTROL: tx_control_RS
     generic map(
       SIM_MODE    => SIM_MODE,
@@ -231,6 +233,7 @@ begin
       TX_K_OUT                 => TX_K_OUT,
      -- synchronous signals
       WORD_SYNC_IN             => WORD_SYNC_IN,
+      WORD_SYNC_OUT            => word_sync_tx_i,
       SEND_DLM_IN              => TX_DLM_IN,
       SEND_DLM_WORD_IN         => TX_DLM_WORD_IN,
       SEND_RST_IN              => TX_RST_IN,
@@ -249,6 +252,12 @@ begin
 
   DEBUG_TX_CONTROL <= debug_tx_control_i;
   
+  -- WordSync is taken from RX in case of SP to sync the MPs in a hub.
+  -- In case of a root MP it is taken from MP to sync DLM sending.
+  -- NB: a root MP nees WORD_SYNC_IN set to '1' for operation.
+  -- MB: a root MP provides WORD_SYNC_OUT for DLM transmission timing.
+  WORD_SYNC_OUT <= word_sync_rx_i when (IS_MODE = c_IS_SLAVE) else word_sync_tx_i;
+  
 -------------------------------------------------      
 -- Generate LED signals
 -------------------------------------------------   

diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd
index 49c8052df9f5ee50818cc4e5d4b74903a0faf7f5..ca7a759b5dc3c17654558b79798d4d447152b373 100644 (file)
--- a/media_interfaces/sync/med_sync_define_RS.vhd
+++ b/media_interfaces/sync/med_sync_define_RS.vhd
@@ -74,28 +74,6 @@ component lattice_ecp3_fifo_18x16_dualport_oreg
   );\r
 end component;\r
 \r
---component main_rx_reset_RS is\r
---  generic(\r
---    SIM_MODE    : integer := 0;\r
---    IS_WAP_ZERO : integer := 0;\r
---    IS_MODE     : integer := c_IS_SLAVE\r
---  );\r
---  port(\r
---    CLEAR                  : in  std_logic; -- async reset, active high\r
---    LOCALCLK               : in  std_logic; -- CDR reference clock\r
---    TX_PLL_LOL_IN          : in  std_logic; -- TX_PLOL form AUX channel\r
---    RX_CDR_LOL_IN          : in  std_logic; -- CDR LOL \r
---    RX_LOS_LOW_IN          : in  std_logic; -- RX LOS\r
---    WA_POSITION_IN         : in  std_logic_vector(3 downto 0);\r
---    SFP_LOS_IN             : in  std_logic; -- SFP LOS signal\r
---    RX_PCS_RST_CH_C_OUT    : out std_logic;\r
---    RX_SERDES_RST_CH_C_OUT : out std_logic;\r
---    LINK_RX_READY_OUT      : out std_logic; -- RX SerDes is fully operational\r
---    MASTER_RESET_OUT       : out std_logic; -- can be used as master reset if sourced from Slave port\r
---    STATE_OUT              : out std_logic_vector(3 downto 0)\r
---  );\r
---end component;\r
-\r
 component main_tx_reset_RS is\r
   generic(\r
     SIM_MODE    : integer := 0\r
@@ -179,6 +157,7 @@ component tx_control_RS is
     TX_K_OUT                       : out std_logic; -- to TX SerDes\r
     -- synchronous signals\r
     WORD_SYNC_IN                   : in  std_logic; -- byte/word sync\r
+    WORD_SYNC_OUT                  : out std_logic;\r
     SEND_DLM_IN                    : in  std_logic;\r
     SEND_DLM_WORD_IN               : in  std_logic_vector(7 downto 0);\r
     SEND_RST_IN                    : in  std_logic;\r

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index acde2e65a9db0542694eef1623548b0e53a751fa..77b259cd01295acbc1285cf772fbffdbbb491e8d 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -28,6 +28,7 @@ entity tx_control_RS is
     TX_K_OUT                       : out std_logic; -- to TX SerDes\r
     -- synchronous signals\r
     WORD_SYNC_IN                   : in  std_logic; -- byte/word sync\r
+    WORD_SYNC_OUT                  : out std_logic; -- for root CTS port\r
     SEND_DLM_IN                    : in  std_logic;\r
     SEND_DLM_WORD_IN               : in  std_logic_vector(7 downto 0);\r
     SEND_RST_IN                    : in  std_logic;\r
@@ -46,7 +47,7 @@ end entity;
 architecture arch of tx_control_RS is\r
 \r
   type state_t is (IDLE, SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, \r
-                     SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H);\r
+                   SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H);\r
   signal current_state           : state_t;\r
   signal state_bits              : std_logic_vector(3 downto 0);\r
   \r
@@ -260,66 +261,71 @@ begin
         current_state <= IDLE;\r
         TX_K_OUT <= '1';\r
         TX_DATA_OUT <= K_NULL;\r
---        toggle_idle <= '1'; -- added\r
+        WORD_SYNC_OUT <= '0';\r
       else \r
         if( rising_edge(CLK_TX) ) then\r
           TX_K_OUT               <= '0';\r
+          WORD_SYNC_OUT          <= '0';\r
           debug_sending_dlm      <= '0';\r
           debug_sending_rst      <= '0';\r
           case current_state is\r
             when SEND_IDLE_L =>\r
-              TX_DATA_OUT        <= K_IDLE;\r
-              TX_K_OUT           <= '1';\r
+              TX_DATA_OUT <= K_IDLE;\r
+              TX_K_OUT    <= '1';\r
               if( WORD_SYNC_IN = '1' )then\r
-                current_state      <= SEND_IDLE_H;\r
+                current_state <= SEND_IDLE_H;\r
               else\r
-                current_state      <= SEND_IDLE_L;\r
+                current_state <= SEND_IDLE_L;\r
               end if;\r
 \r
             when SEND_IDLE_H =>\r
+              WORD_SYNC_OUT <= '1';\r
               if( (send_steady_idle_int = '1') or (toggle_idle = '1') ) then\r
-                TX_DATA_OUT        <= D_IDLE1;\r
-                toggle_idle        <= send_steady_idle_int;\r
+                TX_DATA_OUT <= D_IDLE1;\r
+                toggle_idle <= send_steady_idle_int;\r
               else\r
-                TX_DATA_OUT        <= D_IDLE0;\r
-                toggle_idle        <= '1';\r
+                TX_DATA_OUT <= D_IDLE0;\r
+                toggle_idle <= '1';\r
               end if;\r
 \r
             when SEND_DATA_L =>\r
-              TX_DATA_OUT        <= ram_dout(7 downto 0);\r
-              load_sop           <= ram_dout(16);\r
-              load_eop           <= ram_dout(17);\r
-              current_state      <= SEND_DATA_H;\r
+              TX_DATA_OUT   <= ram_dout(7 downto 0);\r
+              load_sop      <= ram_dout(16);\r
+              load_eop      <= ram_dout(17);\r
+              current_state <= SEND_DATA_H;\r
 \r
             when SEND_DATA_H =>\r
-              TX_DATA_OUT        <= ram_dout(15 downto 8);\r
+              WORD_SYNC_OUT <= '1';\r
+              TX_DATA_OUT   <= ram_dout(15 downto 8);\r
 \r
             when SEND_DLM_L =>\r
-              TX_DATA_OUT        <= K_DLM;\r
-              TX_K_OUT           <= '1';\r
-              current_state      <= SEND_DLM_H;\r
-              debug_sending_dlm  <= '1';\r
+              TX_DATA_OUT       <= K_DLM;\r
+              TX_K_OUT          <= '1';\r
+              current_state     <= SEND_DLM_H;\r
+              debug_sending_dlm <= '1';\r
 \r
             when SEND_DLM_H =>\r
-              TX_DATA_OUT        <= send_dlm_word_i;\r
+              WORD_SYNC_OUT <= '1';\r
+              TX_DATA_OUT   <= send_dlm_word_i;\r
 \r
             when SEND_RST_L =>\r
-              TX_DATA_OUT        <= K_RST;\r
-              TX_K_OUT           <= '1';\r
-              current_state      <= SEND_RST_H;\r
-              debug_sending_rst  <= '1';\r
+              TX_DATA_OUT       <= K_RST;\r
+              TX_K_OUT          <= '1';\r
+              current_state     <= SEND_RST_H;\r
+              debug_sending_rst <= '1';\r
 \r
             when IDLE =>\r
-              TX_DATA_OUT        <= K_NULL;\r
-              TX_K_OUT           <= '1';\r
-              current_state      <= SEND_IDLE_L;\r
+              TX_DATA_OUT   <= K_NULL;\r
+              TX_K_OUT      <= '1';\r
+              current_state <= SEND_IDLE_L;\r
               -- used to get out of async reset\r
 \r
             when SEND_RST_H =>\r
-              TX_DATA_OUT        <= send_rst_word_i;\r
+              WORD_SYNC_OUT <= '1';\r
+              TX_DATA_OUT   <= send_rst_word_i;\r
 \r
             when others =>\r
-              current_state      <= SEND_IDLE_L;\r
+              current_state <= SEND_IDLE_L;\r
           end case;\r
 \r
           if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or\r
@@ -382,7 +388,8 @@ send_dlm_word_i <= SEND_DLM_WORD_IN;
 --      end if;\r
 --    end process THE_STORE_DLM_PROC;\r
 \r
---Send RST message\r
+-- Send RST message\r
+-- UNTESTED\r
   THE_STORE_RST_PROC: process( CLK_TX, RESET )\r
     begin\r
       if( RESET = '1' ) then\r