Updated the Shutdownlogic files

diff --git a/shutdownlogic/code/shutdown_compare.vhd b/shutdownlogic/code/shutdown_compare.vhd
index 47794b8f141e603ef6063c630ce76f5c20da48da..ef32528752ab72758eac64b6d1b03013b5dd1bad 100644 (file)
--- a/shutdownlogic/code/shutdown_compare.vhd
+++ b/shutdownlogic/code/shutdown_compare.vhd
@@ -57,7 +57,7 @@ PROC_COMPARE: process begin
 wait until rising_edge(clk_in);
  if sum_signals >= max_signals then
       temp_out <= (others => '0');
-      temp_out(0)<='1';
+      temp_out(0) <= '1';
       
  else
       temp_out <= (others => '0');

diff --git a/shutdownlogic/code/shutdown_individual.vhd b/shutdownlogic/code/shutdown_individual.vhd
index 6b1028b48e7211bc5c944eb3bb8d5151f76064e0..bba3cda30ace370e183cc308e2162e9d18dc5b5c 100644 (file)
--- a/shutdownlogic/code/shutdown_individual.vhd
+++ b/shutdownlogic/code/shutdown_individual.vhd
@@ -140,10 +140,9 @@ end process;
 -- 
 -- end process;
 --   
-PROC_MSPUSER: process begin          -- generate a pulse every 10.000 pulses so its every 0.1ms
+PROC_MSPUSER: process begin          -- generate a pulse every 0.1 ms
 wait until rising_edge (clk_in);
-  if ms_timer=x"2710" then        -- eqals 10.000 and 14 dual digits ORIGINAL CODE
---   if ms_timer=x"0196" then        -- eqals 150 ticks
+  if ms_timer=x"2710" then           -- eqals 10.000 rising edges
     ms_pulse<='1';
     ms_timer<=x"0000" ;
   else   

diff --git a/shutdownlogic/code/shutdown_logic.vhd b/shutdownlogic/code/shutdown_logic.vhd
index 8e0af47a73eada230bb7d1b684d991e2b0c3a055..a7ba2cede1f8f8b0ae25fa459a19046b4001bc5b 100644 (file)
--- a/shutdownlogic/code/shutdown_logic.vhd
+++ b/shutdownlogic/code/shutdown_logic.vhd
@@ -43,13 +43,19 @@ signal disableReg_compare: std_logic_vector(31 downto 0):=(others => '0');
 
 
 -- registers for READOUT
-signal current_count: Array32bit:=(others => (others => '0'));                      -- OUTPUT from indiv to bussystem to log the live values of every channel
+signal current_count: Array32bit:=(others => (others => '0'));   
+-- OUTPUT from indiv to bussystem to log the live values of every channel
 signal individual_alerts: std_logic_vector(31 downto 0):=(others => '0');
 
 -- ON / OFF Switch register 32
 signal register_onoff :std_logic_vector(31 downto 0):=(others => '0');
 
 
+-- shutdown Pulse handling
+signal signal_register: std_logic_vector(31 downto 0):=(others => '0');
+signal shutdown_signal: std_logic;
+-- signal shutdown_signal:std_logic_vector(OUTPUTS-1 downto 0);
+
 
 -- hand over the signals between entities
 signal in_2_indiv   :std_logic_vector(INPUTS-1 downto 0);
@@ -60,12 +66,19 @@ signal address_i      : integer range 0 to 255;
 
 
 
+
+
+
+
 begin
 
   address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0)));
---  OUTPUT <= comp_2_out;
+
+
   individual_alerts(INPUTS-1 downto 0) <= indiv_2_comp;
   in_2_indiv <= INPUT;
+--   OUTPUT(0) <= shutdown_signal;
+  signal_register(0) <= shutdown_signal; 
 --  comp_2_out(1) <= not comp_2_out(0);
   
   
@@ -83,9 +96,12 @@ begin
 PROC_OFFSWITCH : process (comp_2_out)             --Version 2 out of sync
   begin
   if register_onoff(0) = '1' then
-    OUTPUT <= comp_2_out;
+    shutdown_signal <= comp_2_out(0);
+--     shutdown_signal <= comp_2_out;
   else 
-    OUTPUT <= (others => '0');
+    shutdown_signal <= '0';
+--     shutdown_signal <= (others => '0');
+ 
   end if;
 end process;
   
@@ -124,6 +140,8 @@ PROC_REGS : process begin
             BUS_TX.data <= individual_alerts;
     elsif BUS_RX.addr(11 downto 8) = x"6" then
             BUS_TX.data <= register_onoff;
+    elsif BUS_RX.addr(11 downto 8) = x"7" then
+            BUS_TX.data <= signal_register;        
     else BUS_TX.ack  <= '0'; BUS_TX.unknown <= '1';       
     end if;  
     

diff --git a/shutdownlogic/config.vhd b/shutdownlogic/config.vhd
index 5a676b7fb73187c8bab4426661ddfc7e57de5c89..d6d02f849bf7f49f5be8af3a1b9e1bcd3bbac1c1 100644 (file)
--- a/shutdownlogic/config.vhd
+++ b/shutdownlogic/config.vhd
@@ -13,7 +13,7 @@ package config is
   constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
   constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
-
+    constant FPGA_TYPE              : integer := 3;
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_200MHZOSCILLATOR   : integer := c_YES;    

diff --git a/shutdownlogic/config_compile_frankfurt.pl b/shutdownlogic/config_compile_frankfurt.pl
index 9de99d5191c2ab65d5e23664333e862f3c856aba..5f49246b9e1796a95cdc9bf7cde28047cd5add1b 100644 (file)
--- a/shutdownlogic/config_compile_frankfurt.pl
+++ b/shutdownlogic/config_compile_frankfurt.pl
@@ -1,8 +1,8 @@
 TOPNAME                      => "trb3sc_basic",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
-lattice_path                 => '/d/jspc29/lattice/diamond/3.8_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+lattice_path                 => '/d/jspc29/lattice/diamond/3.11_x64',
+synplify_path                => '/d/jspc29/lattice/synplify/P-2019.09-SP1/',
 #synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 

diff --git a/shutdownlogic/trb3sc_basic.prj b/shutdownlogic/trb3sc_basic.prj
index 241c751d4faac3aa512894dc4845d749f938b45e..fe04f7a21d8c55e9ab431b80484fba3563612ac7 100644 (file)
--- a/shutdownlogic/trb3sc_basic.prj
+++ b/shutdownlogic/trb3sc_basic.prj
@@ -175,7 +175,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"