...was not in last commit

diff --git a/combiner_calib/code_EBR/Cal_Limits_v2.vhd b/combiner_calib/code_EBR/Cal_Limits_v2.vhd
index 0a6ce895eaf3fc088fd9179dc16ecd83affb19b9..84c413d516e65c2f2b2c285014c217730ac90266 100644 (file)
--- a/combiner_calib/code_EBR/Cal_Limits_v2.vhd
+++ b/combiner_calib/code_EBR/Cal_Limits_v2.vhd
@@ -82,9 +82,9 @@ architecture Behavioral of Cal_Limits_v2 is
   
   
   type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0])
-       signal EBRcntr          : tLocalBuffer;
-       signal EBRbufCurr       : tLocalBuffer;
-       signal EBRbufNext       : tLocalBuffer;
+       signal EBRcntr          : tLocalBuffer := (others =>(others => '0'));
+       signal EBRbufCurr       : tLocalBuffer := (others =>(others => '0'));
+       signal EBRbufNext       : tLocalBuffer := (others =>(others => '0'));
        
        signal DIN_r                                    : std_logic_vector(31 downto 0);
        signal DIN_ready_r              : std_logic;
@@ -227,8 +227,8 @@ begin
                        max_next                <= EBRNext_Max_v;
                else -- no calib
                  write_next    <= '0';
-                 min_next              <= "0000000000";
-                       max_next                <= "0000000000";
+                 min_next              <= "1010101010";
+                       max_next                <= "0101010101";
                        EBRbufNext(locBufDepth-1) <= x"00000000";
                end if;
                
@@ -267,9 +267,9 @@ begin
                        else -- no calibr
                                write_curr      <= '0';
                                write_next      <= '0';
-                               min_out                 <= "0000000000";
+                               min_out                 <= "1111111111";
                                max_out                 <= "0000000000";
-                               min_curr                <= "0000000000";
+                               min_curr                <= "1111111111";
                                max_curr                <= "0000000000";
                                EBRbufNext(locBufDepth-1) <= x"00000000";
                                EBRbufCurr(locBufDepth-1) <= x"00000000";

diff --git a/combiner_calib/code_EBR/Calibration.vhd b/combiner_calib/code_EBR/Calibration.vhd
index 61ab41eb5ec5a678cec324976d92a9255ec43712..9bc2922a0023362b4d27bade51e68e4fe19ec858 100644 (file)
--- a/combiner_calib/code_EBR/Calibration.vhd
+++ b/combiner_calib/code_EBR/Calibration.vhd
@@ -154,6 +154,8 @@ architecture Behavioral of TDC_Calibration is
        signal BUS_Flash_value_r                                        : std_logic_vector(27 downto 0);
        signal Flash_flag_r                                                             : std_logic;
        
+       signal docal_debug_out, docal_debug_in : unsigned(31 downto 0);
+       
 begin
 
 --BUS Handler
@@ -195,6 +197,8 @@ begin
                                                                                                BUS_TX.data( 9 downto  0) <= Bus_min;
                        when x"005"   =>        BUS_TX.data(31 downto 10) <= (others => '0');
                                                                                                BUS_TX.data( 9 downto  0) <= Bus_max;
+                       when x"006"             =>      BUS_TX.data <= docal_debug_in;
+                       when x"007"             =>      BUS_TX.data <= docal_debug_out;
                        when others   =>        BUS_TX.ack <= '0';
                                                                                                BUS_TX.unknown <= '1';
                end case;
@@ -467,11 +471,18 @@ begin
        debug : process (CLK)
        begin 
                if rising_edge(CLK) then
-                       if unsigned(Bus_Chnl) = unsigned(chnl_Lim) then
+                       if (unsigned(Bus_Chnl) = unsigned(chnl_Lim)) and (unsigned(Bus_FPGA) = unsigned(FPGA_Lim)) then
                                Bus_min <= min_out_Lim;
                                Bus_max <= max_out_Lim;
                        end if;
-               end if;
+                       
+                       if do_cal_LIM = '1' then
+                         docal_debug_out <= docal_debug_out + 1;
+                       end if;
+                       if Do_Cal_Memory = '1' then
+                         docal_debug_in <= docal_debug_in + 1;
+                       end if;
+               end if; 
        end process;