]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
pending
authorLudwig Maier <lmaier@brett.e12.ph.tum.de>
Wed, 2 Oct 2013 20:24:39 +0000 (22:24 +0200)
committerLudwig Maier <lmaier@brett.e12.ph.tum.de>
Wed, 2 Oct 2013 20:24:39 +0000 (22:24 +0200)
26 files changed:
base/trb3_periph_nxyter.lpf
nxyter/cores/pll_adc_clk192.ipx [deleted file]
nxyter/cores/pll_adc_clk192.lpc [deleted file]
nxyter/cores/pll_adc_clk192.vhd [deleted file]
nxyter/cores/pll_adc_clk32.ipx [deleted file]
nxyter/cores/pll_adc_clk32.lpc [deleted file]
nxyter/cores/pll_adc_clk32.vhd [deleted file]
nxyter/cores/pll_nx_clk250.ipx
nxyter/cores/pll_nx_clk250.lpc
nxyter/cores/pll_nx_clk250.vhd
nxyter/cores/pll_nx_clk256.ipx [deleted file]
nxyter/cores/pll_nx_clk256.lpc [deleted file]
nxyter/cores/pll_nx_clk256.vhd [deleted file]
nxyter/source/adc_spi_master.vhd
nxyter/source/nx_data_validate.vhd
nxyter/source/nx_fpga_timestamp.vhd
nxyter/source/nx_histograms.vhd
nxyter/source/nx_trigger_handler.vhd
nxyter/source/nx_trigger_validate.vhd
nxyter/source/nxyter_components.vhd
nxyter/source/nxyter_fee_board.vhd
nxyter/source/nxyter_registers.vhd
nxyter/source/registers.txt
nxyter/trb3_periph.prj
nxyter/trb3_periph.vhd
nxyter/trb3_periph_constraints.lpf

index 1d81839e07a13fd6af9863e88fdd3dc602c8b38e..0af0430cb185b337ddfd751829ca910a742ab1a5 100644 (file)
@@ -33,11 +33,9 @@ IOBUF GROUP  "CLK_group" IO_TYPE=LVDS25;
 
 #Trigger from fan-out
 LOCATE COMP  "TRIGGER_LEFT"   SITE "V3";
-LOCATE COMP  "TRIGGER_RIGHT"   SITE "N24";
-IOBUF  PORT  "TRIGGER_RIGHT" IO_TYPE=LVDS25 ; 
-IOBUF  PORT  "TRIGGER_LEFT"  IO_TYPE=LVDS25 ;
-
-
+LOCATE COMP  "TRIGGER_RIGHT"  SITE "N24";
+IOBUF  PORT  "TRIGGER_RIGHT"  IO_TYPE=LVDS25 ; 
+IOBUF  PORT  "TRIGGER_LEFT"   IO_TYPE=LVDS25 ;
 
 
 #################################################################
diff --git a/nxyter/cores/pll_adc_clk192.ipx b/nxyter/cores/pll_adc_clk192.ipx
deleted file mode 100644 (file)
index 1a132a6..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk192" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 15 22:18:00.823" version="5.3" type="Module" synthesis="" source_format="VHDL">
-  <Package>
-               <File name="pll_adc_clk192.lpc" type="lpc" modified="2013 04 15 22:17:56.000"/>
-               <File name="pll_adc_clk192.vhd" type="top_level_vhdl" modified="2013 04 15 22:17:56.000"/>
-               <File name="pll_adc_clk192_tmpl.vhd" type="template_vhdl" modified="2013 04 15 22:17:56.000"/>
-  </Package>
-</DiamondModule>
diff --git a/nxyter/cores/pll_adc_clk192.lpc b/nxyter/cores/pll_adc_clk192.lpc
deleted file mode 100644 (file)
index 244167c..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_clk192
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/15/2013
-Time=22:17:56
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=200
-Div=25
-ClkOPBp=0
-Post=4
-U_OFrq=192
-OP_Tol=0.0
-OFrq=192.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=24
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=1.141439
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
diff --git a/nxyter/cores/pll_adc_clk192.vhd b/nxyter/cores/pll_adc_clk192.vhd
deleted file mode 100644 (file)
index bc30248..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module  Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk192 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 192 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
-
--- Mon Apr 15 22:17:56 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_clk192 is
-    port (
-        CLK: in std_logic; 
-        CLKOP: out std_logic; 
-        LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_clk192 : entity is true;
-end pll_adc_clk192;
-
-architecture Structure of pll_adc_clk192 is
-
-    -- internal signal declarations
-    signal CLKOP_t: std_logic;
-    signal scuba_vlo: std_logic;
-
-    -- local component declarations
-    component EHXPLLF
-        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
-                DELAY_PWD : in String; DELAY_VAL : in Integer; 
-                CLKOS_TRIM_DELAY : in Integer; 
-                CLKOS_TRIM_POL : in String; 
-                CLKOP_TRIM_DELAY : in Integer; 
-                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
-                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
-                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
-                PHASEADJ : in String; CLKOK_DIV : in Integer; 
-                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
-                CLKI_DIV : in Integer; FIN : in String);
-        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
-            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
-            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
-            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
-            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
-            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
-            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
-            LOCK: out std_logic; CLKINTFB: out std_logic);
-    end component;
-    component VLO
-        port (Z: out std_logic);
-    end component;
-    attribute FREQUENCY_PIN_CLKOP : string; 
-    attribute FREQUENCY_PIN_CLKI : string; 
-    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "192.000000";
-    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
-    attribute syn_keep : boolean;
-    attribute syn_noprune : boolean;
-    attribute syn_noprune of Structure : architecture is true;
-
-begin
-    -- component instantiation statements
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
-
-    PLLInst_0: EHXPLLF
-        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
-        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
-        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
-        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
-        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
-        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
-        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  24, CLKI_DIV=>  25, 
-        FIN=> "200.000000")
-        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
-            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
-            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
-            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
-            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
-            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
-            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
-            CLKINTFB=>open);
-
-    CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_clk192 is
-    for Structure
-        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
-        for all:VLO use entity ecp3.VLO(V); end for;
-    end for;
-end Structure_CON;
-
--- synopsys translate_on
diff --git a/nxyter/cores/pll_adc_clk32.ipx b/nxyter/cores/pll_adc_clk32.ipx
deleted file mode 100644 (file)
index 890c7f3..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk32" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 14 23:13:37.959" version="5.3" type="Module" synthesis="" source_format="VHDL">
-  <Package>
-               <File name="pll_adc_clk32.lpc" type="lpc" modified="2013 04 14 23:13:35.000"/>
-               <File name="pll_adc_clk32.vhd" type="top_level_vhdl" modified="2013 04 14 23:13:35.000"/>
-               <File name="pll_adc_clk32_tmpl.vhd" type="template_vhdl" modified="2013 04 14 23:13:35.000"/>
-  </Package>
-</DiamondModule>
diff --git a/nxyter/cores/pll_adc_clk32.lpc b/nxyter/cores/pll_adc_clk32.lpc
deleted file mode 100644 (file)
index 2d97f85..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_clk32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/14/2013
-Time=23:13:35
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=200
-Div=25
-ClkOPBp=0
-Post=16
-U_OFrq=32
-OP_Tol=0.0
-OFrq=32.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=4
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=1.712159
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
diff --git a/nxyter/cores/pll_adc_clk32.vhd b/nxyter/cores/pll_adc_clk32.vhd
deleted file mode 100644 (file)
index a293257..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module  Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk32 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 32 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
-
--- Sun Apr 14 23:13:35 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_clk32 is
-    port (
-        CLK: in std_logic; 
-        CLKOP: out std_logic; 
-        LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_clk32 : entity is true;
-end pll_adc_clk32;
-
-architecture Structure of pll_adc_clk32 is
-
-    -- internal signal declarations
-    signal CLKOP_t: std_logic;
-    signal scuba_vlo: std_logic;
-
-    -- local component declarations
-    component EHXPLLF
-        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
-                DELAY_PWD : in String; DELAY_VAL : in Integer; 
-                CLKOS_TRIM_DELAY : in Integer; 
-                CLKOS_TRIM_POL : in String; 
-                CLKOP_TRIM_DELAY : in Integer; 
-                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
-                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
-                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
-                PHASEADJ : in String; CLKOK_DIV : in Integer; 
-                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
-                CLKI_DIV : in Integer; FIN : in String);
-        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
-            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
-            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
-            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
-            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
-            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
-            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
-            LOCK: out std_logic; CLKINTFB: out std_logic);
-    end component;
-    component VLO
-        port (Z: out std_logic);
-    end component;
-    attribute FREQUENCY_PIN_CLKOP : string; 
-    attribute FREQUENCY_PIN_CLKI : string; 
-    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "32.000000";
-    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
-    attribute syn_keep : boolean;
-    attribute syn_noprune : boolean;
-    attribute syn_noprune of Structure : architecture is true;
-
-begin
-    -- component instantiation statements
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
-
-    PLLInst_0: EHXPLLF
-        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
-        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
-        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
-        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
-        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
-        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
-        CLKOK_DIV=>  2, CLKOP_DIV=>  16, CLKFB_DIV=>  4, CLKI_DIV=>  25, 
-        FIN=> "200.000000")
-        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
-            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
-            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
-            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
-            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
-            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
-            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
-            CLKINTFB=>open);
-
-    CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_clk32 is
-    for Structure
-        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
-        for all:VLO use entity ecp3.VLO(V); end for;
-    end for;
-end Structure_CON;
-
--- synopsys translate_on
index b01a1006d778444d708c0a178d8b006cfc2a0f7f..1b83f8396f25b3bbb8729d21d13a328574538971 100644 (file)
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 28 16:45:26.723" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 16:44:47.426" version="5.3" type="Module" synthesis="" source_format="VHDL">
   <Package>
-               <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 03 28 16:45:22.000"/>
-               <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 03 28 16:45:22.000"/>
-               <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 03 28 16:45:22.000"/>
+               <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 10 02 16:44:45.000"/>
+               <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 10 02 16:44:46.000"/>
+               <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 10 02 16:44:46.000"/>
   </Package>
 </DiamondModule>
index dffc8d9ca7588c9a7ccebe0c6e36e6d5661cd2e1..62403ff0fbef73db780e4e6ded3174a29bf911f7 100644 (file)
@@ -16,8 +16,8 @@ CoreRevision=5.3
 ModuleName=pll_nx_clk250
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=03/28/2013
-Time=16:45:21
+Date=10/02/2013
+Time=16:44:45
 
 [Parameters]
 Verilog=0
@@ -29,8 +29,8 @@ Order=None
 IO=0
 Type=ehxpllb
 mode=normal
-IFrq=125
-Div=1
+IFrq=200
+Div=4
 ClkOPBp=0
 Post=4
 U_OFrq=250
@@ -39,7 +39,7 @@ OFrq=250.000000
 DutyTrimP=Rising
 DelayMultP=0
 fb_mode=CLKOP
-Mult=2
+Mult=5
 Phase=0.0
 Duty=8
 DelayMultS=0
@@ -57,7 +57,7 @@ ClkRst=0
 PCDR=0
 FINDELA=0
 VcoRate=
-Bandwidth=1.485393
+Bandwidth=1.753251
 ;DelayControl=No
 EnCLKOS=0
 ClkOSBp=0
index a72a6bdd22d9d576d39d5b798569fd24d6b16f98..7a3029e3776a9dbe1275746eda6deec7fcadd64f 100644 (file)
@@ -1,8 +1,8 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
 -- Module  Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
 
--- Thu Mar 28 16:45:22 2013
+-- Wed Oct  2 16:44:46 2013
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -54,10 +54,12 @@ architecture Structure of pll_nx_clk250 is
     attribute FREQUENCY_PIN_CLKOP : string; 
     attribute FREQUENCY_PIN_CLKI : string; 
     attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
-    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
     attribute syn_keep : boolean;
     attribute syn_noprune : boolean;
     attribute syn_noprune of Structure : architecture is true;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
 
 begin
     -- component instantiation statements
@@ -71,8 +73,8 @@ begin
         CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
         CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
         PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
-        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  2, CLKI_DIV=>  1
-        FIN=> "125.000000")
+        CLKOK_DIV=>  2, CLKOP_DIV=>  4, CLKFB_DIV=>  5, CLKI_DIV=>  4
+        FIN=> "200.000000")
         port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
             RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
             DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
diff --git a/nxyter/cores/pll_nx_clk256.ipx b/nxyter/cores/pll_nx_clk256.ipx
deleted file mode 100644 (file)
index e14fe9e..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk256" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 13 17:24:25.693" version="5.3" type="Module" synthesis="" source_format="VHDL">
-  <Package>
-               <File name="pll_nx_clk256.lpc" type="lpc" modified="2013 04 13 17:24:24.000"/>
-               <File name="pll_nx_clk256.vhd" type="top_level_vhdl" modified="2013 04 13 17:24:24.000"/>
-               <File name="pll_nx_clk256_tmpl.vhd" type="template_vhdl" modified="2013 04 13 17:24:24.000"/>
-  </Package>
-</DiamondModule>
diff --git a/nxyter/cores/pll_nx_clk256.lpc b/nxyter/cores/pll_nx_clk256.lpc
deleted file mode 100644 (file)
index 61c089f..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_nx_clk256
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/13/2013
-Time=17:24:24
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=100
-Div=25
-ClkOPBp=0
-Post=2
-U_OFrq=256
-OP_Tol=0.0
-OFrq=256.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=64
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=0.856080
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
diff --git a/nxyter/cores/pll_nx_clk256.vhd b/nxyter/cores/pll_nx_clk256.vhd
deleted file mode 100644 (file)
index 1299ae5..0000000
+++ /dev/null
@@ -1,97 +0,0 @@
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module  Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk256 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 256 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e 
-
--- Sat Apr 13 17:24:24 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_nx_clk256 is
-    port (
-        CLK: in std_logic; 
-        CLKOP: out std_logic; 
-        LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_nx_clk256 : entity is true;
-end pll_nx_clk256;
-
-architecture Structure of pll_nx_clk256 is
-
-    -- internal signal declarations
-    signal CLKOP_t: std_logic;
-    signal scuba_vlo: std_logic;
-
-    -- local component declarations
-    component EHXPLLF
-        generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; 
-                DELAY_PWD : in String; DELAY_VAL : in Integer; 
-                CLKOS_TRIM_DELAY : in Integer; 
-                CLKOS_TRIM_POL : in String; 
-                CLKOP_TRIM_DELAY : in Integer; 
-                CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; 
-                CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; 
-                PHASE_DELAY_CNTL : in String; DUTY : in Integer; 
-                PHASEADJ : in String; CLKOK_DIV : in Integer; 
-                CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; 
-                CLKI_DIV : in Integer; FIN : in String);
-        port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; 
-            RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; 
-            DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; 
-            DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; 
-            DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; 
-            FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; 
-            CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; 
-            LOCK: out std_logic; CLKINTFB: out std_logic);
-    end component;
-    component VLO
-        port (Z: out std_logic);
-    end component;
-    attribute FREQUENCY_PIN_CLKOP : string; 
-    attribute FREQUENCY_PIN_CLKI : string; 
-    attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "256.000000";
-    attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
-    attribute syn_keep : boolean;
-    attribute syn_noprune : boolean;
-    attribute syn_noprune of Structure : architecture is true;
-
-begin
-    -- component instantiation statements
-    scuba_vlo_inst: VLO
-        port map (Z=>scuba_vlo);
-
-    PLLInst_0: EHXPLLF
-        generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", 
-        CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", 
-        CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=>  0, 
-        CLKOS_TRIM_DELAY=>  0, CLKOS_TRIM_POL=> "RISING", 
-        CLKOP_TRIM_DELAY=>  0, CLKOP_TRIM_POL=> "RISING", 
-        PHASE_DELAY_CNTL=> "STATIC", DUTY=>  8, PHASEADJ=> "0.0", 
-        CLKOK_DIV=>  2, CLKOP_DIV=>  2, CLKFB_DIV=>  64, CLKI_DIV=>  25, 
-        FIN=> "100.000000")
-        port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, 
-            RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, 
-            DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, 
-            DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, 
-            DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, 
-            FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, 
-            CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, 
-            CLKINTFB=>open);
-
-    CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_nx_clk256 is
-    for Structure
-        for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
-        for all:VLO use entity ecp3.VLO(V); end for;
-    end for;
-end Structure_CON;
-
--- synopsys translate_on
index 9b73513d403e8df994161d1ccaa3492901085c20..264a82776499942c8198ee190a23d19eaa96ad68 100644 (file)
@@ -155,9 +155,9 @@ begin
   -- Debug Line
 
   DEBUG_OUT(0)           <= CLK_IN;
-  DEBUG_OUT(1)           <= SCLK_OUT;
+  DEBUG_OUT(1)           <= sclk_o;
   DEBUG_OUT(2)           <= SDIO_INOUT;
-  DEBUG_OUT(3)           <= CSB_OUT;
+  DEBUG_OUT(3)           <= csb_o;
   DEBUG_OUT(4)           <= spi_busy;
   DEBUG_OUT(5)           <= wait_timer_done;
   DEBUG_OUT(6)           <= sendbyte_seq_start;
index ff689639419c1651df49e9f27fc0ee6e1633876c..d3c5907f404cb01c6437189f01fba71bcdb207b3 100644 (file)
@@ -205,7 +205,7 @@ begin
         data_valid_o         <= '0';
         trigger_rate_inc     <= '0';
         frame_rate_inc       <= '0';
-        invalid_adc <= '0';
+        invalid_adc          <= '0';
 
         if (new_timestamp = '1') then
           case valid_frame_bits is
@@ -297,8 +297,16 @@ begin
         else
           nx_trigger_rate      <= nx_trigger_ctr_t;
           nx_frame_rate        <= nx_frame_ctr_t;
-          nx_trigger_ctr_t     <= (others => '0');
-          nx_frame_ctr_t       <= (others => '0');
+          if (trigger_rate_inc = '0') then
+            nx_trigger_ctr_t   <= (others => '0');
+          else
+            nx_trigger_ctr_t   <= x"000_0001";
+          end if;
+          if (frame_rate_inc = '0') then
+            nx_frame_ctr_t     <= (others => '0');
+          else
+            nx_frame_ctr_t     <= x"000_0001";
+          end if;
           nx_rate_timer        <= (others => '0');
         end if;
       end if;
index 21bd917f47da4a25ccb5c0d46a3539706b814e3f..884a0f18a2fe5f2701907a051bd320459f559c23 100644 (file)
@@ -7,9 +7,10 @@ use work.nxyter_components.all;
 
 entity nx_fpga_timestamp is
   port (
-    CLK_IN                : in  std_logic;
+    CLK_IN                : in std_logic;
     RESET_IN              : in  std_logic;
-
+    NX_CLK_IN             : in  std_logic;      
+    
     TIMESTAMP_SYNC_IN     : in  std_logic;
     TRIGGER_IN            : in  std_logic;
     TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
@@ -31,10 +32,9 @@ entity nx_fpga_timestamp is
 end entity;
 
 architecture Behavioral of nx_fpga_timestamp is
-
   signal timestamp_ctr       : unsigned(11 downto 0);
   signal timestamp_current_o : unsigned(11 downto 0);
-  signal timestamp_hold_o    : unsigned(11 downto 0);
+  signal timestamp_hold      : std_logic_vector(11 downto 0);
   signal trigger_x           : std_logic;
   signal trigger_l           : std_logic;
   signal trigger             : std_logic;
@@ -43,19 +43,32 @@ architecture Behavioral of nx_fpga_timestamp is
   signal timestamp_sync      : std_logic;
 
   signal nx_timestamp_sync_o : std_logic;
+
+  signal fifo_full          : std_logic;
+  signal fifo_write_enable    : std_logic;
+
+  -- Main Clock Domain
+  signal fifo_empty          : std_logic;
+  signal fifo_read_enable    : std_logic;
+  signal fifo_data_valid_t   : std_logic; 
+  signal fifo_data_valid     : std_logic;
+  signal fifo_data_out       : std_logic_vector(11 downto 0);
+  signal timestamp_hold_o    : unsigned(11 downto 0);
   
 begin
 
-  DEBUG_OUT(0)           <= CLK_IN;
+  DEBUG_OUT(0)           <= NX_CLK_IN;
   DEBUG_OUT(1)           <= trigger;
   DEBUG_OUT(2)           <= timestamp_sync;
   DEBUG_OUT(3)           <= '0';
   DEBUG_OUT(15 downto 4) <= timestamp_hold_o;
+
+  -- NX Clock Domain
   
-  -- Cross Clockdomain for TRIGGER and SYNC signal
-  PROC_SYNC: process (CLK_IN)
+  -- Cross Clockdomain for TRIGGER and SYNC 
+  PROC_SYNC: process (NX_CLK_IN)
   begin
-    if( rising_edge(CLK_IN) ) then
+    if( rising_edge(NX_CLK_IN) ) then
       if (RESET_IN = '1') then
         trigger_x        <= '0';
         trigger_l        <= '0';
@@ -73,7 +86,7 @@ begin
   -- Convert TRIGGER_IN to Pulse
   level_to_pulse_1: level_to_pulse
     port map (
-      CLK_IN    => CLK_IN,
+      CLK_IN    => NX_CLK_IN,
       RESET_IN  => RESET_IN,
       LEVEL_IN  => trigger_l,
       PULSE_OUT => trigger
@@ -82,7 +95,7 @@ begin
   -- Convert TIMESTAMP_SYNC_IN to Pulse
   level_to_pulse_2: level_to_pulse
     port map (
-      CLK_IN    => CLK_IN,
+      CLK_IN    => NX_CLK_IN,
       RESET_IN  => RESET_IN,
       LEVEL_IN  => timestamp_sync_l,
       PULSE_OUT => timestamp_sync
@@ -90,32 +103,72 @@ begin
 
   -- Timestamp Process + Trigger
   
-  PROC_TIMESTAMP_CTR: process (CLK_IN)
+  PROC_TIMESTAMP_CTR: process (NX_CLK_IN)
   begin
-    if( rising_edge(CLK_IN) ) then
+    if( rising_edge(NX_CLK_IN) ) then
       if( RESET_IN = '1' ) then
         timestamp_ctr         <= (others => '0');
         timestamp_hold_o      <= (others => '0');
         nx_timestamp_sync_o   <= '0';
+        fifo_write_enable     <= '0';
       else
         nx_timestamp_sync_o   <= '0';
-        
+        fifo_write_enable     <= '0';   
+
         if (timestamp_sync = '1') then
           timestamp_ctr       <= (others => '0');
           timestamp_hold_o    <= (others => '0');
           nx_timestamp_sync_o <= '1';
         else
-          if (trigger = '1') then
-            timestamp_hold_o  <= timestamp_ctr - 3;
+          if (trigger = '1' and fifo_full = '0') then
+            timestamp_hold    <= std_logic_vector(timestamp_ctr - 3);
+            fifo_write_enable <= '1';
           end if;
           timestamp_ctr       <= timestamp_ctr + 1;
         end if;
       end if;
     end if;
-  end process;
+  end process PROC_TIMESTAMP_CTR;
 
   timestamp_current_o         <= timestamp_ctr;
 
+  -----------------------------------------------------------------------------
+  -- Main Clock Domain -> Tranfer TimeStamp
+  -----------------------------------------------------------------------------
+  
+  fifo_ts_12to12_dc_1: fifo_ts_12to12_dc
+    port map (
+      Data    => timestamp_hold,
+      WrClock => NX_CLK_IN,
+      RdClock => CLK_IN,
+      WrEn    => fifo_write_enable,
+      RdEn    => fifo_read_enable,
+      Reset   => RESET_IN,
+      RPReset => RESET_IN,
+      Q       => fifo_data_out,
+      Empty   => fifo_empty,
+      Full    => fifo_full
+    );
+
+  fifo_read_enable  <= not fifo_empty;
+
+  PROC_RECEIVE_TS: process (CLK_IN)
+  begin
+    if( rising_edge(NX_CLK_IN) ) then
+      if( RESET_IN = '1' ) then
+        fifo_data_valid_t    <= '0';
+        fifo_data_valid      <= '0';
+        timestamp_hold       <= (others => '0');
+      else
+        if (fifo_data_valid = '1') then
+          timestamp_hold       <= unsigned(fifo_data_out);
+        end if;
+
+        fifo_data_valid_t    <= fifo_read_enable;
+        fifo_data_valid      <= fifo_data_valid;
+      end if;
+    end if;
+  end process PROC_RECEIVE_TS;
   
   -----------------------------------------------------------------------------
   -- Output Signals
index 2465d5ab0ba2681f13213a2983d1ad6b23e540e3..c2c9623795e08e66a136716c1b8f21d61223c0ef 100644 (file)
@@ -15,10 +15,11 @@ entity nx_histograms is
     RESET_IN             : in  std_logic;
                          
     RESET_HISTS_IN       : in  std_logic;
-                         
+
     CHANNEL_STAT_FILL_IN : in  std_logic;
     CHANNEL_ID_IN        : in  std_logic_vector(BUS_WIDTH - 1 downto 0);
-
+    CHANNEL_ADC_IN       : in  std_logic_vector(11 downto 0);
+    
     -- Slave bus         
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
@@ -41,9 +42,13 @@ architecture nx_histograms of nx_histograms is
   -- PROC_CHANNEL_HIST
   signal hist_channel_stat    : histogram_t;
   signal hist_channel_freq    : histogram_t;
+
   signal wait_timer_init      : unsigned(27 downto 0);
   signal wait_timer_done      : std_logic;
 
+  -- PROC_CHANNEL_HIST
+  signal hist_channel_adc     : histogram_t;
+  
   -- Slave Bus                    
   signal slv_data_out_o       : std_logic_vector(31 downto 0);
   signal slv_no_more_data_o   : std_logic;
@@ -58,21 +63,24 @@ hist_enable_1: if ENABLE = 1 generate
   DEBUG_OUT(1)           <= RESET_IN;  
   DEBUG_OUT(2)           <= RESET_HISTS_IN; 
   DEBUG_OUT(3)           <= reset_hists_r;
-  DEBUG_OUT(4)           <= slv_ack_o;
-  DEBUG_OUT(5)           <= SLV_READ_IN;
-  DEBUG_OUT(6)           <= SLV_WRITE_IN;
-  DEBUG_OUT(7)           <= wait_timer_done;
-  DEBUG_OUT(15 downto 8) <= (others => '0');
+  DEBUG_OUT(4)           <= CHANNEL_STAT_FILL_IN;
+  DEBUG_OUT(5)           <= slv_ack_o;
+  DEBUG_OUT(6)           <= SLV_READ_IN;
+  DEBUG_OUT(7)           <= SLV_WRITE_IN;
+  DEBUG_OUT(8)           <= wait_timer_done;
+  DEBUG_OUT(15 downto 9) <= CHANNEL_ID_IN;
   
   -----------------------------------------------------------------------------
   
   PROC_CHANNEL_HIST : process (CLK_IN)
+    variable value : unsigned(31 downto 0);
   begin
     if( rising_edge(CLK_IN) ) then
       if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then
         for I in 0 to (2**BUS_WIDTH - 1) loop
          hist_channel_stat(I) <= (others => '0');
          hist_channel_freq(I) <= (others => '0');
+         hist_channel_adc(I) <= (others => '0');
         end loop;
         wait_timer_init       <= x"000_0001";
       else
@@ -88,12 +96,16 @@ hist_enable_1: if ENABLE = 1 generate
           if (CHANNEL_STAT_FILL_IN = '1') then
             hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
               hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
+            
+            value := (hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN)))
+                      + unsigned(CHANNEL_ADC_IN)) / 2;
+            hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) <= value;
           end if;
         end if;
       end if;
     end if;
   end process PROC_CHANNEL_HIST;  
-
+  
   -- Timer
   nx_timer_1: nx_timer
     generic map (
@@ -133,14 +145,18 @@ hist_enable_1: if ENABLE = 1 generate
             slv_data_out_o(31 downto 0)  <= std_logic_vector(
               hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
               );
-           -- slv_data_out_o(31 downto 24) <= (others => '0');
             slv_ack_o                    <= '1';
           elsif (unsigned(SLV_ADDR_IN) >= x"0080" and
                  unsigned(SLV_ADDR_IN) <= x"00ff") then
             slv_data_out_o(31 downto 0)  <= std_logic_vector(
               hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
               );
-           -- slv_data_out_o(31 downto 24) <= (others => '0');
+            slv_ack_o                    <= '1';
+          elsif (unsigned(SLV_ADDR_IN) >= x"0100" and
+                 unsigned(SLV_ADDR_IN) <= x"017f") then
+            slv_data_out_o(31 downto 0)  <= std_logic_vector(
+              hist_channel_adc(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
+              );
             slv_ack_o                    <= '1';
           else
             slv_ack_o                    <= '0';
index 8df99a7ac841285b49f462fc368f944ae6eb02b8..095ee7324d8e45033d9a228c52e876b95d3b910f 100644 (file)
@@ -64,15 +64,15 @@ architecture Behavioral of nx_trigger_handler is
 
   -- Trigger Handler
   signal validate_trigger_o       : std_logic;
-  signal timestamp_hold           : std_logic;
   signal lvl2_trigger_o           : std_logic;
   signal event_buffer_clear_o     : std_logic;
   signal fast_clear_o             : std_logic;
   signal trigger_busy_o           : std_logic;
   signal fee_trg_release_o        : std_logic;
   signal fee_trg_statusbits_o     : std_logic_vector(31 downto 0);
-  signal trigger_testpulse_o      : std_logic;
-
+  signal timestamp_trigger_o      : std_logic;
+  signal send_testpulse           : std_logic;
+  
   type STATES is (S_IDLE,
                   S_CTS_TRIGGER,
                   S_WAIT_TRG_DATA_VALID,
@@ -85,13 +85,15 @@ architecture Behavioral of nx_trigger_handler is
                   );
   signal STATE : STATES;
 
-  -- Timestamp Hold Handler
-  type TS_STATES is (TS_IDLE,
-                     TS_WAIT_TIMER_DONE
-                     );
-  signal TS_STATE : TS_STATES;
+  -- Testpulse Handler
+  type T_STATES is (T_IDLE,
+                    T_WAIT_TIMER,
+                    T_SET_TESTPULSE
+                    );
+  
+  signal T_STATE : T_STATES;
 
-  signal timestamp_trigger_o         : std_logic;
+  signal trigger_testpulse_o      : std_logic;
   signal wait_timer_reset            : std_logic;
   signal wait_timer_init             : unsigned(7 downto 0);
   signal wait_timer_done             : std_logic;
@@ -106,7 +108,7 @@ architecture Behavioral of nx_trigger_handler is
   signal slv_unknown_addr_o          : std_logic;
   signal slv_ack_o                   : std_logic;
 
-  signal reg_timestamp_trigger_delay : unsigned(7 downto 0);
+  signal reg_testpulse_delay         : unsigned(7 downto 0);
   signal reg_testpulse_enable        : std_logic;
   signal accepted_trigger_rate       : unsigned(27 downto 0);
   
@@ -126,11 +128,10 @@ begin
   DEBUG_OUT(9)            <= event_buffer_clear_o;
   DEBUG_OUT(10)           <= fee_trg_release_o;
   DEBUG_OUT(11)           <= trigger_busy_o;
-  DEBUG_OUT(12)           <= trigger_testpulse_o;
-  DEBUG_OUT(13)           <= slv_unknown_addr_o;
-  DEBUG_OUT(14)           <= slv_no_more_data_o;
-  DEBUG_OUT(15)           <= slv_unknown_addr_o;
---  DEBUG_OUT(15 downto 13) <= (others => '0');
+  DEBUG_OUT(12)           <= timestamp_trigger_o;
+  DEBUG_OUT(13)           <= send_testpulse;
+  DEBUG_OUT(14)           <= trigger_testpulse_o;
+  DEBUG_OUT(15)           <= '0';
 
   -- Timer
   nx_timer_1: nx_timer
@@ -155,25 +156,25 @@ begin
     if( rising_edge(CLK_IN) ) then
       if (RESET_IN = '1') then
         validate_trigger_o   <= '0';
-        timestamp_hold       <= '0';
         lvl2_trigger_o       <= '0';
         fee_trg_release_o    <= '0';
         fee_trg_statusbits_o <= (others => '0');
         fast_clear_o         <= '0';
         event_buffer_clear_o <= '0';
         trigger_busy_o       <= '0';
-        trigger_testpulse_o  <= '0';
+        send_testpulse       <= '0';
+        timestamp_trigger_o  <= '0';
         STATE                <= S_IDLE;
       else
         validate_trigger_o   <= '0';
-        timestamp_hold       <= '0';
         lvl2_trigger_o       <= '0';
         fee_trg_release_o    <= '0';
         fee_trg_statusbits_o <= (others => '0');
         fast_clear_o         <= '0';
         event_buffer_clear_o <= '0';
         trigger_busy_o       <= '1';
-        trigger_testpulse_o  <= '0';
+        send_testpulse       <= '0';
+        timestamp_trigger_o  <= '0';
 
         if (LVL1_INVALID_TRG_IN = '1') then
           fast_clear_o         <= '1';
@@ -198,14 +199,14 @@ begin
                 STATE                <= S_IDLE;
               end if;     
 
-              -- CTS Trigger Handler
+                                        -- CTS Trigger Handler
             when S_CTS_TRIGGER =>
               event_buffer_clear_o   <= '1';
               validate_trigger_o     <= '1';
-              timestamp_hold         <= '1';
+              timestamp_trigger_o    <= '1';
               lvl2_trigger_o         <= '1';
               if (reg_testpulse_enable = '1') then
-                trigger_testpulse_o  <= '1';
+                send_testpulse       <= '1';
               end if;
               STATE                  <= S_WAIT_TRG_DATA_VALID;
 
@@ -237,7 +238,7 @@ begin
               -- Internal Trigger Handler
             when S_INTERNAL_TRIGGER =>
               validate_trigger_o     <= '1';
-              timestamp_hold         <= '1';
+              timestamp_trigger_o    <= '1';
               event_buffer_clear_o   <= '1';
               STATE                  <= S_WAIT_TRIGGER_VALIDATE_ACK;
 
@@ -261,41 +262,46 @@ begin
     end if;
   end process PROC_TRIGGER_HANDLER;
 
-  PROC_SEND_TIMSTAMP_TRIGGER: process(CLK_IN)
-  begin
+  PROC_TESTPULSE_HANDLER: process (CLK_IN)
+  begin 
     if( rising_edge(CLK_IN) ) then
-      if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then
+      if (RESET_IN = '1' or fast_clear_o = '1') then
         wait_timer_init      <= (others => '0');
-        timestamp_trigger_o  <= '0';
-        TS_STATE             <= TS_IDLE;
+        trigger_testpulse_o  <= '0';
+        T_STATE              <= T_IDLE;
       else
+        trigger_testpulse_o  <= '0';
         wait_timer_init      <= (others => '0');
-        timestamp_trigger_o  <= '0';
 
-        case TS_STATE is
+        case T_STATE is
 
-          when TS_IDLE =>
-            if (timestamp_hold = '0') then
-              TS_STATE            <= TS_IDLE;
+          when T_IDLE => 
+            if (send_testpulse = '1') then
+              if (reg_testpulse_delay > 0) then
+                wait_timer_init <= reg_testpulse_delay;
+                T_STATE         <= T_WAIT_TIMER;
+              else
+                T_STATE         <= T_SET_TESTPULSE;
+              end if;
             else
-              wait_timer_init     <= reg_timestamp_trigger_delay;
-              TS_STATE            <= TS_WAIT_TIMER_DONE;
+              T_STATE           <= T_IDLE;
             end if;
 
-          when TS_WAIT_TIMER_DONE =>
+          when T_WAIT_TIMER =>
             if (wait_timer_done = '0') then
-              TS_STATE            <= TS_WAIT_TIMER_DONE;
+              T_STATE           <= T_WAIT_TIMER;
             else
-              timestamp_trigger_o <= '1';
-              TS_STATE            <= TS_IDLE;
+              T_STATE           <= T_SET_TESTPULSE;
             end if;
 
-        end case;
-            
+          when T_SET_TESTPULSE =>
+            trigger_testpulse_o <= '1';
+            T_STATE             <= T_IDLE;
+        end case;           
       end if;
     end if;
-  end process PROC_SEND_TIMSTAMP_TRIGGER;
-
+  end process PROC_TESTPULSE_HANDLER; 
+      
   PROC_CAL_RATES: process (CLK_IN)
   begin 
     if( rising_edge(CLK_IN) ) then
@@ -326,33 +332,30 @@ begin
   begin
     if( rising_edge(CLK_IN) ) then
       if( RESET_IN = '1' ) then
-        slv_data_out_o              <= (others => '0');
-        slv_no_more_data_o          <= '0';
-        slv_unknown_addr_o          <= '0';
-        slv_ack_o                   <= '0';
-        reg_timestamp_trigger_delay <= x"01";
-        reg_testpulse_enable        <= '0';
+        slv_data_out_o          <= (others => '0');
+        slv_no_more_data_o      <= '0';
+        slv_unknown_addr_o      <= '0';
+        slv_ack_o               <= '0';
+        reg_testpulse_delay     <= (others => '0');
+        reg_testpulse_enable    <= '0';
       else
-        slv_unknown_addr_o          <= '0';
-        slv_no_more_data_o          <= '0';
-        slv_data_out_o              <= (others => '0');
-        slv_ack_o                   <= '0';
+        slv_unknown_addr_o      <= '0';
+        slv_no_more_data_o      <= '0';
+        slv_data_out_o          <= (others => '0');
+        slv_ack_o               <= '0';
         
         if (SLV_WRITE_IN  = '1') then
           case SLV_ADDR_IN is
             when x"0000" =>
-              if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then
-                reg_timestamp_trigger_delay <=
-                  unsigned(SLV_DATA_IN(7 downto 0));
-              end if;
-              slv_ack_o                   <= '1';
+              reg_testpulse_delay          <= unsigned(SLV_DATA_IN(7 downto 0));
+              slv_ack_o                    <= '1';
 
             when x"0001" =>
-              reg_testpulse_enable        <= SLV_DATA_IN(0);
-              slv_ack_o                   <= '1';
-              
+              reg_testpulse_enable         <= SLV_DATA_IN(0);
+              slv_ack_o                    <= '1';
+
             when others =>
-              slv_unknown_addr_o          <= '1';
+              slv_unknown_addr_o           <= '1';
 
           end case;
 
@@ -361,7 +364,7 @@ begin
 
             when x"0000" =>
               slv_data_out_o(7 downto 0)   <=
-                std_logic_vector(reg_timestamp_trigger_delay);
+                std_logic_vector(reg_testpulse_delay);
               slv_data_out_o(31 downto 8)  <= (others => '0');
               slv_ack_o                    <= '1';
 
index 462b1a6cf44de9803afcdb907c21ebf110ee94bb..7219ddca480e0f13bb66ff0cd091fc0d40801385 100644 (file)
@@ -35,6 +35,7 @@ entity nx_trigger_validate is
     -- Histogram
     HISTOGRAM_FILL_OUT   : out std_logic;
     HISTOGRAM_BIN_OUT    : out std_logic_vector(6 downto 0);
+    HISTOGRAM_ADC_OUT    : out std_logic_vector(11 downto 0);
     
     -- Slave bus         
     SLV_READ_IN          : in  std_logic;
@@ -53,10 +54,6 @@ end entity;
 
 architecture Behavioral of nx_trigger_validate is
 
-  -- Sync Ref
-  signal timestamp_ref_x      : unsigned(11 downto 0);
-  signal timestamp_ref        : unsigned(11 downto 0);
-
   -- Process Channel_Status
   signal channel_index        : std_logic_vector(6 downto 0);
   signal channel_wait         : std_logic_vector(127 downto 0);
@@ -103,14 +100,19 @@ architecture Behavioral of nx_trigger_validate is
   signal busy_time_ctr        : unsigned(11 downto 0);
   signal busy_time_min_done   : std_logic;
   signal wait_timer_reset     : std_logic;
+  signal event_counter        : unsigned(9 downto 0);
+  
+  signal readout_mode         : std_logic_vector(3 downto 0);
+  signal timestamp_ref        : unsigned(11 downto 0);
 
-    -- Timer
+  -- Timer
   signal timer_reset          : std_logic;
   signal wait_timer_done      : std_logic;
     
   -- Histogram
   signal histogram_fill_o     : std_logic;
   signal histogram_bin_o      : std_logic_vector(6 downto 0);
+  signal histogram_adc_o      : std_logic_vector(11 downto 0);
 
   -- Slave Bus                    
   signal slv_data_out_o       : std_logic_vector(31 downto 0);
@@ -118,7 +120,7 @@ architecture Behavioral of nx_trigger_validate is
   signal slv_unknown_addr_o   : std_logic;
   signal slv_ack_o            : std_logic;
 
-  signal readout_mode         : std_logic_vector(3 downto 0);
+  signal readout_mode_r       : std_logic_vector(3 downto 0);
   signal trigger_window_width : unsigned(11 downto 0);
   signal trigger_window_delay : unsigned(11 downto 0);
   signal readout_time_max     : unsigned(11 downto 0);
@@ -158,25 +160,11 @@ begin
 
   timer_reset <= RESET_IN or wait_timer_reset;
   
-  -- Sync Timestamp Ref
-  PROC_SYNC_TIMESTAMP_REF: process (CLK_IN)
-  begin
-    if( rising_edge(CLK_IN) ) then
-      if (RESET_IN = '1') then
-        timestamp_ref_x <= (others => '0');
-        timestamp_ref   <= (others => '0');
-      else
-        timestamp_ref_x <= TIMESTAMP_REF_IN;
-        timestamp_ref   <= timestamp_ref_x;
-      end if;
-    end if;
-  end process PROC_SYNC_TIMESTAMP_REF;
-  
   -----------------------------------------------------------------------------
   -- Filter only valid events
   -----------------------------------------------------------------------------
 
-  PROC_PROCESS_TIMESTAMP: process (CLK_IN)
+  PROC_FILTER_TIMESTAMPS: process (CLK_IN)
     variable ts_ref             : unsigned(11 downto 0);
     variable window_lower_thr   : unsigned(11 downto 0);
     variable window_upper_thr   : unsigned(11 downto 0);
@@ -201,6 +189,7 @@ begin
 
         histogram_fill_o     <= '0';
         histogram_bin_o      <= (others => '0');
+        histogram_adc_o      <= (others => '0');
         
         if (DATA_CLK_IN = '1') then
           if (store_to_fifo = '1') then
@@ -215,7 +204,7 @@ begin
             
             case readout_mode is
               
-              when x"0" =>            -- RefValue + valid and window filter 
+              when x"0" =>            -- RefValue + valid + window filter limit
                 if (TIMESTAMP_STATUS_IN(1) = '0') then
                   if (deltaT < window_lower_thr) then
                     out_of_window_l        <= '1';
@@ -233,59 +222,52 @@ begin
                     -- IN LUT-Data bit setzten.
                     channel_index          <= CHANNEL_IN;
                     ch_status_cmd_pr       <= CS_SET_WAIT;
-
-                    data_o( 6 downto  0)   <= CHANNEL_IN;
-                    data_o(7)              <= TIMESTAMP_STATUS_IN(1);
-                    data_o( 9 downto  8)   <= TIMESTAMP_IN(1 downto 0);
-                    data_o(18 downto  10)  <= deltaTStore(8 downto 0);
-                    data_o(30 downto 19)   <= ADC_DATA_IN;
+                    
+                    data_o( 1 downto  0)   <= TIMESTAMP_IN(1 downto 0);
+                    data_o(11 downto  2)   <= deltaTStore(9 downto 0);
+                    data_o(23 downto 12)   <= ADC_DATA_IN;
+                    data_o(30 downto 24)   <= CHANNEL_IN;
                     data_o(31)             <= TIMESTAMP_STATUS_IN(2);
                     data_clk_o             <= '1';
                   end if;
                 end if;
                 
-              when x"1" =>            -- RefValue + valid filter
+              when x"1" =>            -- RefValue + valid filter + maxtime limit
                 if (TIMESTAMP_STATUS_IN(1) = '0') then
-                  data_o( 6 downto  0)     <= CHANNEL_IN;
-                  data_o(7)                <= TIMESTAMP_STATUS_IN(1);
-                  data_o( 9 downto  8)     <= TIMESTAMP_IN(1 downto 0);
-                  data_o(18 downto  10)    <= deltaTStore(8 downto 0);
-                  data_o(30 downto 19)     <= ADC_DATA_IN;
+                  data_o( 1 downto  0)     <= TIMESTAMP_IN(1 downto 0);
+                  data_o(11 downto  2)     <= deltaTStore(9 downto 0);
+                  data_o(23 downto 12)     <= ADC_DATA_IN;
+                  data_o(30 downto 24)     <= CHANNEL_IN;
                   data_o(31)               <= TIMESTAMP_STATUS_IN(2);
                   data_clk_o               <= '1';
                 end if;
 
               when x"3" =>            -- RefValue + valid filter
                 if (TIMESTAMP_STATUS_IN(1) = '0') then
-                  data_o( 6 downto  0)     <= CHANNEL_IN;
-                  data_o(7)                <= TIMESTAMP_STATUS_IN(1);
-                  data_o( 9 downto  8)     <= TIMESTAMP_IN(1 downto 0);
-                  data_o(18 downto  10)    <= deltaTStore(8 downto 0);
-                  data_o(30 downto 19)     <= ADC_DATA_IN;
+                  data_o( 1 downto  0)     <= TIMESTAMP_IN(1 downto 0);
+                  data_o(11 downto  2)     <= deltaTStore(9 downto 0);
+                  data_o(23 downto 12)     <= ADC_DATA_IN;
+                  data_o(30 downto 24)     <= CHANNEL_IN;
                   data_o(31)               <= TIMESTAMP_STATUS_IN(2);
-                  data_clk_o <= '1';
+                  data_clk_o               <= '1';
                 end if;
-                
-              when x"4" =>            -- RawValue
-                data_o( 6 downto  0)       <= CHANNEL_IN;
-                data_o(7)                  <= TIMESTAMP_STATUS_IN(1);
-                data_o( 9 downto  8)       <= TIMESTAMP_IN(1 downto 0);
-                data_o(18 downto  10)      <= deltaTStore(8 downto 0);
-                data_o(30 downto 19)       <= ADC_DATA_IN;
-                data_o(31)                 <= TIMESTAMP_STATUS_IN(2);
-                data_clk_o                 <= '1';
 
-              when x"5" =>            -- RawValue + valid filter
+              when x"4" =>            -- RawValue + valid filter
                 if (TIMESTAMP_STATUS_IN(1) = '0') then
-                  data_o( 6 downto  0)     <= CHANNEL_IN;
-                  data_o(7)                <= TIMESTAMP_STATUS_IN(1);
-                  data_o( 9 downto  8)     <= TIMESTAMP_IN(1 downto 0);
-                  data_o(18 downto  10)    <= deltaTStore(8 downto 0);
-                  data_o(30 downto 19)     <= ADC_DATA_IN;
-                  data_o(31)               <= TIMESTAMP_STATUS_IN(2);
-                  data_clk_o               <= '1';
+                  data_o(11 downto  0)       <= TIMESTAMP_IN(13 downto 2);
+                  data_o(23 downto 12)       <= ADC_DATA_IN;
+                  data_o(30 downto 24)       <= CHANNEL_IN;
+                  data_o(31)                 <= TIMESTAMP_STATUS_IN(2);
+                  data_clk_o                 <= '1';
                 end if;
-
+  
+              when x"5" =>            -- RawValue + maxtime limit
+                data_o(11 downto  0)       <= TIMESTAMP_IN(13 downto 2);
+                data_o(23 downto 12)       <= ADC_DATA_IN;
+                data_o(30 downto 24)       <= CHANNEL_IN;
+                data_o(31)                 <= TIMESTAMP_STATUS_IN(2);
+                data_clk_o                 <= '1';
+              
               when others => null;
 
             end case;
@@ -295,10 +277,11 @@ begin
           -- Fill Histogram
           histogram_fill_o    <= '1';
           histogram_bin_o     <= CHANNEL_IN;
+          histogram_adc_o     <= ADC_DATA_IN;
         end if;
       end if;
     end if;
-  end process PROC_PROCESS_TIMESTAMP;
+  end process PROC_FILTER_TIMESTAMPS;
 
   -----------------------------------------------------------------------------
   -- Trigger Handler
@@ -321,6 +304,9 @@ begin
         busy_time_min_done    <= '0';
         token_return_ctr      <= '0';
         ch_status_cmd_tr      <= CS_RESET;
+        event_counter         <= (others => '0');
+        readout_mode          <= (others => '0');
+        timestamp_ref         <= (others => '0');
         STATE                 <= S_IDLE;
       else
         store_to_fifo         <= '0';
@@ -335,7 +321,6 @@ begin
         min_validation_time := x"020" +
                                (trigger_window_delay / 2) +
                                (trigger_window_width / 2);
-
         
         case STATE is
           
@@ -349,6 +334,7 @@ begin
             end if;
             
           when S_TRIGGER =>
+            readout_mode           <= readout_mode_r;
             ch_status_cmd_tr       <= CS_RESET;
             wait_timer_init        <= x"020";    -- wait 320ns for first event
             STATE                  <= S_WAIT_DATA;
@@ -357,15 +343,27 @@ begin
             if (wait_timer_done = '0') then
               STATE                <= S_WAIT_DATA;
             else
+              timestamp_ref        <= TIMESTAMP_REF_IN;
               STATE                <= S_WRITE_HEADER;
             end if;
 
           when S_WRITE_HEADER =>
-            --ts_ref                 := timestamp_ref - x"010";
-            t_data_o(11 downto 0)  <=  timestamp_ref;
-            t_data_o(15 downto 12) <= (others => '0');
-            t_data_o(31 downto 16) <= BOARD_ID;
+            t_data_o(11 downto 0)  <= timestamp_ref;
+            t_data_o(21 downto 12) <= event_counter;
+            -- Readout Mode Mapping (so far)
+            -- 00: Standard
+            -- 01: Special
+            -- 10: DEBUG
+            -- 11: UNDEF
+            case readout_mode is
+              when x"0"   => t_data_o(23 downto 22) <= "00";
+              when x"1"   => t_data_o(23 downto 22) <= "01";
+              when others => t_data_o(23 downto 22) <= "11";
+            end case;
+            t_data_o(31 downto 24) <= BOARD_ID(7 downto 0);
             t_data_clk_o           <= '1';
+            
+            event_counter          <= event_counter + 1;
             STATE                  <= S_PROCESS_START;
                         
           when S_PROCESS_START =>
@@ -375,10 +373,10 @@ begin
             STATE                  <= S_WAIT_PROCESS_END;
             
           when S_WAIT_PROCESS_END =>
-            if (wait_timer_done   = '1' or
-                channel_all_done  = '1' or
+            if (wait_timer_done    = '1' or
+                channel_all_done   = '1' or
                 (NX_NOMORE_DATA_IN = '1' and
-                 busy_time_ctr > min_validation_time(11 downto 0))
+                 busy_time_ctr     > min_validation_time(11 downto 0))
                 )
             then
               wait_timer_reset     <= '1';
@@ -400,9 +398,7 @@ begin
             end if;
                     
           when S_WRITE_TRAILER =>
-            t_data_o(11 downto  0) <= busy_time_ctr;
-            t_data_o(15 downto 12) <= (others => '0');
-            t_data_o(31 downto 16) <= BOARD_ID;
+            t_data_o               <= (others => '1');
             t_data_clk_o           <= '1';
             ch_status_cmd_tr       <= CS_RESET;
             STATE                  <= S_SET_NOMORE_DATA;
@@ -497,7 +493,7 @@ begin
         slv_ack_o              <= '0';
         slv_unknown_addr_o     <= '0';
         slv_no_more_data_o     <= '0';
-        readout_mode           <= "0000";
+        readout_mode_r         <= x"0";
         trigger_window_delay   <= (others => '0');
         trigger_window_width   <= x"020";
         readout_time_max       <= x"640";
@@ -509,7 +505,7 @@ begin
         if (SLV_READ_IN  = '1') then
           case SLV_ADDR_IN is
             when x"0000" =>
-              slv_data_out_o(3 downto 0)   <= readout_mode;
+              slv_data_out_o(3 downto 0)   <= readout_mode_r;
               slv_data_out_o(31 downto 4)  <= (others => '0');
               slv_ack_o                    <= '1';
 
@@ -581,7 +577,7 @@ begin
         elsif (SLV_WRITE_IN  = '1') then
           case SLV_ADDR_IN is
             when x"0000" =>
-              readout_mode                 <= SLV_DATA_IN(3 downto 0);
+              readout_mode_r               <= SLV_DATA_IN(3 downto 0);
               slv_ack_o                    <= '1';
 
             when x"0001" =>
@@ -620,6 +616,7 @@ begin
 
   HISTOGRAM_FILL_OUT    <= histogram_fill_o;
   HISTOGRAM_BIN_OUT     <= histogram_bin_o;
+  HISTOGRAM_ADC_OUT     <= histogram_adc_o;
   
   -- Slave 
   SLV_DATA_OUT          <= slv_data_out_o;    
index c9b34845579de7ea2c75ea43574200e3d41ebd30..e4f44d67c733201824fabded3a7da51161b6a79a 100644 (file)
@@ -283,6 +283,21 @@ component fifo_ts_32to32_dc
     );
 end component;
 
+component fifo_ts_12to12_dc
+  port (
+    Data    : in  std_logic_vector(11 downto 0);
+    WrClock : in  std_logic;
+    RdClock : in  std_logic;
+    WrEn    : in  std_logic;
+    RdEn    : in  std_logic;
+    Reset   : in  std_logic;
+    RPReset : in  std_logic;
+    Q       : out std_logic_vector(11 downto 0);
+    Empty   : out std_logic;
+    Full    : out std_logic
+    );
+end component;
+
 component fifo_44_data_delay
   port (
     Data          : in  std_logic_vector(43 downto 0);
@@ -414,6 +429,7 @@ component nx_trigger_validate
     NOMORE_DATA_OUT      : out std_logic;
     HISTOGRAM_FILL_OUT   : out std_logic;
     HISTOGRAM_BIN_OUT    : out std_logic_vector(6 downto 0);
+    HISTOGRAM_ADC_OUT    : out std_logic_vector(11 downto 0);
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
@@ -469,6 +485,7 @@ component nx_histograms
     RESET_HISTS_IN       : in  std_logic;
     CHANNEL_STAT_FILL_IN : in  std_logic;
     CHANNEL_ID_IN        : in  std_logic_vector(BUS_WIDTH - 1 downto 0);
+    CHANNEL_ADC_IN       : in  std_logic_vector(11 downto 0);
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
@@ -527,38 +544,11 @@ component Gray_Encoder
     );
 end component;
 
-component pll_125_hub
-  port (
-    CLK   : in  std_logic;
-    CLKOP : out std_logic;
-    CLKOK : out std_logic;
-    LOCK  : out std_logic
-    );
-end component;
-
-component pll_nx_clk256
-  port (
-    CLK   : in  std_logic;
-    CLKOP : out std_logic;
-    LOCK  : out std_logic);
-end component;
+-------------------------------------------------------------------------------
+-- PLLs
+-------------------------------------------------------------------------------
 
 component pll_nx_clk250
-  port (
-    CLK   : in  std_logic;
-    CLKOP : out std_logic;
-    LOCK  : out std_logic);
-end component;
-
-component pll_adc_clk32
-  port (
-    CLK    : in  std_logic;
-    CLKOP  : out std_logic;
-    LOCK   : out std_logic
-    );
-end component;
-
-component pll_adc_clk192
   port (
     CLK   : in  std_logic;
     CLKOP : out std_logic;
@@ -566,7 +556,7 @@ component pll_adc_clk192
     );
 end component;
 
-component pll_adc_clk3125
+component pll_adc_clk
   port (
     CLK   : in  std_logic;
     CLKOP : out std_logic;
@@ -578,6 +568,7 @@ component nx_fpga_timestamp
   port (
     CLK_IN                : in  std_logic;
     RESET_IN              : in  std_logic;
+    NX_CLK_IN             : in  std_logic;
     TIMESTAMP_SYNC_IN     : in  std_logic;
     TRIGGER_IN            : in  std_logic;
     TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
@@ -652,24 +643,6 @@ component nx_trigger_generator
     );
 end component;
 
--------------------------------------------------------------------------------
--- ADC Handler
--------------------------------------------------------------------------------
-component adc_ad9228
-  port (
-    CLK_IN           : in  std_logic;
-    RESET_IN         : in  std_logic;
-    ADC_FCLK_IN      : in  std_logic;
-    ADC_DCLK_IN      : in  std_logic;
-    ADC_SC_CLK32_OUT : out std_logic;
-    ADC_A_IN         : in  std_logic;
-    ADC_B_IN         : in  std_logic;
-    ADC_NX_IN        : in  std_logic;
-    ADC_D_IN         : in  std_logic;
-    DEBUG_OUT        : out std_logic_vector(15 downto 0)
-    );
-end component;
-
 -------------------------------------------------------------------------------
 -- Misc Tools
 -------------------------------------------------------------------------------
index 4404c6c114d101c8c6de4eba83d57730992d849d..f87438afd8dbdaac36bafcf94b80a51faf7ae61d 100644 (file)
@@ -163,6 +163,7 @@ architecture Behavioral of nXyter_FEE_board is
   
   signal trigger_validate_fill : std_logic;
   signal trigger_validate_bin  : std_logic_vector(6 downto 0);
+  signal trigger_validate_adc  : std_logic_vector(11 downto 0);
   
   -- Event Buffer               
   signal trigger_evt_busy      : std_logic;
@@ -281,7 +282,7 @@ begin
                                 7 => 2,          -- Trigger Handler
                                 8 => 4,          -- Trigger Validate
                                 9 => 8,          -- NX Register Setup
-                               10 => 8,          -- NX Histograms
+                               10 => 9,          -- NX Histograms
                                11 => 0,          -- Debug Handler
                                12 => 2,          -- Data Delay
                                 others => 0
@@ -432,8 +433,9 @@ begin
   
   nx_fpga_timestamp_1: nx_fpga_timestamp
     port map (
-      CLK_IN                => CLK_NX_IN,
+      CLK_IN                => CLK_IN,
       RESET_IN              => RESET_IN,
+      NX_CLK_IN             => CLK_NX_IN,
       TIMESTAMP_SYNC_IN     => nx_ts_reset_o,
       TRIGGER_IN            => timestamp_trigger,
       TIMESTAMP_CURRENT_OUT => timestamp_current,
@@ -655,6 +657,7 @@ begin
 
       HISTOGRAM_FILL_OUT     => trigger_validate_fill,
       HISTOGRAM_BIN_OUT      => trigger_validate_bin,
+      HISTOGRAM_ADC_OUT      => trigger_validate_adc,
       
       SLV_READ_IN            => slv_read(8),
       SLV_WRITE_IN           => slv_write(8),
@@ -716,10 +719,11 @@ begin
       CLK_IN                      => CLK_IN,
       RESET_IN                    => RESET_IN,
                                   
-      RESET_HISTS_IN              => open,
+      RESET_HISTS_IN              => '0',
       CHANNEL_STAT_FILL_IN        => trigger_validate_fill,
       CHANNEL_ID_IN               => trigger_validate_bin,
-                                  
+      CHANNEL_ADC_IN              => trigger_validate_adc,
+      
       SLV_READ_IN                 => slv_read(10),
       SLV_WRITE_IN                => slv_write(10),
       SLV_DATA_OUT                => slv_data_rd(10*32+31 downto 10*32),
index b9f589104bf71f1bf74a7025fc69b49ba8aa4f9d..b89ce62e44ba100d00675abb7760a0e5e2b2ee69 100644 (file)
@@ -64,9 +64,9 @@ architecture Behavioral of nxyter_registers is
   
 begin
 
-  DEBUG_OUT(0) <=  I2C_SM_RESET_OUT ;
-  DEBUG_OUT(1) <=  I2C_REG_RESET_OUT;
-  DEBUG_OUT(2) <=  NX_TS_RESET_OUT;
+  DEBUG_OUT(0) <=  i2c_sm_reset_o ;
+  DEBUG_OUT(1) <=  i2c_reg_reset_o;
+  DEBUG_OUT(2) <=  nx_ts_reset_o;
 
   DEBUG_OUT(15 downto 3) <= (others => '0');
   
index 23a706d6b0dc7c69167c0163e03b73fc1e7100a7..b6709b03f805814683cacf4005f5e37fdbd48d41 100644 (file)
@@ -21,7 +21,7 @@
 0x8145 :  r             : Testpulse Rate (in Hz)    
 
 -- Trigger Handler
-0x8160 :  r/w  Bit 15-0 : Delay Timestamp Hold Signal (8bit, 10ns)
+0x8160 :  r/w  Bit 7-0  : Delay Testpulse Signal after Trigger (10ns)
 0x8161 :  r/w  Bit 0    : Enable Testpulse Signal (default: off)
 0x8162 :  r             : Accepted Trigger Rate (in Hz)
 
 0x8183 :  r/w  Readout Time Max (12 bit, in 10ns)
 0x8184 :  r    Busy Time Counter (12 bit, in 10ns)
 
-0x8185 :  r    done counter
-0x8186 :  r    done counter
-0x8187 :  r    done counter
-0x8188 :  r    done counter
+0x8185 :  r    timestamp_ref
+0x8186 :  r    window_lower_thr
+0x8187 :  r    window_upper_thr
+0x8188 :  r    done counter ch 0..31
+0x8189 :  r    done counter ch 32..63
+0x818a :  r    done counter ch 94..95
+0x818b :  r    done counter ch 96..127
 
 -- Event Data Buffer
 0x8600 :  r    read FIFO buffer
 0x8800 :      r: Read Channel Statistic (128 channel in a row)
               w: reset all Histograms
 0x8880 :      r: Read Channel Trigger Rate (128 channel in a row, 1/s)
+0x8900 :      r: Read Channel ADC Value (128 channel in a row)
 
 -- Debug Multiplexer
 0x8020 : r/w   Select Debug Entity
index 4f94a0666f0cc2f8b5064b599894241eef925d38..dfd1fcb3f9522b14bc1116c50fb9f77de759170f 100644 (file)
@@ -142,14 +142,12 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
 
 # nXyter Files
 
-add_file -vhdl -lib "work" "cores/pll_125_hub.vhd"
-add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd"
 add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd"
 add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
 add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd"
 add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
+add_file -vhdl -lib "work" "cores/fifo_ts_12to12_dc.vhd"
 
 add_file -vhdl -lib "work" "trb3_periph.vhd"
 
index a4f3a1802cea323d7f5772aa026382eae5595436..0c789268ddb4f6dfd3a31df86ec668ee12179cd6 100644 (file)
@@ -140,6 +140,12 @@ entity trb3_periph is
   --attribute syn_useioff of INP           : signal is false;
   attribute syn_useioff of NX1_TIMESTAMP_IN   : signal is true;
   attribute syn_useioff of NX2_TIMESTAMP_IN   : signal is true;
+
+  --attribute syn_useioff of NX1_ADC_NX_IN   : signal is true;
+  --attribute syn_useioff of NX2_ADC_NX_IN   : signal is true;
+  --attribute syn_useioff of NX1_ADC_D_IN    : signal is true;
+  --attribute syn_useioff of NX2_ADC_D_IN    : signal is true;
+  
   --attribute syn_useioff of NX1_ADC_NX_IN   : signal is true;
   --attribute syn_useioff of DAC_SDO       : signal is true;
   --attribute syn_useioff of DAC_SDI       : signal is true;
@@ -158,11 +164,6 @@ architecture trb3_periph_arch of trb3_periph is
   attribute syn_keep     : boolean;
   attribute syn_preserve : boolean;
 
-  -- For 250MHz PLL nxyter clock, THE_256M_ODDR_1
- --attribute ODDRAPPS : string;
- --attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED";
-
-  
   --Clock / Reset
   signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
@@ -275,12 +276,11 @@ architecture trb3_periph_arch of trb3_periph is
   --FPGA Test
   signal time_counter : unsigned(31 downto 0);
 
-
   -- nXyter-FEB-Board Clocks
-  signal nx_clk256                   : std_logic;
-  signal pll_lock_clk256             : std_logic;
+  signal nx_main_clk                   : std_logic;
+  signal pll_nx_clk_lock             : std_logic;
   signal clk_adc_dat                 : std_logic;
-  signal clk_adc_dat_lock            : std_logic;
+  signal pll_adc_clk_lock            : std_logic;
   
   -- nXyter 1 Regio Bus
   signal nx1_regio_addr_in           : std_logic_vector (15 downto 0);
@@ -518,12 +518,6 @@ begin
 
   timing_trg_received_i <= TRIGGER_LEFT;
   
---  fee_trg_release_i(1)                      <= '1';
---  fee_data_i(1*32+31 downto 1*32)           <= (others => '1');
---  fee_trg_statusbits_i(1*32+31 downto 1*32) <= (others => '0');
---  fee_data_write_i(1)                       <= '0';
---  fee_data_finished_i(1)                    <= '1';
-  
 ---------------------------------------------------------------------------
 -- AddOn
 ---------------------------------------------------------------------------
@@ -692,12 +686,12 @@ begin
 
   nXyter_FEE_board_0: nXyter_FEE_board
     generic map (
-      BOARD_ID => x"affe"
+      BOARD_ID => x"0001"
       )
     port map (
       CLK_IN                     => clk_100_i,
       RESET_IN                   => reset_i,
-      CLK_NX_IN                  => nx_clk256,
+      CLK_NX_IN                  => nx_main_clk,
       CLK_ADC_IN                 => clk_adc_dat,
       TRIGGER_OUT                => fee1_trigger,                       
 
@@ -770,12 +764,12 @@ begin
 
   nXyter_FEE_board_1: nXyter_FEE_board
     generic map (
-      BOARD_ID => x"babe"
+      BOARD_ID => x"0002"
       )
     port map (
       CLK_IN                     => clk_100_i,
       RESET_IN                   => reset_i,
-      CLK_NX_IN                  => nx_clk256,
+      CLK_NX_IN                  => nx_main_clk,
       CLK_ADC_IN                 => clk_adc_dat,
       TRIGGER_OUT                => fee2_trigger,
       
@@ -844,54 +838,31 @@ begin
   ADDON_TRIGGER_OUT              <= fee1_trigger or fee2_trigger;
 
   -----------------------------------------------------------------------------
-  -- nXyter common Clocks
+  -- nXyter Main and ADC Clocks
   -----------------------------------------------------------------------------
-  pll_nx_clk256_1: entity work.pll_nx_clk256
+
+  -- nXyter Main Clock (250/256 MHz)
+  pll_nx_clk250_1: entity work.pll_nx_clk250
     port map (
-      CLK   => clk_100_i,
-      CLKOP => nx_clk256,
-      LOCK  => pll_lock_clk256
+      CLK   => clk_200_i,
+      CLKOP => nx_main_clk,
+      LOCK  => pll_nx_clk_lock
       );
 
-  NX1_CLK256A_OUT <= nx_clk256;
-  NX2_CLK256A_OUT <= nx_clk256;
+  NX1_CLK256A_OUT <= nx_main_clk;
+  NX2_CLK256A_OUT <= nx_main_clk;
 
-  -- ADC Receiver Clock
-  pll_adc_clk192_1: pll_adc_clk192
+  -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be base on same
+  -- ClockSource as nXyter Main Clock)
+  pll_adc_clk_1: pll_adc_clk
     port map (
-      CLK   => CLK_PCLK_LEFT,
+      CLK   => clk_200_i,
       CLKOP => clk_adc_dat,
-      LOCK  => clk_adc_dat_lock
+      LOCK  => pll_adc_clk_lock
       );
 
   -----------------------------------------------------------------------------
   
-  -- 250MHz Clock to nXyters
-  --pll_nx_clk250_1: entity work.pll_nx_clk250
-  --  port map (
-  --    CLK   => CLK_GPLL_LEFT,
-  --    CLKOP => nx1_clk256_o,
-  --    LOCK  => open
-  --    );
-
-  --pll_125_hub_1: pll_125_hub
-  --  port map (
-  --    CLK   => CLK_GPLL_LEFT,
-  --    CLKOP => open,
-  --    CLKOK => nx1_clk256_o,
-  --    LOCK  => open
-  --    );
- -- NX1_CLK256A_OUT <= CLK_PCLK_RIGHT;
-  
-  --THE_256M_ODDR_1: ODDRXD1
-  --  port map(
-  --    SCLK  => nx1_clk256_o,
-  --    DA    => '1',
-  --    DB    => '0',
-  --    Q     => NX1_CLK256A_OUT
-  --    );
-
-
 -------------------------------------------------------------------------------
 -- Timestamp Simulator
 -------------------------------------------------------------------------------
index c93bfebf309d1c581a5971e35df298e849667e2a..6758f2d8f74052be6b017326bd833989fc66a7a2 100644 (file)
@@ -6,46 +6,88 @@
 # Basic Settings
 #################################################################
 
+  #Speed for the configuration Flash access
   SYSCONFIG MCCLK_FREQ = 20;
 
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+
+  # Clock Setup:
+  #
+  # CLK_GPLL_RIGHT : real Oszillator 200MHz
+  # CLK_GPLL_RIGHT --> PLL#0 --> clk_100_i     -----> Main Clock all entities
+  # CLK_GPLL_RIGHT --> PLL#0 --> clk_200_i     -----> PLL#1
+  #
+  # clk_200_i (PLL#1) --> nx_main_clk
+  #                        (250/256 MHz)       -----> nXyter Main Clock
+  #                                            | 
+  #                                            |----> FPGA Timestamp Entity
+  #
+  # clk_200_i (PLL#1) --> clk_adc_dat 
+  #                        (nx_main_clk * 3/8) -----> ADC Handler 
+  #
+  # nXyter Main Clock --> nXyter Data Clock    -----> FPGA Data Receiver
+  #                                            |
+  #                                            |----> Johnson 1/4 --> ADC SCLK
+
+
+  # Not used in current design
+  #FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+  #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  #FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+
   FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+  #USE PRIMARY NET CLK_GPLL_RIGHT; 
+  #USE PRIMARY NET CLK_GPLL_RIGHT_c;
 
-  FREQUENCY PORT NX1_CLK256A_OUT 256 MHz;
-  FREQUENCY PORT NX2_CLK256A_OUT 256 MHz;
-    
-#Put the names of your nxyter inputs here:  
-  FREQUENCY PORT NX1_CLK128_IN 128 MHz;
-  FREQUENCY PORT NX2_CLK128_IN 128 MHz;
-  FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz;   
-  FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;  
+  #FREQUENCY PORT nx_main_clk 250 MHz;
+  USE PRIMARY NET "nx_main_clk"; 
+  #USE PRIMARY NET CLK_GPLL_RIGHT_c;
 
-#Change the next two lines to the clk_fast signal of the ADC  
-  USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0";
-  USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0";
+  LOCATE COMP  THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C5;
+
+
+# Put the names of your nxyter inputs here:  
+  FREQUENCY PORT NX1_CLK128_IN 125 MHz;
+  FREQUENCY PORT NX2_CLK128_IN 125 MHz;
+  #FREQUENCY PORT NX1_ADC_DCLK_IN 93.75 MHz;   
+  #FREQUENCY PORT NX2_ADC_DCLK_IN 93.75 MHz;  
+
+  FREQUENCY PORT NX1_ADC_SAMPLE_CLK_OUT 31.25 MHz;  
+  FREQUENCY PORT NX2_ADC_SAMPLE_CLK_OUT 31.25 MHz;  
+
+# ------ ADC Stuff ---------------------------
+
+# ADC Settings
 
   
-  USE PRIMARY NET "CLK_PCLK_LEFT";
-  USE PRIMARY NET "CLK_PCLK_LEFT_c";
-  
-  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
-  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c";
+  #FREQUENCY PORT clk_adc_dat 93.75 MHz;
+  #USE PRIMARY NET "clk_adc_dat";
 
+  USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
   USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
-  USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c";
 
-  USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
-  USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
-  
-  #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
-  #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+  #PROHIBIT PRIMARY NET "NX1_ADC_FCLK_IN";
+  #PROHIBIT PRIMARY NET "NX1B_ADC_FCLK_IN";
+  #PROHIBIT SECONDARY NET "NX1_ADC_FCLK_IN";
+  #PROHIBIT SECONDARY NET "NX1B_ADC_FCLK_IN";
+  #PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN";
+  #PROHIBIT PRIMARY NET "NX1B_ADC_DCLK_IN";
+  #PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN";
+  #PROHIBIT SECONDARY NET "NX1B_ADC_DCLK_IN";
+
+  #PROHIBIT PRIMARY NET "NX2_ADC_FCLK_IN";
+  #PROHIBIT PRIMARY NET "NX2B_ADC_FCLK_IN";
+  #PROHIBIT SECONDARY NET "NX2_ADC_FCLK_IN";
+  #PROHIBIT SECONDARY NET "NX2B_ADC_FCLK_IN";
+  #PROHIBIT PRIMARY NET "NX2_ADC_DCLK_IN";
+  #PROHIBIT PRIMARY NET "NX2B_ADC_DCLK_IN";
+  #PROHIBIT SECONDARY NET "NX2_ADC_DCLK_IN";
+  #PROHIBIT SECONDARY NET "NX2B_ADC_DCLK_IN";
   
 #################################################################
 # Reset Nets
 #################################################################  
-GSR_NET NET "GSR_N";  
+
+#GSR_NET NET "GSR_N";  
 
 
 #################################################################
@@ -59,10 +101,13 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
 #################################################################
 # Relax some of the timing constraints
 #################################################################
-MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
 
+# WARNING: matches no cells in the design. 
+#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns;
+MULTICYCLE FROM CLKNET "nx_main_clk" 50 ns;
 
 #################################################################
 # Constraints for nxyter inputs
@@ -70,24 +115,15 @@ MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
 
 # look at .par and .twr.setup file for clocks 
 # and .mrp or errors
-PROHIBIT PRIMARY NET "NX1_CLK128_IN_c";
+PROHIBIT PRIMARY   NET "NX1_CLK128_IN_c";
 PROHIBIT SECONDARY NET "NX1_CLK128_IN_c";
 
-PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
+PROHIBIT PRIMARY   NET "NX2_CLK128_IN_c";
 PROHIBIT SECONDARY NET "NX2_CLK128_IN_c";
 
-PROHIBIT PRIMARY NET "TEST_LINE_c_0_1";
-PROHIBIT SECONDARY NET "TEST_LINE_c_0_1";
-
 DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" 
+INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN"; 
 
 DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN" ; 
-
-MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c" 50 ns;
-MULTICYCLE FROM CLKNET "NX2_CLK256A_OUT_c" 50 ns;
-
-#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c";
-#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";
+INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN";