#Trigger from fan-out
LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-
-
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
#################################################################
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk192" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 15 22:18:00.823" version="5.3" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_adc_clk192.lpc" type="lpc" modified="2013 04 15 22:17:56.000"/>
- <File name="pll_adc_clk192.vhd" type="top_level_vhdl" modified="2013 04 15 22:17:56.000"/>
- <File name="pll_adc_clk192_tmpl.vhd" type="template_vhdl" modified="2013 04 15 22:17:56.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_clk192
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/15/2013
-Time=22:17:56
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=200
-Div=25
-ClkOPBp=0
-Post=4
-U_OFrq=192
-OP_Tol=0.0
-OFrq=192.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=24
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=1.141439
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk192 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 192 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
-
--- Mon Apr 15 22:17:56 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_clk192 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_clk192 : entity is true;
-end pll_adc_clk192;
-
-architecture Structure of pll_adc_clk192 is
-
- -- internal signal declarations
- signal CLKOP_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "192.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 24, CLKI_DIV=> 25,
- FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
-
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_clk192 is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_adc_clk32" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 14 23:13:37.959" version="5.3" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_adc_clk32.lpc" type="lpc" modified="2013 04 14 23:13:35.000"/>
- <File name="pll_adc_clk32.vhd" type="top_level_vhdl" modified="2013 04 14 23:13:35.000"/>
- <File name="pll_adc_clk32_tmpl.vhd" type="template_vhdl" modified="2013 04 14 23:13:35.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_adc_clk32
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/14/2013
-Time=23:13:35
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=200
-Div=25
-ClkOPBp=0
-Post=16
-U_OFrq=32
-OP_Tol=0.0
-OFrq=32.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=4
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=1.712159
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_adc_clk32 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 32 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
-
--- Sun Apr 14 23:13:35 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_adc_clk32 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_adc_clk32 : entity is true;
-end pll_adc_clk32;
-
-architecture Structure of pll_adc_clk32 is
-
- -- internal signal declarations
- signal CLKOP_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "32.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 16, CLKFB_DIV=> 4, CLKI_DIV=> 25,
- FIN=> "200.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
-
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_adc_clk32 is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 03 28 16:45:26.723" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="pll_nx_clk250" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 10 02 16:44:47.426" version="5.3" type="Module" synthesis="" source_format="VHDL">
<Package>
- <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 03 28 16:45:22.000"/>
- <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 03 28 16:45:22.000"/>
- <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 03 28 16:45:22.000"/>
+ <File name="pll_nx_clk250.lpc" type="lpc" modified="2013 10 02 16:44:45.000"/>
+ <File name="pll_nx_clk250.vhd" type="top_level_vhdl" modified="2013 10 02 16:44:46.000"/>
+ <File name="pll_nx_clk250_tmpl.vhd" type="template_vhdl" modified="2013 10 02 16:44:46.000"/>
</Package>
</DiamondModule>
ModuleName=pll_nx_clk250
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=03/28/2013
-Time=16:45:21
+Date=10/02/2013
+Time=16:44:45
[Parameters]
Verilog=0
IO=0
Type=ehxpllb
mode=normal
-IFrq=125
-Div=1
+IFrq=200
+Div=4
ClkOPBp=0
Post=4
U_OFrq=250
DutyTrimP=Rising
DelayMultP=0
fb_mode=CLKOP
-Mult=2
+Mult=5
Phase=0.0
Duty=8
DelayMultS=0
PCDR=0
FINDELA=0
VcoRate=
-Bandwidth=1.485393
+Bandwidth=1.753251
;DelayControl=No
EnCLKOS=0
ClkOSBp=0
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
--- Thu Mar 28 16:45:22 2013
+-- Wed Oct 2 16:44:46 2013
library IEEE;
use IEEE.std_logic_1164.all;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 2, CLKI_DIV=> 1,
- FIN=> "125.000000")
+ CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 5, CLKI_DIV=> 4,
+ FIN=> "200.000000")
port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="pll_nx_clk256" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 04 13 17:24:25.693" version="5.3" type="Module" synthesis="" source_format="VHDL">
- <Package>
- <File name="pll_nx_clk256.lpc" type="lpc" modified="2013 04 13 17:24:24.000"/>
- <File name="pll_nx_clk256.vhd" type="top_level_vhdl" modified="2013 04 13 17:24:24.000"/>
- <File name="pll_nx_clk256_tmpl.vhd" type="template_vhdl" modified="2013 04 13 17:24:24.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PLL
-CoreRevision=5.3
-ModuleName=pll_nx_clk256
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/13/2013
-Time=17:24:24
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=None
-Order=None
-IO=0
-Type=ehxpllb
-mode=normal
-IFrq=100
-Div=25
-ClkOPBp=0
-Post=2
-U_OFrq=256
-OP_Tol=0.0
-OFrq=256.000000
-DutyTrimP=Rising
-DelayMultP=0
-fb_mode=CLKOP
-Mult=64
-Phase=0.0
-Duty=8
-DelayMultS=0
-DPD=50% Duty
-DutyTrimS=Rising
-DelayMultD=0
-ClkOSDelay=0
-PhaseDuty=Static
-CLKOK_INPUT=CLKOP
-SecD=2
-U_KFrq=50
-OK_Tol=0.0
-KFrq=
-ClkRst=0
-PCDR=0
-FINDELA=0
-VcoRate=
-Bandwidth=0.856080
-;DelayControl=No
-EnCLKOS=0
-ClkOSBp=0
-EnCLKOK=0
-ClkOKBp=0
-enClkOK2=0
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
--- Module Version: 5.3
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_nx_clk256 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 100 -phase_cntl STATIC -fclkop 256 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
-
--- Sat Apr 13 17:24:24 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity pll_nx_clk256 is
- port (
- CLK: in std_logic;
- CLKOP: out std_logic;
- LOCK: out std_logic);
- attribute dont_touch : boolean;
- attribute dont_touch of pll_nx_clk256 : entity is true;
-end pll_nx_clk256;
-
-architecture Structure of pll_nx_clk256 is
-
- -- internal signal declarations
- signal CLKOP_t: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component EHXPLLF
- generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
- DELAY_PWD : in String; DELAY_VAL : in Integer;
- CLKOS_TRIM_DELAY : in Integer;
- CLKOS_TRIM_POL : in String;
- CLKOP_TRIM_DELAY : in Integer;
- CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
- CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
- PHASE_DELAY_CNTL : in String; DUTY : in Integer;
- PHASEADJ : in String; CLKOK_DIV : in Integer;
- CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
- CLKI_DIV : in Integer; FIN : in String);
- port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
- RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
- DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
- DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
- DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
- FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
- CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
- LOCK: out std_logic; CLKINTFB: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- attribute FREQUENCY_PIN_CLKOP : string;
- attribute FREQUENCY_PIN_CLKI : string;
- attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "256.000000";
- attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
- attribute syn_keep : boolean;
- attribute syn_noprune : boolean;
- attribute syn_noprune of Structure : architecture is true;
-
-begin
- -- component instantiation statements
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- PLLInst_0: EHXPLLF
- generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
- CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
- CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
- CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
- CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
- PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
- CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 64, CLKI_DIV=> 25,
- FIN=> "100.000000")
- port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
- RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
- DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
- DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
- DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
- FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
- CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
- CLKINTFB=>open);
-
- CLKOP <= CLKOP_t;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of pll_nx_clk256 is
- for Structure
- for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
-- Debug Line
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= SCLK_OUT;
+ DEBUG_OUT(1) <= sclk_o;
DEBUG_OUT(2) <= SDIO_INOUT;
- DEBUG_OUT(3) <= CSB_OUT;
+ DEBUG_OUT(3) <= csb_o;
DEBUG_OUT(4) <= spi_busy;
DEBUG_OUT(5) <= wait_timer_done;
DEBUG_OUT(6) <= sendbyte_seq_start;
data_valid_o <= '0';
trigger_rate_inc <= '0';
frame_rate_inc <= '0';
- invalid_adc <= '0';
+ invalid_adc <= '0';
if (new_timestamp = '1') then
case valid_frame_bits is
else
nx_trigger_rate <= nx_trigger_ctr_t;
nx_frame_rate <= nx_frame_ctr_t;
- nx_trigger_ctr_t <= (others => '0');
- nx_frame_ctr_t <= (others => '0');
+ if (trigger_rate_inc = '0') then
+ nx_trigger_ctr_t <= (others => '0');
+ else
+ nx_trigger_ctr_t <= x"000_0001";
+ end if;
+ if (frame_rate_inc = '0') then
+ nx_frame_ctr_t <= (others => '0');
+ else
+ nx_frame_ctr_t <= x"000_0001";
+ end if;
nx_rate_timer <= (others => '0');
end if;
end if;
entity nx_fpga_timestamp is
port (
- CLK_IN : in std_logic;
+ CLK_IN : in std_logic;
RESET_IN : in std_logic;
-
+ NX_CLK_IN : in std_logic;
+
TIMESTAMP_SYNC_IN : in std_logic;
TRIGGER_IN : in std_logic;
TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
end entity;
architecture Behavioral of nx_fpga_timestamp is
-
signal timestamp_ctr : unsigned(11 downto 0);
signal timestamp_current_o : unsigned(11 downto 0);
- signal timestamp_hold_o : unsigned(11 downto 0);
+ signal timestamp_hold : std_logic_vector(11 downto 0);
signal trigger_x : std_logic;
signal trigger_l : std_logic;
signal trigger : std_logic;
signal timestamp_sync : std_logic;
signal nx_timestamp_sync_o : std_logic;
+
+ signal fifo_full : std_logic;
+ signal fifo_write_enable : std_logic;
+
+ -- Main Clock Domain
+ signal fifo_empty : std_logic;
+ signal fifo_read_enable : std_logic;
+ signal fifo_data_valid_t : std_logic;
+ signal fifo_data_valid : std_logic;
+ signal fifo_data_out : std_logic_vector(11 downto 0);
+ signal timestamp_hold_o : unsigned(11 downto 0);
begin
- DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(0) <= NX_CLK_IN;
DEBUG_OUT(1) <= trigger;
DEBUG_OUT(2) <= timestamp_sync;
DEBUG_OUT(3) <= '0';
DEBUG_OUT(15 downto 4) <= timestamp_hold_o;
+
+ -- NX Clock Domain
- -- Cross Clockdomain for TRIGGER and SYNC signal
- PROC_SYNC: process (CLK_IN)
+ -- Cross Clockdomain for TRIGGER and SYNC
+ PROC_SYNC: process (NX_CLK_IN)
begin
- if( rising_edge(CLK_IN) ) then
+ if( rising_edge(NX_CLK_IN) ) then
if (RESET_IN = '1') then
trigger_x <= '0';
trigger_l <= '0';
-- Convert TRIGGER_IN to Pulse
level_to_pulse_1: level_to_pulse
port map (
- CLK_IN => CLK_IN,
+ CLK_IN => NX_CLK_IN,
RESET_IN => RESET_IN,
LEVEL_IN => trigger_l,
PULSE_OUT => trigger
-- Convert TIMESTAMP_SYNC_IN to Pulse
level_to_pulse_2: level_to_pulse
port map (
- CLK_IN => CLK_IN,
+ CLK_IN => NX_CLK_IN,
RESET_IN => RESET_IN,
LEVEL_IN => timestamp_sync_l,
PULSE_OUT => timestamp_sync
-- Timestamp Process + Trigger
- PROC_TIMESTAMP_CTR: process (CLK_IN)
+ PROC_TIMESTAMP_CTR: process (NX_CLK_IN)
begin
- if( rising_edge(CLK_IN) ) then
+ if( rising_edge(NX_CLK_IN) ) then
if( RESET_IN = '1' ) then
timestamp_ctr <= (others => '0');
timestamp_hold_o <= (others => '0');
nx_timestamp_sync_o <= '0';
+ fifo_write_enable <= '0';
else
nx_timestamp_sync_o <= '0';
-
+ fifo_write_enable <= '0';
+
if (timestamp_sync = '1') then
timestamp_ctr <= (others => '0');
timestamp_hold_o <= (others => '0');
nx_timestamp_sync_o <= '1';
else
- if (trigger = '1') then
- timestamp_hold_o <= timestamp_ctr - 3;
+ if (trigger = '1' and fifo_full = '0') then
+ timestamp_hold <= std_logic_vector(timestamp_ctr - 3);
+ fifo_write_enable <= '1';
end if;
timestamp_ctr <= timestamp_ctr + 1;
end if;
end if;
end if;
- end process;
+ end process PROC_TIMESTAMP_CTR;
timestamp_current_o <= timestamp_ctr;
+ -----------------------------------------------------------------------------
+ -- Main Clock Domain -> Tranfer TimeStamp
+ -----------------------------------------------------------------------------
+
+ fifo_ts_12to12_dc_1: fifo_ts_12to12_dc
+ port map (
+ Data => timestamp_hold,
+ WrClock => NX_CLK_IN,
+ RdClock => CLK_IN,
+ WrEn => fifo_write_enable,
+ RdEn => fifo_read_enable,
+ Reset => RESET_IN,
+ RPReset => RESET_IN,
+ Q => fifo_data_out,
+ Empty => fifo_empty,
+ Full => fifo_full
+ );
+
+ fifo_read_enable <= not fifo_empty;
+
+ PROC_RECEIVE_TS: process (CLK_IN)
+ begin
+ if( rising_edge(NX_CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ fifo_data_valid_t <= '0';
+ fifo_data_valid <= '0';
+ timestamp_hold <= (others => '0');
+ else
+ if (fifo_data_valid = '1') then
+ timestamp_hold <= unsigned(fifo_data_out);
+ end if;
+
+ fifo_data_valid_t <= fifo_read_enable;
+ fifo_data_valid <= fifo_data_valid;
+ end if;
+ end if;
+ end process PROC_RECEIVE_TS;
-----------------------------------------------------------------------------
-- Output Signals
RESET_IN : in std_logic;
RESET_HISTS_IN : in std_logic;
-
+
CHANNEL_STAT_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
-
+ CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
+
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
-- PROC_CHANNEL_HIST
signal hist_channel_stat : histogram_t;
signal hist_channel_freq : histogram_t;
+
signal wait_timer_init : unsigned(27 downto 0);
signal wait_timer_done : std_logic;
+ -- PROC_CHANNEL_HIST
+ signal hist_channel_adc : histogram_t;
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
DEBUG_OUT(1) <= RESET_IN;
DEBUG_OUT(2) <= RESET_HISTS_IN;
DEBUG_OUT(3) <= reset_hists_r;
- DEBUG_OUT(4) <= slv_ack_o;
- DEBUG_OUT(5) <= SLV_READ_IN;
- DEBUG_OUT(6) <= SLV_WRITE_IN;
- DEBUG_OUT(7) <= wait_timer_done;
- DEBUG_OUT(15 downto 8) <= (others => '0');
+ DEBUG_OUT(4) <= CHANNEL_STAT_FILL_IN;
+ DEBUG_OUT(5) <= slv_ack_o;
+ DEBUG_OUT(6) <= SLV_READ_IN;
+ DEBUG_OUT(7) <= SLV_WRITE_IN;
+ DEBUG_OUT(8) <= wait_timer_done;
+ DEBUG_OUT(15 downto 9) <= CHANNEL_ID_IN;
-----------------------------------------------------------------------------
PROC_CHANNEL_HIST : process (CLK_IN)
+ variable value : unsigned(31 downto 0);
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then
for I in 0 to (2**BUS_WIDTH - 1) loop
hist_channel_stat(I) <= (others => '0');
hist_channel_freq(I) <= (others => '0');
+ hist_channel_adc(I) <= (others => '0');
end loop;
wait_timer_init <= x"000_0001";
else
if (CHANNEL_STAT_FILL_IN = '1') then
hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <=
hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1;
+
+ value := (hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN)))
+ + unsigned(CHANNEL_ADC_IN)) / 2;
+ hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) <= value;
end if;
end if;
end if;
end if;
end process PROC_CHANNEL_HIST;
-
+
-- Timer
nx_timer_1: nx_timer
generic map (
slv_data_out_o(31 downto 0) <= std_logic_vector(
hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
);
- -- slv_data_out_o(31 downto 24) <= (others => '0');
slv_ack_o <= '1';
elsif (unsigned(SLV_ADDR_IN) >= x"0080" and
unsigned(SLV_ADDR_IN) <= x"00ff") then
slv_data_out_o(31 downto 0) <= std_logic_vector(
hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
);
- -- slv_data_out_o(31 downto 24) <= (others => '0');
+ slv_ack_o <= '1';
+ elsif (unsigned(SLV_ADDR_IN) >= x"0100" and
+ unsigned(SLV_ADDR_IN) <= x"017f") then
+ slv_data_out_o(31 downto 0) <= std_logic_vector(
+ hist_channel_adc(to_integer(unsigned(SLV_ADDR_IN(7 downto 0))))
+ );
slv_ack_o <= '1';
else
slv_ack_o <= '0';
-- Trigger Handler
signal validate_trigger_o : std_logic;
- signal timestamp_hold : std_logic;
signal lvl2_trigger_o : std_logic;
signal event_buffer_clear_o : std_logic;
signal fast_clear_o : std_logic;
signal trigger_busy_o : std_logic;
signal fee_trg_release_o : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal trigger_testpulse_o : std_logic;
-
+ signal timestamp_trigger_o : std_logic;
+ signal send_testpulse : std_logic;
+
type STATES is (S_IDLE,
S_CTS_TRIGGER,
S_WAIT_TRG_DATA_VALID,
);
signal STATE : STATES;
- -- Timestamp Hold Handler
- type TS_STATES is (TS_IDLE,
- TS_WAIT_TIMER_DONE
- );
- signal TS_STATE : TS_STATES;
+ -- Testpulse Handler
+ type T_STATES is (T_IDLE,
+ T_WAIT_TIMER,
+ T_SET_TESTPULSE
+ );
+
+ signal T_STATE : T_STATES;
- signal timestamp_trigger_o : std_logic;
+ signal trigger_testpulse_o : std_logic;
signal wait_timer_reset : std_logic;
signal wait_timer_init : unsigned(7 downto 0);
signal wait_timer_done : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal reg_timestamp_trigger_delay : unsigned(7 downto 0);
+ signal reg_testpulse_delay : unsigned(7 downto 0);
signal reg_testpulse_enable : std_logic;
signal accepted_trigger_rate : unsigned(27 downto 0);
DEBUG_OUT(9) <= event_buffer_clear_o;
DEBUG_OUT(10) <= fee_trg_release_o;
DEBUG_OUT(11) <= trigger_busy_o;
- DEBUG_OUT(12) <= trigger_testpulse_o;
- DEBUG_OUT(13) <= slv_unknown_addr_o;
- DEBUG_OUT(14) <= slv_no_more_data_o;
- DEBUG_OUT(15) <= slv_unknown_addr_o;
--- DEBUG_OUT(15 downto 13) <= (others => '0');
+ DEBUG_OUT(12) <= timestamp_trigger_o;
+ DEBUG_OUT(13) <= send_testpulse;
+ DEBUG_OUT(14) <= trigger_testpulse_o;
+ DEBUG_OUT(15) <= '0';
-- Timer
nx_timer_1: nx_timer
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
validate_trigger_o <= '0';
- timestamp_hold <= '0';
lvl2_trigger_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
fast_clear_o <= '0';
event_buffer_clear_o <= '0';
trigger_busy_o <= '0';
- trigger_testpulse_o <= '0';
+ send_testpulse <= '0';
+ timestamp_trigger_o <= '0';
STATE <= S_IDLE;
else
validate_trigger_o <= '0';
- timestamp_hold <= '0';
lvl2_trigger_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
fast_clear_o <= '0';
event_buffer_clear_o <= '0';
trigger_busy_o <= '1';
- trigger_testpulse_o <= '0';
+ send_testpulse <= '0';
+ timestamp_trigger_o <= '0';
if (LVL1_INVALID_TRG_IN = '1') then
fast_clear_o <= '1';
STATE <= S_IDLE;
end if;
- -- CTS Trigger Handler
+ -- CTS Trigger Handler
when S_CTS_TRIGGER =>
event_buffer_clear_o <= '1';
validate_trigger_o <= '1';
- timestamp_hold <= '1';
+ timestamp_trigger_o <= '1';
lvl2_trigger_o <= '1';
if (reg_testpulse_enable = '1') then
- trigger_testpulse_o <= '1';
+ send_testpulse <= '1';
end if;
STATE <= S_WAIT_TRG_DATA_VALID;
-- Internal Trigger Handler
when S_INTERNAL_TRIGGER =>
validate_trigger_o <= '1';
- timestamp_hold <= '1';
+ timestamp_trigger_o <= '1';
event_buffer_clear_o <= '1';
STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
end if;
end process PROC_TRIGGER_HANDLER;
- PROC_SEND_TIMSTAMP_TRIGGER: process(CLK_IN)
- begin
+ PROC_TESTPULSE_HANDLER: process (CLK_IN)
+ begin
if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then
+ if (RESET_IN = '1' or fast_clear_o = '1') then
wait_timer_init <= (others => '0');
- timestamp_trigger_o <= '0';
- TS_STATE <= TS_IDLE;
+ trigger_testpulse_o <= '0';
+ T_STATE <= T_IDLE;
else
+ trigger_testpulse_o <= '0';
wait_timer_init <= (others => '0');
- timestamp_trigger_o <= '0';
- case TS_STATE is
+ case T_STATE is
- when TS_IDLE =>
- if (timestamp_hold = '0') then
- TS_STATE <= TS_IDLE;
+ when T_IDLE =>
+ if (send_testpulse = '1') then
+ if (reg_testpulse_delay > 0) then
+ wait_timer_init <= reg_testpulse_delay;
+ T_STATE <= T_WAIT_TIMER;
+ else
+ T_STATE <= T_SET_TESTPULSE;
+ end if;
else
- wait_timer_init <= reg_timestamp_trigger_delay;
- TS_STATE <= TS_WAIT_TIMER_DONE;
+ T_STATE <= T_IDLE;
end if;
- when TS_WAIT_TIMER_DONE =>
+ when T_WAIT_TIMER =>
if (wait_timer_done = '0') then
- TS_STATE <= TS_WAIT_TIMER_DONE;
+ T_STATE <= T_WAIT_TIMER;
else
- timestamp_trigger_o <= '1';
- TS_STATE <= TS_IDLE;
+ T_STATE <= T_SET_TESTPULSE;
end if;
- end case;
-
+ when T_SET_TESTPULSE =>
+ trigger_testpulse_o <= '1';
+ T_STATE <= T_IDLE;
+ end case;
end if;
end if;
- end process PROC_SEND_TIMSTAMP_TRIGGER;
-
+ end process PROC_TESTPULSE_HANDLER;
+
PROC_CAL_RATES: process (CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_no_more_data_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_ack_o <= '0';
- reg_timestamp_trigger_delay <= x"01";
- reg_testpulse_enable <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_no_more_data_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_ack_o <= '0';
+ reg_testpulse_delay <= (others => '0');
+ reg_testpulse_enable <= '0';
else
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
if (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then
- reg_timestamp_trigger_delay <=
- unsigned(SLV_DATA_IN(7 downto 0));
- end if;
- slv_ack_o <= '1';
+ reg_testpulse_delay <= unsigned(SLV_DATA_IN(7 downto 0));
+ slv_ack_o <= '1';
when x"0001" =>
- reg_testpulse_enable <= SLV_DATA_IN(0);
- slv_ack_o <= '1';
-
+ reg_testpulse_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+
when others =>
- slv_unknown_addr_o <= '1';
+ slv_unknown_addr_o <= '1';
end case;
when x"0000" =>
slv_data_out_o(7 downto 0) <=
- std_logic_vector(reg_timestamp_trigger_delay);
+ std_logic_vector(reg_testpulse_delay);
slv_data_out_o(31 downto 8) <= (others => '0');
slv_ack_o <= '1';
-- Histogram
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
+ HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
-- Slave bus
SLV_READ_IN : in std_logic;
architecture Behavioral of nx_trigger_validate is
- -- Sync Ref
- signal timestamp_ref_x : unsigned(11 downto 0);
- signal timestamp_ref : unsigned(11 downto 0);
-
-- Process Channel_Status
signal channel_index : std_logic_vector(6 downto 0);
signal channel_wait : std_logic_vector(127 downto 0);
signal busy_time_ctr : unsigned(11 downto 0);
signal busy_time_min_done : std_logic;
signal wait_timer_reset : std_logic;
+ signal event_counter : unsigned(9 downto 0);
+
+ signal readout_mode : std_logic_vector(3 downto 0);
+ signal timestamp_ref : unsigned(11 downto 0);
- -- Timer
+ -- Timer
signal timer_reset : std_logic;
signal wait_timer_done : std_logic;
-- Histogram
signal histogram_fill_o : std_logic;
signal histogram_bin_o : std_logic_vector(6 downto 0);
+ signal histogram_adc_o : std_logic_vector(11 downto 0);
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
- signal readout_mode : std_logic_vector(3 downto 0);
+ signal readout_mode_r : std_logic_vector(3 downto 0);
signal trigger_window_width : unsigned(11 downto 0);
signal trigger_window_delay : unsigned(11 downto 0);
signal readout_time_max : unsigned(11 downto 0);
timer_reset <= RESET_IN or wait_timer_reset;
- -- Sync Timestamp Ref
- PROC_SYNC_TIMESTAMP_REF: process (CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- timestamp_ref_x <= (others => '0');
- timestamp_ref <= (others => '0');
- else
- timestamp_ref_x <= TIMESTAMP_REF_IN;
- timestamp_ref <= timestamp_ref_x;
- end if;
- end if;
- end process PROC_SYNC_TIMESTAMP_REF;
-
-----------------------------------------------------------------------------
-- Filter only valid events
-----------------------------------------------------------------------------
- PROC_PROCESS_TIMESTAMP: process (CLK_IN)
+ PROC_FILTER_TIMESTAMPS: process (CLK_IN)
variable ts_ref : unsigned(11 downto 0);
variable window_lower_thr : unsigned(11 downto 0);
variable window_upper_thr : unsigned(11 downto 0);
histogram_fill_o <= '0';
histogram_bin_o <= (others => '0');
+ histogram_adc_o <= (others => '0');
if (DATA_CLK_IN = '1') then
if (store_to_fifo = '1') then
case readout_mode is
- when x"0" => -- RefValue + valid and window filter
+ when x"0" => -- RefValue + valid + window filter limit
if (TIMESTAMP_STATUS_IN(1) = '0') then
if (deltaT < window_lower_thr) then
out_of_window_l <= '1';
-- IN LUT-Data bit setzten.
channel_index <= CHANNEL_IN;
ch_status_cmd_pr <= CS_SET_WAIT;
-
- data_o( 6 downto 0) <= CHANNEL_IN;
- data_o(7) <= TIMESTAMP_STATUS_IN(1);
- data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
- data_o(18 downto 10) <= deltaTStore(8 downto 0);
- data_o(30 downto 19) <= ADC_DATA_IN;
+
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
end if;
end if;
- when x"1" => -- RefValue + valid filter
+ when x"1" => -- RefValue + valid filter + maxtime limit
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o( 6 downto 0) <= CHANNEL_IN;
- data_o(7) <= TIMESTAMP_STATUS_IN(1);
- data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
- data_o(18 downto 10) <= deltaTStore(8 downto 0);
- data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
data_o(31) <= TIMESTAMP_STATUS_IN(2);
data_clk_o <= '1';
end if;
when x"3" => -- RefValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o( 6 downto 0) <= CHANNEL_IN;
- data_o(7) <= TIMESTAMP_STATUS_IN(1);
- data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
- data_o(18 downto 10) <= deltaTStore(8 downto 0);
- data_o(30 downto 19) <= ADC_DATA_IN;
+ data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ data_o(11 downto 2) <= deltaTStore(9 downto 0);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
+ data_clk_o <= '1';
end if;
-
- when x"4" => -- RawValue
- data_o( 6 downto 0) <= CHANNEL_IN;
- data_o(7) <= TIMESTAMP_STATUS_IN(1);
- data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
- data_o(18 downto 10) <= deltaTStore(8 downto 0);
- data_o(30 downto 19) <= ADC_DATA_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
- when x"5" => -- RawValue + valid filter
+ when x"4" => -- RawValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o( 6 downto 0) <= CHANNEL_IN;
- data_o(7) <= TIMESTAMP_STATUS_IN(1);
- data_o( 9 downto 8) <= TIMESTAMP_IN(1 downto 0);
- data_o(18 downto 10) <= deltaTStore(8 downto 0);
- data_o(30 downto 19) <= ADC_DATA_IN;
- data_o(31) <= TIMESTAMP_STATUS_IN(2);
- data_clk_o <= '1';
+ data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
end if;
-
+
+ when x"5" => -- RawValue + maxtime limit
+ data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= TIMESTAMP_STATUS_IN(2);
+ data_clk_o <= '1';
+
when others => null;
end case;
-- Fill Histogram
histogram_fill_o <= '1';
histogram_bin_o <= CHANNEL_IN;
+ histogram_adc_o <= ADC_DATA_IN;
end if;
end if;
end if;
- end process PROC_PROCESS_TIMESTAMP;
+ end process PROC_FILTER_TIMESTAMPS;
-----------------------------------------------------------------------------
-- Trigger Handler
busy_time_min_done <= '0';
token_return_ctr <= '0';
ch_status_cmd_tr <= CS_RESET;
+ event_counter <= (others => '0');
+ readout_mode <= (others => '0');
+ timestamp_ref <= (others => '0');
STATE <= S_IDLE;
else
store_to_fifo <= '0';
min_validation_time := x"020" +
(trigger_window_delay / 2) +
(trigger_window_width / 2);
-
case STATE is
end if;
when S_TRIGGER =>
+ readout_mode <= readout_mode_r;
ch_status_cmd_tr <= CS_RESET;
wait_timer_init <= x"020"; -- wait 320ns for first event
STATE <= S_WAIT_DATA;
if (wait_timer_done = '0') then
STATE <= S_WAIT_DATA;
else
+ timestamp_ref <= TIMESTAMP_REF_IN;
STATE <= S_WRITE_HEADER;
end if;
when S_WRITE_HEADER =>
- --ts_ref := timestamp_ref - x"010";
- t_data_o(11 downto 0) <= timestamp_ref;
- t_data_o(15 downto 12) <= (others => '0');
- t_data_o(31 downto 16) <= BOARD_ID;
+ t_data_o(11 downto 0) <= timestamp_ref;
+ t_data_o(21 downto 12) <= event_counter;
+ -- Readout Mode Mapping (so far)
+ -- 00: Standard
+ -- 01: Special
+ -- 10: DEBUG
+ -- 11: UNDEF
+ case readout_mode is
+ when x"0" => t_data_o(23 downto 22) <= "00";
+ when x"1" => t_data_o(23 downto 22) <= "01";
+ when others => t_data_o(23 downto 22) <= "11";
+ end case;
+ t_data_o(31 downto 24) <= BOARD_ID(7 downto 0);
t_data_clk_o <= '1';
+
+ event_counter <= event_counter + 1;
STATE <= S_PROCESS_START;
when S_PROCESS_START =>
STATE <= S_WAIT_PROCESS_END;
when S_WAIT_PROCESS_END =>
- if (wait_timer_done = '1' or
- channel_all_done = '1' or
+ if (wait_timer_done = '1' or
+ channel_all_done = '1' or
(NX_NOMORE_DATA_IN = '1' and
- busy_time_ctr > min_validation_time(11 downto 0))
+ busy_time_ctr > min_validation_time(11 downto 0))
)
then
wait_timer_reset <= '1';
end if;
when S_WRITE_TRAILER =>
- t_data_o(11 downto 0) <= busy_time_ctr;
- t_data_o(15 downto 12) <= (others => '0');
- t_data_o(31 downto 16) <= BOARD_ID;
+ t_data_o <= (others => '1');
t_data_clk_o <= '1';
ch_status_cmd_tr <= CS_RESET;
STATE <= S_SET_NOMORE_DATA;
slv_ack_o <= '0';
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
- readout_mode <= "0000";
+ readout_mode_r <= x"0";
trigger_window_delay <= (others => '0');
trigger_window_width <= x"020";
readout_time_max <= x"640";
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- slv_data_out_o(3 downto 0) <= readout_mode;
+ slv_data_out_o(3 downto 0) <= readout_mode_r;
slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
elsif (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
when x"0000" =>
- readout_mode <= SLV_DATA_IN(3 downto 0);
+ readout_mode_r <= SLV_DATA_IN(3 downto 0);
slv_ack_o <= '1';
when x"0001" =>
HISTOGRAM_FILL_OUT <= histogram_fill_o;
HISTOGRAM_BIN_OUT <= histogram_bin_o;
+ HISTOGRAM_ADC_OUT <= histogram_adc_o;
-- Slave
SLV_DATA_OUT <= slv_data_out_o;
);
end component;
+component fifo_ts_12to12_dc
+ port (
+ Data : in std_logic_vector(11 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(11 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
+ );
+end component;
+
component fifo_44_data_delay
port (
Data : in std_logic_vector(43 downto 0);
NOMORE_DATA_OUT : out std_logic;
HISTOGRAM_FILL_OUT : out std_logic;
HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0);
+ HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
RESET_HISTS_IN : in std_logic;
CHANNEL_STAT_FILL_IN : in std_logic;
CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0);
+ CHANNEL_ADC_IN : in std_logic_vector(11 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
);
end component;
-component pll_125_hub
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- CLKOK : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_nx_clk256
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic);
-end component;
+-------------------------------------------------------------------------------
+-- PLLs
+-------------------------------------------------------------------------------
component pll_nx_clk250
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic);
-end component;
-
-component pll_adc_clk32
- port (
- CLK : in std_logic;
- CLKOP : out std_logic;
- LOCK : out std_logic
- );
-end component;
-
-component pll_adc_clk192
port (
CLK : in std_logic;
CLKOP : out std_logic;
);
end component;
-component pll_adc_clk3125
+component pll_adc_clk
port (
CLK : in std_logic;
CLKOP : out std_logic;
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
+ NX_CLK_IN : in std_logic;
TIMESTAMP_SYNC_IN : in std_logic;
TRIGGER_IN : in std_logic;
TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0);
);
end component;
--------------------------------------------------------------------------------
--- ADC Handler
--------------------------------------------------------------------------------
-component adc_ad9228
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- ADC_FCLK_IN : in std_logic;
- ADC_DCLK_IN : in std_logic;
- ADC_SC_CLK32_OUT : out std_logic;
- ADC_A_IN : in std_logic;
- ADC_B_IN : in std_logic;
- ADC_NX_IN : in std_logic;
- ADC_D_IN : in std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
-------------------------------------------------------------------------------
-- Misc Tools
-------------------------------------------------------------------------------
signal trigger_validate_fill : std_logic;
signal trigger_validate_bin : std_logic_vector(6 downto 0);
+ signal trigger_validate_adc : std_logic_vector(11 downto 0);
-- Event Buffer
signal trigger_evt_busy : std_logic;
7 => 2, -- Trigger Handler
8 => 4, -- Trigger Validate
9 => 8, -- NX Register Setup
- 10 => 8, -- NX Histograms
+ 10 => 9, -- NX Histograms
11 => 0, -- Debug Handler
12 => 2, -- Data Delay
others => 0
nx_fpga_timestamp_1: nx_fpga_timestamp
port map (
- CLK_IN => CLK_NX_IN,
+ CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
+ NX_CLK_IN => CLK_NX_IN,
TIMESTAMP_SYNC_IN => nx_ts_reset_o,
TRIGGER_IN => timestamp_trigger,
TIMESTAMP_CURRENT_OUT => timestamp_current,
HISTOGRAM_FILL_OUT => trigger_validate_fill,
HISTOGRAM_BIN_OUT => trigger_validate_bin,
+ HISTOGRAM_ADC_OUT => trigger_validate_adc,
SLV_READ_IN => slv_read(8),
SLV_WRITE_IN => slv_write(8),
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- RESET_HISTS_IN => open,
+ RESET_HISTS_IN => '0',
CHANNEL_STAT_FILL_IN => trigger_validate_fill,
CHANNEL_ID_IN => trigger_validate_bin,
-
+ CHANNEL_ADC_IN => trigger_validate_adc,
+
SLV_READ_IN => slv_read(10),
SLV_WRITE_IN => slv_write(10),
SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32),
begin
- DEBUG_OUT(0) <= I2C_SM_RESET_OUT ;
- DEBUG_OUT(1) <= I2C_REG_RESET_OUT;
- DEBUG_OUT(2) <= NX_TS_RESET_OUT;
+ DEBUG_OUT(0) <= i2c_sm_reset_o ;
+ DEBUG_OUT(1) <= i2c_reg_reset_o;
+ DEBUG_OUT(2) <= nx_ts_reset_o;
DEBUG_OUT(15 downto 3) <= (others => '0');
0x8145 : r : Testpulse Rate (in Hz)
-- Trigger Handler
-0x8160 : r/w Bit 15-0 : Delay Timestamp Hold Signal (8bit, 10ns)
+0x8160 : r/w Bit 7-0 : Delay Testpulse Signal after Trigger (10ns)
0x8161 : r/w Bit 0 : Enable Testpulse Signal (default: off)
0x8162 : r : Accepted Trigger Rate (in Hz)
0x8183 : r/w Readout Time Max (12 bit, in 10ns)
0x8184 : r Busy Time Counter (12 bit, in 10ns)
-0x8185 : r done counter
-0x8186 : r done counter
-0x8187 : r done counter
-0x8188 : r done counter
+0x8185 : r timestamp_ref
+0x8186 : r window_lower_thr
+0x8187 : r window_upper_thr
+0x8188 : r done counter ch 0..31
+0x8189 : r done counter ch 32..63
+0x818a : r done counter ch 94..95
+0x818b : r done counter ch 96..127
-- Event Data Buffer
0x8600 : r read FIFO buffer
0x8800 : r: Read Channel Statistic (128 channel in a row)
w: reset all Histograms
0x8880 : r: Read Channel Trigger Rate (128 channel in a row, 1/s)
+0x8900 : r: Read Channel ADC Value (128 channel in a row)
-- Debug Multiplexer
0x8020 : r/w Select Debug Entity
# nXyter Files
-add_file -vhdl -lib "work" "cores/pll_125_hub.vhd"
-add_file -vhdl -lib "work" "cores/pll_nx_clk256.vhd"
add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd"
-add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd"
+add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd"
add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd"
add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
+add_file -vhdl -lib "work" "cores/fifo_ts_12to12_dc.vhd"
add_file -vhdl -lib "work" "trb3_periph.vhd"
--attribute syn_useioff of INP : signal is false;
attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true;
attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true;
+
+ --attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX2_ADC_NX_IN : signal is true;
+ --attribute syn_useioff of NX1_ADC_D_IN : signal is true;
+ --attribute syn_useioff of NX2_ADC_D_IN : signal is true;
+
--attribute syn_useioff of NX1_ADC_NX_IN : signal is true;
--attribute syn_useioff of DAC_SDO : signal is true;
--attribute syn_useioff of DAC_SDI : signal is true;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
- -- For 250MHz PLL nxyter clock, THE_256M_ODDR_1
- --attribute ODDRAPPS : string;
- --attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED";
-
-
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
--FPGA Test
signal time_counter : unsigned(31 downto 0);
-
-- nXyter-FEB-Board Clocks
- signal nx_clk256 : std_logic;
- signal pll_lock_clk256 : std_logic;
+ signal nx_main_clk : std_logic;
+ signal pll_nx_clk_lock : std_logic;
signal clk_adc_dat : std_logic;
- signal clk_adc_dat_lock : std_logic;
+ signal pll_adc_clk_lock : std_logic;
-- nXyter 1 Regio Bus
signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
timing_trg_received_i <= TRIGGER_LEFT;
--- fee_trg_release_i(1) <= '1';
--- fee_data_i(1*32+31 downto 1*32) <= (others => '1');
--- fee_trg_statusbits_i(1*32+31 downto 1*32) <= (others => '0');
--- fee_data_write_i(1) <= '0';
--- fee_data_finished_i(1) <= '1';
-
---------------------------------------------------------------------------
-- AddOn
---------------------------------------------------------------------------
nXyter_FEE_board_0: nXyter_FEE_board
generic map (
- BOARD_ID => x"affe"
+ BOARD_ID => x"0001"
)
port map (
CLK_IN => clk_100_i,
RESET_IN => reset_i,
- CLK_NX_IN => nx_clk256,
+ CLK_NX_IN => nx_main_clk,
CLK_ADC_IN => clk_adc_dat,
TRIGGER_OUT => fee1_trigger,
nXyter_FEE_board_1: nXyter_FEE_board
generic map (
- BOARD_ID => x"babe"
+ BOARD_ID => x"0002"
)
port map (
CLK_IN => clk_100_i,
RESET_IN => reset_i,
- CLK_NX_IN => nx_clk256,
+ CLK_NX_IN => nx_main_clk,
CLK_ADC_IN => clk_adc_dat,
TRIGGER_OUT => fee2_trigger,
ADDON_TRIGGER_OUT <= fee1_trigger or fee2_trigger;
-----------------------------------------------------------------------------
- -- nXyter common Clocks
+ -- nXyter Main and ADC Clocks
-----------------------------------------------------------------------------
- pll_nx_clk256_1: entity work.pll_nx_clk256
+
+ -- nXyter Main Clock (250/256 MHz)
+ pll_nx_clk250_1: entity work.pll_nx_clk250
port map (
- CLK => clk_100_i,
- CLKOP => nx_clk256,
- LOCK => pll_lock_clk256
+ CLK => clk_200_i,
+ CLKOP => nx_main_clk,
+ LOCK => pll_nx_clk_lock
);
- NX1_CLK256A_OUT <= nx_clk256;
- NX2_CLK256A_OUT <= nx_clk256;
+ NX1_CLK256A_OUT <= nx_main_clk;
+ NX2_CLK256A_OUT <= nx_main_clk;
- -- ADC Receiver Clock
- pll_adc_clk192_1: pll_adc_clk192
+ -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be base on same
+ -- ClockSource as nXyter Main Clock)
+ pll_adc_clk_1: pll_adc_clk
port map (
- CLK => CLK_PCLK_LEFT,
+ CLK => clk_200_i,
CLKOP => clk_adc_dat,
- LOCK => clk_adc_dat_lock
+ LOCK => pll_adc_clk_lock
);
-----------------------------------------------------------------------------
- -- 250MHz Clock to nXyters
- --pll_nx_clk250_1: entity work.pll_nx_clk250
- -- port map (
- -- CLK => CLK_GPLL_LEFT,
- -- CLKOP => nx1_clk256_o,
- -- LOCK => open
- -- );
-
- --pll_125_hub_1: pll_125_hub
- -- port map (
- -- CLK => CLK_GPLL_LEFT,
- -- CLKOP => open,
- -- CLKOK => nx1_clk256_o,
- -- LOCK => open
- -- );
- -- NX1_CLK256A_OUT <= CLK_PCLK_RIGHT;
-
- --THE_256M_ODDR_1: ODDRXD1
- -- port map(
- -- SCLK => nx1_clk256_o,
- -- DA => '1',
- -- DB => '0',
- -- Q => NX1_CLK256A_OUT
- -- );
-
-
-------------------------------------------------------------------------------
-- Timestamp Simulator
-------------------------------------------------------------------------------
# Basic Settings
#################################################################
+ #Speed for the configuration Flash access
SYSCONFIG MCCLK_FREQ = 20;
- FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
- FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+
+ # Clock Setup:
+ #
+ # CLK_GPLL_RIGHT : real Oszillator 200MHz
+ # CLK_GPLL_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities
+ # CLK_GPLL_RIGHT --> PLL#0 --> clk_200_i -----> PLL#1
+ #
+ # clk_200_i (PLL#1) --> nx_main_clk
+ # (250/256 MHz) -----> nXyter Main Clock
+ # |
+ # |----> FPGA Timestamp Entity
+ #
+ # clk_200_i (PLL#1) --> clk_adc_dat
+ # (nx_main_clk * 3/8) -----> ADC Handler
+ #
+ # nXyter Main Clock --> nXyter Data Clock -----> FPGA Data Receiver
+ # |
+ # |----> Johnson 1/4 --> ADC SCLK
+
+
+ # Not used in current design
+ #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+ #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+
FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
- FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+ #USE PRIMARY NET CLK_GPLL_RIGHT;
+ #USE PRIMARY NET CLK_GPLL_RIGHT_c;
- FREQUENCY PORT NX1_CLK256A_OUT 256 MHz;
- FREQUENCY PORT NX2_CLK256A_OUT 256 MHz;
-
-#Put the names of your nxyter inputs here:
- FREQUENCY PORT NX1_CLK128_IN 128 MHz;
- FREQUENCY PORT NX2_CLK128_IN 128 MHz;
- FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz;
- FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;
+ #FREQUENCY PORT nx_main_clk 250 MHz;
+ USE PRIMARY NET "nx_main_clk";
+ #USE PRIMARY NET CLK_GPLL_RIGHT_c;
-#Change the next two lines to the clk_fast signal of the ADC
- USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0";
- USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0";
+ LOCATE COMP THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C5;
+
+
+# Put the names of your nxyter inputs here:
+ FREQUENCY PORT NX1_CLK128_IN 125 MHz;
+ FREQUENCY PORT NX2_CLK128_IN 125 MHz;
+ #FREQUENCY PORT NX1_ADC_DCLK_IN 93.75 MHz;
+ #FREQUENCY PORT NX2_ADC_DCLK_IN 93.75 MHz;
+
+ FREQUENCY PORT NX1_ADC_SAMPLE_CLK_OUT 31.25 MHz;
+ FREQUENCY PORT NX2_ADC_SAMPLE_CLK_OUT 31.25 MHz;
+
+# ------ ADC Stuff ---------------------------
+
+# ADC Settings
- USE PRIMARY NET "CLK_PCLK_LEFT";
- USE PRIMARY NET "CLK_PCLK_LEFT_c";
-
- USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
- USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c";
+ #FREQUENCY PORT clk_adc_dat 93.75 MHz;
+ #USE PRIMARY NET "clk_adc_dat";
+ USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
- USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c";
- USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
- USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
-
- #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
- #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+ #PROHIBIT PRIMARY NET "NX1_ADC_FCLK_IN";
+ #PROHIBIT PRIMARY NET "NX1B_ADC_FCLK_IN";
+ #PROHIBIT SECONDARY NET "NX1_ADC_FCLK_IN";
+ #PROHIBIT SECONDARY NET "NX1B_ADC_FCLK_IN";
+ #PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN";
+ #PROHIBIT PRIMARY NET "NX1B_ADC_DCLK_IN";
+ #PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN";
+ #PROHIBIT SECONDARY NET "NX1B_ADC_DCLK_IN";
+
+ #PROHIBIT PRIMARY NET "NX2_ADC_FCLK_IN";
+ #PROHIBIT PRIMARY NET "NX2B_ADC_FCLK_IN";
+ #PROHIBIT SECONDARY NET "NX2_ADC_FCLK_IN";
+ #PROHIBIT SECONDARY NET "NX2B_ADC_FCLK_IN";
+ #PROHIBIT PRIMARY NET "NX2_ADC_DCLK_IN";
+ #PROHIBIT PRIMARY NET "NX2B_ADC_DCLK_IN";
+ #PROHIBIT SECONDARY NET "NX2_ADC_DCLK_IN";
+ #PROHIBIT SECONDARY NET "NX2B_ADC_DCLK_IN";
#################################################################
# Reset Nets
#################################################################
-GSR_NET NET "GSR_N";
+
+#GSR_NET NET "GSR_N";
#################################################################
#################################################################
# Relax some of the timing constraints
#################################################################
-MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns;
+# WARNING: matches no cells in the design.
+#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns;
+MULTICYCLE FROM CLKNET "nx_main_clk" 50 ns;
#################################################################
# Constraints for nxyter inputs
# look at .par and .twr.setup file for clocks
# and .mrp or errors
-PROHIBIT PRIMARY NET "NX1_CLK128_IN_c";
+PROHIBIT PRIMARY NET "NX1_CLK128_IN_c";
PROHIBIT SECONDARY NET "NX1_CLK128_IN_c";
-PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
+PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
PROHIBIT SECONDARY NET "NX2_CLK128_IN_c";
-PROHIBIT PRIMARY NET "TEST_LINE_c_0_1";
-PROHIBIT SECONDARY NET "TEST_LINE_c_0_1";
-
DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ;
+INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN";
DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN" ;
-
-MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c" 50 ns;
-MULTICYCLE FROM CLKNET "NX2_CLK256A_OUT_c" 50 ns;
-
-#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c";
-#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";
+INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN";
jspc29 / trb3.git / commitdiff