--- /dev/null
+MODULE serdes_gbe_2\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=PCS\r
+CoreRevision=7.0\r
+ModuleName=serdes_gbe_2\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=07/30/2009\r
+Time=11:43:53\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Protocol=Quad\r
+mode=Gigabit Ethernet\r
+Channel0=DISABLE\r
+Channel1=DISABLE\r
+Channel2=SINGLE\r
+Channel3=DISABLE\r
+Rate0=None\r
+Rate1=None\r
+Rate2=None\r
+Rate3=None\r
+TxRefClk=CORE_TXREFCLK\r
+RxRefClk=CORE_RXREFCLK\r
+ClkRate=2.0\r
+ClkMult=20X\r
+CalClkRate=100.0\r
+DataWidth=16\r
+FPGAClkRate=100.0\r
+TxRefClkCM=REFCLK\r
+RxRefClk0CM=REFCLK\r
+RxRefClk1CM=REFCLK\r
+RxRefClk2CM=REFCLK\r
+RxRefClk3CM=REFCLK\r
+ClkRateH=1.0\r
+ClkMultH=20XH\r
+CalClkRateH=100.0\r
+DataWidthH=8\r
+FPGAClkRateH=100.0\r
+VCh0=0\r
+VCh1=0\r
+VCh2=0\r
+VCh3=0\r
+PreCh0=DISABLE\r
+PreCh1=DISABLE\r
+PreCh2=DISABLE\r
+PreCh3=DISABLE\r
+TxCh0=50\r
+TxCh1=50\r
+TxCh2=50\r
+TxCh3=50\r
+EqCh0=DISABLE\r
+EqCh1=DISABLE\r
+EqCh2=DISABLE\r
+EqCh3=DISABLE\r
+RxTermCh0=50\r
+RxTermCh1=50\r
+RxTermCh2=50\r
+RxTermCh3=50\r
+RxCoupCh0=AC\r
+RxCoupCh1=AC\r
+RxCoupCh2=DC\r
+RxCoupCh3=AC\r
+Loss=0\r
+CDRLoss=0\r
+TxTerm=50\r
+TxCoup=AC\r
+TxPllLoss=0\r
+TxInvCh0=NORMAL\r
+TxInvCh1=NORMAL\r
+TxInvCh2=NORMAL\r
+TxInvCh3=NORMAL\r
+RxInvCh0=NORMAL\r
+RxInvCh1=NORMAL\r
+RxInvCh2=NORMAL\r
+RxInvCh3=NORMAL\r
+RxModeCh0=NORMAL\r
+RxModeCh1=NORMAL\r
+RxModeCh2=NORMAL\r
+RxModeCh3=NORMAL\r
+Plus=1100000101\r
+Minus=0011111010\r
+Mask=1111111111\r
+Align=AUTO\r
+CTCCh0=NORMAL\r
+CTCCh1=NORMAL\r
+CTCCh2=NORMAL\r
+CTCCh3=NORMAL\r
+CC_MATCH1=0000000000\r
+CC_MATCH2=0000000000\r
+CC_MATCH3=0110111100\r
+CC_MATCH4=0001010000\r
+MinIPG=3\r
+High=9\r
+Low=7\r
+CC_MATCH_MODE=MATCH_3_4\r
+RxDataCh0=FALSE\r
+RxDataCh1=FALSE\r
+RxDataCh2=FALSE\r
+RxDataCh3=FALSE\r
+AlignerCh0=FALSE\r
+AlignerCh1=FALSE\r
+AlignerCh2=FALSE\r
+AlignerCh3=FALSE\r
+DetectCh0=FALSE\r
+DetectCh1=FALSE\r
+DetectCh2=FALSE\r
+DetectCh3=FALSE\r
+ELSMCh0=FALSE\r
+ELSMCh1=FALSE\r
+ELSMCh2=FALSE\r
+ELSMCh3=FALSE\r
+_teidleCh0=FALSE\r
+_teidleCh1=FALSE\r
+_teidleCh2=FALSE\r
+_teidleCh3=FALSE\r
+Ports0=FALSE\r
+rdoPorts0=Serial Loopback\r
+Ports1=TRUE\r
+Ports2=TRUE\r
+Ports3=FALSE\r
+Ports3_1=FALSE\r
+Ports4=FALSE\r
--- /dev/null
+#define _device_name "LFE2M100E"\r
+#define _protocol_mode "Quad Based Protocol Mode"\r
+#define _protocol "GIGE" \r
+#define _ch0_mode "DISABLE" \r
+#define _ch1_mode "DISABLE" \r
+#define _ch2_mode "SINGLE" \r
+#define _ch3_mode "DISABLE" \r
+#define _pll_txsrc "CORE_TXREFCLK" \r
+#define _pll_rxsrc "CORE_RXREFCLK" \r
+#define _datarange "MEDHIGH" \r
+#define _refclk_mult "20X" \r
+#define _refclk_rate 100.0\r
+#define _data_width "16" \r
+#define _fpgaintclk_rate 100.0\r
+#define _ch0_tdrv_amp "0" \r
+#define _ch1_tdrv_amp "0" \r
+#define _ch2_tdrv_amp "0" \r
+#define _ch3_tdrv_amp "0" \r
+#define _ch0_tx_pre "DISABLE" \r
+#define _ch1_tx_pre "DISABLE" \r
+#define _ch2_tx_pre "DISABLE" \r
+#define _ch3_tx_pre "DISABLE" \r
+#define _ch0_rterm_tx "50" \r
+#define _ch1_rterm_tx "50" \r
+#define _ch2_rterm_tx "50" \r
+#define _ch3_rterm_tx "50" \r
+#define _ch0_rx_eq "DISABLE" \r
+#define _ch1_rx_eq "DISABLE" \r
+#define _ch2_rx_eq "DISABLE" \r
+#define _ch3_rx_eq "DISABLE" \r
+#define _ch0_rterm_rx "50" \r
+#define _ch1_rterm_rx "50" \r
+#define _ch2_rterm_rx "50" \r
+#define _ch3_rterm_rx "50" \r
+#define _ch0_rx_dcc "AC" \r
+#define _ch1_rx_dcc "AC" \r
+#define _ch2_rx_dcc "DC" \r
+#define _ch3_rx_dcc "AC" \r
+#define _los_threshold "0" \r
+#define _pll_term "50" \r
+#define _pll_dcc "AC" \r
+#define _pll_lol_set "0" \r
+#define _ch0_tx_sb "NORMAL" \r
+#define _ch1_tx_sb "NORMAL" \r
+#define _ch2_tx_sb "NORMAL" \r
+#define _ch3_tx_sb "NORMAL" \r
+#define _ch0_rx_sb "NORMAL" \r
+#define _ch1_rx_sb "NORMAL" \r
+#define _ch2_rx_sb "NORMAL" \r
+#define _ch3_rx_sb "NORMAL" \r
+#define _ch0_8b10b "NORMAL" \r
+#define _ch1_8b10b "NORMAL" \r
+#define _ch2_8b10b "NORMAL" \r
+#define _ch3_8b10b "NORMAL" \r
+#define _comma_a "1100000101" \r
+#define _comma_b "0011111010" \r
+#define _comma_m "1111111111" \r
+#define _comma_align "AUTO" \r
+#define _ch0_ctc_byp "NORMAL" \r
+#define _ch1_ctc_byp "NORMAL" \r
+#define _ch2_ctc_byp "NORMAL" \r
+#define _ch3_ctc_byp "NORMAL" \r
+#define _cc_match1 "0000000000" \r
+#define _cc_match2 "0000000000" \r
+#define _cc_match3 "0110111100" \r
+#define _cc_match4 "0001010000" \r
+#define _cc_match_mode "MATCH_3_4" \r
+#define _cc_min_ipg "3" \r
+#define _cchmark "9" \r
+#define _cclmark "7" \r
+#define _ch0_ird "FALSE" \r
+#define _ch1_ird "FALSE" \r
+#define _ch2_ird "FALSE" \r
+#define _ch3_ird "FALSE" \r
+#define _ch0_elsm "FALSE" \r
+#define _ch1_elsm "FALSE" \r
+#define _ch2_elsm "FALSE" \r
+#define _ch3_elsm "FALSE" \r
+#define _ch0_teidle "FALSE"\r
+#define _ch1_teidle "FALSE"\r
+#define _ch2_teidle "FALSE"\r
+#define _ch3_teidle "FALSE"\r
+#define _loopback "FALSE" \r
+#define _lbtype "Serial Loopback"\r
+#define _refck2core "TRUE" \r
+#define _pllqclkports "FALSE"\r
+#define _sci_ports "FALSE" \r
+#define _sci_int_port "FALSE" \r
+#define _errsports "TRUE" \r
+\r
+#define _circuit_name serdes_gbe_2\r
+#define _lang vhdl\r
+\r
+#include <pcs/PCSC.vhd>\r
+#include <pcs/pcsc_cfg.txt>\r
--- /dev/null
+\r
+ TOOL: orcapp \r
+ DATE: 19-MAR-2008 13:11:51 \r
+ TITLE: Lattice Semiconductor Corporation\r
+ MODULE: serdes_gbe_2\r
+ DESIGN: serdes_gbe_2\r
+ FILENAME: serdes_gbe_2.readme\r
+ PROJECT: Unknown\r
+ VERSION: 2.0\r
+ This file is auto generated by the ispLEVER\r
+\r
+\r
+NOTE: This readme file has been provided to instantiate the interface\r
+netlist. Since this template contains synthesis attributes for precision that\r
+are crucial to the design flow, we recommend that you use this\r
+template in your FPGA design.\r
+entity chip is\r
+port (\r
+\r
+-- Add your FPGA design top level I/Os here\r
+\r
+\r
+-- ASIC side pins for PCSA. These pins must exist for the\r
+-- PCS core.\r
+ refclkp : in std_logic;\r
+ refclkn : in std_logic;\r
+ hdinp0 : in std_logic;\r
+ hdinn0 : in std_logic;\r
+ hdinp1 : in std_logic;\r
+ hdinn1 : in std_logic;\r
+ hdinp2 : in std_logic;\r
+ hdinn2 : in std_logic;\r
+ hdinp3 : in std_logic;\r
+ hdinn3 : in std_logic;\r
+\r
+ hdoutp0 : out std_logic;\r
+ hdoutn0 : out std_logic;\r
+ hdoutp1 : out std_logic;\r
+ hdoutn1 : out std_logic;\r
+ hdoutp2 : out std_logic;\r
+ hdoutn2 : out std_logic;\r
+ hdoutp3 : out std_logic;\r
+ hdoutn3 : out std_logic;\r
+\r
+\r
+);\r
+end chip;\r
+\r
+architecture chip_arch of chip is\r
+\r
+-- This defines all the high-speed ports. You may have to remove\r
+-- some of them depending on your design.\r
+attribute nopad : string;\r
+attribute nopad of\r
+ refclkp, refclkn,\r
+ hdinp0, hdinn0, hdinp1, hdinn1,\r
+ hdinp2, hdinn2, hdinp3, hdinn3,\r
+ hdoutp0, hdoutn0, hdoutp1, hdoutn1,\r
+ hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";\r
+\r
+ COMPONENT serdes_gbe_2\r
+ PORT(\r
+ core_txrefclk : IN std_logic;\r
+ core_rxrefclk : IN std_logic;\r
+ hdinp2 : IN std_logic;\r
+ hdinn2 : IN std_logic;\r
+ ff_rxiclk_ch2 : IN std_logic;\r
+ ff_txiclk_ch2 : IN std_logic;\r
+ ff_ebrd_clk_2 : IN std_logic;\r
+ ff_txdata_ch2 : IN std_logic_vector(15 downto 0);\r
+ ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0);\r
+ ff_xmit_ch2 : IN std_logic_vector(1 downto 0);\r
+ ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0);\r
+ ffc_rrst_ch2 : IN std_logic;\r
+ ffc_lane_tx_rst_ch2 : IN std_logic;\r
+ ffc_lane_rx_rst_ch2 : IN std_logic;\r
+ ffc_txpwdnb_ch2 : IN std_logic;\r
+ ffc_rxpwdnb_ch2 : IN std_logic;\r
+ ffc_macro_rst : IN std_logic;\r
+ ffc_quad_rst : IN std_logic;\r
+ ffc_trst : IN std_logic; \r
+ hdoutp2 : OUT std_logic;\r
+ hdoutn2 : OUT std_logic;\r
+ ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0);\r
+ ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_rxfullclk_ch2 : OUT std_logic;\r
+ ff_rxhalfclk_ch2 : OUT std_logic;\r
+ ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_cv_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ffs_rlos_lo_ch2 : OUT std_logic;\r
+ ffs_ls_sync_status_ch2 : OUT std_logic;\r
+ ffs_cc_underrun_ch2 : OUT std_logic;\r
+ ffs_cc_overrun_ch2 : OUT std_logic;\r
+ ffs_txfbfifo_error_ch2 : OUT std_logic;\r
+ ffs_rxfbfifo_error_ch2 : OUT std_logic;\r
+ ffs_rlol_ch2 : OUT std_logic;\r
+ oob_out_ch2 : OUT std_logic;\r
+ ff_txfullclk : OUT std_logic;\r
+ ff_txhalfclk : OUT std_logic;\r
+ refck2core : OUT std_logic;\r
+ ffs_plol : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+\r
+\r
+ uut: serdes_gbe_2 PORT MAP(\r
+ core_txrefclk => core_txrefclk,\r
+ core_rxrefclk => core_rxrefclk,\r
+ hdinp2 => hdinp2,\r
+ hdinn2 => hdinn2,\r
+ hdoutp2 => hdoutp2,\r
+ hdoutn2 => hdoutn2,\r
+ ff_rxiclk_ch2 => ff_rxiclk_ch2,\r
+ ff_txiclk_ch2 => ff_txiclk_ch2,\r
+ ff_ebrd_clk_2 => ff_ebrd_clk_2,\r
+ ff_txdata_ch2 => ff_txdata_ch2,\r
+ ff_rxdata_ch2 => ff_rxdata_ch2,\r
+ ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2,\r
+ ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2,\r
+ ff_rxfullclk_ch2 => ff_rxfullclk_ch2,\r
+ ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2,\r
+ ff_xmit_ch2 => ff_xmit_ch2,\r
+ ff_correct_disp_ch2 => ff_correct_disp_ch2,\r
+ ff_disp_err_ch2 => ff_disp_err_ch2,\r
+ ff_cv_ch2 => ff_cv_ch2,\r
+ ff_rx_even_ch2 => ff_rx_even_ch2,\r
+ ffc_rrst_ch2 => ffc_rrst_ch2,\r
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2,\r
+ ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2,\r
+ ffc_txpwdnb_ch2 => ffc_txpwdnb_ch2,\r
+ ffc_rxpwdnb_ch2 => ffc_rxpwdnb_ch2,\r
+ ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2,\r
+ ffs_ls_sync_status_ch2 => ffs_ls_sync_status_ch2,\r
+ ffs_cc_underrun_ch2 => ffs_cc_underrun_ch2,\r
+ ffs_cc_overrun_ch2 => ffs_cc_overrun_ch2,\r
+ ffs_txfbfifo_error_ch2 => ffs_txfbfifo_error_ch2,\r
+ ffs_rxfbfifo_error_ch2 => ffs_rxfbfifo_error_ch2,\r
+ ffs_rlol_ch2 => ffs_rlol_ch2,\r
+ oob_out_ch2 => oob_out_ch2,\r
+ ffc_macro_rst => ffc_macro_rst,\r
+ ffc_quad_rst => ffc_quad_rst,\r
+ ffc_trst => ffc_trst,\r
+ ff_txfullclk => ff_txfullclk,\r
+ ff_txhalfclk => ff_txhalfclk,\r
+ refck2core => refck2core,\r
+ ffs_plol => ffs_plol\r
+ );\r
+\r
+\r
--- /dev/null
+@set suppresnewline=on@\r
+\r
+@comment --------------------------------------------------------------------- @\r
+@comment Template-drive TFI generator @\r
+@comment Template for TFI generation. @\r
+@comment --------------------------------------------------------------------- @\r
+\r
+@set suppresnewline=off@\r
+ TOOL: orcapp \r
+ DATE: 19-MAR-2008 13:11:51 \r
+ TITLE: %title%\r
+ MODULE: %module%\r
+ DESIGN: %module%\r
+ FILENAME: %filename%\r
+ PROJECT: %project%\r
+ VERSION: %ver%\r
+ This file is auto generated by the ispLEVER\r
+@set suppresnewline=on@\r
+\r
+@cr@\r
+@cr@\r
+\r
+@set sigdelim=@\r
+\r
+NOTE: This readme file has been provided to instantiate the interface@cr@\r
+netlist. Since this template contains synthesis attributes for precision that@cr@\r
+are crucial to the design flow, we recommend that you use this@cr@\r
+template in your FPGA design.@cr@\r
+entity chip is@cr@\r
+port (@cr@\r
+@cr@\r
+-- Add your FPGA design top level I/Os here@cr@\r
+@cr@\r
+@cr@\r
+-- ASIC side pins for PCSA. These pins must exist for the@cr@\r
+-- PCS core.@cr@\r
+ refclkp : in std_logic;@cr@\r
+ refclkn : in std_logic;@cr@\r
+ hdinp0 : in std_logic;@cr@\r
+ hdinn0 : in std_logic;@cr@\r
+ hdinp1 : in std_logic;@cr@\r
+ hdinn1 : in std_logic;@cr@\r
+ hdinp2 : in std_logic;@cr@\r
+ hdinn2 : in std_logic;@cr@\r
+ hdinp3 : in std_logic;@cr@\r
+ hdinn3 : in std_logic;@cr@\r
+@cr@\r
+ hdoutp0 : out std_logic;@cr@\r
+ hdoutn0 : out std_logic;@cr@\r
+ hdoutp1 : out std_logic;@cr@\r
+ hdoutn1 : out std_logic;@cr@\r
+ hdoutp2 : out std_logic;@cr@\r
+ hdoutn2 : out std_logic;@cr@\r
+ hdoutp3 : out std_logic;@cr@\r
+ hdoutn3 : out std_logic;@cr@\r
+@cr@\r
+@cr@\r
+);@cr@\r
+end chip;@cr@\r
+@cr@\r
+architecture chip_arch of chip is@cr@\r
+@cr@\r
+-- This defines all the high-speed ports. You may have to remove@cr@\r
+-- some of them depending on your design.@cr@\r
+attribute nopad : string;@cr@\r
+attribute nopad of@cr@\r
+ refclkp, refclkn,@cr@\r
+ hdinp0, hdinn0, hdinp1, hdinn1,@cr@\r
+ hdinp2, hdinn2, hdinp3, hdinn3,@cr@\r
+ hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@\r
+ hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@\r
+\r
+@cr@\r
+@tab@COMPONENT %module%\r
+@set sigdelim=@\r
+@cr@@tab@PORT(\r
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@\r
+@ifhas oport=*@ @comment if the design has any output ports... @\r
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@\r
+ @set sigdelim=;@\r
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@\r
+@endif@\r
+@ifnhas oport=*@ @comment we need an "else in this language! @\r
+ @set sigdelim=;@\r
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@\r
+@endif@\r
+@cr@@tab@@tab@);@cr@\r
+@tab@END COMPONENT;@cr@@cr@\r
+@comment Now do a signal declaration for each port @\r
+\r
+@cr@@cr@\r
+@comment do the component instantiation @\r
+@set sigdelim=,@\r
+@tab@uut: %module% PORT MAP(\r
+@iterate@%port%\r
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@\r
+@cr@@tab@);@cr@@cr@\r
+@set suppresnewline=off@\r
--- /dev/null
+\r
+# This file is used by the simulation model as well as the ispLEVER bitstream\r
+# generation process to automatically initialize the PCSC quad to the mode\r
+# selected in the IPexpress. This file is expected to be modified by the\r
+# end user to adjust the PCSC quad to the final design requirements.\r
+\r
+DEVICE_NAME "LFE2M100E"\r
+PROTOCOL "GIGE" \r
+CH0_MODE "DISABLE" \r
+CH1_MODE "DISABLE" \r
+CH2_MODE "SINGLE" \r
+CH3_MODE "DISABLE" \r
+PLL_SRC "CORE_TXREFCLK" \r
+DATARANGE "MEDHIGH" \r
+CH2_CDR_SRC "CORE_RXREFCLK" \r
+CH2_DATA_WIDTH "16" \r
+CH2_REFCK_MULT "20X" \r
+#REFCLK_RATE 100.0\r
+#FPGAINTCLK_RATE 100.0\r
+CH2_TDRV_AMP "0" \r
+CH2_TX_PRE "DISABLE" \r
+CH2_RTERM_TX "50" \r
+CH2_RX_EQ "DISABLE" \r
+CH2_RTERM_RX "50" \r
+CH2_RX_DCC "DC" \r
+LOS_THRESHOLD "0" \r
+PLL_TERM "50" \r
+PLL_DCC "AC" \r
+PLL_LOL_SET "0" \r
+CH2_TX_SB "NORMAL" \r
+CH2_RX_SB "NORMAL" \r
+CH2_8B10B "NORMAL" \r
+COMMA_A "1100000101" \r
+COMMA_B "0011111010" \r
+COMMA_M "1111111111" \r
+CH2_COMMA_ALIGN "AUTO" \r
+CH2_CTC_BYP "NORMAL" \r
+CC_MATCH1 "0000000000" \r
+CC_MATCH2 "0000000000" \r
+CC_MATCH3 "0110111100" \r
+CC_MATCH4 "0001010000" \r
+CC_MATCH_MODE "MATCH_3_4" \r
+CC_MIN_IPG "3" \r
+CCHMARK "9" \r
+CCLMARK "7" \r
+OS_REFCK2CORE "1"\r
+OS_PLLQCLKPORTS "0"\r
+OS_INT_ALL "0"\r
+\r
--- /dev/null
+\r
+\r
+--synopsys translate_off\r
+\r
+library pcsc_work;\r
+use pcsc_work.all;\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity PCSC is\r
+GENERIC(\r
+ CONFIG_FILE : String := "serdes_gbe_2.txt"\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+\r
+end PCSC;\r
+\r
+architecture PCSC_arch of PCSC is\r
+\r
+component PCSC_sim\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+PCSC_sim_inst : PCSC_sim\r
+generic map (\r
+ CONFIG_FILE => CONFIG_FILE)\r
+port map (\r
+ HDINN0 => HDINN0,\r
+ HDINN1 => HDINN1,\r
+ HDINN2 => HDINN2,\r
+ HDINN3 => HDINN3,\r
+ HDINP0 => HDINP0,\r
+ HDINP1 => HDINP1,\r
+ HDINP2 => HDINP2,\r
+ HDINP3 => HDINP3,\r
+ REFCLKN => REFCLKN,\r
+ REFCLKP => REFCLKP,\r
+ CIN11 => CIN11,\r
+ CIN10 => CIN10,\r
+ CIN9 => CIN9,\r
+ CIN8 => CIN8,\r
+ CIN7 => CIN7,\r
+ CIN6 => CIN6,\r
+ CIN5 => CIN5,\r
+ CIN4 => CIN4,\r
+ CIN3 => CIN3,\r
+ CIN2 => CIN2,\r
+ CIN1 => CIN1,\r
+ CIN0 => CIN0,\r
+ CYAWSTN => CYAWSTN,\r
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,\r
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,\r
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,\r
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,\r
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,\r
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,\r
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,\r
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,\r
+\r
+ FF_TX_D_0_0 => FF_TX_D_0_0,\r
+ FF_TX_D_0_1 => FF_TX_D_0_1,\r
+ FF_TX_D_0_2 => FF_TX_D_0_2,\r
+ FF_TX_D_0_3 => FF_TX_D_0_3,\r
+ FF_TX_D_0_4 => FF_TX_D_0_4,\r
+ FF_TX_D_0_5 => FF_TX_D_0_5,\r
+ FF_TX_D_0_6 => FF_TX_D_0_6,\r
+ FF_TX_D_0_7 => FF_TX_D_0_7,\r
+ FF_TX_D_0_8 => FF_TX_D_0_8,\r
+ FF_TX_D_0_9 => FF_TX_D_0_9,\r
+ FF_TX_D_0_10 => FF_TX_D_0_10,\r
+ FF_TX_D_0_11 => FF_TX_D_0_11,\r
+ FF_TX_D_0_12 => FF_TX_D_0_12,\r
+ FF_TX_D_0_13 => FF_TX_D_0_13,\r
+ FF_TX_D_0_14 => FF_TX_D_0_14,\r
+ FF_TX_D_0_15 => FF_TX_D_0_15,\r
+ FF_TX_D_0_16 => FF_TX_D_0_16,\r
+ FF_TX_D_0_17 => FF_TX_D_0_17,\r
+ FF_TX_D_0_18 => FF_TX_D_0_18,\r
+ FF_TX_D_0_19 => FF_TX_D_0_19,\r
+ FF_TX_D_0_20 => FF_TX_D_0_20,\r
+ FF_TX_D_0_21 => FF_TX_D_0_21,\r
+ FF_TX_D_0_22 => FF_TX_D_0_22,\r
+ FF_TX_D_0_23 => FF_TX_D_0_23,\r
+ FF_TX_D_1_0 => FF_TX_D_1_0,\r
+ FF_TX_D_1_1 => FF_TX_D_1_1,\r
+ FF_TX_D_1_2 => FF_TX_D_1_2,\r
+ FF_TX_D_1_3 => FF_TX_D_1_3,\r
+ FF_TX_D_1_4 => FF_TX_D_1_4,\r
+ FF_TX_D_1_5 => FF_TX_D_1_5,\r
+ FF_TX_D_1_6 => FF_TX_D_1_6,\r
+ FF_TX_D_1_7 => FF_TX_D_1_7,\r
+ FF_TX_D_1_8 => FF_TX_D_1_8,\r
+ FF_TX_D_1_9 => FF_TX_D_1_9,\r
+ FF_TX_D_1_10 => FF_TX_D_1_10,\r
+ FF_TX_D_1_11 => FF_TX_D_1_11,\r
+ FF_TX_D_1_12 => FF_TX_D_1_12,\r
+ FF_TX_D_1_13 => FF_TX_D_1_13,\r
+ FF_TX_D_1_14 => FF_TX_D_1_14,\r
+ FF_TX_D_1_15 => FF_TX_D_1_15,\r
+ FF_TX_D_1_16 => FF_TX_D_1_16,\r
+ FF_TX_D_1_17 => FF_TX_D_1_17,\r
+ FF_TX_D_1_18 => FF_TX_D_1_18,\r
+ FF_TX_D_1_19 => FF_TX_D_1_19,\r
+ FF_TX_D_1_20 => FF_TX_D_1_20,\r
+ FF_TX_D_1_21 => FF_TX_D_1_21,\r
+ FF_TX_D_1_22 => FF_TX_D_1_22,\r
+ FF_TX_D_1_23 => FF_TX_D_1_23,\r
+ FF_TX_D_2_0 => FF_TX_D_2_0,\r
+ FF_TX_D_2_1 => FF_TX_D_2_1,\r
+ FF_TX_D_2_2 => FF_TX_D_2_2,\r
+ FF_TX_D_2_3 => FF_TX_D_2_3,\r
+ FF_TX_D_2_4 => FF_TX_D_2_4,\r
+ FF_TX_D_2_5 => FF_TX_D_2_5,\r
+ FF_TX_D_2_6 => FF_TX_D_2_6,\r
+ FF_TX_D_2_7 => FF_TX_D_2_7,\r
+ FF_TX_D_2_8 => FF_TX_D_2_8,\r
+ FF_TX_D_2_9 => FF_TX_D_2_9,\r
+ FF_TX_D_2_10 => FF_TX_D_2_10,\r
+ FF_TX_D_2_11 => FF_TX_D_2_11,\r
+ FF_TX_D_2_12 => FF_TX_D_2_12,\r
+ FF_TX_D_2_13 => FF_TX_D_2_13,\r
+ FF_TX_D_2_14 => FF_TX_D_2_14,\r
+ FF_TX_D_2_15 => FF_TX_D_2_15,\r
+ FF_TX_D_2_16 => FF_TX_D_2_16,\r
+ FF_TX_D_2_17 => FF_TX_D_2_17,\r
+ FF_TX_D_2_18 => FF_TX_D_2_18,\r
+ FF_TX_D_2_19 => FF_TX_D_2_19,\r
+ FF_TX_D_2_20 => FF_TX_D_2_20,\r
+ FF_TX_D_2_21 => FF_TX_D_2_21,\r
+ FF_TX_D_2_22 => FF_TX_D_2_22,\r
+ FF_TX_D_2_23 => FF_TX_D_2_23,\r
+ FF_TX_D_3_0 => FF_TX_D_3_0,\r
+ FF_TX_D_3_1 => FF_TX_D_3_1,\r
+ FF_TX_D_3_2 => FF_TX_D_3_2,\r
+ FF_TX_D_3_3 => FF_TX_D_3_3,\r
+ FF_TX_D_3_4 => FF_TX_D_3_4,\r
+ FF_TX_D_3_5 => FF_TX_D_3_5,\r
+ FF_TX_D_3_6 => FF_TX_D_3_6,\r
+ FF_TX_D_3_7 => FF_TX_D_3_7,\r
+ FF_TX_D_3_8 => FF_TX_D_3_8,\r
+ FF_TX_D_3_9 => FF_TX_D_3_9,\r
+ FF_TX_D_3_10 => FF_TX_D_3_10,\r
+ FF_TX_D_3_11 => FF_TX_D_3_11,\r
+ FF_TX_D_3_12 => FF_TX_D_3_12,\r
+ FF_TX_D_3_13 => FF_TX_D_3_13,\r
+ FF_TX_D_3_14 => FF_TX_D_3_14,\r
+ FF_TX_D_3_15 => FF_TX_D_3_15,\r
+ FF_TX_D_3_16 => FF_TX_D_3_16,\r
+ FF_TX_D_3_17 => FF_TX_D_3_17,\r
+ FF_TX_D_3_18 => FF_TX_D_3_18,\r
+ FF_TX_D_3_19 => FF_TX_D_3_19,\r
+ FF_TX_D_3_20 => FF_TX_D_3_20,\r
+ FF_TX_D_3_21 => FF_TX_D_3_21,\r
+ FF_TX_D_3_22 => FF_TX_D_3_22,\r
+ FF_TX_D_3_23 => FF_TX_D_3_23,\r
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,\r
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,\r
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,\r
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,\r
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
+ FFC_EI_EN_0 => FFC_EI_EN_0,\r
+ FFC_EI_EN_1 => FFC_EI_EN_1,\r
+ FFC_EI_EN_2 => FFC_EI_EN_2,\r
+ FFC_EI_EN_3 => FFC_EI_EN_3,\r
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,\r
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,\r
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,\r
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,\r
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,\r
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,\r
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,\r
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,\r
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,\r
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,\r
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,\r
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,\r
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,\r
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,\r
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,\r
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,\r
+ FFC_MACRO_RST => FFC_MACRO_RST,\r
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,\r
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,\r
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,\r
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,\r
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,\r
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,\r
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,\r
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,\r
+ FFC_QUAD_RST => FFC_QUAD_RST,\r
+ FFC_RRST_0 => FFC_RRST_0,\r
+ FFC_RRST_1 => FFC_RRST_1,\r
+ FFC_RRST_2 => FFC_RRST_2,\r
+ FFC_RRST_3 => FFC_RRST_3,\r
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,\r
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,\r
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,\r
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,\r
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,\r
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,\r
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,\r
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,\r
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,\r
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,\r
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,\r
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,\r
+ FFC_TRST => FFC_TRST,\r
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,\r
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,\r
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,\r
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,\r
+ SCIADDR0 => SCIADDR0,\r
+ SCIADDR1 => SCIADDR1,\r
+ SCIADDR2 => SCIADDR2,\r
+ SCIADDR3 => SCIADDR3,\r
+ SCIADDR4 => SCIADDR4,\r
+ SCIADDR5 => SCIADDR5,\r
+ SCIENAUX => SCIENAUX,\r
+ SCIENCH0 => SCIENCH0,\r
+ SCIENCH1 => SCIENCH1,\r
+ SCIENCH2 => SCIENCH2,\r
+ SCIENCH3 => SCIENCH3,\r
+ SCIRD => SCIRD,\r
+ SCISELAUX => SCISELAUX,\r
+ SCISELCH0 => SCISELCH0,\r
+ SCISELCH1 => SCISELCH1,\r
+ SCISELCH2 => SCISELCH2,\r
+ SCISELCH3 => SCISELCH3,\r
+ SCIWDATA0 => SCIWDATA0,\r
+ SCIWDATA1 => SCIWDATA1,\r
+ SCIWDATA2 => SCIWDATA2,\r
+ SCIWDATA3 => SCIWDATA3,\r
+ SCIWDATA4 => SCIWDATA4,\r
+ SCIWDATA5 => SCIWDATA5,\r
+ SCIWDATA6 => SCIWDATA6,\r
+ SCIWDATA7 => SCIWDATA7,\r
+ SCIWSTN => SCIWSTN,\r
+ HDOUTN0 => HDOUTN0,\r
+ HDOUTN1 => HDOUTN1,\r
+ HDOUTN2 => HDOUTN2,\r
+ HDOUTN3 => HDOUTN3,\r
+ HDOUTP0 => HDOUTP0,\r
+ HDOUTP1 => HDOUTP1,\r
+ HDOUTP2 => HDOUTP2,\r
+ HDOUTP3 => HDOUTP3,\r
+ COUT19 => COUT19,\r
+ COUT18 => COUT18,\r
+ COUT17 => COUT17,\r
+ COUT16 => COUT16,\r
+ COUT15 => COUT15,\r
+ COUT14 => COUT14,\r
+ COUT13 => COUT13,\r
+ COUT12 => COUT12,\r
+ COUT11 => COUT11,\r
+ COUT10 => COUT10,\r
+ COUT9 => COUT9,\r
+ COUT8 => COUT8,\r
+ COUT7 => COUT7,\r
+ COUT6 => COUT6,\r
+ COUT5 => COUT5,\r
+ COUT4 => COUT4,\r
+ COUT3 => COUT3,\r
+ COUT2 => COUT2,\r
+ COUT1 => COUT1,\r
+ COUT0 => COUT0,\r
+ FF_RX_D_0_0 => FF_RX_D_0_0,\r
+ FF_RX_D_0_1 => FF_RX_D_0_1,\r
+ FF_RX_D_0_2 => FF_RX_D_0_2,\r
+ FF_RX_D_0_3 => FF_RX_D_0_3,\r
+ FF_RX_D_0_4 => FF_RX_D_0_4,\r
+ FF_RX_D_0_5 => FF_RX_D_0_5,\r
+ FF_RX_D_0_6 => FF_RX_D_0_6,\r
+ FF_RX_D_0_7 => FF_RX_D_0_7,\r
+ FF_RX_D_0_8 => FF_RX_D_0_8,\r
+ FF_RX_D_0_9 => FF_RX_D_0_9,\r
+ FF_RX_D_0_10 => FF_RX_D_0_10,\r
+ FF_RX_D_0_11 => FF_RX_D_0_11,\r
+ FF_RX_D_0_12 => FF_RX_D_0_12,\r
+ FF_RX_D_0_13 => FF_RX_D_0_13,\r
+ FF_RX_D_0_14 => FF_RX_D_0_14,\r
+ FF_RX_D_0_15 => FF_RX_D_0_15,\r
+ FF_RX_D_0_16 => FF_RX_D_0_16,\r
+ FF_RX_D_0_17 => FF_RX_D_0_17,\r
+ FF_RX_D_0_18 => FF_RX_D_0_18,\r
+ FF_RX_D_0_19 => FF_RX_D_0_19,\r
+ FF_RX_D_0_20 => FF_RX_D_0_20,\r
+ FF_RX_D_0_21 => FF_RX_D_0_21,\r
+ FF_RX_D_0_22 => FF_RX_D_0_22,\r
+ FF_RX_D_0_23 => FF_RX_D_0_23,\r
+ FF_RX_D_1_0 => FF_RX_D_1_0,\r
+ FF_RX_D_1_1 => FF_RX_D_1_1,\r
+ FF_RX_D_1_2 => FF_RX_D_1_2,\r
+ FF_RX_D_1_3 => FF_RX_D_1_3,\r
+ FF_RX_D_1_4 => FF_RX_D_1_4,\r
+ FF_RX_D_1_5 => FF_RX_D_1_5,\r
+ FF_RX_D_1_6 => FF_RX_D_1_6,\r
+ FF_RX_D_1_7 => FF_RX_D_1_7,\r
+ FF_RX_D_1_8 => FF_RX_D_1_8,\r
+ FF_RX_D_1_9 => FF_RX_D_1_9,\r
+ FF_RX_D_1_10 => FF_RX_D_1_10,\r
+ FF_RX_D_1_11 => FF_RX_D_1_11,\r
+ FF_RX_D_1_12 => FF_RX_D_1_12,\r
+ FF_RX_D_1_13 => FF_RX_D_1_13,\r
+ FF_RX_D_1_14 => FF_RX_D_1_14,\r
+ FF_RX_D_1_15 => FF_RX_D_1_15,\r
+ FF_RX_D_1_16 => FF_RX_D_1_16,\r
+ FF_RX_D_1_17 => FF_RX_D_1_17,\r
+ FF_RX_D_1_18 => FF_RX_D_1_18,\r
+ FF_RX_D_1_19 => FF_RX_D_1_19,\r
+ FF_RX_D_1_20 => FF_RX_D_1_20,\r
+ FF_RX_D_1_21 => FF_RX_D_1_21,\r
+ FF_RX_D_1_22 => FF_RX_D_1_22,\r
+ FF_RX_D_1_23 => FF_RX_D_1_23,\r
+ FF_RX_D_2_0 => FF_RX_D_2_0,\r
+ FF_RX_D_2_1 => FF_RX_D_2_1,\r
+ FF_RX_D_2_2 => FF_RX_D_2_2,\r
+ FF_RX_D_2_3 => FF_RX_D_2_3,\r
+ FF_RX_D_2_4 => FF_RX_D_2_4,\r
+ FF_RX_D_2_5 => FF_RX_D_2_5,\r
+ FF_RX_D_2_6 => FF_RX_D_2_6,\r
+ FF_RX_D_2_7 => FF_RX_D_2_7,\r
+ FF_RX_D_2_8 => FF_RX_D_2_8,\r
+ FF_RX_D_2_9 => FF_RX_D_2_9,\r
+ FF_RX_D_2_10 => FF_RX_D_2_10,\r
+ FF_RX_D_2_11 => FF_RX_D_2_11,\r
+ FF_RX_D_2_12 => FF_RX_D_2_12,\r
+ FF_RX_D_2_13 => FF_RX_D_2_13,\r
+ FF_RX_D_2_14 => FF_RX_D_2_14,\r
+ FF_RX_D_2_15 => FF_RX_D_2_15,\r
+ FF_RX_D_2_16 => FF_RX_D_2_16,\r
+ FF_RX_D_2_17 => FF_RX_D_2_17,\r
+ FF_RX_D_2_18 => FF_RX_D_2_18,\r
+ FF_RX_D_2_19 => FF_RX_D_2_19,\r
+ FF_RX_D_2_20 => FF_RX_D_2_20,\r
+ FF_RX_D_2_21 => FF_RX_D_2_21,\r
+ FF_RX_D_2_22 => FF_RX_D_2_22,\r
+ FF_RX_D_2_23 => FF_RX_D_2_23,\r
+ FF_RX_D_3_0 => FF_RX_D_3_0,\r
+ FF_RX_D_3_1 => FF_RX_D_3_1,\r
+ FF_RX_D_3_2 => FF_RX_D_3_2,\r
+ FF_RX_D_3_3 => FF_RX_D_3_3,\r
+ FF_RX_D_3_4 => FF_RX_D_3_4,\r
+ FF_RX_D_3_5 => FF_RX_D_3_5,\r
+ FF_RX_D_3_6 => FF_RX_D_3_6,\r
+ FF_RX_D_3_7 => FF_RX_D_3_7,\r
+ FF_RX_D_3_8 => FF_RX_D_3_8,\r
+ FF_RX_D_3_9 => FF_RX_D_3_9,\r
+ FF_RX_D_3_10 => FF_RX_D_3_10,\r
+ FF_RX_D_3_11 => FF_RX_D_3_11,\r
+ FF_RX_D_3_12 => FF_RX_D_3_12,\r
+ FF_RX_D_3_13 => FF_RX_D_3_13,\r
+ FF_RX_D_3_14 => FF_RX_D_3_14,\r
+ FF_RX_D_3_15 => FF_RX_D_3_15,\r
+ FF_RX_D_3_16 => FF_RX_D_3_16,\r
+ FF_RX_D_3_17 => FF_RX_D_3_17,\r
+ FF_RX_D_3_18 => FF_RX_D_3_18,\r
+ FF_RX_D_3_19 => FF_RX_D_3_19,\r
+ FF_RX_D_3_20 => FF_RX_D_3_20,\r
+ FF_RX_D_3_21 => FF_RX_D_3_21,\r
+ FF_RX_D_3_22 => FF_RX_D_3_22,\r
+ FF_RX_D_3_23 => FF_RX_D_3_23,\r
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,\r
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,\r
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,\r
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,\r
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,\r
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,\r
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,\r
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,\r
+ FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,\r
+ FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,\r
+ FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,\r
+ FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,\r
+ FF_TX_F_CLK => FF_TX_F_CLK,\r
+ FF_TX_H_CLK => FF_TX_H_CLK,\r
+ FF_TX_Q_CLK => FF_TX_Q_CLK,\r
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,\r
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,\r
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,\r
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,\r
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,\r
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,\r
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,\r
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,\r
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,\r
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,\r
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,\r
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,\r
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,\r
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,\r
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,\r
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,\r
+ FFS_PLOL => FFS_PLOL,\r
+ FFS_RLOL_0 => FFS_RLOL_0,\r
+ FFS_RLOL_1 => FFS_RLOL_1,\r
+ FFS_RLOL_2 => FFS_RLOL_2,\r
+ FFS_RLOL_3 => FFS_RLOL_3,\r
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,\r
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,\r
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,\r
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,\r
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,\r
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,\r
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,\r
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,\r
+ OOB_OUT_0 => OOB_OUT_0,\r
+ OOB_OUT_1 => OOB_OUT_1,\r
+ OOB_OUT_2 => OOB_OUT_2,\r
+ OOB_OUT_3 => OOB_OUT_3,\r
+ REFCK2CORE => REFCK2CORE,\r
+ SCIINT => SCIINT,\r
+ SCIRDATA0 => SCIRDATA0,\r
+ SCIRDATA1 => SCIRDATA1,\r
+ SCIRDATA2 => SCIRDATA2,\r
+ SCIRDATA3 => SCIRDATA3,\r
+ SCIRDATA4 => SCIRDATA4,\r
+ SCIRDATA5 => SCIRDATA5,\r
+ SCIRDATA6 => SCIRDATA6,\r
+ SCIRDATA7 => SCIRDATA7\r
+ );\r
+\r
+end PCSC_arch;\r
+\r
+--synopsys translate_on\r
+\r
+--synopsys translate_off\r
+library ECP2;\r
+use ECP2.components.all;\r
+--synopsys translate_on\r
+\r
+library IEEE, STD;\r
+use IEEE.std_logic_1164.all;\r
+use STD.TEXTIO.all;\r
+\r
+entity serdes_gbe_2 is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_2.txt");\r
+ port (\r
+ core_txrefclk : in std_logic;\r
+ core_rxrefclk : in std_logic;\r
+ hdinp2, hdinn2 : in std_logic;\r
+ hdoutp2, hdoutn2 : out std_logic;\r
+ ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic;\r
+ ff_txdata_ch2 : in std_logic_vector (15 downto 0);\r
+ ff_rxdata_ch2 : out std_logic_vector (15 downto 0);\r
+ ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0);\r
+ ff_rxfullclk_ch2 : out std_logic;\r
+ ff_rxhalfclk_ch2 : out std_logic;\r
+ ff_xmit_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_correct_disp_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0);\r
+ ff_rx_even_ch2 : out std_logic_vector (1 downto 0);\r
+ ffc_rrst_ch2 : in std_logic;\r
+ ffc_lane_tx_rst_ch2 : in std_logic;\r
+ ffc_lane_rx_rst_ch2 : in std_logic;\r
+ ffc_txpwdnb_ch2 : in std_logic;\r
+ ffc_rxpwdnb_ch2 : in std_logic;\r
+ ffs_rlos_lo_ch2 : out std_logic;\r
+ ffs_ls_sync_status_ch2 : out std_logic;\r
+ ffs_cc_underrun_ch2 : out std_logic;\r
+ ffs_cc_overrun_ch2 : out std_logic;\r
+ ffs_txfbfifo_error_ch2 : out std_logic;\r
+ ffs_rxfbfifo_error_ch2 : out std_logic;\r
+ ffs_rlol_ch2 : out std_logic;\r
+ oob_out_ch2 : out std_logic;\r
+ ffc_macro_rst : in std_logic;\r
+ ffc_quad_rst : in std_logic;\r
+ ffc_trst : in std_logic;\r
+ ff_txfullclk : out std_logic;\r
+ ff_txhalfclk : out std_logic;\r
+ refck2core : out std_logic;\r
+ ffs_plol : out std_logic);\r
+\r
+end serdes_gbe_2;\r
+\r
+architecture serdes_gbe_2_arch of serdes_gbe_2 is\r
+\r
+component VLO\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+\r
+component VHI\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+component PCSC\r
+--synopsys translate_off\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+--synopsys translate_on\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+ attribute IS_ASB: string;\r
+ attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";\r
+ attribute CONFIG_FILE: string;\r
+ attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;\r
+ attribute black_box_pad_pin: string;\r
+ attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";\r
+\r
+signal fpsc_vlo : std_logic := '0';\r
+signal cin : std_logic_vector (11 downto 0) := "000000000000";\r
+signal cout : std_logic_vector (19 downto 0);\r
+\r
+begin\r
+\r
+vlo_inst : VLO port map(Z => fpsc_vlo);\r
+\r
+-- pcs_quad instance\r
+PCSC_INST : PCSC\r
+--synopsys translate_off\r
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
+--synopsys translate_on\r
+port map (\r
+ FFC_CK_CORE_TX => core_txrefclk,\r
+ FFC_CK_CORE_RX => core_rxrefclk,\r
+ REFCLKP => fpsc_vlo,\r
+ REFCLKN => fpsc_vlo,\r
+ HDINP0 => fpsc_vlo,\r
+ HDINN0 => fpsc_vlo,\r
+ HDOUTP0 => open,\r
+ HDOUTN0 => open,\r
+ SCISELCH0 => fpsc_vlo,\r
+ SCIENCH0 => fpsc_vlo,\r
+ FF_RXI_CLK_0 => fpsc_vlo,\r
+ FF_TXI_CLK_0 => fpsc_vlo,\r
+ FF_EBRD_CLK_0 => fpsc_vlo,\r
+ FF_RX_F_CLK_0 => open,\r
+ FF_RX_H_CLK_0 => open,\r
+ FF_RX_Q_CLK_0 => open,\r
+ FF_TX_D_0_0 => fpsc_vlo,\r
+ FF_TX_D_0_1 => fpsc_vlo,\r
+ FF_TX_D_0_2 => fpsc_vlo,\r
+ FF_TX_D_0_3 => fpsc_vlo,\r
+ FF_TX_D_0_4 => fpsc_vlo,\r
+ FF_TX_D_0_5 => fpsc_vlo,\r
+ FF_TX_D_0_6 => fpsc_vlo,\r
+ FF_TX_D_0_7 => fpsc_vlo,\r
+ FF_TX_D_0_8 => fpsc_vlo,\r
+ FF_TX_D_0_9 => fpsc_vlo,\r
+ FF_TX_D_0_10 => fpsc_vlo,\r
+ FF_TX_D_0_11 => fpsc_vlo,\r
+ FF_TX_D_0_12 => fpsc_vlo,\r
+ FF_TX_D_0_13 => fpsc_vlo,\r
+ FF_TX_D_0_14 => fpsc_vlo,\r
+ FF_TX_D_0_15 => fpsc_vlo,\r
+ FF_TX_D_0_16 => fpsc_vlo,\r
+ FF_TX_D_0_17 => fpsc_vlo,\r
+ FF_TX_D_0_18 => fpsc_vlo,\r
+ FF_TX_D_0_19 => fpsc_vlo,\r
+ FF_TX_D_0_20 => fpsc_vlo,\r
+ FF_TX_D_0_21 => fpsc_vlo,\r
+ FF_TX_D_0_22 => fpsc_vlo,\r
+ FF_TX_D_0_23 => fpsc_vlo,\r
+ FF_RX_D_0_0 => open,\r
+ FF_RX_D_0_1 => open,\r
+ FF_RX_D_0_2 => open,\r
+ FF_RX_D_0_3 => open,\r
+ FF_RX_D_0_4 => open,\r
+ FF_RX_D_0_5 => open,\r
+ FF_RX_D_0_6 => open,\r
+ FF_RX_D_0_7 => open,\r
+ FF_RX_D_0_8 => open,\r
+ FF_RX_D_0_9 => open,\r
+ FF_RX_D_0_10 => open,\r
+ FF_RX_D_0_11 => open,\r
+ FF_RX_D_0_12 => open,\r
+ FF_RX_D_0_13 => open,\r
+ FF_RX_D_0_14 => open,\r
+ FF_RX_D_0_15 => open,\r
+ FF_RX_D_0_16 => open,\r
+ FF_RX_D_0_17 => open,\r
+ FF_RX_D_0_18 => open,\r
+ FF_RX_D_0_19 => open,\r
+ FF_RX_D_0_20 => open,\r
+ FF_RX_D_0_21 => open,\r
+ FF_RX_D_0_22 => open,\r
+ FF_RX_D_0_23 => open,\r
+ FFC_RRST_0 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,\r
+ FFC_SB_INV_RX_0 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_0 => fpsc_vlo,\r
+ FFC_PCIE_CT_0 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_0 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,\r
+ FFC_EI_EN_0 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_0 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_0 => fpsc_vlo,\r
+ FFC_TXPWDNB_0 => fpsc_vlo,\r
+ FFC_RXPWDNB_0 => fpsc_vlo,\r
+ FFS_RLOS_LO_0 => open,\r
+ FFS_PCIE_DONE_0 => open,\r
+ FFS_PCIE_CON_0 => open,\r
+ FFS_LS_SYNC_STATUS_0 => open,\r
+ FFS_CC_UNDERRUN_0 => open,\r
+ FFS_CC_OVERRUN_0 => open,\r
+ FFS_RLOL_0 => open,\r
+ FFS_RXFBFIFO_ERROR_0 => open,\r
+ FFS_TXFBFIFO_ERROR_0 => open,\r
+ OOB_OUT_0 => open,\r
+ HDINP1 => fpsc_vlo,\r
+ HDINN1 => fpsc_vlo,\r
+ HDOUTP1 => open,\r
+ HDOUTN1 => open,\r
+ SCISELCH1 => fpsc_vlo,\r
+ SCIENCH1 => fpsc_vlo,\r
+ FF_RXI_CLK_1 => fpsc_vlo,\r
+ FF_TXI_CLK_1 => fpsc_vlo,\r
+ FF_EBRD_CLK_1 => fpsc_vlo,\r
+ FF_RX_F_CLK_1 => open,\r
+ FF_RX_H_CLK_1 => open,\r
+ FF_RX_Q_CLK_1 => open,\r
+ FF_TX_D_1_0 => fpsc_vlo,\r
+ FF_TX_D_1_1 => fpsc_vlo,\r
+ FF_TX_D_1_2 => fpsc_vlo,\r
+ FF_TX_D_1_3 => fpsc_vlo,\r
+ FF_TX_D_1_4 => fpsc_vlo,\r
+ FF_TX_D_1_5 => fpsc_vlo,\r
+ FF_TX_D_1_6 => fpsc_vlo,\r
+ FF_TX_D_1_7 => fpsc_vlo,\r
+ FF_TX_D_1_8 => fpsc_vlo,\r
+ FF_TX_D_1_9 => fpsc_vlo,\r
+ FF_TX_D_1_10 => fpsc_vlo,\r
+ FF_TX_D_1_11 => fpsc_vlo,\r
+ FF_TX_D_1_12 => fpsc_vlo,\r
+ FF_TX_D_1_13 => fpsc_vlo,\r
+ FF_TX_D_1_14 => fpsc_vlo,\r
+ FF_TX_D_1_15 => fpsc_vlo,\r
+ FF_TX_D_1_16 => fpsc_vlo,\r
+ FF_TX_D_1_17 => fpsc_vlo,\r
+ FF_TX_D_1_18 => fpsc_vlo,\r
+ FF_TX_D_1_19 => fpsc_vlo,\r
+ FF_TX_D_1_20 => fpsc_vlo,\r
+ FF_TX_D_1_21 => fpsc_vlo,\r
+ FF_TX_D_1_22 => fpsc_vlo,\r
+ FF_TX_D_1_23 => fpsc_vlo,\r
+ FF_RX_D_1_0 => open,\r
+ FF_RX_D_1_1 => open,\r
+ FF_RX_D_1_2 => open,\r
+ FF_RX_D_1_3 => open,\r
+ FF_RX_D_1_4 => open,\r
+ FF_RX_D_1_5 => open,\r
+ FF_RX_D_1_6 => open,\r
+ FF_RX_D_1_7 => open,\r
+ FF_RX_D_1_8 => open,\r
+ FF_RX_D_1_9 => open,\r
+ FF_RX_D_1_10 => open,\r
+ FF_RX_D_1_11 => open,\r
+ FF_RX_D_1_12 => open,\r
+ FF_RX_D_1_13 => open,\r
+ FF_RX_D_1_14 => open,\r
+ FF_RX_D_1_15 => open,\r
+ FF_RX_D_1_16 => open,\r
+ FF_RX_D_1_17 => open,\r
+ FF_RX_D_1_18 => open,\r
+ FF_RX_D_1_19 => open,\r
+ FF_RX_D_1_20 => open,\r
+ FF_RX_D_1_21 => open,\r
+ FF_RX_D_1_22 => open,\r
+ FF_RX_D_1_23 => open,\r
+ FFC_RRST_1 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,\r
+ FFC_SB_INV_RX_1 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_1 => fpsc_vlo,\r
+ FFC_PCIE_CT_1 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_1 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,\r
+ FFC_EI_EN_1 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_1 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_1 => fpsc_vlo,\r
+ FFC_TXPWDNB_1 => fpsc_vlo,\r
+ FFC_RXPWDNB_1 => fpsc_vlo,\r
+ FFS_RLOS_LO_1 => open,\r
+ FFS_PCIE_DONE_1 => open,\r
+ FFS_PCIE_CON_1 => open,\r
+ FFS_LS_SYNC_STATUS_1 => open,\r
+ FFS_CC_UNDERRUN_1 => open,\r
+ FFS_CC_OVERRUN_1 => open,\r
+ FFS_RLOL_1 => open,\r
+ FFS_RXFBFIFO_ERROR_1 => open,\r
+ FFS_TXFBFIFO_ERROR_1 => open,\r
+ OOB_OUT_1 => open,\r
+ HDINP2 => hdinp2,\r
+ HDINN2 => hdinn2,\r
+ HDOUTP2 => hdoutp2,\r
+ HDOUTN2 => hdoutn2,\r
+ SCISELCH2 => fpsc_vlo,\r
+ SCIENCH2 => fpsc_vlo,\r
+ FF_RXI_CLK_2 => ff_rxiclk_ch2,\r
+ FF_TXI_CLK_2 => ff_txiclk_ch2,\r
+ FF_EBRD_CLK_2 => ff_ebrd_clk_2,\r
+ FF_RX_F_CLK_2 => ff_rxfullclk_ch2,\r
+ FF_RX_H_CLK_2 => ff_rxhalfclk_ch2,\r
+ FF_RX_Q_CLK_2 => open,\r
+ FF_TX_D_2_0 => ff_txdata_ch2(0),\r
+ FF_TX_D_2_1 => ff_txdata_ch2(1),\r
+ FF_TX_D_2_2 => ff_txdata_ch2(2),\r
+ FF_TX_D_2_3 => ff_txdata_ch2(3),\r
+ FF_TX_D_2_4 => ff_txdata_ch2(4),\r
+ FF_TX_D_2_5 => ff_txdata_ch2(5),\r
+ FF_TX_D_2_6 => ff_txdata_ch2(6),\r
+ FF_TX_D_2_7 => ff_txdata_ch2(7),\r
+ FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0),\r
+ FF_TX_D_2_9 => fpsc_vlo,\r
+ FF_TX_D_2_10 => ff_xmit_ch2(0),\r
+ FF_TX_D_2_11 => ff_correct_disp_ch2(0),\r
+ FF_TX_D_2_12 => ff_txdata_ch2(8),\r
+ FF_TX_D_2_13 => ff_txdata_ch2(9),\r
+ FF_TX_D_2_14 => ff_txdata_ch2(10),\r
+ FF_TX_D_2_15 => ff_txdata_ch2(11),\r
+ FF_TX_D_2_16 => ff_txdata_ch2(12),\r
+ FF_TX_D_2_17 => ff_txdata_ch2(13),\r
+ FF_TX_D_2_18 => ff_txdata_ch2(14),\r
+ FF_TX_D_2_19 => ff_txdata_ch2(15),\r
+ FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1),\r
+ FF_TX_D_2_21 => fpsc_vlo,\r
+ FF_TX_D_2_22 => ff_xmit_ch2(1),\r
+ FF_TX_D_2_23 => ff_correct_disp_ch2(1),\r
+ FF_RX_D_2_0 => ff_rxdata_ch2(0),\r
+ FF_RX_D_2_1 => ff_rxdata_ch2(1),\r
+ FF_RX_D_2_2 => ff_rxdata_ch2(2),\r
+ FF_RX_D_2_3 => ff_rxdata_ch2(3),\r
+ FF_RX_D_2_4 => ff_rxdata_ch2(4),\r
+ FF_RX_D_2_5 => ff_rxdata_ch2(5),\r
+ FF_RX_D_2_6 => ff_rxdata_ch2(6),\r
+ FF_RX_D_2_7 => ff_rxdata_ch2(7),\r
+ FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0),\r
+ FF_RX_D_2_9 => ff_disp_err_ch2(0),\r
+ FF_RX_D_2_10 => ff_cv_ch2(0),\r
+ FF_RX_D_2_11 => ff_rx_even_ch2(0),\r
+ FF_RX_D_2_12 => ff_rxdata_ch2(8),\r
+ FF_RX_D_2_13 => ff_rxdata_ch2(9),\r
+ FF_RX_D_2_14 => ff_rxdata_ch2(10),\r
+ FF_RX_D_2_15 => ff_rxdata_ch2(11),\r
+ FF_RX_D_2_16 => ff_rxdata_ch2(12),\r
+ FF_RX_D_2_17 => ff_rxdata_ch2(13),\r
+ FF_RX_D_2_18 => ff_rxdata_ch2(14),\r
+ FF_RX_D_2_19 => ff_rxdata_ch2(15),\r
+ FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1),\r
+ FF_RX_D_2_21 => ff_disp_err_ch2(1),\r
+ FF_RX_D_2_22 => ff_cv_ch2(1),\r
+ FF_RX_D_2_23 => ff_rx_even_ch2(1),\r
+ FFC_RRST_2 => ffc_rrst_ch2,\r
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_2 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,\r
+ FFC_SB_INV_RX_2 => fpsc_vlo,\r
+ FFC_PCIE_CT_2 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_2 => fpsc_vlo,\r
+ FFS_PCIE_DONE_2 => open,\r
+ FFS_PCIE_CON_2 => open,\r
+ FFC_EI_EN_2 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2,\r
+ FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2,\r
+ FFC_TXPWDNB_2 => ffc_txpwdnb_ch2,\r
+ FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2,\r
+ FFS_RLOS_LO_2 => ffs_rlos_lo_ch2,\r
+ FFS_LS_SYNC_STATUS_2 => ffs_ls_sync_status_ch2,\r
+ FFS_CC_UNDERRUN_2 => ffs_cc_underrun_ch2,\r
+ FFS_CC_OVERRUN_2 => ffs_cc_overrun_ch2,\r
+ FFS_RXFBFIFO_ERROR_2 => ffs_rxfbfifo_error_ch2,\r
+ FFS_TXFBFIFO_ERROR_2 => ffs_txfbfifo_error_ch2,\r
+ FFS_RLOL_2 => ffs_rlol_ch2,\r
+ OOB_OUT_2 => oob_out_ch2,\r
+ HDINP3 => fpsc_vlo,\r
+ HDINN3 => fpsc_vlo,\r
+ HDOUTP3 => open,\r
+ HDOUTN3 => open,\r
+ SCISELCH3 => fpsc_vlo,\r
+ SCIENCH3 => fpsc_vlo,\r
+ FF_RXI_CLK_3 => fpsc_vlo,\r
+ FF_TXI_CLK_3 => fpsc_vlo,\r
+ FF_EBRD_CLK_3 => fpsc_vlo,\r
+ FF_RX_F_CLK_3 => open,\r
+ FF_RX_H_CLK_3 => open,\r
+ FF_RX_Q_CLK_3 => open,\r
+ FF_TX_D_3_0 => fpsc_vlo,\r
+ FF_TX_D_3_1 => fpsc_vlo,\r
+ FF_TX_D_3_2 => fpsc_vlo,\r
+ FF_TX_D_3_3 => fpsc_vlo,\r
+ FF_TX_D_3_4 => fpsc_vlo,\r
+ FF_TX_D_3_5 => fpsc_vlo,\r
+ FF_TX_D_3_6 => fpsc_vlo,\r
+ FF_TX_D_3_7 => fpsc_vlo,\r
+ FF_TX_D_3_8 => fpsc_vlo,\r
+ FF_TX_D_3_9 => fpsc_vlo,\r
+ FF_TX_D_3_10 => fpsc_vlo,\r
+ FF_TX_D_3_11 => fpsc_vlo,\r
+ FF_TX_D_3_12 => fpsc_vlo,\r
+ FF_TX_D_3_13 => fpsc_vlo,\r
+ FF_TX_D_3_14 => fpsc_vlo,\r
+ FF_TX_D_3_15 => fpsc_vlo,\r
+ FF_TX_D_3_16 => fpsc_vlo,\r
+ FF_TX_D_3_17 => fpsc_vlo,\r
+ FF_TX_D_3_18 => fpsc_vlo,\r
+ FF_TX_D_3_19 => fpsc_vlo,\r
+ FF_TX_D_3_20 => fpsc_vlo,\r
+ FF_TX_D_3_21 => fpsc_vlo,\r
+ FF_TX_D_3_22 => fpsc_vlo,\r
+ FF_TX_D_3_23 => fpsc_vlo,\r
+ FF_RX_D_3_0 => open,\r
+ FF_RX_D_3_1 => open,\r
+ FF_RX_D_3_2 => open,\r
+ FF_RX_D_3_3 => open,\r
+ FF_RX_D_3_4 => open,\r
+ FF_RX_D_3_5 => open,\r
+ FF_RX_D_3_6 => open,\r
+ FF_RX_D_3_7 => open,\r
+ FF_RX_D_3_8 => open,\r
+ FF_RX_D_3_9 => open,\r
+ FF_RX_D_3_10 => open,\r
+ FF_RX_D_3_11 => open,\r
+ FF_RX_D_3_12 => open,\r
+ FF_RX_D_3_13 => open,\r
+ FF_RX_D_3_14 => open,\r
+ FF_RX_D_3_15 => open,\r
+ FF_RX_D_3_16 => open,\r
+ FF_RX_D_3_17 => open,\r
+ FF_RX_D_3_18 => open,\r
+ FF_RX_D_3_19 => open,\r
+ FF_RX_D_3_20 => open,\r
+ FF_RX_D_3_21 => open,\r
+ FF_RX_D_3_22 => open,\r
+ FF_RX_D_3_23 => open,\r
+ FFC_RRST_3 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,\r
+ FFC_SB_INV_RX_3 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_3 => fpsc_vlo,\r
+ FFC_PCIE_CT_3 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_3 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,\r
+ FFC_EI_EN_3 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_3 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_3 => fpsc_vlo,\r
+ FFC_TXPWDNB_3 => fpsc_vlo,\r
+ FFC_RXPWDNB_3 => fpsc_vlo,\r
+ FFS_RLOS_LO_3 => open,\r
+ FFS_PCIE_DONE_3 => open,\r
+ FFS_PCIE_CON_3 => open,\r
+ FFS_LS_SYNC_STATUS_3 => open,\r
+ FFS_CC_UNDERRUN_3 => open,\r
+ FFS_CC_OVERRUN_3 => open,\r
+ FFS_RLOL_3 => open,\r
+ FFS_RXFBFIFO_ERROR_3 => open,\r
+ FFS_TXFBFIFO_ERROR_3 => open,\r
+ OOB_OUT_3 => open,\r
+ SCIWDATA0 => fpsc_vlo,\r
+ SCIWDATA1 => fpsc_vlo,\r
+ SCIWDATA2 => fpsc_vlo,\r
+ SCIWDATA3 => fpsc_vlo,\r
+ SCIWDATA4 => fpsc_vlo,\r
+ SCIWDATA5 => fpsc_vlo,\r
+ SCIWDATA6 => fpsc_vlo,\r
+ SCIWDATA7 => fpsc_vlo,\r
+ SCIADDR0 => fpsc_vlo,\r
+ SCIADDR1 => fpsc_vlo,\r
+ SCIADDR2 => fpsc_vlo,\r
+ SCIADDR3 => fpsc_vlo,\r
+ SCIADDR4 => fpsc_vlo,\r
+ SCIADDR5 => fpsc_vlo,\r
+ SCIRDATA0 => open,\r
+ SCIRDATA1 => open,\r
+ SCIRDATA2 => open,\r
+ SCIRDATA3 => open,\r
+ SCIRDATA4 => open,\r
+ SCIRDATA5 => open,\r
+ SCIRDATA6 => open,\r
+ SCIRDATA7 => open,\r
+ SCIENAUX => fpsc_vlo,\r
+ SCISELAUX => fpsc_vlo,\r
+ SCIRD => fpsc_vlo,\r
+ SCIWSTN => fpsc_vlo,\r
+ CYAWSTN => fpsc_vlo,\r
+ SCIINT => open,\r
+ FFC_MACRO_RST => ffc_macro_rst,\r
+ FFC_QUAD_RST => ffc_quad_rst,\r
+ FFC_TRST => ffc_trst,\r
+ FF_TX_F_CLK => ff_txfullclk,\r
+ FF_TX_H_CLK => ff_txhalfclk,\r
+ FF_TX_Q_CLK => open,\r
+ REFCK2CORE => refck2core,\r
+ CIN0 => cin(0),\r
+ CIN1 => cin(1),\r
+ CIN2 => cin(2),\r
+ CIN3 => cin(3),\r
+ CIN4 => cin(4),\r
+ CIN5 => cin(5),\r
+ CIN6 => cin(6),\r
+ CIN7 => cin(7),\r
+ CIN8 => cin(8),\r
+ CIN9 => cin(9),\r
+ CIN10 => cin(10),\r
+ CIN11 => cin(11),\r
+ COUT0 => cout(0),\r
+ COUT1 => cout(1),\r
+ COUT2 => cout(2),\r
+ COUT3 => cout(3),\r
+ COUT4 => cout(4),\r
+ COUT5 => cout(5),\r
+ COUT6 => cout(6),\r
+ COUT7 => cout(7),\r
+ COUT8 => cout(8),\r
+ COUT9 => cout(9),\r
+ COUT10 => cout(10),\r
+ COUT11 => cout(11),\r
+ COUT12 => cout(12),\r
+ COUT13 => cout(13),\r
+ COUT14 => cout(14),\r
+ COUT15 => cout(15),\r
+ COUT16 => cout(16),\r
+ COUT17 => cout(17),\r
+ COUT18 => cout(18),\r
+ COUT19 => cout(19),\r
+ FFS_PLOL => ffs_plol);\r
+\r
+--synopsys translate_off\r
+file_read : PROCESS\r
+VARIABLE open_status : file_open_status;\r
+FILE config : text;\r
+BEGIN\r
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
+ IF (open_status = name_error) THEN\r
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
+ severity ERROR;\r
+ END IF;\r
+ wait;\r
+END PROCESS;\r
+--synopsys translate_on\r
+\r
+end serdes_gbe_2_arch ;\r
--- /dev/null
+MODULE serdes_gbe_2\r
--- /dev/null
+[Device]\r
+Family=latticeecp2m\r
+PartType=LFE2M100E\r
+PartName=LFE2M100E-6F900C\r
+SpeedGrade=-6\r
+Package=FPBGA900\r
+OperatingCondition=COM\r
+Status=P\r
+\r
+[IP]\r
+VendorName=Lattice Semiconductor Corporation\r
+CoreType=LPM\r
+CoreStatus=Demo\r
+CoreName=PCS\r
+CoreRevision=7.0\r
+ModuleName=serdes_gbe_2\r
+SourceFormat=VHDL\r
+ParameterFileVersion=1.0\r
+Date=07/30/2009\r
+Time=14:05:48\r
+\r
+[Parameters]\r
+Verilog=0\r
+VHDL=1\r
+EDIF=1\r
+Destination=Synplicity\r
+Expression=BusA(0 to 7)\r
+Order=Big Endian [MSB:LSB]\r
+IO=0\r
+Protocol=Quad\r
+mode=Gigabit Ethernet\r
+Channel0=SINGLE\r
+Channel1=SINGLE\r
+Channel2=SINGLE\r
+Channel3=SINGLE\r
+Rate0=None\r
+Rate1=None\r
+Rate2=None\r
+Rate3=None\r
+TxRefClk=CORE_TXREFCLK\r
+RxRefClk=CORE_RXREFCLK\r
+ClkRate=2.0\r
+ClkMult=20X\r
+CalClkRate=100.0\r
+DataWidth=16\r
+FPGAClkRate=100.0\r
+TxRefClkCM=REFCLK\r
+RxRefClk0CM=REFCLK\r
+RxRefClk1CM=REFCLK\r
+RxRefClk2CM=REFCLK\r
+RxRefClk3CM=REFCLK\r
+ClkRateH=1.0\r
+ClkMultH=20XH\r
+CalClkRateH=100.0\r
+DataWidthH=8\r
+FPGAClkRateH=100.0\r
+VCh0=0\r
+VCh1=0\r
+VCh2=0\r
+VCh3=0\r
+PreCh0=DISABLE\r
+PreCh1=DISABLE\r
+PreCh2=DISABLE\r
+PreCh3=DISABLE\r
+TxCh0=50\r
+TxCh1=50\r
+TxCh2=50\r
+TxCh3=50\r
+EqCh0=DISABLE\r
+EqCh1=DISABLE\r
+EqCh2=DISABLE\r
+EqCh3=DISABLE\r
+RxTermCh0=50\r
+RxTermCh1=50\r
+RxTermCh2=50\r
+RxTermCh3=50\r
+RxCoupCh0=DC\r
+RxCoupCh1=DC\r
+RxCoupCh2=DC\r
+RxCoupCh3=DC\r
+Loss=0\r
+CDRLoss=0\r
+TxTerm=50\r
+TxCoup=AC\r
+TxPllLoss=0\r
+TxInvCh0=NORMAL\r
+TxInvCh1=NORMAL\r
+TxInvCh2=NORMAL\r
+TxInvCh3=NORMAL\r
+RxInvCh0=NORMAL\r
+RxInvCh1=NORMAL\r
+RxInvCh2=NORMAL\r
+RxInvCh3=NORMAL\r
+RxModeCh0=NORMAL\r
+RxModeCh1=NORMAL\r
+RxModeCh2=NORMAL\r
+RxModeCh3=NORMAL\r
+Plus=1100000101\r
+Minus=0011111010\r
+Mask=1111111111\r
+Align=AUTO\r
+CTCCh0=NORMAL\r
+CTCCh1=NORMAL\r
+CTCCh2=NORMAL\r
+CTCCh3=NORMAL\r
+CC_MATCH1=0000000000\r
+CC_MATCH2=0000000000\r
+CC_MATCH3=0110111100\r
+CC_MATCH4=0001010000\r
+MinIPG=3\r
+High=9\r
+Low=7\r
+CC_MATCH_MODE=MATCH_3_4\r
+RxDataCh0=FALSE\r
+RxDataCh1=FALSE\r
+RxDataCh2=FALSE\r
+RxDataCh3=FALSE\r
+AlignerCh0=FALSE\r
+AlignerCh1=FALSE\r
+AlignerCh2=FALSE\r
+AlignerCh3=FALSE\r
+DetectCh0=FALSE\r
+DetectCh1=FALSE\r
+DetectCh2=FALSE\r
+DetectCh3=FALSE\r
+ELSMCh0=FALSE\r
+ELSMCh1=FALSE\r
+ELSMCh2=FALSE\r
+ELSMCh3=FALSE\r
+_teidleCh0=FALSE\r
+_teidleCh1=FALSE\r
+_teidleCh2=FALSE\r
+_teidleCh3=FALSE\r
+Ports0=FALSE\r
+rdoPorts0=Serial Loopback\r
+Ports1=TRUE\r
+Ports2=TRUE\r
+Ports3=FALSE\r
+Ports3_1=FALSE\r
+Ports4=FALSE\r
--- /dev/null
+#define _device_name "LFE2M100E"\r
+#define _protocol_mode "Quad Based Protocol Mode"\r
+#define _protocol "GIGE" \r
+#define _ch0_mode "SINGLE" \r
+#define _ch1_mode "SINGLE" \r
+#define _ch2_mode "SINGLE" \r
+#define _ch3_mode "SINGLE" \r
+#define _pll_txsrc "CORE_TXREFCLK" \r
+#define _pll_rxsrc "CORE_RXREFCLK" \r
+#define _datarange "MEDHIGH" \r
+#define _refclk_mult "20X" \r
+#define _refclk_rate 100.0\r
+#define _data_width "16" \r
+#define _fpgaintclk_rate 100.0\r
+#define _ch0_tdrv_amp "0" \r
+#define _ch1_tdrv_amp "0" \r
+#define _ch2_tdrv_amp "0" \r
+#define _ch3_tdrv_amp "0" \r
+#define _ch0_tx_pre "DISABLE" \r
+#define _ch1_tx_pre "DISABLE" \r
+#define _ch2_tx_pre "DISABLE" \r
+#define _ch3_tx_pre "DISABLE" \r
+#define _ch0_rterm_tx "50" \r
+#define _ch1_rterm_tx "50" \r
+#define _ch2_rterm_tx "50" \r
+#define _ch3_rterm_tx "50" \r
+#define _ch0_rx_eq "DISABLE" \r
+#define _ch1_rx_eq "DISABLE" \r
+#define _ch2_rx_eq "DISABLE" \r
+#define _ch3_rx_eq "DISABLE" \r
+#define _ch0_rterm_rx "50" \r
+#define _ch1_rterm_rx "50" \r
+#define _ch2_rterm_rx "50" \r
+#define _ch3_rterm_rx "50" \r
+#define _ch0_rx_dcc "DC" \r
+#define _ch1_rx_dcc "DC" \r
+#define _ch2_rx_dcc "DC" \r
+#define _ch3_rx_dcc "DC" \r
+#define _los_threshold "0" \r
+#define _pll_term "50" \r
+#define _pll_dcc "AC" \r
+#define _pll_lol_set "0" \r
+#define _ch0_tx_sb "NORMAL" \r
+#define _ch1_tx_sb "NORMAL" \r
+#define _ch2_tx_sb "NORMAL" \r
+#define _ch3_tx_sb "NORMAL" \r
+#define _ch0_rx_sb "NORMAL" \r
+#define _ch1_rx_sb "NORMAL" \r
+#define _ch2_rx_sb "NORMAL" \r
+#define _ch3_rx_sb "NORMAL" \r
+#define _ch0_8b10b "NORMAL" \r
+#define _ch1_8b10b "NORMAL" \r
+#define _ch2_8b10b "NORMAL" \r
+#define _ch3_8b10b "NORMAL" \r
+#define _comma_a "1100000101" \r
+#define _comma_b "0011111010" \r
+#define _comma_m "1111111111" \r
+#define _comma_align "AUTO" \r
+#define _ch0_ctc_byp "NORMAL" \r
+#define _ch1_ctc_byp "NORMAL" \r
+#define _ch2_ctc_byp "NORMAL" \r
+#define _ch3_ctc_byp "NORMAL" \r
+#define _cc_match1 "0000000000" \r
+#define _cc_match2 "0000000000" \r
+#define _cc_match3 "0110111100" \r
+#define _cc_match4 "0001010000" \r
+#define _cc_match_mode "MATCH_3_4" \r
+#define _cc_min_ipg "3" \r
+#define _cchmark "9" \r
+#define _cclmark "7" \r
+#define _ch0_ird "FALSE" \r
+#define _ch1_ird "FALSE" \r
+#define _ch2_ird "FALSE" \r
+#define _ch3_ird "FALSE" \r
+#define _ch0_elsm "FALSE" \r
+#define _ch1_elsm "FALSE" \r
+#define _ch2_elsm "FALSE" \r
+#define _ch3_elsm "FALSE" \r
+#define _ch0_teidle "FALSE"\r
+#define _ch1_teidle "FALSE"\r
+#define _ch2_teidle "FALSE"\r
+#define _ch3_teidle "FALSE"\r
+#define _loopback "FALSE" \r
+#define _lbtype "Serial Loopback"\r
+#define _refck2core "TRUE" \r
+#define _pllqclkports "FALSE"\r
+#define _sci_ports "FALSE" \r
+#define _sci_int_port "FALSE" \r
+#define _errsports "TRUE" \r
+\r
+#define _circuit_name serdes_gbe_2\r
+#define _lang vhdl\r
+\r
+#include <pcs/PCSC.vhd>\r
+#include <pcs/pcsc_cfg.txt>\r
--- /dev/null
+\r
+ TOOL: orcapp \r
+ DATE: 19-MAR-2008 13:11:51 \r
+ TITLE: Lattice Semiconductor Corporation\r
+ MODULE: serdes_gbe_2\r
+ DESIGN: serdes_gbe_2\r
+ FILENAME: serdes_gbe_2.readme\r
+ PROJECT: Unknown\r
+ VERSION: 2.0\r
+ This file is auto generated by the ispLEVER\r
+\r
+\r
+NOTE: This readme file has been provided to instantiate the interface\r
+netlist. Since this template contains synthesis attributes for precision that\r
+are crucial to the design flow, we recommend that you use this\r
+template in your FPGA design.\r
+entity chip is\r
+port (\r
+\r
+-- Add your FPGA design top level I/Os here\r
+\r
+\r
+-- ASIC side pins for PCSA. These pins must exist for the\r
+-- PCS core.\r
+ refclkp : in std_logic;\r
+ refclkn : in std_logic;\r
+ hdinp0 : in std_logic;\r
+ hdinn0 : in std_logic;\r
+ hdinp1 : in std_logic;\r
+ hdinn1 : in std_logic;\r
+ hdinp2 : in std_logic;\r
+ hdinn2 : in std_logic;\r
+ hdinp3 : in std_logic;\r
+ hdinn3 : in std_logic;\r
+\r
+ hdoutp0 : out std_logic;\r
+ hdoutn0 : out std_logic;\r
+ hdoutp1 : out std_logic;\r
+ hdoutn1 : out std_logic;\r
+ hdoutp2 : out std_logic;\r
+ hdoutn2 : out std_logic;\r
+ hdoutp3 : out std_logic;\r
+ hdoutn3 : out std_logic;\r
+\r
+\r
+);\r
+end chip;\r
+\r
+architecture chip_arch of chip is\r
+\r
+-- This defines all the high-speed ports. You may have to remove\r
+-- some of them depending on your design.\r
+attribute nopad : string;\r
+attribute nopad of\r
+ refclkp, refclkn,\r
+ hdinp0, hdinn0, hdinp1, hdinn1,\r
+ hdinp2, hdinn2, hdinp3, hdinn3,\r
+ hdoutp0, hdoutn0, hdoutp1, hdoutn1,\r
+ hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";\r
+\r
+ COMPONENT serdes_gbe_2\r
+ PORT(\r
+ core_txrefclk : IN std_logic;\r
+ core_rxrefclk : IN std_logic;\r
+ hdinp0 : IN std_logic;\r
+ hdinn0 : IN std_logic;\r
+ ff_rxiclk_ch0 : IN std_logic;\r
+ ff_txiclk_ch0 : IN std_logic;\r
+ ff_ebrd_clk_0 : IN std_logic;\r
+ ff_txdata_ch0 : IN std_logic_vector(15 downto 0);\r
+ ff_tx_k_cntrl_ch0 : IN std_logic_vector(1 downto 0);\r
+ ff_xmit_ch0 : IN std_logic_vector(1 downto 0);\r
+ ff_correct_disp_ch0 : IN std_logic_vector(1 downto 0);\r
+ ffc_rrst_ch0 : IN std_logic;\r
+ ffc_lane_tx_rst_ch0 : IN std_logic;\r
+ ffc_lane_rx_rst_ch0 : IN std_logic;\r
+ ffc_txpwdnb_ch0 : IN std_logic;\r
+ ffc_rxpwdnb_ch0 : IN std_logic;\r
+ hdinp1 : IN std_logic;\r
+ hdinn1 : IN std_logic;\r
+ ff_rxiclk_ch1 : IN std_logic;\r
+ ff_txiclk_ch1 : IN std_logic;\r
+ ff_ebrd_clk_1 : IN std_logic;\r
+ ff_txdata_ch1 : IN std_logic_vector(15 downto 0);\r
+ ff_tx_k_cntrl_ch1 : IN std_logic_vector(1 downto 0);\r
+ ff_xmit_ch1 : IN std_logic_vector(1 downto 0);\r
+ ff_correct_disp_ch1 : IN std_logic_vector(1 downto 0);\r
+ ffc_rrst_ch1 : IN std_logic;\r
+ ffc_lane_tx_rst_ch1 : IN std_logic;\r
+ ffc_lane_rx_rst_ch1 : IN std_logic;\r
+ ffc_txpwdnb_ch1 : IN std_logic;\r
+ ffc_rxpwdnb_ch1 : IN std_logic;\r
+ hdinp2 : IN std_logic;\r
+ hdinn2 : IN std_logic;\r
+ ff_rxiclk_ch2 : IN std_logic;\r
+ ff_txiclk_ch2 : IN std_logic;\r
+ ff_ebrd_clk_2 : IN std_logic;\r
+ ff_txdata_ch2 : IN std_logic_vector(15 downto 0);\r
+ ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0);\r
+ ff_xmit_ch2 : IN std_logic_vector(1 downto 0);\r
+ ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0);\r
+ ffc_rrst_ch2 : IN std_logic;\r
+ ffc_lane_tx_rst_ch2 : IN std_logic;\r
+ ffc_lane_rx_rst_ch2 : IN std_logic;\r
+ ffc_txpwdnb_ch2 : IN std_logic;\r
+ ffc_rxpwdnb_ch2 : IN std_logic;\r
+ hdinp3 : IN std_logic;\r
+ hdinn3 : IN std_logic;\r
+ ff_rxiclk_ch3 : IN std_logic;\r
+ ff_txiclk_ch3 : IN std_logic;\r
+ ff_ebrd_clk_3 : IN std_logic;\r
+ ff_txdata_ch3 : IN std_logic_vector(15 downto 0);\r
+ ff_tx_k_cntrl_ch3 : IN std_logic_vector(1 downto 0);\r
+ ff_xmit_ch3 : IN std_logic_vector(1 downto 0);\r
+ ff_correct_disp_ch3 : IN std_logic_vector(1 downto 0);\r
+ ffc_rrst_ch3 : IN std_logic;\r
+ ffc_lane_tx_rst_ch3 : IN std_logic;\r
+ ffc_lane_rx_rst_ch3 : IN std_logic;\r
+ ffc_txpwdnb_ch3 : IN std_logic;\r
+ ffc_rxpwdnb_ch3 : IN std_logic;\r
+ ffc_macro_rst : IN std_logic;\r
+ ffc_quad_rst : IN std_logic;\r
+ ffc_trst : IN std_logic; \r
+ hdoutp0 : OUT std_logic;\r
+ hdoutn0 : OUT std_logic;\r
+ ff_rxdata_ch0 : OUT std_logic_vector(15 downto 0);\r
+ ff_rx_k_cntrl_ch0 : OUT std_logic_vector(1 downto 0);\r
+ ff_rxfullclk_ch0 : OUT std_logic;\r
+ ff_rxhalfclk_ch0 : OUT std_logic;\r
+ ff_disp_err_ch0 : OUT std_logic_vector(1 downto 0);\r
+ ff_cv_ch0 : OUT std_logic_vector(1 downto 0);\r
+ ff_rx_even_ch0 : OUT std_logic_vector(1 downto 0);\r
+ ffs_rlos_lo_ch0 : OUT std_logic;\r
+ ffs_ls_sync_status_ch0 : OUT std_logic;\r
+ ffs_cc_underrun_ch0 : OUT std_logic;\r
+ ffs_cc_overrun_ch0 : OUT std_logic;\r
+ ffs_txfbfifo_error_ch0 : OUT std_logic;\r
+ ffs_rxfbfifo_error_ch0 : OUT std_logic;\r
+ ffs_rlol_ch0 : OUT std_logic;\r
+ oob_out_ch0 : OUT std_logic;\r
+ hdoutp1 : OUT std_logic;\r
+ hdoutn1 : OUT std_logic;\r
+ ff_rxdata_ch1 : OUT std_logic_vector(15 downto 0);\r
+ ff_rx_k_cntrl_ch1 : OUT std_logic_vector(1 downto 0);\r
+ ff_rxfullclk_ch1 : OUT std_logic;\r
+ ff_rxhalfclk_ch1 : OUT std_logic;\r
+ ff_disp_err_ch1 : OUT std_logic_vector(1 downto 0);\r
+ ff_cv_ch1 : OUT std_logic_vector(1 downto 0);\r
+ ff_rx_even_ch1 : OUT std_logic_vector(1 downto 0);\r
+ ffs_rlos_lo_ch1 : OUT std_logic;\r
+ ffs_ls_sync_status_ch1 : OUT std_logic;\r
+ ffs_cc_underrun_ch1 : OUT std_logic;\r
+ ffs_cc_overrun_ch1 : OUT std_logic;\r
+ ffs_txfbfifo_error_ch1 : OUT std_logic;\r
+ ffs_rxfbfifo_error_ch1 : OUT std_logic;\r
+ ffs_rlol_ch1 : OUT std_logic;\r
+ oob_out_ch1 : OUT std_logic;\r
+ hdoutp2 : OUT std_logic;\r
+ hdoutn2 : OUT std_logic;\r
+ ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0);\r
+ ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_rxfullclk_ch2 : OUT std_logic;\r
+ ff_rxhalfclk_ch2 : OUT std_logic;\r
+ ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_cv_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0);\r
+ ffs_rlos_lo_ch2 : OUT std_logic;\r
+ ffs_ls_sync_status_ch2 : OUT std_logic;\r
+ ffs_cc_underrun_ch2 : OUT std_logic;\r
+ ffs_cc_overrun_ch2 : OUT std_logic;\r
+ ffs_txfbfifo_error_ch2 : OUT std_logic;\r
+ ffs_rxfbfifo_error_ch2 : OUT std_logic;\r
+ ffs_rlol_ch2 : OUT std_logic;\r
+ oob_out_ch2 : OUT std_logic;\r
+ hdoutp3 : OUT std_logic;\r
+ hdoutn3 : OUT std_logic;\r
+ ff_rxdata_ch3 : OUT std_logic_vector(15 downto 0);\r
+ ff_rx_k_cntrl_ch3 : OUT std_logic_vector(1 downto 0);\r
+ ff_rxfullclk_ch3 : OUT std_logic;\r
+ ff_rxhalfclk_ch3 : OUT std_logic;\r
+ ff_disp_err_ch3 : OUT std_logic_vector(1 downto 0);\r
+ ff_cv_ch3 : OUT std_logic_vector(1 downto 0);\r
+ ff_rx_even_ch3 : OUT std_logic_vector(1 downto 0);\r
+ ffs_rlos_lo_ch3 : OUT std_logic;\r
+ ffs_ls_sync_status_ch3 : OUT std_logic;\r
+ ffs_cc_underrun_ch3 : OUT std_logic;\r
+ ffs_cc_overrun_ch3 : OUT std_logic;\r
+ ffs_txfbfifo_error_ch3 : OUT std_logic;\r
+ ffs_rxfbfifo_error_ch3 : OUT std_logic;\r
+ ffs_rlol_ch3 : OUT std_logic;\r
+ oob_out_ch3 : OUT std_logic;\r
+ ff_txfullclk : OUT std_logic;\r
+ ff_txhalfclk : OUT std_logic;\r
+ refck2core : OUT std_logic;\r
+ ffs_plol : OUT std_logic\r
+ );\r
+ END COMPONENT;\r
+\r
+\r
+\r
+ uut: serdes_gbe_2 PORT MAP(\r
+ core_txrefclk => core_txrefclk,\r
+ core_rxrefclk => core_rxrefclk,\r
+ hdinp0 => hdinp0,\r
+ hdinn0 => hdinn0,\r
+ hdoutp0 => hdoutp0,\r
+ hdoutn0 => hdoutn0,\r
+ ff_rxiclk_ch0 => ff_rxiclk_ch0,\r
+ ff_txiclk_ch0 => ff_txiclk_ch0,\r
+ ff_ebrd_clk_0 => ff_ebrd_clk_0,\r
+ ff_txdata_ch0 => ff_txdata_ch0,\r
+ ff_rxdata_ch0 => ff_rxdata_ch0,\r
+ ff_tx_k_cntrl_ch0 => ff_tx_k_cntrl_ch0,\r
+ ff_rx_k_cntrl_ch0 => ff_rx_k_cntrl_ch0,\r
+ ff_rxfullclk_ch0 => ff_rxfullclk_ch0,\r
+ ff_rxhalfclk_ch0 => ff_rxhalfclk_ch0,\r
+ ff_xmit_ch0 => ff_xmit_ch0,\r
+ ff_correct_disp_ch0 => ff_correct_disp_ch0,\r
+ ff_disp_err_ch0 => ff_disp_err_ch0,\r
+ ff_cv_ch0 => ff_cv_ch0,\r
+ ff_rx_even_ch0 => ff_rx_even_ch0,\r
+ ffc_rrst_ch0 => ffc_rrst_ch0,\r
+ ffc_lane_tx_rst_ch0 => ffc_lane_tx_rst_ch0,\r
+ ffc_lane_rx_rst_ch0 => ffc_lane_rx_rst_ch0,\r
+ ffc_txpwdnb_ch0 => ffc_txpwdnb_ch0,\r
+ ffc_rxpwdnb_ch0 => ffc_rxpwdnb_ch0,\r
+ ffs_rlos_lo_ch0 => ffs_rlos_lo_ch0,\r
+ ffs_ls_sync_status_ch0 => ffs_ls_sync_status_ch0,\r
+ ffs_cc_underrun_ch0 => ffs_cc_underrun_ch0,\r
+ ffs_cc_overrun_ch0 => ffs_cc_overrun_ch0,\r
+ ffs_txfbfifo_error_ch0 => ffs_txfbfifo_error_ch0,\r
+ ffs_rxfbfifo_error_ch0 => ffs_rxfbfifo_error_ch0,\r
+ ffs_rlol_ch0 => ffs_rlol_ch0,\r
+ oob_out_ch0 => oob_out_ch0,\r
+ hdinp1 => hdinp1,\r
+ hdinn1 => hdinn1,\r
+ hdoutp1 => hdoutp1,\r
+ hdoutn1 => hdoutn1,\r
+ ff_rxiclk_ch1 => ff_rxiclk_ch1,\r
+ ff_txiclk_ch1 => ff_txiclk_ch1,\r
+ ff_ebrd_clk_1 => ff_ebrd_clk_1,\r
+ ff_txdata_ch1 => ff_txdata_ch1,\r
+ ff_rxdata_ch1 => ff_rxdata_ch1,\r
+ ff_tx_k_cntrl_ch1 => ff_tx_k_cntrl_ch1,\r
+ ff_rx_k_cntrl_ch1 => ff_rx_k_cntrl_ch1,\r
+ ff_rxfullclk_ch1 => ff_rxfullclk_ch1,\r
+ ff_rxhalfclk_ch1 => ff_rxhalfclk_ch1,\r
+ ff_xmit_ch1 => ff_xmit_ch1,\r
+ ff_correct_disp_ch1 => ff_correct_disp_ch1,\r
+ ff_disp_err_ch1 => ff_disp_err_ch1,\r
+ ff_cv_ch1 => ff_cv_ch1,\r
+ ff_rx_even_ch1 => ff_rx_even_ch1,\r
+ ffc_rrst_ch1 => ffc_rrst_ch1,\r
+ ffc_lane_tx_rst_ch1 => ffc_lane_tx_rst_ch1,\r
+ ffc_lane_rx_rst_ch1 => ffc_lane_rx_rst_ch1,\r
+ ffc_txpwdnb_ch1 => ffc_txpwdnb_ch1,\r
+ ffc_rxpwdnb_ch1 => ffc_rxpwdnb_ch1,\r
+ ffs_rlos_lo_ch1 => ffs_rlos_lo_ch1,\r
+ ffs_ls_sync_status_ch1 => ffs_ls_sync_status_ch1,\r
+ ffs_cc_underrun_ch1 => ffs_cc_underrun_ch1,\r
+ ffs_cc_overrun_ch1 => ffs_cc_overrun_ch1,\r
+ ffs_txfbfifo_error_ch1 => ffs_txfbfifo_error_ch1,\r
+ ffs_rxfbfifo_error_ch1 => ffs_rxfbfifo_error_ch1,\r
+ ffs_rlol_ch1 => ffs_rlol_ch1,\r
+ oob_out_ch1 => oob_out_ch1,\r
+ hdinp2 => hdinp2,\r
+ hdinn2 => hdinn2,\r
+ hdoutp2 => hdoutp2,\r
+ hdoutn2 => hdoutn2,\r
+ ff_rxiclk_ch2 => ff_rxiclk_ch2,\r
+ ff_txiclk_ch2 => ff_txiclk_ch2,\r
+ ff_ebrd_clk_2 => ff_ebrd_clk_2,\r
+ ff_txdata_ch2 => ff_txdata_ch2,\r
+ ff_rxdata_ch2 => ff_rxdata_ch2,\r
+ ff_tx_k_cntrl_ch2 => ff_tx_k_cntrl_ch2,\r
+ ff_rx_k_cntrl_ch2 => ff_rx_k_cntrl_ch2,\r
+ ff_rxfullclk_ch2 => ff_rxfullclk_ch2,\r
+ ff_rxhalfclk_ch2 => ff_rxhalfclk_ch2,\r
+ ff_xmit_ch2 => ff_xmit_ch2,\r
+ ff_correct_disp_ch2 => ff_correct_disp_ch2,\r
+ ff_disp_err_ch2 => ff_disp_err_ch2,\r
+ ff_cv_ch2 => ff_cv_ch2,\r
+ ff_rx_even_ch2 => ff_rx_even_ch2,\r
+ ffc_rrst_ch2 => ffc_rrst_ch2,\r
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2,\r
+ ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2,\r
+ ffc_txpwdnb_ch2 => ffc_txpwdnb_ch2,\r
+ ffc_rxpwdnb_ch2 => ffc_rxpwdnb_ch2,\r
+ ffs_rlos_lo_ch2 => ffs_rlos_lo_ch2,\r
+ ffs_ls_sync_status_ch2 => ffs_ls_sync_status_ch2,\r
+ ffs_cc_underrun_ch2 => ffs_cc_underrun_ch2,\r
+ ffs_cc_overrun_ch2 => ffs_cc_overrun_ch2,\r
+ ffs_txfbfifo_error_ch2 => ffs_txfbfifo_error_ch2,\r
+ ffs_rxfbfifo_error_ch2 => ffs_rxfbfifo_error_ch2,\r
+ ffs_rlol_ch2 => ffs_rlol_ch2,\r
+ oob_out_ch2 => oob_out_ch2,\r
+ hdinp3 => hdinp3,\r
+ hdinn3 => hdinn3,\r
+ hdoutp3 => hdoutp3,\r
+ hdoutn3 => hdoutn3,\r
+ ff_rxiclk_ch3 => ff_rxiclk_ch3,\r
+ ff_txiclk_ch3 => ff_txiclk_ch3,\r
+ ff_ebrd_clk_3 => ff_ebrd_clk_3,\r
+ ff_txdata_ch3 => ff_txdata_ch3,\r
+ ff_rxdata_ch3 => ff_rxdata_ch3,\r
+ ff_tx_k_cntrl_ch3 => ff_tx_k_cntrl_ch3,\r
+ ff_rx_k_cntrl_ch3 => ff_rx_k_cntrl_ch3,\r
+ ff_rxfullclk_ch3 => ff_rxfullclk_ch3,\r
+ ff_rxhalfclk_ch3 => ff_rxhalfclk_ch3,\r
+ ff_xmit_ch3 => ff_xmit_ch3,\r
+ ff_correct_disp_ch3 => ff_correct_disp_ch3,\r
+ ff_disp_err_ch3 => ff_disp_err_ch3,\r
+ ff_cv_ch3 => ff_cv_ch3,\r
+ ff_rx_even_ch3 => ff_rx_even_ch3,\r
+ ffc_rrst_ch3 => ffc_rrst_ch3,\r
+ ffc_lane_tx_rst_ch3 => ffc_lane_tx_rst_ch3,\r
+ ffc_lane_rx_rst_ch3 => ffc_lane_rx_rst_ch3,\r
+ ffc_txpwdnb_ch3 => ffc_txpwdnb_ch3,\r
+ ffc_rxpwdnb_ch3 => ffc_rxpwdnb_ch3,\r
+ ffs_rlos_lo_ch3 => ffs_rlos_lo_ch3,\r
+ ffs_ls_sync_status_ch3 => ffs_ls_sync_status_ch3,\r
+ ffs_cc_underrun_ch3 => ffs_cc_underrun_ch3,\r
+ ffs_cc_overrun_ch3 => ffs_cc_overrun_ch3,\r
+ ffs_txfbfifo_error_ch3 => ffs_txfbfifo_error_ch3,\r
+ ffs_rxfbfifo_error_ch3 => ffs_rxfbfifo_error_ch3,\r
+ ffs_rlol_ch3 => ffs_rlol_ch3,\r
+ oob_out_ch3 => oob_out_ch3,\r
+ ffc_macro_rst => ffc_macro_rst,\r
+ ffc_quad_rst => ffc_quad_rst,\r
+ ffc_trst => ffc_trst,\r
+ ff_txfullclk => ff_txfullclk,\r
+ ff_txhalfclk => ff_txhalfclk,\r
+ refck2core => refck2core,\r
+ ffs_plol => ffs_plol\r
+ );\r
+\r
+\r
--- /dev/null
+@set suppresnewline=on@\r
+\r
+@comment --------------------------------------------------------------------- @\r
+@comment Template-drive TFI generator @\r
+@comment Template for TFI generation. @\r
+@comment --------------------------------------------------------------------- @\r
+\r
+@set suppresnewline=off@\r
+ TOOL: orcapp \r
+ DATE: 19-MAR-2008 13:11:51 \r
+ TITLE: %title%\r
+ MODULE: %module%\r
+ DESIGN: %module%\r
+ FILENAME: %filename%\r
+ PROJECT: %project%\r
+ VERSION: %ver%\r
+ This file is auto generated by the ispLEVER\r
+@set suppresnewline=on@\r
+\r
+@cr@\r
+@cr@\r
+\r
+@set sigdelim=@\r
+\r
+NOTE: This readme file has been provided to instantiate the interface@cr@\r
+netlist. Since this template contains synthesis attributes for precision that@cr@\r
+are crucial to the design flow, we recommend that you use this@cr@\r
+template in your FPGA design.@cr@\r
+entity chip is@cr@\r
+port (@cr@\r
+@cr@\r
+-- Add your FPGA design top level I/Os here@cr@\r
+@cr@\r
+@cr@\r
+-- ASIC side pins for PCSA. These pins must exist for the@cr@\r
+-- PCS core.@cr@\r
+ refclkp : in std_logic;@cr@\r
+ refclkn : in std_logic;@cr@\r
+ hdinp0 : in std_logic;@cr@\r
+ hdinn0 : in std_logic;@cr@\r
+ hdinp1 : in std_logic;@cr@\r
+ hdinn1 : in std_logic;@cr@\r
+ hdinp2 : in std_logic;@cr@\r
+ hdinn2 : in std_logic;@cr@\r
+ hdinp3 : in std_logic;@cr@\r
+ hdinn3 : in std_logic;@cr@\r
+@cr@\r
+ hdoutp0 : out std_logic;@cr@\r
+ hdoutn0 : out std_logic;@cr@\r
+ hdoutp1 : out std_logic;@cr@\r
+ hdoutn1 : out std_logic;@cr@\r
+ hdoutp2 : out std_logic;@cr@\r
+ hdoutn2 : out std_logic;@cr@\r
+ hdoutp3 : out std_logic;@cr@\r
+ hdoutn3 : out std_logic;@cr@\r
+@cr@\r
+@cr@\r
+);@cr@\r
+end chip;@cr@\r
+@cr@\r
+architecture chip_arch of chip is@cr@\r
+@cr@\r
+-- This defines all the high-speed ports. You may have to remove@cr@\r
+-- some of them depending on your design.@cr@\r
+attribute nopad : string;@cr@\r
+attribute nopad of@cr@\r
+ refclkp, refclkn,@cr@\r
+ hdinp0, hdinn0, hdinp1, hdinn1,@cr@\r
+ hdinp2, hdinn2, hdinp3, hdinn3,@cr@\r
+ hdoutp0, hdoutn0, hdoutp1, hdoutn1,@cr@\r
+ hdoutp2, hdoutn2, hdoutp3, hdoutn3 : signal is "true";@cr@\r
+\r
+@cr@\r
+@tab@COMPONENT %module%\r
+@set sigdelim=@\r
+@cr@@tab@PORT(\r
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@\r
+@ifhas oport=*@ @comment if the design has any output ports... @\r
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@\r
+ @set sigdelim=;@\r
+ @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@\r
+@endif@\r
+@ifnhas oport=*@ @comment we need an "else in this language! @\r
+ @set sigdelim=;@\r
+ @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@\r
+@endif@\r
+@cr@@tab@@tab@);@cr@\r
+@tab@END COMPONENT;@cr@@cr@\r
+@comment Now do a signal declaration for each port @\r
+\r
+@cr@@cr@\r
+@comment do the component instantiation @\r
+@set sigdelim=,@\r
+@tab@uut: %module% PORT MAP(\r
+@iterate@%port%\r
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@\r
+@cr@@tab@);@cr@@cr@\r
+@set suppresnewline=off@\r
--- /dev/null
+\r
+# This file is used by the simulation model as well as the ispLEVER bitstream\r
+# generation process to automatically initialize the PCSC quad to the mode\r
+# selected in the IPexpress. This file is expected to be modified by the\r
+# end user to adjust the PCSC quad to the final design requirements.\r
+\r
+DEVICE_NAME "LFE2M100E"\r
+PROTOCOL "GIGE" \r
+CH0_MODE "SINGLE" \r
+CH1_MODE "SINGLE" \r
+CH2_MODE "SINGLE" \r
+CH3_MODE "SINGLE" \r
+PLL_SRC "CORE_TXREFCLK" \r
+DATARANGE "MEDHIGH" \r
+CH0_CDR_SRC "CORE_RXREFCLK" \r
+CH1_CDR_SRC "CORE_RXREFCLK" \r
+CH2_CDR_SRC "CORE_RXREFCLK" \r
+CH3_CDR_SRC "CORE_RXREFCLK" \r
+CH0_DATA_WIDTH "16" \r
+CH1_DATA_WIDTH "16" \r
+CH2_DATA_WIDTH "16" \r
+CH3_DATA_WIDTH "16" \r
+CH0_REFCK_MULT "20X" \r
+CH1_REFCK_MULT "20X" \r
+CH2_REFCK_MULT "20X" \r
+CH3_REFCK_MULT "20X" \r
+#REFCLK_RATE 100.0\r
+#FPGAINTCLK_RATE 100.0\r
+CH0_TDRV_AMP "0" \r
+CH1_TDRV_AMP "0" \r
+CH2_TDRV_AMP "0" \r
+CH3_TDRV_AMP "0" \r
+CH0_TX_PRE "DISABLE" \r
+CH1_TX_PRE "DISABLE" \r
+CH2_TX_PRE "DISABLE" \r
+CH3_TX_PRE "DISABLE" \r
+CH0_RTERM_TX "50" \r
+CH1_RTERM_TX "50" \r
+CH2_RTERM_TX "50" \r
+CH3_RTERM_TX "50" \r
+CH0_RX_EQ "DISABLE" \r
+CH1_RX_EQ "DISABLE" \r
+CH2_RX_EQ "DISABLE" \r
+CH3_RX_EQ "DISABLE" \r
+CH0_RTERM_RX "50" \r
+CH1_RTERM_RX "50" \r
+CH2_RTERM_RX "50" \r
+CH3_RTERM_RX "50" \r
+CH0_RX_DCC "DC" \r
+CH1_RX_DCC "DC" \r
+CH2_RX_DCC "DC" \r
+CH3_RX_DCC "DC" \r
+LOS_THRESHOLD "0" \r
+PLL_TERM "50" \r
+PLL_DCC "AC" \r
+PLL_LOL_SET "0" \r
+CH0_TX_SB "NORMAL" \r
+CH1_TX_SB "NORMAL" \r
+CH2_TX_SB "NORMAL" \r
+CH3_TX_SB "NORMAL" \r
+CH0_RX_SB "NORMAL" \r
+CH1_RX_SB "NORMAL" \r
+CH2_RX_SB "NORMAL" \r
+CH3_RX_SB "NORMAL" \r
+CH0_8B10B "NORMAL" \r
+CH1_8B10B "NORMAL" \r
+CH2_8B10B "NORMAL" \r
+CH3_8B10B "NORMAL" \r
+COMMA_A "1100000101" \r
+COMMA_B "0011111010" \r
+COMMA_M "1111111111" \r
+CH0_COMMA_ALIGN "AUTO" \r
+CH1_COMMA_ALIGN "AUTO" \r
+CH2_COMMA_ALIGN "AUTO" \r
+CH3_COMMA_ALIGN "AUTO" \r
+CH0_CTC_BYP "NORMAL" \r
+CH1_CTC_BYP "NORMAL" \r
+CH2_CTC_BYP "NORMAL" \r
+CH3_CTC_BYP "NORMAL" \r
+CC_MATCH1 "0000000000" \r
+CC_MATCH2 "0000000000" \r
+CC_MATCH3 "0110111100" \r
+CC_MATCH4 "0001010000" \r
+CC_MATCH_MODE "MATCH_3_4" \r
+CC_MIN_IPG "3" \r
+CCHMARK "9" \r
+CCLMARK "7" \r
+OS_REFCK2CORE "1"\r
+OS_PLLQCLKPORTS "0"\r
+OS_INT_ALL "0"\r
+\r
--- /dev/null
+\r
+\r
+--synopsys translate_off\r
+\r
+library pcsc_work;\r
+use pcsc_work.all;\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity PCSC is\r
+GENERIC(\r
+ CONFIG_FILE : String := "serdes_gbe_2.txt"\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+\r
+end PCSC;\r
+\r
+architecture PCSC_arch of PCSC is\r
+\r
+component PCSC_sim\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+PCSC_sim_inst : PCSC_sim\r
+generic map (\r
+ CONFIG_FILE => CONFIG_FILE)\r
+port map (\r
+ HDINN0 => HDINN0,\r
+ HDINN1 => HDINN1,\r
+ HDINN2 => HDINN2,\r
+ HDINN3 => HDINN3,\r
+ HDINP0 => HDINP0,\r
+ HDINP1 => HDINP1,\r
+ HDINP2 => HDINP2,\r
+ HDINP3 => HDINP3,\r
+ REFCLKN => REFCLKN,\r
+ REFCLKP => REFCLKP,\r
+ CIN11 => CIN11,\r
+ CIN10 => CIN10,\r
+ CIN9 => CIN9,\r
+ CIN8 => CIN8,\r
+ CIN7 => CIN7,\r
+ CIN6 => CIN6,\r
+ CIN5 => CIN5,\r
+ CIN4 => CIN4,\r
+ CIN3 => CIN3,\r
+ CIN2 => CIN2,\r
+ CIN1 => CIN1,\r
+ CIN0 => CIN0,\r
+ CYAWSTN => CYAWSTN,\r
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,\r
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,\r
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,\r
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,\r
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,\r
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,\r
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,\r
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,\r
+\r
+ FF_TX_D_0_0 => FF_TX_D_0_0,\r
+ FF_TX_D_0_1 => FF_TX_D_0_1,\r
+ FF_TX_D_0_2 => FF_TX_D_0_2,\r
+ FF_TX_D_0_3 => FF_TX_D_0_3,\r
+ FF_TX_D_0_4 => FF_TX_D_0_4,\r
+ FF_TX_D_0_5 => FF_TX_D_0_5,\r
+ FF_TX_D_0_6 => FF_TX_D_0_6,\r
+ FF_TX_D_0_7 => FF_TX_D_0_7,\r
+ FF_TX_D_0_8 => FF_TX_D_0_8,\r
+ FF_TX_D_0_9 => FF_TX_D_0_9,\r
+ FF_TX_D_0_10 => FF_TX_D_0_10,\r
+ FF_TX_D_0_11 => FF_TX_D_0_11,\r
+ FF_TX_D_0_12 => FF_TX_D_0_12,\r
+ FF_TX_D_0_13 => FF_TX_D_0_13,\r
+ FF_TX_D_0_14 => FF_TX_D_0_14,\r
+ FF_TX_D_0_15 => FF_TX_D_0_15,\r
+ FF_TX_D_0_16 => FF_TX_D_0_16,\r
+ FF_TX_D_0_17 => FF_TX_D_0_17,\r
+ FF_TX_D_0_18 => FF_TX_D_0_18,\r
+ FF_TX_D_0_19 => FF_TX_D_0_19,\r
+ FF_TX_D_0_20 => FF_TX_D_0_20,\r
+ FF_TX_D_0_21 => FF_TX_D_0_21,\r
+ FF_TX_D_0_22 => FF_TX_D_0_22,\r
+ FF_TX_D_0_23 => FF_TX_D_0_23,\r
+ FF_TX_D_1_0 => FF_TX_D_1_0,\r
+ FF_TX_D_1_1 => FF_TX_D_1_1,\r
+ FF_TX_D_1_2 => FF_TX_D_1_2,\r
+ FF_TX_D_1_3 => FF_TX_D_1_3,\r
+ FF_TX_D_1_4 => FF_TX_D_1_4,\r
+ FF_TX_D_1_5 => FF_TX_D_1_5,\r
+ FF_TX_D_1_6 => FF_TX_D_1_6,\r
+ FF_TX_D_1_7 => FF_TX_D_1_7,\r
+ FF_TX_D_1_8 => FF_TX_D_1_8,\r
+ FF_TX_D_1_9 => FF_TX_D_1_9,\r
+ FF_TX_D_1_10 => FF_TX_D_1_10,\r
+ FF_TX_D_1_11 => FF_TX_D_1_11,\r
+ FF_TX_D_1_12 => FF_TX_D_1_12,\r
+ FF_TX_D_1_13 => FF_TX_D_1_13,\r
+ FF_TX_D_1_14 => FF_TX_D_1_14,\r
+ FF_TX_D_1_15 => FF_TX_D_1_15,\r
+ FF_TX_D_1_16 => FF_TX_D_1_16,\r
+ FF_TX_D_1_17 => FF_TX_D_1_17,\r
+ FF_TX_D_1_18 => FF_TX_D_1_18,\r
+ FF_TX_D_1_19 => FF_TX_D_1_19,\r
+ FF_TX_D_1_20 => FF_TX_D_1_20,\r
+ FF_TX_D_1_21 => FF_TX_D_1_21,\r
+ FF_TX_D_1_22 => FF_TX_D_1_22,\r
+ FF_TX_D_1_23 => FF_TX_D_1_23,\r
+ FF_TX_D_2_0 => FF_TX_D_2_0,\r
+ FF_TX_D_2_1 => FF_TX_D_2_1,\r
+ FF_TX_D_2_2 => FF_TX_D_2_2,\r
+ FF_TX_D_2_3 => FF_TX_D_2_3,\r
+ FF_TX_D_2_4 => FF_TX_D_2_4,\r
+ FF_TX_D_2_5 => FF_TX_D_2_5,\r
+ FF_TX_D_2_6 => FF_TX_D_2_6,\r
+ FF_TX_D_2_7 => FF_TX_D_2_7,\r
+ FF_TX_D_2_8 => FF_TX_D_2_8,\r
+ FF_TX_D_2_9 => FF_TX_D_2_9,\r
+ FF_TX_D_2_10 => FF_TX_D_2_10,\r
+ FF_TX_D_2_11 => FF_TX_D_2_11,\r
+ FF_TX_D_2_12 => FF_TX_D_2_12,\r
+ FF_TX_D_2_13 => FF_TX_D_2_13,\r
+ FF_TX_D_2_14 => FF_TX_D_2_14,\r
+ FF_TX_D_2_15 => FF_TX_D_2_15,\r
+ FF_TX_D_2_16 => FF_TX_D_2_16,\r
+ FF_TX_D_2_17 => FF_TX_D_2_17,\r
+ FF_TX_D_2_18 => FF_TX_D_2_18,\r
+ FF_TX_D_2_19 => FF_TX_D_2_19,\r
+ FF_TX_D_2_20 => FF_TX_D_2_20,\r
+ FF_TX_D_2_21 => FF_TX_D_2_21,\r
+ FF_TX_D_2_22 => FF_TX_D_2_22,\r
+ FF_TX_D_2_23 => FF_TX_D_2_23,\r
+ FF_TX_D_3_0 => FF_TX_D_3_0,\r
+ FF_TX_D_3_1 => FF_TX_D_3_1,\r
+ FF_TX_D_3_2 => FF_TX_D_3_2,\r
+ FF_TX_D_3_3 => FF_TX_D_3_3,\r
+ FF_TX_D_3_4 => FF_TX_D_3_4,\r
+ FF_TX_D_3_5 => FF_TX_D_3_5,\r
+ FF_TX_D_3_6 => FF_TX_D_3_6,\r
+ FF_TX_D_3_7 => FF_TX_D_3_7,\r
+ FF_TX_D_3_8 => FF_TX_D_3_8,\r
+ FF_TX_D_3_9 => FF_TX_D_3_9,\r
+ FF_TX_D_3_10 => FF_TX_D_3_10,\r
+ FF_TX_D_3_11 => FF_TX_D_3_11,\r
+ FF_TX_D_3_12 => FF_TX_D_3_12,\r
+ FF_TX_D_3_13 => FF_TX_D_3_13,\r
+ FF_TX_D_3_14 => FF_TX_D_3_14,\r
+ FF_TX_D_3_15 => FF_TX_D_3_15,\r
+ FF_TX_D_3_16 => FF_TX_D_3_16,\r
+ FF_TX_D_3_17 => FF_TX_D_3_17,\r
+ FF_TX_D_3_18 => FF_TX_D_3_18,\r
+ FF_TX_D_3_19 => FF_TX_D_3_19,\r
+ FF_TX_D_3_20 => FF_TX_D_3_20,\r
+ FF_TX_D_3_21 => FF_TX_D_3_21,\r
+ FF_TX_D_3_22 => FF_TX_D_3_22,\r
+ FF_TX_D_3_23 => FF_TX_D_3_23,\r
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,\r
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,\r
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,\r
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,\r
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
+ FFC_EI_EN_0 => FFC_EI_EN_0,\r
+ FFC_EI_EN_1 => FFC_EI_EN_1,\r
+ FFC_EI_EN_2 => FFC_EI_EN_2,\r
+ FFC_EI_EN_3 => FFC_EI_EN_3,\r
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,\r
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,\r
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,\r
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,\r
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,\r
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,\r
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,\r
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,\r
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,\r
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,\r
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,\r
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,\r
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,\r
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,\r
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,\r
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,\r
+ FFC_MACRO_RST => FFC_MACRO_RST,\r
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,\r
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,\r
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,\r
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,\r
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,\r
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,\r
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,\r
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,\r
+ FFC_QUAD_RST => FFC_QUAD_RST,\r
+ FFC_RRST_0 => FFC_RRST_0,\r
+ FFC_RRST_1 => FFC_RRST_1,\r
+ FFC_RRST_2 => FFC_RRST_2,\r
+ FFC_RRST_3 => FFC_RRST_3,\r
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,\r
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,\r
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,\r
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,\r
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,\r
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,\r
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,\r
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,\r
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,\r
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,\r
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,\r
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,\r
+ FFC_TRST => FFC_TRST,\r
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,\r
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,\r
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,\r
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,\r
+ SCIADDR0 => SCIADDR0,\r
+ SCIADDR1 => SCIADDR1,\r
+ SCIADDR2 => SCIADDR2,\r
+ SCIADDR3 => SCIADDR3,\r
+ SCIADDR4 => SCIADDR4,\r
+ SCIADDR5 => SCIADDR5,\r
+ SCIENAUX => SCIENAUX,\r
+ SCIENCH0 => SCIENCH0,\r
+ SCIENCH1 => SCIENCH1,\r
+ SCIENCH2 => SCIENCH2,\r
+ SCIENCH3 => SCIENCH3,\r
+ SCIRD => SCIRD,\r
+ SCISELAUX => SCISELAUX,\r
+ SCISELCH0 => SCISELCH0,\r
+ SCISELCH1 => SCISELCH1,\r
+ SCISELCH2 => SCISELCH2,\r
+ SCISELCH3 => SCISELCH3,\r
+ SCIWDATA0 => SCIWDATA0,\r
+ SCIWDATA1 => SCIWDATA1,\r
+ SCIWDATA2 => SCIWDATA2,\r
+ SCIWDATA3 => SCIWDATA3,\r
+ SCIWDATA4 => SCIWDATA4,\r
+ SCIWDATA5 => SCIWDATA5,\r
+ SCIWDATA6 => SCIWDATA6,\r
+ SCIWDATA7 => SCIWDATA7,\r
+ SCIWSTN => SCIWSTN,\r
+ HDOUTN0 => HDOUTN0,\r
+ HDOUTN1 => HDOUTN1,\r
+ HDOUTN2 => HDOUTN2,\r
+ HDOUTN3 => HDOUTN3,\r
+ HDOUTP0 => HDOUTP0,\r
+ HDOUTP1 => HDOUTP1,\r
+ HDOUTP2 => HDOUTP2,\r
+ HDOUTP3 => HDOUTP3,\r
+ COUT19 => COUT19,\r
+ COUT18 => COUT18,\r
+ COUT17 => COUT17,\r
+ COUT16 => COUT16,\r
+ COUT15 => COUT15,\r
+ COUT14 => COUT14,\r
+ COUT13 => COUT13,\r
+ COUT12 => COUT12,\r
+ COUT11 => COUT11,\r
+ COUT10 => COUT10,\r
+ COUT9 => COUT9,\r
+ COUT8 => COUT8,\r
+ COUT7 => COUT7,\r
+ COUT6 => COUT6,\r
+ COUT5 => COUT5,\r
+ COUT4 => COUT4,\r
+ COUT3 => COUT3,\r
+ COUT2 => COUT2,\r
+ COUT1 => COUT1,\r
+ COUT0 => COUT0,\r
+ FF_RX_D_0_0 => FF_RX_D_0_0,\r
+ FF_RX_D_0_1 => FF_RX_D_0_1,\r
+ FF_RX_D_0_2 => FF_RX_D_0_2,\r
+ FF_RX_D_0_3 => FF_RX_D_0_3,\r
+ FF_RX_D_0_4 => FF_RX_D_0_4,\r
+ FF_RX_D_0_5 => FF_RX_D_0_5,\r
+ FF_RX_D_0_6 => FF_RX_D_0_6,\r
+ FF_RX_D_0_7 => FF_RX_D_0_7,\r
+ FF_RX_D_0_8 => FF_RX_D_0_8,\r
+ FF_RX_D_0_9 => FF_RX_D_0_9,\r
+ FF_RX_D_0_10 => FF_RX_D_0_10,\r
+ FF_RX_D_0_11 => FF_RX_D_0_11,\r
+ FF_RX_D_0_12 => FF_RX_D_0_12,\r
+ FF_RX_D_0_13 => FF_RX_D_0_13,\r
+ FF_RX_D_0_14 => FF_RX_D_0_14,\r
+ FF_RX_D_0_15 => FF_RX_D_0_15,\r
+ FF_RX_D_0_16 => FF_RX_D_0_16,\r
+ FF_RX_D_0_17 => FF_RX_D_0_17,\r
+ FF_RX_D_0_18 => FF_RX_D_0_18,\r
+ FF_RX_D_0_19 => FF_RX_D_0_19,\r
+ FF_RX_D_0_20 => FF_RX_D_0_20,\r
+ FF_RX_D_0_21 => FF_RX_D_0_21,\r
+ FF_RX_D_0_22 => FF_RX_D_0_22,\r
+ FF_RX_D_0_23 => FF_RX_D_0_23,\r
+ FF_RX_D_1_0 => FF_RX_D_1_0,\r
+ FF_RX_D_1_1 => FF_RX_D_1_1,\r
+ FF_RX_D_1_2 => FF_RX_D_1_2,\r
+ FF_RX_D_1_3 => FF_RX_D_1_3,\r
+ FF_RX_D_1_4 => FF_RX_D_1_4,\r
+ FF_RX_D_1_5 => FF_RX_D_1_5,\r
+ FF_RX_D_1_6 => FF_RX_D_1_6,\r
+ FF_RX_D_1_7 => FF_RX_D_1_7,\r
+ FF_RX_D_1_8 => FF_RX_D_1_8,\r
+ FF_RX_D_1_9 => FF_RX_D_1_9,\r
+ FF_RX_D_1_10 => FF_RX_D_1_10,\r
+ FF_RX_D_1_11 => FF_RX_D_1_11,\r
+ FF_RX_D_1_12 => FF_RX_D_1_12,\r
+ FF_RX_D_1_13 => FF_RX_D_1_13,\r
+ FF_RX_D_1_14 => FF_RX_D_1_14,\r
+ FF_RX_D_1_15 => FF_RX_D_1_15,\r
+ FF_RX_D_1_16 => FF_RX_D_1_16,\r
+ FF_RX_D_1_17 => FF_RX_D_1_17,\r
+ FF_RX_D_1_18 => FF_RX_D_1_18,\r
+ FF_RX_D_1_19 => FF_RX_D_1_19,\r
+ FF_RX_D_1_20 => FF_RX_D_1_20,\r
+ FF_RX_D_1_21 => FF_RX_D_1_21,\r
+ FF_RX_D_1_22 => FF_RX_D_1_22,\r
+ FF_RX_D_1_23 => FF_RX_D_1_23,\r
+ FF_RX_D_2_0 => FF_RX_D_2_0,\r
+ FF_RX_D_2_1 => FF_RX_D_2_1,\r
+ FF_RX_D_2_2 => FF_RX_D_2_2,\r
+ FF_RX_D_2_3 => FF_RX_D_2_3,\r
+ FF_RX_D_2_4 => FF_RX_D_2_4,\r
+ FF_RX_D_2_5 => FF_RX_D_2_5,\r
+ FF_RX_D_2_6 => FF_RX_D_2_6,\r
+ FF_RX_D_2_7 => FF_RX_D_2_7,\r
+ FF_RX_D_2_8 => FF_RX_D_2_8,\r
+ FF_RX_D_2_9 => FF_RX_D_2_9,\r
+ FF_RX_D_2_10 => FF_RX_D_2_10,\r
+ FF_RX_D_2_11 => FF_RX_D_2_11,\r
+ FF_RX_D_2_12 => FF_RX_D_2_12,\r
+ FF_RX_D_2_13 => FF_RX_D_2_13,\r
+ FF_RX_D_2_14 => FF_RX_D_2_14,\r
+ FF_RX_D_2_15 => FF_RX_D_2_15,\r
+ FF_RX_D_2_16 => FF_RX_D_2_16,\r
+ FF_RX_D_2_17 => FF_RX_D_2_17,\r
+ FF_RX_D_2_18 => FF_RX_D_2_18,\r
+ FF_RX_D_2_19 => FF_RX_D_2_19,\r
+ FF_RX_D_2_20 => FF_RX_D_2_20,\r
+ FF_RX_D_2_21 => FF_RX_D_2_21,\r
+ FF_RX_D_2_22 => FF_RX_D_2_22,\r
+ FF_RX_D_2_23 => FF_RX_D_2_23,\r
+ FF_RX_D_3_0 => FF_RX_D_3_0,\r
+ FF_RX_D_3_1 => FF_RX_D_3_1,\r
+ FF_RX_D_3_2 => FF_RX_D_3_2,\r
+ FF_RX_D_3_3 => FF_RX_D_3_3,\r
+ FF_RX_D_3_4 => FF_RX_D_3_4,\r
+ FF_RX_D_3_5 => FF_RX_D_3_5,\r
+ FF_RX_D_3_6 => FF_RX_D_3_6,\r
+ FF_RX_D_3_7 => FF_RX_D_3_7,\r
+ FF_RX_D_3_8 => FF_RX_D_3_8,\r
+ FF_RX_D_3_9 => FF_RX_D_3_9,\r
+ FF_RX_D_3_10 => FF_RX_D_3_10,\r
+ FF_RX_D_3_11 => FF_RX_D_3_11,\r
+ FF_RX_D_3_12 => FF_RX_D_3_12,\r
+ FF_RX_D_3_13 => FF_RX_D_3_13,\r
+ FF_RX_D_3_14 => FF_RX_D_3_14,\r
+ FF_RX_D_3_15 => FF_RX_D_3_15,\r
+ FF_RX_D_3_16 => FF_RX_D_3_16,\r
+ FF_RX_D_3_17 => FF_RX_D_3_17,\r
+ FF_RX_D_3_18 => FF_RX_D_3_18,\r
+ FF_RX_D_3_19 => FF_RX_D_3_19,\r
+ FF_RX_D_3_20 => FF_RX_D_3_20,\r
+ FF_RX_D_3_21 => FF_RX_D_3_21,\r
+ FF_RX_D_3_22 => FF_RX_D_3_22,\r
+ FF_RX_D_3_23 => FF_RX_D_3_23,\r
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,\r
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,\r
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,\r
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,\r
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,\r
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,\r
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,\r
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,\r
+ FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,\r
+ FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,\r
+ FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,\r
+ FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,\r
+ FF_TX_F_CLK => FF_TX_F_CLK,\r
+ FF_TX_H_CLK => FF_TX_H_CLK,\r
+ FF_TX_Q_CLK => FF_TX_Q_CLK,\r
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,\r
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,\r
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,\r
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,\r
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,\r
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,\r
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,\r
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,\r
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,\r
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,\r
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,\r
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,\r
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,\r
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,\r
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,\r
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,\r
+ FFS_PLOL => FFS_PLOL,\r
+ FFS_RLOL_0 => FFS_RLOL_0,\r
+ FFS_RLOL_1 => FFS_RLOL_1,\r
+ FFS_RLOL_2 => FFS_RLOL_2,\r
+ FFS_RLOL_3 => FFS_RLOL_3,\r
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,\r
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,\r
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,\r
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,\r
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,\r
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,\r
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,\r
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,\r
+ OOB_OUT_0 => OOB_OUT_0,\r
+ OOB_OUT_1 => OOB_OUT_1,\r
+ OOB_OUT_2 => OOB_OUT_2,\r
+ OOB_OUT_3 => OOB_OUT_3,\r
+ REFCK2CORE => REFCK2CORE,\r
+ SCIINT => SCIINT,\r
+ SCIRDATA0 => SCIRDATA0,\r
+ SCIRDATA1 => SCIRDATA1,\r
+ SCIRDATA2 => SCIRDATA2,\r
+ SCIRDATA3 => SCIRDATA3,\r
+ SCIRDATA4 => SCIRDATA4,\r
+ SCIRDATA5 => SCIRDATA5,\r
+ SCIRDATA6 => SCIRDATA6,\r
+ SCIRDATA7 => SCIRDATA7\r
+ );\r
+\r
+end PCSC_arch;\r
+\r
+--synopsys translate_on\r
+\r
+--synopsys translate_off\r
+library ECP2;\r
+use ECP2.components.all;\r
+--synopsys translate_on\r
+\r
+library IEEE, STD;\r
+use IEEE.std_logic_1164.all;\r
+use STD.TEXTIO.all;\r
+\r
+entity serdes_gbe_2 is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_2.txt");\r
+ port (\r
+ core_txrefclk : in std_logic;\r
+ core_rxrefclk : in std_logic;\r
+ hdinp0, hdinn0 : in std_logic;\r
+ hdoutp0, hdoutn0 : out std_logic;\r
+ ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
+ ff_txdata_ch0 : in std_logic_vector (15 downto 0);\r
+ ff_rxdata_ch0 : out std_logic_vector (15 downto 0);\r
+ ff_tx_k_cntrl_ch0 : in std_logic_vector (1 downto 0);\r
+ ff_rx_k_cntrl_ch0 : out std_logic_vector (1 downto 0);\r
+ ff_rxfullclk_ch0 : out std_logic;\r
+ ff_rxhalfclk_ch0 : out std_logic;\r
+ ff_xmit_ch0 : in std_logic_vector (1 downto 0);\r
+ ff_correct_disp_ch0 : in std_logic_vector (1 downto 0);\r
+ ff_disp_err_ch0, ff_cv_ch0 : out std_logic_vector (1 downto 0);\r
+ ff_rx_even_ch0 : out std_logic_vector (1 downto 0);\r
+ ffc_rrst_ch0 : in std_logic;\r
+ ffc_lane_tx_rst_ch0 : in std_logic;\r
+ ffc_lane_rx_rst_ch0 : in std_logic;\r
+ ffc_txpwdnb_ch0 : in std_logic;\r
+ ffc_rxpwdnb_ch0 : in std_logic;\r
+ ffs_rlos_lo_ch0 : out std_logic;\r
+ ffs_ls_sync_status_ch0 : out std_logic;\r
+ ffs_cc_underrun_ch0 : out std_logic;\r
+ ffs_cc_overrun_ch0 : out std_logic;\r
+ ffs_txfbfifo_error_ch0 : out std_logic;\r
+ ffs_rxfbfifo_error_ch0 : out std_logic;\r
+ ffs_rlol_ch0 : out std_logic;\r
+ oob_out_ch0 : out std_logic;\r
+ hdinp1, hdinn1 : in std_logic;\r
+ hdoutp1, hdoutn1 : out std_logic;\r
+ ff_rxiclk_ch1, ff_txiclk_ch1, ff_ebrd_clk_1 : in std_logic;\r
+ ff_txdata_ch1 : in std_logic_vector (15 downto 0);\r
+ ff_rxdata_ch1 : out std_logic_vector (15 downto 0);\r
+ ff_tx_k_cntrl_ch1 : in std_logic_vector (1 downto 0);\r
+ ff_rx_k_cntrl_ch1 : out std_logic_vector (1 downto 0);\r
+ ff_rxfullclk_ch1 : out std_logic;\r
+ ff_rxhalfclk_ch1 : out std_logic;\r
+ ff_xmit_ch1 : in std_logic_vector (1 downto 0);\r
+ ff_correct_disp_ch1 : in std_logic_vector (1 downto 0);\r
+ ff_disp_err_ch1, ff_cv_ch1 : out std_logic_vector (1 downto 0);\r
+ ff_rx_even_ch1 : out std_logic_vector (1 downto 0);\r
+ ffc_rrst_ch1 : in std_logic;\r
+ ffc_lane_tx_rst_ch1 : in std_logic;\r
+ ffc_lane_rx_rst_ch1 : in std_logic;\r
+ ffc_txpwdnb_ch1 : in std_logic;\r
+ ffc_rxpwdnb_ch1 : in std_logic;\r
+ ffs_rlos_lo_ch1 : out std_logic;\r
+ ffs_ls_sync_status_ch1 : out std_logic;\r
+ ffs_cc_underrun_ch1 : out std_logic;\r
+ ffs_cc_overrun_ch1 : out std_logic;\r
+ ffs_txfbfifo_error_ch1 : out std_logic;\r
+ ffs_rxfbfifo_error_ch1 : out std_logic;\r
+ ffs_rlol_ch1 : out std_logic;\r
+ oob_out_ch1 : out std_logic;\r
+ hdinp2, hdinn2 : in std_logic;\r
+ hdoutp2, hdoutn2 : out std_logic;\r
+ ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic;\r
+ ff_txdata_ch2 : in std_logic_vector (15 downto 0);\r
+ ff_rxdata_ch2 : out std_logic_vector (15 downto 0);\r
+ ff_tx_k_cntrl_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_rx_k_cntrl_ch2 : out std_logic_vector (1 downto 0);\r
+ ff_rxfullclk_ch2 : out std_logic;\r
+ ff_rxhalfclk_ch2 : out std_logic;\r
+ ff_xmit_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_correct_disp_ch2 : in std_logic_vector (1 downto 0);\r
+ ff_disp_err_ch2, ff_cv_ch2 : out std_logic_vector (1 downto 0);\r
+ ff_rx_even_ch2 : out std_logic_vector (1 downto 0);\r
+ ffc_rrst_ch2 : in std_logic;\r
+ ffc_lane_tx_rst_ch2 : in std_logic;\r
+ ffc_lane_rx_rst_ch2 : in std_logic;\r
+ ffc_txpwdnb_ch2 : in std_logic;\r
+ ffc_rxpwdnb_ch2 : in std_logic;\r
+ ffs_rlos_lo_ch2 : out std_logic;\r
+ ffs_ls_sync_status_ch2 : out std_logic;\r
+ ffs_cc_underrun_ch2 : out std_logic;\r
+ ffs_cc_overrun_ch2 : out std_logic;\r
+ ffs_txfbfifo_error_ch2 : out std_logic;\r
+ ffs_rxfbfifo_error_ch2 : out std_logic;\r
+ ffs_rlol_ch2 : out std_logic;\r
+ oob_out_ch2 : out std_logic;\r
+ hdinp3, hdinn3 : in std_logic;\r
+ hdoutp3, hdoutn3 : out std_logic;\r
+ ff_rxiclk_ch3, ff_txiclk_ch3, ff_ebrd_clk_3 : in std_logic;\r
+ ff_txdata_ch3 : in std_logic_vector (15 downto 0);\r
+ ff_rxdata_ch3 : out std_logic_vector (15 downto 0);\r
+ ff_tx_k_cntrl_ch3 : in std_logic_vector (1 downto 0);\r
+ ff_rx_k_cntrl_ch3 : out std_logic_vector (1 downto 0);\r
+ ff_rxfullclk_ch3 : out std_logic;\r
+ ff_rxhalfclk_ch3 : out std_logic;\r
+ ff_xmit_ch3 : in std_logic_vector (1 downto 0);\r
+ ff_correct_disp_ch3 : in std_logic_vector (1 downto 0);\r
+ ff_disp_err_ch3, ff_cv_ch3 : out std_logic_vector (1 downto 0);\r
+ ff_rx_even_ch3 : out std_logic_vector (1 downto 0);\r
+ ffc_rrst_ch3 : in std_logic;\r
+ ffc_lane_tx_rst_ch3 : in std_logic;\r
+ ffc_lane_rx_rst_ch3 : in std_logic;\r
+ ffc_txpwdnb_ch3 : in std_logic;\r
+ ffc_rxpwdnb_ch3 : in std_logic;\r
+ ffs_rlos_lo_ch3 : out std_logic;\r
+ ffs_ls_sync_status_ch3 : out std_logic;\r
+ ffs_cc_underrun_ch3 : out std_logic;\r
+ ffs_cc_overrun_ch3 : out std_logic;\r
+ ffs_txfbfifo_error_ch3 : out std_logic;\r
+ ffs_rxfbfifo_error_ch3 : out std_logic;\r
+ ffs_rlol_ch3 : out std_logic;\r
+ oob_out_ch3 : out std_logic;\r
+ ffc_macro_rst : in std_logic;\r
+ ffc_quad_rst : in std_logic;\r
+ ffc_trst : in std_logic;\r
+ ff_txfullclk : out std_logic;\r
+ ff_txhalfclk : out std_logic;\r
+ refck2core : out std_logic;\r
+ ffs_plol : out std_logic);\r
+\r
+end serdes_gbe_2;\r
+\r
+architecture serdes_gbe_2_arch of serdes_gbe_2 is\r
+\r
+component VLO\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+\r
+component VHI\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+component PCSC\r
+--synopsys translate_off\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+--synopsys translate_on\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+ attribute IS_ASB: string;\r
+ attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";\r
+ attribute CONFIG_FILE: string;\r
+ attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;\r
+ attribute black_box_pad_pin: string;\r
+ attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";\r
+\r
+signal fpsc_vlo : std_logic := '0';\r
+signal cin : std_logic_vector (11 downto 0) := "000000000000";\r
+signal cout : std_logic_vector (19 downto 0);\r
+\r
+begin\r
+\r
+vlo_inst : VLO port map(Z => fpsc_vlo);\r
+\r
+-- pcs_quad instance\r
+PCSC_INST : PCSC\r
+--synopsys translate_off\r
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
+--synopsys translate_on\r
+port map (\r
+ FFC_CK_CORE_TX => core_txrefclk,\r
+ FFC_CK_CORE_RX => core_rxrefclk,\r
+ REFCLKP => fpsc_vlo,\r
+ REFCLKN => fpsc_vlo,\r
+ HDINP0 => hdinp0,\r
+ HDINN0 => hdinn0,\r
+ HDOUTP0 => hdoutp0,\r
+ HDOUTN0 => hdoutn0,\r
+ SCISELCH0 => fpsc_vlo,\r
+ SCIENCH0 => fpsc_vlo,\r
+ FF_RXI_CLK_0 => ff_rxiclk_ch0,\r
+ FF_TXI_CLK_0 => ff_txiclk_ch0,\r
+ FF_EBRD_CLK_0 => ff_ebrd_clk_0,\r
+ FF_RX_F_CLK_0 => ff_rxfullclk_ch0,\r
+ FF_RX_H_CLK_0 => ff_rxhalfclk_ch0,\r
+ FF_RX_Q_CLK_0 => open,\r
+ FF_TX_D_0_0 => ff_txdata_ch0(0),\r
+ FF_TX_D_0_1 => ff_txdata_ch0(1),\r
+ FF_TX_D_0_2 => ff_txdata_ch0(2),\r
+ FF_TX_D_0_3 => ff_txdata_ch0(3),\r
+ FF_TX_D_0_4 => ff_txdata_ch0(4),\r
+ FF_TX_D_0_5 => ff_txdata_ch0(5),\r
+ FF_TX_D_0_6 => ff_txdata_ch0(6),\r
+ FF_TX_D_0_7 => ff_txdata_ch0(7),\r
+ FF_TX_D_0_8 => ff_tx_k_cntrl_ch0(0),\r
+ FF_TX_D_0_9 => fpsc_vlo,\r
+ FF_TX_D_0_10 => ff_xmit_ch0(0),\r
+ FF_TX_D_0_11 => ff_correct_disp_ch0(0),\r
+ FF_TX_D_0_12 => ff_txdata_ch0(8),\r
+ FF_TX_D_0_13 => ff_txdata_ch0(9),\r
+ FF_TX_D_0_14 => ff_txdata_ch0(10),\r
+ FF_TX_D_0_15 => ff_txdata_ch0(11),\r
+ FF_TX_D_0_16 => ff_txdata_ch0(12),\r
+ FF_TX_D_0_17 => ff_txdata_ch0(13),\r
+ FF_TX_D_0_18 => ff_txdata_ch0(14),\r
+ FF_TX_D_0_19 => ff_txdata_ch0(15),\r
+ FF_TX_D_0_20 => ff_tx_k_cntrl_ch0(1),\r
+ FF_TX_D_0_21 => fpsc_vlo,\r
+ FF_TX_D_0_22 => ff_xmit_ch0(1),\r
+ FF_TX_D_0_23 => ff_correct_disp_ch0(1),\r
+ FF_RX_D_0_0 => ff_rxdata_ch0(0),\r
+ FF_RX_D_0_1 => ff_rxdata_ch0(1),\r
+ FF_RX_D_0_2 => ff_rxdata_ch0(2),\r
+ FF_RX_D_0_3 => ff_rxdata_ch0(3),\r
+ FF_RX_D_0_4 => ff_rxdata_ch0(4),\r
+ FF_RX_D_0_5 => ff_rxdata_ch0(5),\r
+ FF_RX_D_0_6 => ff_rxdata_ch0(6),\r
+ FF_RX_D_0_7 => ff_rxdata_ch0(7),\r
+ FF_RX_D_0_8 => ff_rx_k_cntrl_ch0(0),\r
+ FF_RX_D_0_9 => ff_disp_err_ch0(0),\r
+ FF_RX_D_0_10 => ff_cv_ch0(0),\r
+ FF_RX_D_0_11 => ff_rx_even_ch0(0),\r
+ FF_RX_D_0_12 => ff_rxdata_ch0(8),\r
+ FF_RX_D_0_13 => ff_rxdata_ch0(9),\r
+ FF_RX_D_0_14 => ff_rxdata_ch0(10),\r
+ FF_RX_D_0_15 => ff_rxdata_ch0(11),\r
+ FF_RX_D_0_16 => ff_rxdata_ch0(12),\r
+ FF_RX_D_0_17 => ff_rxdata_ch0(13),\r
+ FF_RX_D_0_18 => ff_rxdata_ch0(14),\r
+ FF_RX_D_0_19 => ff_rxdata_ch0(15),\r
+ FF_RX_D_0_20 => ff_rx_k_cntrl_ch0(1),\r
+ FF_RX_D_0_21 => ff_disp_err_ch0(1),\r
+ FF_RX_D_0_22 => ff_cv_ch0(1),\r
+ FF_RX_D_0_23 => ff_rx_even_ch0(1),\r
+ FFC_RRST_0 => ffc_rrst_ch0,\r
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_0 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,\r
+ FFC_SB_INV_RX_0 => fpsc_vlo,\r
+ FFC_PCIE_CT_0 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_0 => fpsc_vlo,\r
+ FFS_PCIE_DONE_0 => open,\r
+ FFS_PCIE_CON_0 => open,\r
+ FFC_EI_EN_0 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,\r
+ FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,\r
+ FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,\r
+ FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,\r
+ FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,\r
+ FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,\r
+ FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0,\r
+ FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0,\r
+ FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0,\r
+ FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0,\r
+ FFS_RLOL_0 => ffs_rlol_ch0,\r
+ OOB_OUT_0 => oob_out_ch0,\r
+ HDINP1 => hdinp1,\r
+ HDINN1 => hdinn1,\r
+ HDOUTP1 => hdoutp1,\r
+ HDOUTN1 => hdoutn1,\r
+ SCISELCH1 => fpsc_vlo,\r
+ SCIENCH1 => fpsc_vlo,\r
+ FF_RXI_CLK_1 => ff_rxiclk_ch1,\r
+ FF_TXI_CLK_1 => ff_txiclk_ch1,\r
+ FF_EBRD_CLK_1 => ff_ebrd_clk_1,\r
+ FF_RX_F_CLK_1 => ff_rxfullclk_ch1,\r
+ FF_RX_H_CLK_1 => ff_rxhalfclk_ch1,\r
+ FF_RX_Q_CLK_1 => open,\r
+ FF_TX_D_1_0 => ff_txdata_ch1(0),\r
+ FF_TX_D_1_1 => ff_txdata_ch1(1),\r
+ FF_TX_D_1_2 => ff_txdata_ch1(2),\r
+ FF_TX_D_1_3 => ff_txdata_ch1(3),\r
+ FF_TX_D_1_4 => ff_txdata_ch1(4),\r
+ FF_TX_D_1_5 => ff_txdata_ch1(5),\r
+ FF_TX_D_1_6 => ff_txdata_ch1(6),\r
+ FF_TX_D_1_7 => ff_txdata_ch1(7),\r
+ FF_TX_D_1_8 => ff_tx_k_cntrl_ch1(0),\r
+ FF_TX_D_1_9 => fpsc_vlo,\r
+ FF_TX_D_1_10 => ff_xmit_ch1(0),\r
+ FF_TX_D_1_11 => ff_correct_disp_ch1(0),\r
+ FF_TX_D_1_12 => ff_txdata_ch1(8),\r
+ FF_TX_D_1_13 => ff_txdata_ch1(9),\r
+ FF_TX_D_1_14 => ff_txdata_ch1(10),\r
+ FF_TX_D_1_15 => ff_txdata_ch1(11),\r
+ FF_TX_D_1_16 => ff_txdata_ch1(12),\r
+ FF_TX_D_1_17 => ff_txdata_ch1(13),\r
+ FF_TX_D_1_18 => ff_txdata_ch1(14),\r
+ FF_TX_D_1_19 => ff_txdata_ch1(15),\r
+ FF_TX_D_1_20 => ff_tx_k_cntrl_ch1(1),\r
+ FF_TX_D_1_21 => fpsc_vlo,\r
+ FF_TX_D_1_22 => ff_xmit_ch1(1),\r
+ FF_TX_D_1_23 => ff_correct_disp_ch1(1),\r
+ FF_RX_D_1_0 => ff_rxdata_ch1(0),\r
+ FF_RX_D_1_1 => ff_rxdata_ch1(1),\r
+ FF_RX_D_1_2 => ff_rxdata_ch1(2),\r
+ FF_RX_D_1_3 => ff_rxdata_ch1(3),\r
+ FF_RX_D_1_4 => ff_rxdata_ch1(4),\r
+ FF_RX_D_1_5 => ff_rxdata_ch1(5),\r
+ FF_RX_D_1_6 => ff_rxdata_ch1(6),\r
+ FF_RX_D_1_7 => ff_rxdata_ch1(7),\r
+ FF_RX_D_1_8 => ff_rx_k_cntrl_ch1(0),\r
+ FF_RX_D_1_9 => ff_disp_err_ch1(0),\r
+ FF_RX_D_1_10 => ff_cv_ch1(0),\r
+ FF_RX_D_1_11 => ff_rx_even_ch1(0),\r
+ FF_RX_D_1_12 => ff_rxdata_ch1(8),\r
+ FF_RX_D_1_13 => ff_rxdata_ch1(9),\r
+ FF_RX_D_1_14 => ff_rxdata_ch1(10),\r
+ FF_RX_D_1_15 => ff_rxdata_ch1(11),\r
+ FF_RX_D_1_16 => ff_rxdata_ch1(12),\r
+ FF_RX_D_1_17 => ff_rxdata_ch1(13),\r
+ FF_RX_D_1_18 => ff_rxdata_ch1(14),\r
+ FF_RX_D_1_19 => ff_rxdata_ch1(15),\r
+ FF_RX_D_1_20 => ff_rx_k_cntrl_ch1(1),\r
+ FF_RX_D_1_21 => ff_disp_err_ch1(1),\r
+ FF_RX_D_1_22 => ff_cv_ch1(1),\r
+ FF_RX_D_1_23 => ff_rx_even_ch1(1),\r
+ FFC_RRST_1 => ffc_rrst_ch1,\r
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_1 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,\r
+ FFC_SB_INV_RX_1 => fpsc_vlo,\r
+ FFC_PCIE_CT_1 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_1 => fpsc_vlo,\r
+ FFS_PCIE_DONE_1 => open,\r
+ FFS_PCIE_CON_1 => open,\r
+ FFC_EI_EN_1 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_1 => ffc_lane_tx_rst_ch1,\r
+ FFC_LANE_RX_RST_1 => ffc_lane_rx_rst_ch1,\r
+ FFC_TXPWDNB_1 => ffc_txpwdnb_ch1,\r
+ FFC_RXPWDNB_1 => ffc_rxpwdnb_ch1,\r
+ FFS_RLOS_LO_1 => ffs_rlos_lo_ch1,\r
+ FFS_LS_SYNC_STATUS_1 => ffs_ls_sync_status_ch1,\r
+ FFS_CC_UNDERRUN_1 => ffs_cc_underrun_ch1,\r
+ FFS_CC_OVERRUN_1 => ffs_cc_overrun_ch1,\r
+ FFS_RXFBFIFO_ERROR_1 => ffs_rxfbfifo_error_ch1,\r
+ FFS_TXFBFIFO_ERROR_1 => ffs_txfbfifo_error_ch1,\r
+ FFS_RLOL_1 => ffs_rlol_ch1,\r
+ OOB_OUT_1 => oob_out_ch1,\r
+ HDINP2 => hdinp2,\r
+ HDINN2 => hdinn2,\r
+ HDOUTP2 => hdoutp2,\r
+ HDOUTN2 => hdoutn2,\r
+ SCISELCH2 => fpsc_vlo,\r
+ SCIENCH2 => fpsc_vlo,\r
+ FF_RXI_CLK_2 => ff_rxiclk_ch2,\r
+ FF_TXI_CLK_2 => ff_txiclk_ch2,\r
+ FF_EBRD_CLK_2 => ff_ebrd_clk_2,\r
+ FF_RX_F_CLK_2 => ff_rxfullclk_ch2,\r
+ FF_RX_H_CLK_2 => ff_rxhalfclk_ch2,\r
+ FF_RX_Q_CLK_2 => open,\r
+ FF_TX_D_2_0 => ff_txdata_ch2(0),\r
+ FF_TX_D_2_1 => ff_txdata_ch2(1),\r
+ FF_TX_D_2_2 => ff_txdata_ch2(2),\r
+ FF_TX_D_2_3 => ff_txdata_ch2(3),\r
+ FF_TX_D_2_4 => ff_txdata_ch2(4),\r
+ FF_TX_D_2_5 => ff_txdata_ch2(5),\r
+ FF_TX_D_2_6 => ff_txdata_ch2(6),\r
+ FF_TX_D_2_7 => ff_txdata_ch2(7),\r
+ FF_TX_D_2_8 => ff_tx_k_cntrl_ch2(0),\r
+ FF_TX_D_2_9 => fpsc_vlo,\r
+ FF_TX_D_2_10 => ff_xmit_ch2(0),\r
+ FF_TX_D_2_11 => ff_correct_disp_ch2(0),\r
+ FF_TX_D_2_12 => ff_txdata_ch2(8),\r
+ FF_TX_D_2_13 => ff_txdata_ch2(9),\r
+ FF_TX_D_2_14 => ff_txdata_ch2(10),\r
+ FF_TX_D_2_15 => ff_txdata_ch2(11),\r
+ FF_TX_D_2_16 => ff_txdata_ch2(12),\r
+ FF_TX_D_2_17 => ff_txdata_ch2(13),\r
+ FF_TX_D_2_18 => ff_txdata_ch2(14),\r
+ FF_TX_D_2_19 => ff_txdata_ch2(15),\r
+ FF_TX_D_2_20 => ff_tx_k_cntrl_ch2(1),\r
+ FF_TX_D_2_21 => fpsc_vlo,\r
+ FF_TX_D_2_22 => ff_xmit_ch2(1),\r
+ FF_TX_D_2_23 => ff_correct_disp_ch2(1),\r
+ FF_RX_D_2_0 => ff_rxdata_ch2(0),\r
+ FF_RX_D_2_1 => ff_rxdata_ch2(1),\r
+ FF_RX_D_2_2 => ff_rxdata_ch2(2),\r
+ FF_RX_D_2_3 => ff_rxdata_ch2(3),\r
+ FF_RX_D_2_4 => ff_rxdata_ch2(4),\r
+ FF_RX_D_2_5 => ff_rxdata_ch2(5),\r
+ FF_RX_D_2_6 => ff_rxdata_ch2(6),\r
+ FF_RX_D_2_7 => ff_rxdata_ch2(7),\r
+ FF_RX_D_2_8 => ff_rx_k_cntrl_ch2(0),\r
+ FF_RX_D_2_9 => ff_disp_err_ch2(0),\r
+ FF_RX_D_2_10 => ff_cv_ch2(0),\r
+ FF_RX_D_2_11 => ff_rx_even_ch2(0),\r
+ FF_RX_D_2_12 => ff_rxdata_ch2(8),\r
+ FF_RX_D_2_13 => ff_rxdata_ch2(9),\r
+ FF_RX_D_2_14 => ff_rxdata_ch2(10),\r
+ FF_RX_D_2_15 => ff_rxdata_ch2(11),\r
+ FF_RX_D_2_16 => ff_rxdata_ch2(12),\r
+ FF_RX_D_2_17 => ff_rxdata_ch2(13),\r
+ FF_RX_D_2_18 => ff_rxdata_ch2(14),\r
+ FF_RX_D_2_19 => ff_rxdata_ch2(15),\r
+ FF_RX_D_2_20 => ff_rx_k_cntrl_ch2(1),\r
+ FF_RX_D_2_21 => ff_disp_err_ch2(1),\r
+ FF_RX_D_2_22 => ff_cv_ch2(1),\r
+ FF_RX_D_2_23 => ff_rx_even_ch2(1),\r
+ FFC_RRST_2 => ffc_rrst_ch2,\r
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_2 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,\r
+ FFC_SB_INV_RX_2 => fpsc_vlo,\r
+ FFC_PCIE_CT_2 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_2 => fpsc_vlo,\r
+ FFS_PCIE_DONE_2 => open,\r
+ FFS_PCIE_CON_2 => open,\r
+ FFC_EI_EN_2 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2,\r
+ FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2,\r
+ FFC_TXPWDNB_2 => ffc_txpwdnb_ch2,\r
+ FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2,\r
+ FFS_RLOS_LO_2 => ffs_rlos_lo_ch2,\r
+ FFS_LS_SYNC_STATUS_2 => ffs_ls_sync_status_ch2,\r
+ FFS_CC_UNDERRUN_2 => ffs_cc_underrun_ch2,\r
+ FFS_CC_OVERRUN_2 => ffs_cc_overrun_ch2,\r
+ FFS_RXFBFIFO_ERROR_2 => ffs_rxfbfifo_error_ch2,\r
+ FFS_TXFBFIFO_ERROR_2 => ffs_txfbfifo_error_ch2,\r
+ FFS_RLOL_2 => ffs_rlol_ch2,\r
+ OOB_OUT_2 => oob_out_ch2,\r
+ HDINP3 => hdinp3,\r
+ HDINN3 => hdinn3,\r
+ HDOUTP3 => hdoutp3,\r
+ HDOUTN3 => hdoutn3,\r
+ SCISELCH3 => fpsc_vlo,\r
+ SCIENCH3 => fpsc_vlo,\r
+ FF_RXI_CLK_3 => ff_rxiclk_ch3,\r
+ FF_TXI_CLK_3 => ff_txiclk_ch3,\r
+ FF_EBRD_CLK_3 => ff_ebrd_clk_3,\r
+ FF_RX_F_CLK_3 => ff_rxfullclk_ch3,\r
+ FF_RX_H_CLK_3 => ff_rxhalfclk_ch3,\r
+ FF_RX_Q_CLK_3 => open,\r
+ FF_TX_D_3_0 => ff_txdata_ch3(0),\r
+ FF_TX_D_3_1 => ff_txdata_ch3(1),\r
+ FF_TX_D_3_2 => ff_txdata_ch3(2),\r
+ FF_TX_D_3_3 => ff_txdata_ch3(3),\r
+ FF_TX_D_3_4 => ff_txdata_ch3(4),\r
+ FF_TX_D_3_5 => ff_txdata_ch3(5),\r
+ FF_TX_D_3_6 => ff_txdata_ch3(6),\r
+ FF_TX_D_3_7 => ff_txdata_ch3(7),\r
+ FF_TX_D_3_8 => ff_tx_k_cntrl_ch3(0),\r
+ FF_TX_D_3_9 => fpsc_vlo,\r
+ FF_TX_D_3_10 => ff_xmit_ch3(0),\r
+ FF_TX_D_3_11 => ff_correct_disp_ch3(0),\r
+ FF_TX_D_3_12 => ff_txdata_ch3(8),\r
+ FF_TX_D_3_13 => ff_txdata_ch3(9),\r
+ FF_TX_D_3_14 => ff_txdata_ch3(10),\r
+ FF_TX_D_3_15 => ff_txdata_ch3(11),\r
+ FF_TX_D_3_16 => ff_txdata_ch3(12),\r
+ FF_TX_D_3_17 => ff_txdata_ch3(13),\r
+ FF_TX_D_3_18 => ff_txdata_ch3(14),\r
+ FF_TX_D_3_19 => ff_txdata_ch3(15),\r
+ FF_TX_D_3_20 => ff_tx_k_cntrl_ch3(1),\r
+ FF_TX_D_3_21 => fpsc_vlo,\r
+ FF_TX_D_3_22 => ff_xmit_ch3(1),\r
+ FF_TX_D_3_23 => ff_correct_disp_ch3(1),\r
+ FF_RX_D_3_0 => ff_rxdata_ch3(0),\r
+ FF_RX_D_3_1 => ff_rxdata_ch3(1),\r
+ FF_RX_D_3_2 => ff_rxdata_ch3(2),\r
+ FF_RX_D_3_3 => ff_rxdata_ch3(3),\r
+ FF_RX_D_3_4 => ff_rxdata_ch3(4),\r
+ FF_RX_D_3_5 => ff_rxdata_ch3(5),\r
+ FF_RX_D_3_6 => ff_rxdata_ch3(6),\r
+ FF_RX_D_3_7 => ff_rxdata_ch3(7),\r
+ FF_RX_D_3_8 => ff_rx_k_cntrl_ch3(0),\r
+ FF_RX_D_3_9 => ff_disp_err_ch3(0),\r
+ FF_RX_D_3_10 => ff_cv_ch3(0),\r
+ FF_RX_D_3_11 => ff_rx_even_ch3(0),\r
+ FF_RX_D_3_12 => ff_rxdata_ch3(8),\r
+ FF_RX_D_3_13 => ff_rxdata_ch3(9),\r
+ FF_RX_D_3_14 => ff_rxdata_ch3(10),\r
+ FF_RX_D_3_15 => ff_rxdata_ch3(11),\r
+ FF_RX_D_3_16 => ff_rxdata_ch3(12),\r
+ FF_RX_D_3_17 => ff_rxdata_ch3(13),\r
+ FF_RX_D_3_18 => ff_rxdata_ch3(14),\r
+ FF_RX_D_3_19 => ff_rxdata_ch3(15),\r
+ FF_RX_D_3_20 => ff_rx_k_cntrl_ch3(1),\r
+ FF_RX_D_3_21 => ff_disp_err_ch3(1),\r
+ FF_RX_D_3_22 => ff_cv_ch3(1),\r
+ FF_RX_D_3_23 => ff_rx_even_ch3(1),\r
+ FFC_RRST_3 => ffc_rrst_ch3,\r
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_3 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,\r
+ FFC_SB_INV_RX_3 => fpsc_vlo,\r
+ FFC_PCIE_CT_3 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_3 => fpsc_vlo,\r
+ FFS_PCIE_DONE_3 => open,\r
+ FFS_PCIE_CON_3 => open,\r
+ FFC_EI_EN_3 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_3 => ffc_lane_tx_rst_ch3,\r
+ FFC_LANE_RX_RST_3 => ffc_lane_rx_rst_ch3,\r
+ FFC_TXPWDNB_3 => ffc_txpwdnb_ch3,\r
+ FFC_RXPWDNB_3 => ffc_rxpwdnb_ch3,\r
+ FFS_RLOS_LO_3 => ffs_rlos_lo_ch3,\r
+ FFS_LS_SYNC_STATUS_3 => ffs_ls_sync_status_ch3,\r
+ FFS_CC_UNDERRUN_3 => ffs_cc_underrun_ch3,\r
+ FFS_CC_OVERRUN_3 => ffs_cc_overrun_ch3,\r
+ FFS_RXFBFIFO_ERROR_3 => ffs_rxfbfifo_error_ch3,\r
+ FFS_TXFBFIFO_ERROR_3 => ffs_txfbfifo_error_ch3,\r
+ FFS_RLOL_3 => ffs_rlol_ch3,\r
+ OOB_OUT_3 => oob_out_ch3,\r
+ SCIWDATA0 => fpsc_vlo,\r
+ SCIWDATA1 => fpsc_vlo,\r
+ SCIWDATA2 => fpsc_vlo,\r
+ SCIWDATA3 => fpsc_vlo,\r
+ SCIWDATA4 => fpsc_vlo,\r
+ SCIWDATA5 => fpsc_vlo,\r
+ SCIWDATA6 => fpsc_vlo,\r
+ SCIWDATA7 => fpsc_vlo,\r
+ SCIADDR0 => fpsc_vlo,\r
+ SCIADDR1 => fpsc_vlo,\r
+ SCIADDR2 => fpsc_vlo,\r
+ SCIADDR3 => fpsc_vlo,\r
+ SCIADDR4 => fpsc_vlo,\r
+ SCIADDR5 => fpsc_vlo,\r
+ SCIRDATA0 => open,\r
+ SCIRDATA1 => open,\r
+ SCIRDATA2 => open,\r
+ SCIRDATA3 => open,\r
+ SCIRDATA4 => open,\r
+ SCIRDATA5 => open,\r
+ SCIRDATA6 => open,\r
+ SCIRDATA7 => open,\r
+ SCIENAUX => fpsc_vlo,\r
+ SCISELAUX => fpsc_vlo,\r
+ SCIRD => fpsc_vlo,\r
+ SCIWSTN => fpsc_vlo,\r
+ CYAWSTN => fpsc_vlo,\r
+ SCIINT => open,\r
+ FFC_MACRO_RST => ffc_macro_rst,\r
+ FFC_QUAD_RST => ffc_quad_rst,\r
+ FFC_TRST => ffc_trst,\r
+ FF_TX_F_CLK => ff_txfullclk,\r
+ FF_TX_H_CLK => ff_txhalfclk,\r
+ FF_TX_Q_CLK => open,\r
+ REFCK2CORE => refck2core,\r
+ CIN0 => cin(0),\r
+ CIN1 => cin(1),\r
+ CIN2 => cin(2),\r
+ CIN3 => cin(3),\r
+ CIN4 => cin(4),\r
+ CIN5 => cin(5),\r
+ CIN6 => cin(6),\r
+ CIN7 => cin(7),\r
+ CIN8 => cin(8),\r
+ CIN9 => cin(9),\r
+ CIN10 => cin(10),\r
+ CIN11 => cin(11),\r
+ COUT0 => cout(0),\r
+ COUT1 => cout(1),\r
+ COUT2 => cout(2),\r
+ COUT3 => cout(3),\r
+ COUT4 => cout(4),\r
+ COUT5 => cout(5),\r
+ COUT6 => cout(6),\r
+ COUT7 => cout(7),\r
+ COUT8 => cout(8),\r
+ COUT9 => cout(9),\r
+ COUT10 => cout(10),\r
+ COUT11 => cout(11),\r
+ COUT12 => cout(12),\r
+ COUT13 => cout(13),\r
+ COUT14 => cout(14),\r
+ COUT15 => cout(15),\r
+ COUT16 => cout(16),\r
+ COUT17 => cout(17),\r
+ COUT18 => cout(18),\r
+ COUT19 => cout(19),\r
+ FFS_PLOL => ffs_plol);\r
+\r
+--synopsys translate_off\r
+file_read : PROCESS\r
+VARIABLE open_status : file_open_status;\r
+FILE config : text;\r
+BEGIN\r
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
+ IF (open_status = name_error) THEN\r
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
+ severity ERROR;\r
+ END IF;\r
+ wait;\r
+END PROCESS;\r
+--synopsys translate_on\r
+\r
+end serdes_gbe_2_arch ;\r
--- /dev/null
+Starting process: \r
+\r
+ Module Name: serdes_gbe_2\r
+ Core Name: PCS\r
+ LPC file : serdes_gbe_2.lpc\r
+ Parameter File : serdes_gbe_2.pp\r
+ Command line: X:/Programme/ispTOOLS_72/ispfpga/bin/nt/orcapp.exe -Fmaco serdes_gbe_2.pp\r
+ Return Value:\r
+\r
+\r
+ Module PCS has been generated in i:/vhdl_pro/adcmv2/lever successfully!\r
+\r
+X:/Programme/ispTOOLS_72/ispcpld/bin/hdl2jhd.exe -tfi -mod serdes_gbe_2 -ext readme -out serdes_gbe_2 -tpl serdes_gbe_2.tft serdes_gbe_2.vhd\r
+\r
+Done successfully!\r
+File: serdes_gbe_all.lpc created.\r
+\r
+\r
+End process: completed successfully.\r
+\r
+\r
+Total Warnings: 0\r
+\r
+Total Errors: 0\r
+\r
+\r
--- /dev/null
+--Media interface for Lattice ECP2M using PCS at 2GHz
+
+--Still missing: link reset features, fifo full error handling
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity trb_net16_med_ecp_sfp is
+ generic(
+ SERDES_NUM : integer range 0 to 3 := 2;
+ EXT_CLOCK : integer range 0 to 1 := c_NO
+ );
+ port(
+ CLK : in std_logic; -- SerDes clock
+ SYSCLK : in std_logic; -- fabric clock
+ RESET : in std_logic; -- synchronous reset
+ CLEAR : in std_logic; -- asynchronous reset
+ CLK_EN : in std_logic;
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_IN : in std_logic;
+ MED_READ_OUT : out std_logic;
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic;
+ MED_READ_IN : in std_logic;
+ REFCLK2CORE_OUT : out std_logic;
+ --SFP Connection
+ SD_RXD_P_IN : in std_logic;
+ SD_RXD_N_IN : in std_logic;
+ SD_TXD_P_OUT : out std_logic;
+ SD_TXD_N_OUT : out std_logic;
+ SD_REFCLK_P_IN : in std_logic;
+ SD_REFCLK_N_IN : in std_logic;
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+ SD_TXDIS_OUT : out std_logic; -- SFP disable
+ -- Status and control port
+ STAT_OP : out std_logic_vector (15 downto 0);
+ CTRL_OP : in std_logic_vector (15 downto 0);
+ STAT_DEBUG : out std_logic_vector (63 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture med_ecp_sfp of trb_net16_med_ecp_sfp is
+
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of med_ecp_sfp : architecture is "media_interface_group";
+ attribute syn_sharing : string;
+ attribute syn_sharing of med_ecp_sfp : architecture is "off";
+
+-- component serdes_sfp_2
+-- port(
+-- core_txrefclk : in std_logic;
+-- core_rxrefclk : in std_logic;
+-- hdinp2 : in std_logic;
+-- hdinn2 : in std_logic;
+-- ff_rxiclk_ch2 : in std_logic;
+-- ff_txiclk_ch2 : in std_logic;
+-- ff_ebrd_clk_2 : in std_logic;
+-- ff_txdata_ch2 : in std_logic_vector(15 downto 0);
+-- ff_tx_k_cntrl_ch2 : in std_logic_vector(1 downto 0);
+-- ff_force_disp_ch2 : in std_logic_vector(1 downto 0);
+-- ff_disp_sel_ch2 : in std_logic_vector(1 downto 0);
+-- ff_correct_disp_ch2 : in std_logic_vector(1 downto 0);
+-- ffc_rrst_ch2 : in std_logic;
+-- ffc_lane_tx_rst_ch2 : in std_logic;
+-- ffc_lane_rx_rst_ch2 : in std_logic;
+-- ffc_txpwdnb_ch2 : in std_logic;
+-- ffc_rxpwdnb_ch2 : in std_logic;
+-- ffc_macro_rst : in std_logic;
+-- ffc_quad_rst : in std_logic;
+-- ffc_trst : in std_logic;
+-- hdoutp2 : out std_logic;
+-- hdoutn2 : out std_logic;
+-- ff_rxdata_ch2 : out std_logic_vector(15 downto 0);
+-- ff_rx_k_cntrl_ch2 : out std_logic_vector(1 downto 0);
+-- ff_rxfullclk_ch2 : out std_logic;
+-- ff_rxhalfclk_ch2 : out std_logic;
+-- ff_disp_err_ch2 : out std_logic_vector(1 downto 0);
+-- ff_cv_ch2 : out std_logic_vector(1 downto 0);
+-- ffs_rlos_lo_ch2 : out std_logic;
+-- ffs_ls_sync_status_ch2 : out std_logic;
+-- ffs_cc_underrun_ch2 : out std_logic;
+-- ffs_cc_overrun_ch2 : out std_logic;
+-- ffs_txfbfifo_error_ch2 : out std_logic;
+-- ffs_rxfbfifo_error_ch2 : out std_logic;
+-- ffs_rlol_ch2 : out std_logic;
+-- oob_out_ch2 : out std_logic;
+-- ff_txfullclk : out std_logic;
+-- ff_txhalfclk : out std_logic;
+-- refck2core : out std_logic;
+-- ffs_plol : out std_logic
+-- );
+-- end component;
+
+ component serdes_gbe_2
+ port(
+ core_txrefclk : IN std_logic;
+ core_rxrefclk : IN std_logic;
+ hdinp2 : IN std_logic;
+ hdinn2 : IN std_logic;
+ ff_rxiclk_ch2 : IN std_logic;
+ ff_txiclk_ch2 : IN std_logic;
+ ff_ebrd_clk_2 : IN std_logic;
+ ff_txdata_ch2 : IN std_logic_vector(15 downto 0);
+ ff_tx_k_cntrl_ch2 : IN std_logic_vector(1 downto 0);
+ ff_xmit_ch2 : IN std_logic_vector(1 downto 0);
+ ff_correct_disp_ch2 : IN std_logic_vector(1 downto 0);
+ ffc_rrst_ch2 : IN std_logic;
+ ffc_lane_tx_rst_ch2 : IN std_logic;
+ ffc_lane_rx_rst_ch2 : IN std_logic;
+ ffc_txpwdnb_ch2 : IN std_logic;
+ ffc_rxpwdnb_ch2 : IN std_logic;
+ ffc_macro_rst : IN std_logic;
+ ffc_quad_rst : IN std_logic;
+ ffc_trst : IN std_logic;
+ hdoutp2 : OUT std_logic;
+ hdoutn2 : OUT std_logic;
+ ff_rxdata_ch2 : OUT std_logic_vector(15 downto 0);
+ ff_rx_k_cntrl_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_rxfullclk_ch2 : OUT std_logic;
+ ff_rxhalfclk_ch2 : OUT std_logic;
+ ff_disp_err_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_cv_ch2 : OUT std_logic_vector(1 downto 0);
+ ff_rx_even_ch2 : OUT std_logic_vector(1 downto 0);
+ ffs_rlos_lo_ch2 : OUT std_logic;
+ ffs_ls_sync_status_ch2 : OUT std_logic;
+ ffs_cc_underrun_ch2 : OUT std_logic;
+ ffs_cc_overrun_ch2 : OUT std_logic;
+ ffs_txfbfifo_error_ch2 : OUT std_logic;
+ ffs_rxfbfifo_error_ch2 : OUT std_logic;
+ ffs_rlol_ch2 : OUT std_logic;
+ oob_out_ch2 : OUT std_logic;
+ ff_txfullclk : OUT std_logic;
+ ff_txhalfclk : OUT std_logic;
+ refck2core : OUT std_logic;
+ ffs_plol : OUT std_logic
+ );
+ end component;
+
+
+
+ signal refck2core : std_logic;
+-- signal clock : std_logic;
+ --reset signals
+ signal ffc_quad_rst : std_logic;
+ signal ffc_lane_tx_rst : std_logic;
+ signal ffc_lane_rx_rst : std_logic;
+ --serdes connections
+ signal tx_data : std_logic_vector(15 downto 0);
+ signal tx_k : std_logic_vector(1 downto 0);
+ signal rx_data : std_logic_vector(15 downto 0); -- delayed signals
+ signal rx_k : std_logic_vector(1 downto 0); -- delayed signals
+ signal comb_rx_data : std_logic_vector(15 downto 0); -- original signals from SFP
+ signal comb_rx_k : std_logic_vector(1 downto 0); -- original signals from SFP
+ signal link_ok : std_logic_vector(0 downto 0);
+ signal link_error : std_logic_vector(8 downto 0);
+-- signal ff_rxhalfclk : std_logic;
+ signal ff_txhalfclk : std_logic;
+ signal ff_txfullclk : std_logic;
+ --rx fifo signals
+ signal fifo_rx_rd_en : std_logic;
+ signal fifo_rx_wr_en : std_logic;
+ signal fifo_rx_reset : std_logic;
+ signal fifo_rx_din : std_logic_vector(17 downto 0);
+ signal fifo_rx_dout : std_logic_vector(17 downto 0);
+ signal fifo_rx_full : std_logic;
+ signal fifo_rx_empty : std_logic;
+ --tx fifo signals
+ signal fifo_tx_rd_en : std_logic;
+ signal fifo_tx_wr_en : std_logic;
+ signal fifo_tx_reset : std_logic;
+ signal fifo_tx_din : std_logic_vector(17 downto 0);
+ signal fifo_tx_dout : std_logic_vector(17 downto 0);
+ signal fifo_tx_full : std_logic;
+ signal fifo_tx_empty : std_logic;
+ --rx path
+ signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal buf_med_dataready_out : std_logic;
+ signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal last_rx : std_logic_vector(8 downto 0);
+ signal last_fifo_rx_empty : std_logic;
+ --tx path
+ signal last_fifo_tx_empty : std_logic;
+ --link status
+ signal link_led : std_logic;
+ signal rx_k_q : std_logic_vector(1 downto 0);
+
+ signal info_led : std_logic;
+
+ signal quad_rst : std_logic;
+ signal lane_rst : std_logic;
+ signal tx_allow : std_logic;
+ signal rx_allow : std_logic;
+
+ signal rx_allow_q : std_logic; -- clock domain changed signal
+ signal tx_allow_q : std_logic;
+ signal swap_bytes : std_logic;
+ signal buf_stat_debug : std_logic_vector(31 downto 0);
+
+ -- status inputs from SFP
+ signal sfp_prsnt_n : std_logic; -- synchronized input signals
+ signal sfp_los : std_logic; -- synchronized input signals
+
+ signal buf_STAT_OP : std_logic_vector(15 downto 0);
+
+ signal led_counter : std_logic_vector(17 downto 0);
+ signal rx_led : std_logic;
+ signal tx_led : std_logic;
+ attribute syn_keep : boolean;
+ attribute syn_keep of led_counter : signal is true;
+
+ signal reset_i : std_logic;
+ signal pwr_up : std_logic;
+begin
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+
+ PROC_RESET : process(SYSCLK)
+ begin
+ if rising_edge(SYSCLK) then
+ reset_i <= RESET or CTRL_OP(14);
+ pwr_up <= '1'; --not CTRL_OP(i*16+14);
+ end if;
+ end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(0) => sd_prsnt_n_in,
+ D_IN(1) => sd_los_in,
+ CLK0 => sysclk,
+ CLK1 => sysclk,
+ D_OUT(0) => sfp_prsnt_n,
+ D_OUT(1) => sfp_los
+ );
+
+-- Komma delimiter transfer for training phase
+THE_RX_K_SYNC: signal_sync
+ generic map(
+ DEPTH => 3,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_k,
+ CLK0 => ff_txhalfclk, -- CHANGED
+ CLK1 => sysclk,
+ D_OUT => rx_k_q
+ );
+
+-- delay line for RX_K and RX_DATA (directly from SFP to fabric logic)
+THE_RX_DATA_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 16
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_data,
+ CLK0 => ff_txhalfclk, -- CHANGED
+ CLK1 => ff_txhalfclk, -- CHANGED
+ D_OUT => rx_data
+ );
+
+THE_RX_K_DELAY: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN => comb_rx_k,
+ CLK0 => ff_txhalfclk, -- CHANGED
+ CLK1 => ff_txhalfclk, -- CHANGED
+ D_OUT => rx_k
+ );
+
+
+-- Transfer for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync -- really needed?!?
+ generic map(
+ DEPTH => 2,
+ WIDTH => 2
+ )
+ port map(
+ RESET => reset_i,
+ D_IN(0) => rx_allow,
+ D_IN(1) => tx_allow,
+ CLK0 => sysclk,
+ CLK1 => sysclk,
+ D_OUT(0) => rx_allow_q,
+ D_OUT(1) => tx_allow_q
+ );
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+ port map(
+ SYSCLK => sysclk,
+ RESET => reset_i,
+ CLEAR => clear,
+ SFP_MISSING_IN => sfp_prsnt_n,
+ SFP_LOS_IN => sfp_los,
+ SD_LINK_OK_IN => link_ok(0),
+ SD_LOS_IN => link_error(8),
+ SD_TXCLK_BAD_IN => link_error(5),
+ SD_RXCLK_BAD_IN => link_error(4),
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => rx_k_q,
+ SD_CV_IN => link_error(7 downto 6),
+ FULL_RESET_OUT => quad_rst,
+ LANE_RESET_OUT => lane_rst,
+ TX_ALLOW_OUT => tx_allow,
+ RX_ALLOW_OUT => rx_allow,
+ SWAP_BYTES_OUT => swap_bytes,
+ STAT_OP => buf_stat_op,
+ CTRL_OP => ctrl_op,
+ STAT_DEBUG => buf_stat_debug
+ );
+
+sd_txdis_out <= quad_rst;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+ffc_quad_rst <= quad_rst;
+ffc_lane_tx_rst <= lane_rst;
+ffc_lane_rx_rst <= lane_rst;
+
+-- SerDes clock output to FPGA fabric
+refclk2core_out <= refck2core;
+
+-- Instantiation of serdes module
+ gen_serdes_2 : if SERDES_NUM = 2 generate
+ THE_SERDES: serdes_gbe_2
+ port map(
+ core_txrefclk => clk,
+ core_rxrefclk => clk,
+ hdinp2 => sd_rxd_p_in,
+ hdinn2 => sd_rxd_n_in,
+ ff_rxiclk_ch2 => ff_txhalfclk, -- CHANGED
+ ff_txiclk_ch2 => ff_txhalfclk,
+ ff_ebrd_clk_2 => ff_txfullclk, -- CHANGED
+ ff_txdata_ch2 => tx_data,
+ ff_tx_k_cntrl_ch2 => tx_k,
+ ff_xmit_ch2 => "00", -- UNKNOWN
+ ff_correct_disp_ch2 => "00",
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
+ ffc_lane_rx_rst_ch2 => ffc_lane_tx_rst,
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffc_macro_rst => '0',
+ ffc_quad_rst => ffc_quad_rst,
+ ffc_trst => '0',
+ hdoutp2 => sd_txd_p_out,
+ hdoutn2 => sd_txd_n_out,
+ ff_rxdata_ch2 => comb_rx_data,
+ ff_rx_k_cntrl_ch2 => comb_rx_k,
+ ff_rxfullclk_ch2 => open,
+ ff_rxhalfclk_ch2 => open, --ff_rxhalfclk,
+ ff_disp_err_ch2 => open,
+ ff_cv_ch2 => link_error(7 downto 6),
+ ff_rx_even_ch2 => open, -- UNKNOWN
+ ffs_rlos_lo_ch2 => link_error(8),
+ ffs_ls_sync_status_ch2 => link_ok(0),
+ ffs_cc_underrun_ch2 => link_error(0),
+ ffs_cc_overrun_ch2 => link_error(1),
+ ffs_txfbfifo_error_ch2 => link_error(2),
+ ffs_rxfbfifo_error_ch2 => link_error(3),
+ ffs_rlol_ch2 => link_error(4),
+ oob_out_ch2 => open,
+ ff_txfullclk => ff_txfullclk, -- CHANGED
+ ff_txhalfclk => ff_txhalfclk,
+ refck2core => refck2core,
+ ffs_plol => link_error(5)
+ );
+-- THE_SERDES: serdes_sfp_2
+-- port map(
+-- core_txrefclk => clk,
+-- core_rxrefclk => clk,
+-- hdinp2 => sd_rxd_p_in,
+-- hdinn2 => sd_rxd_n_in,
+-- ff_rxiclk_ch2 => ff_rxhalfclk,
+-- ff_txiclk_ch2 => ff_txhalfclk,
+-- ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness
+-- ff_txdata_ch2 => tx_data,
+-- ff_tx_k_cntrl_ch2 => tx_k,
+---- ff_force_disp_ch2 => "00",
+---- ff_disp_sel_ch2 => "00",
+-- ff_correct_disp_ch2 => "00",
+-- ffc_rrst_ch2 => '0',
+-- ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst,
+-- ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst,
+-- ffc_txpwdnb_ch2 => '1',
+-- ffc_rxpwdnb_ch2 => '1',
+-- ffc_macro_rst => '0',
+-- ffc_quad_rst => ffc_quad_rst,
+-- ffc_trst => '0',
+-- hdoutp2 => sd_txd_p_out,
+-- hdoutn2 => sd_txd_n_out,
+-- ff_rxdata_ch2 => comb_rx_data, --rx_data,
+-- ff_rx_k_cntrl_ch2 => comb_rx_k, --rx_k,
+-- ff_rxfullclk_ch2 => open,
+-- ff_rxhalfclk_ch2 => ff_rxhalfclk,
+-- ff_disp_err_ch2 => open,
+-- ff_cv_ch2 => link_error(7 downto 6),
+-- ffs_rlos_lo_ch2 => link_error(8),
+-- ffs_ls_sync_status_ch2 => link_ok(0),
+-- ffs_cc_underrun_ch2 => link_error(0),
+-- ffs_cc_overrun_ch2 => link_error(1),
+-- ffs_txfbfifo_error_ch2 => link_error(2),
+-- ffs_rxfbfifo_error_ch2 => link_error(3),
+-- ffs_rlol_ch2 => link_error(4),
+-- oob_out_ch2 => open,
+-- ff_txfullclk => open,
+-- ff_txhalfclk => ff_txhalfclk,
+-- refck2core => refck2core,
+-- ffs_plol => link_error(5)
+-- );
+ end generate;
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+port map( read_clock_in => sysclk,
+ write_clock_in => ff_txhalfclk, -- CHANGED
+ read_enable_in => fifo_rx_rd_en,
+ write_enable_in => fifo_rx_wr_en,
+ fifo_gsr_in => fifo_rx_reset,
+ write_data_in => fifo_rx_din,
+ read_data_out => fifo_rx_dout,
+ full_out => fifo_rx_full,
+ empty_out => fifo_rx_empty
+ );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= '1';
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process( ff_txhalfclk ) -- CHANGED
+begin
+ if( rising_edge(ff_txhalfclk) ) then -- CHANGED
+ last_rx <= rx_k(1) & rx_data(15 downto 8);
+ if( swap_bytes = '0' ) then
+ fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+ fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
+ else
+ fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+ fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
+ end if;
+ end if;
+end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out <= rx_counter;
+med_read_out <= tx_allow_q;
+
+THE_SYNC_PROC: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ if reset_i = '1' then
+ med_dataready_out <= '0';
+ else
+ med_dataready_out <= buf_med_dataready_out;
+ med_data_out <= buf_med_data_out;
+ med_packet_num_out <= buf_med_packet_num_out;
+ end if;
+ end if;
+end process THE_SYNC_PROC;
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( sysclk )
+begin
+ if( rising_edge(sysclk) ) then
+ last_fifo_rx_empty <= fifo_rx_empty;
+ if reset_i = '1' or rx_allow_q = '0' then
+ rx_counter <= c_H0;
+ else
+ if( buf_med_dataready_out = '1' ) then
+ if( rx_counter = c_max_word_number ) then
+ rx_counter <= (others => '0');
+ else
+ rx_counter <= rx_counter + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+port map( read_clock_in => ff_txhalfclk,
+ write_clock_in => sysclk,
+ read_enable_in => fifo_tx_rd_en,
+ write_enable_in => fifo_tx_wr_en,
+ fifo_gsr_in => fifo_tx_reset,
+ write_data_in => fifo_tx_din,
+ read_data_out => fifo_tx_dout,
+ full_out => fifo_tx_full,
+ empty_out => fifo_tx_empty
+ );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow;
+
+
+THE_SERDES_INPUT_PROC: process( ff_txhalfclk )
+begin
+ if( rising_edge(ff_txhalfclk) ) then
+ last_fifo_tx_empty <= fifo_tx_empty;
+ if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then
+ tx_data <= x"c5bc";
+ tx_k <= "01";
+-- elsif send_resync = '1' then
+-- tx_data <= x"7F7F";
+-- tx_k <= "00";
+ else
+ tx_data <= fifo_tx_dout(15 downto 0);
+ tx_k <= "00";
+ end if;
+ end if;
+end process THE_SERDES_INPUT_PROC;
+
+--
+
+
+--Generate LED signals
+----------------------
+process(sysclk)
+ begin
+ if rising_edge(sysclk) then
+ led_counter <= led_counter + 1;
+
+ if buf_med_dataready_out = '1' then
+ rx_led <= '1';
+ elsif led_counter = 0 then
+ rx_led <= '0';
+ end if;
+
+ if tx_k(0) = '0' then -- tx_k clock domain crossing!
+ tx_led <= '1';
+ elsif led_counter = 0 then
+ tx_led <= '0';
+ end if;
+
+ end if;
+ end process;
+
+stat_op(15 downto 12) <= buf_stat_op(15 downto 12);
+stat_op(11) <= tx_led; --tx led
+stat_op(10) <= rx_led; --rx led
+stat_op(9 downto 0) <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0) <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(41 downto 24) <= (others => '0');
+stat_debug(42) <= ff_txhalfclk; -- CHANGED
+stat_debug(43) <= ff_txhalfclk; -- CHANGED
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); --link_error(3 downto 0);
+
+--stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits
+--stat_debug(4) <= buf_stat_debug(4); -- alignme
+--stat_debug(5) <= sfp_prsnt_n;
+--stat_debug(6) <= tx_k(0);
+--stat_debug(7) <= tx_k(1);
+--stat_debug(8) <= rx_k_q(0);
+--stat_debug(9) <= rx_k_q(1);
+--stat_debug(18 downto 10) <= link_error;
+--stat_debug(19) <= '0';
+--stat_debug(20) <= link_ok(0);
+--stat_debug(38 downto 21) <= fifo_rx_din;
+--stat_debug(39) <= swap_bytes;
+--stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in
+--stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in
+--stat_debug(42) <= buf_stat_debug(6); -- resync
+--stat_debug(59 downto 43) <= (others => '0');
+--stat_debug(63 downto 60) <= link_error(3 downto 0);
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff