--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+config_compile_frankfurt.pl
\ No newline at end of file
--- /dev/null
+Familyname => 'MachXO3LF',
+Devicename => 'LCMXO3LF-6900C',
+Package => 'CABGA256',
+Speedgrade => '6',
+
+TOPNAME => "padiwa_amps2",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/d/jspc29/lattice/diamond/3.9_x64',
+synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/',
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
+make_jed => 1,
--- /dev/null
+#-- Synopsys, Inc.
+#-- Version J-2015.03L-SP1
+#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt
+
+#project files
+
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.9_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "../source/spi_slave.vhd"
+add_file -vhdl -lib work "../source/Stretcher.vhd"
+add_file -vhdl -lib work "../source/Stretcher_A.vhd"
+add_file -vhdl -lib work "../source/Stretcher_B.vhd"
+
+add_file -vhdl -lib work "../source/pwm.vhd"
+add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
+add_file -vhdl -lib work "padiwa_amps2.vhd"
+
+
+
+#add_file -vhdl -lib work "../cores/flashram.vhd"
+#add_file -vhdl -lib work "../cores/efb.vhd"
+#add_file -verilog -lib work "../cores/efb_define_def.v"
+#add_file -verilog -lib work "../cores/UFM_WB.v"
+#add_file -vhdl -lib work "../code/sedcheck.vhd"
+#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
+
+
+#implementation: "PadiwaAmps2"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+
+#device options
+set_option -technology MACHXO3LF
+set_option -part LCMXO3LF_6900C
+set_option -package BG256C
+set_option -speed_grade -6
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "padiwa_amps2"
+
+# mapper_options
+set_option -frequency 1
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/padiwa_amps2.edf"
+
+#set log file
+set_option log_file "workdir/padiwa_amps2.srf"
+impl -active "workdir"
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+-- use work.trb3_components.all;\r
+use work.version.all;\r
+\r
+library machxo3lf;\r
+use machxo3lf.all;\r
+\r
+\r
+entity padiwa_amps2 is\r
+ generic(\r
+ TEMP_CORRECTION: integer := c_YES\r
+ );\r
+ port(\r
+ OSC_CORE : in std_logic;\r
+ \r
+ CON : out std_logic_vector(16 downto 1);\r
+ INP_FAST : in std_logic_vector(8 downto 1);\r
+ INP_SLOW : in std_logic_vector(8 downto 1);\r
+ PWM : out std_logic_vector(16 downto 1);\r
+ DISCHARGE : out std_logic_vector( 8 downto 1);\r
+\r
+ SPARE_LINE : out std_logic;\r
+ LED : out std_logic_vector( 8 downto 1);\r
+\r
+ SPI_CLK : in std_logic;\r
+ SPI_CS : in std_logic;\r
+ SPI_IN : in std_logic;\r
+ SPI_OUT : out std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ I2C_SDA : inout std_logic;\r
+ TEST_LINE : out std_logic_vector(13 downto 0)\r
+ );\r
+end entity;\r
+\r
+\r
+\r
+architecture arch of padiwa_amps2 is\r
+ constant DELAYDEPTH : integer := 16;\r
+\r
+ attribute NOM_FREQ : string;\r
+ attribute NOM_FREQ of clk_source : label is "133.00";\r
+\r
+ signal clk_i, clk_osc, clk_33,clk_266 : std_logic;\r
+\r
+ type led_timer_t is array(1 to 8) of unsigned(24 downto 0);\r
+ signal led_timer : led_timer_t;\r
+ signal led_state : std_logic_vector(8 downto 1);\r
+\r
+ signal ram_write_i : std_logic;\r
+ signal ram_data_i: std_logic_vector(7 downto 0);\r
+ signal ram_data_o: std_logic_vector(7 downto 0);\r
+ signal ram_addr_i: std_logic_vector(3 downto 0);\r
+ signal temperature_i : std_logic_vector(11 downto 0);\r
+\r
+ \r
+ signal pwm_i : std_logic_vector(32 downto 1);\r
+ signal INP_i : std_logic_vector(15 downto 0);\r
+ signal fast_input : std_logic_vector(8 downto 1);\r
+ signal slow_input : std_logic_vector(8 downto 1);\r
+ signal spi_reg00_i : std_logic_vector(15 downto 0);\r
+ signal spi_reg10_i : std_logic_vector(15 downto 0);\r
+ signal spi_reg20_i : std_logic_vector(15 downto 0);\r
+ signal spi_reg40_i : std_logic_vector(15 downto 0);\r
+ signal spi_data_i : std_logic_vector(15 downto 0);\r
+ signal spi_operation_i : std_logic_vector(3 downto 0);\r
+ signal spi_channel_i : std_logic_vector(7 downto 0);\r
+ signal spi_write_i : std_logic_vector(15 downto 0);\r
+ signal buf_SPI_OUT : std_logic;\r
+ signal spi_debug_i : std_logic_vector(15 downto 0);\r
+ signal last_spi_channel: std_logic_vector(7 downto 0);\r
+\r
+ \r
+\r
+ signal inp_select : integer range 0 to 31 := 0;\r
+ signal inp_invert : std_logic_vector(15 downto 0) := x"aaaa"; --invert slow inputs only\r
+ signal input_enable : std_logic_vector(15 downto 0);\r
+ signal inp_status : std_logic_vector(15 downto 0);\r
+ signal led_status : std_logic_vector(8 downto 0) := "100000000";\r
+ signal discharge_disable : std_logic_vector(8 downto 1);\r
+ signal discharge_highz : std_logic_vector(8 downto 1);\r
+ signal discharge_override : std_logic_vector(8 downto 1);\r
+ signal delay_invert : std_logic_vector(8 downto 1);\r
+\r
+\r
+ signal timer : unsigned(18 downto 0) := (others => '0');\r
+ signal last_inp : std_logic_vector(15 downto 0) := (others => '0');\r
+ signal inp_or : std_logic;\r
+ signal inp_long_or : std_logic;\r
+ signal inp_long_reg : std_logic;\r
+ signal last_inp_long_reg : std_logic;\r
+ \r
+\r
+ signal inp_stretch : std_logic_vector(15 downto 0);\r
+ signal inp_stretched : std_logic_vector(15 downto 0);\r
+ signal inp_hold : std_logic_vector(15 downto 0);\r
+ signal inp_gated : std_logic_vector(15 downto 0);\r
+ signal inp_hold_reg: std_logic_vector(15 downto 0);\r
+ signal last_inp_hold_reg: std_logic_vector(15 downto 0); \r
+\r
+ signal pwm_data_i : std_logic_vector(15 downto 0);\r
+ signal pwm_data_o : std_logic_vector(15 downto 0);\r
+ signal pwm_write_i : std_logic;\r
+ signal pwm_addr_i : std_logic_vector(3 downto 0);\r
+\r
+ signal comp_setting : std_logic_vector(15 downto 0);\r
+ signal compensate_i : signed(15 downto 0);\r
+ signal temp_calc_i : signed(27 downto 0);\r
+ signal temperature_i_s : std_logic_vector(11 downto 0);\r
+ signal comp_setting_s : std_logic_vector(15 downto 0);\r
+\r
+ signal delayed_inputs : std_logic_vector(127 downto 0);\r
+ signal selected_delay : std_logic_vector(8 downto 1);\r
+ signal delayselect : integer range 0 to 15;\r
+ \r
+ component OSCH\r
+ generic (NOM_FREQ: string := "133.00");\r
+ port (\r
+ STDBY :IN std_logic;\r
+ OSC :OUT std_logic;\r
+ SEDSTDBY :OUT std_logic\r
+ );\r
+ end component; \r
+ \r
+ \r
+begin\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock\r
+---------------------------------------------------------------------------\r
+clk_source: OSCH\r
+ generic map ( NOM_FREQ => "133" )\r
+ port map (\r
+ STDBY => '0',\r
+ OSC => clk_osc,\r
+ SEDSTDBY => open\r
+ );\r
+ \r
+THE_PLL : entity work.pll_in133_out33_133_266 \r
+ port map (\r
+ CLKI => clk_osc,\r
+ CLKOP => clk_i, --133\r
+ CLKOS => clk_33, --33 \r
+ CLKOS2=> clk_266 --266\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Input re-ordering\r
+---------------------------------------------------------------------------\r
+ INP_i <= INP_SLOW(8) & INP_FAST(8) & INP_SLOW(7) & INP_FAST(7) &\r
+ INP_SLOW(6) & INP_FAST(6) & INP_SLOW(5) & INP_FAST(5) &\r
+ INP_SLOW(4) & INP_FAST(4) & INP_SLOW(3) & INP_FAST(3) &\r
+ INP_SLOW(2) & INP_FAST(2) & INP_SLOW(1) & INP_FAST(1);\r
+ PWM <= pwm_i(16 downto 1);\r
+ \r
+\r
+ inp_status <= INP_i when rising_edge(clk_i);\r
+ last_inp <= inp_status(15 downto 0) when rising_edge(clk_i);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- SPI Interface\r
+--------------------------------------------------------------------------- \r
+THE_SPI_SLAVE : entity work.spi_slave\r
+ port map(\r
+ CLK => clk_i,\r
+ SPI_CLK => SPI_CLK,\r
+ SPI_CS => SPI_CS,\r
+ SPI_IN => SPI_IN,\r
+ SPI_OUT => buf_SPI_OUT,\r
+ DATA_OUT => spi_data_i,\r
+ REG00_IN => spi_reg00_i,\r
+ REG10_IN => spi_reg10_i,\r
+ REG20_IN => spi_reg20_i,\r
+ REG40_IN => spi_reg40_i,\r
+ OPERATION_OUT => spi_operation_i,\r
+ CHANNEL_OUT => spi_channel_i,\r
+ WRITE_OUT => spi_write_i,\r
+ DEBUG_OUT => spi_debug_i\r
+ );\r
+\r
+SPI_OUT <= buf_SPI_OUT; \r
+\r
+spi_reg00_i <= pwm_data_o;\r
+-- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
+-- spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;\r
+spi_reg10_i <= (others => '0');\r
+spi_reg40_i <= '0' & '0' & "000000" & ram_data_o;\r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- RAM Interface\r
+--------------------------------------------------------------------------- \r
+\r
+---------------------------------------------------------------------------\r
+-- Flash Controller\r
+--------------------------------------------------------------------------- \r
+\r
+---------------------------------------------------------------------------\r
+-- Temperature and UID reader\r
+--------------------------------------------------------------------------- \r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Temperature Compensation\r
+--------------------------------------------------------------------------- \r
+temperature_i_s <= temperature_i when rising_edge(clk_33);\r
+comp_setting_s <= comp_setting when rising_edge(clk_33);\r
+temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_33);\r
+\r
+gen_comp: if TEMP_CORRECTION = 1 generate\r
+ compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_33);\r
+end generate;\r
+gen_no_comp: if TEMP_CORRECTION = 0 generate\r
+ compensate_i <= (others => '0');\r
+end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- I/O Register 0x20\r
+--------------------------------------------------------------------------- \r
+THE_IO_REG_READ : process begin\r
+ wait until rising_edge(clk_i);\r
+ if spi_channel_i(4) = '0' then\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => spi_reg20_i <= input_enable;\r
+ when x"1" => spi_reg20_i <= inp_status;\r
+ when x"2" => spi_reg20_i <= x"0" & "000" & led_status(8) & led_state ;\r
+ when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
+ when x"4" => spi_reg20_i <= inp_invert;\r
+ when x"5" => spi_reg20_i <= inp_stretch;\r
+ when x"6" => spi_reg20_i <= comp_setting;\r
+ when x"7" => spi_reg20_i <= x"00" & discharge_disable;\r
+ when x"8" => spi_reg20_i <= x"00" & discharge_override;\r
+ when x"9" => spi_reg20_i <= x"00" & discharge_highz;\r
+ when x"a" => spi_reg20_i <= x"00" & delay_invert;\r
+ when x"b" => spi_reg20_i <= x"00" & std_logic_vector(to_unsigned(delayselect,8));\r
+-- when x"f" => spi_reg20_i <= ffarr_data; \r
+ when others => null;\r
+ end case;\r
+ else\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
+ when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+ when x"2" => spi_reg20_i <= x"0000";\r
+ when others => null;\r
+ end case;\r
+ end if;\r
+end process;\r
+\r
+THE_IO_REG_WRITE : process begin\r
+ wait until rising_edge(clk_i);\r
+ if spi_write_i(2) = '1' then\r
+ case spi_channel_i(3 downto 0) is\r
+ when x"0" => input_enable <= spi_data_i;\r
+ when x"1" => null;\r
+ when x"2" => led_status <= spi_data_i(8 downto 0);\r
+ when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));\r
+ when x"4" => inp_invert <= spi_data_i;\r
+ when x"5" => inp_stretch <= spi_data_i;\r
+ when x"6" => comp_setting <= spi_data_i;\r
+ when x"7" => discharge_disable <= spi_data_i(7 downto 0);\r
+ when x"8" => discharge_override <= spi_data_i(7 downto 0);\r
+ when x"9" => discharge_highz <= spi_data_i(7 downto 0);\r
+ when x"a" => delay_invert <= spi_data_i(7 downto 0);\r
+ when x"b" => delayselect <= to_integer(unsigned(spi_data_i(7 downto 0)));\r
+ when others => null;\r
+ end case;\r
+ end if;\r
+end process;\r
+\r
+---------------------------------------------------------------------------\r
+-- PWM\r
+--------------------------------------------------------------------------- \r
+\r
+THE_PWM_GEN : entity work.pwm_generator\r
+ port map(\r
+ CLK => clk_i,\r
+ DATA_IN => pwm_data_i,\r
+ DATA_OUT => pwm_data_o,\r
+ COMP_IN => compensate_i,\r
+ WRITE_IN => pwm_write_i,\r
+ ADDR_IN => pwm_addr_i,\r
+ PWM => pwm_i\r
+ );\r
+\r
+\r
+\r
+-- PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,\r
+-- pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,\r
+-- ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i)\r
+-- begin\r
+-- if(fsm_copydat = IDLE) then\r
+ pwm_data_i <= spi_data_i;\r
+ pwm_write_i <= spi_write_i(0);\r
+ pwm_addr_i <= spi_channel_i(3 downto 0);\r
+ ram_write_i <= spi_write_i(4);\r
+ ram_data_i <= spi_data_i(7 downto 0);\r
+ ram_addr_i <= spi_channel_i(3 downto 0);\r
+-- else\r
+-- pwm_data_i <= pwm_fsm_data_i;\r
+-- pwm_write_i <= pwm_fsm_write;\r
+-- pwm_addr_i <= pwm_fsm_addr;\r
+-- ram_write_i <= ram_fsm_write_i;\r
+-- ram_data_i <= ram_fsm_data_i;\r
+-- ram_addr_i <= ram_fsm_addr_i;\r
+-- end if;\r
+-- end process;\r
+\r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ PROC_LED_STATE : process begin\r
+ wait until rising_edge(clk_i);\r
+ for i in 1 to 8 loop\r
+ if (last_inp(i/2+1) xor inp_status(i/2+1)) = '1' and (led_timer(i)(23 downto 21) > 0) then\r
+ led_state(i) <= not led_state(i);\r
+ led_timer(i) <= 0;\r
+ elsif led_timer(i)(23) = '1' then\r
+ led_state(i) <= inp_status(i/2+1);\r
+ else\r
+ led_timer(i) <= led_timer(i) + 1;\r
+ end if;\r
+ end loop;\r
+ end process; \r
+\r
+ LED <= led_state;\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- Rest of the I/O\r
+---------------------------------------------------------------------------\r
+\r
+inp_gated <= (INP_i xor inp_invert) and not input_enable;\r
+CON <= inp_gated or (inp_stretched and inp_stretch);\r
+\r
+\r
+inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg;\r
+inp_hold_reg <= inp_hold when rising_edge(clk_i);\r
+last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i);\r
+inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold;\r
+\r
+fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0);\r
+slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1);\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Stretcher\r
+---------------------------------------------------------------------------\r
+THE_STRETCHER : entity work.Stretcher\r
+ generic map(\r
+ CHANNEL => 8,\r
+ DEPTH => DELAYDEPTH\r
+ )\r
+ port map(\r
+ PULSE_IN => fast_input,\r
+ PULSE_OUT => delayed_inputs\r
+ );\r
+ \r
+ \r
+---------------------------------------------------------------------------\r
+-- Discharge\r
+--------------------------------------------------------------------------- \r
+gen_discharge : for i in 1 to 8 generate\r
+ process (slow_input, selected_delay)\r
+ begin\r
+ if (slow_input(i)='0') then\r
+ DISCHARGE(i)<='0'; \r
+ elsif (selected_delay(i)='1') then\r
+ DISCHARGE(i)<='1';\r
+ end if;\r
+ end process;\r
+\r
+ selected_delay(i) <= delayed_inputs(i*DELAYDEPTH-1-delayselect);\r
+end generate;\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Trigger Output\r
+--------------------------------------------------------------------------- \r
+SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg)\r
+ begin\r
+ if inp_select < 16 then\r
+ SPARE_LINE <= INP_i(inp_select);\r
+ elsif inp_select < 24 then\r
+ SPARE_LINE <= inp_or;\r
+ else\r
+ SPARE_LINE <= inp_long_reg or last_inp_long_reg or inp_long_or ;\r
+ end if;\r
+ end process;\r
+\r
+inp_or <= or_all((INP_i xor inp_invert) and not input_enable);\r
+inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg;\r
+inp_long_reg <= inp_long_or when rising_edge(clk_i);\r
+last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);\r
+\r
+---------------------------------------------------------------------------\r
+-- Test Output\r
+--------------------------------------------------------------------------- \r
+ TEST_LINE(7 downto 0) <= selected_delay;\r
+ TEST_LINE(13 downto 8) <= (others => '0');\r
+end architecture;\r
+\r
+\r
+\r
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 1
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
--- /dev/null
+(edif pll_in133_out33_133_266
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2016 4 25 11 53 34)
+ (program "SCUBA" (version "Diamond (64-bit) 3.7.0.96.1"))))
+ (comment "/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_in133_out33_133_266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkos 33 -fclkos_tol 1.0 -fclkos2 266 -fclkos2_tol 0.0 -bypassp -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2 ")
+ (library ORCLIB
+ (edifLevel 0)
+ (technology
+ (numberDefinition))
+ (cell VLO
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port Z
+ (direction OUTPUT)))))
+ (cell EHXPLLJ
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port CLKI
+ (direction INPUT))
+ (port CLKFB
+ (direction INPUT))
+ (port PHASESEL1
+ (direction INPUT))
+ (port PHASESEL0
+ (direction INPUT))
+ (port PHASEDIR
+ (direction INPUT))
+ (port PHASESTEP
+ (direction INPUT))
+ (port LOADREG
+ (direction INPUT))
+ (port STDBY
+ (direction INPUT))
+ (port PLLWAKESYNC
+ (direction INPUT))
+ (port RST
+ (direction INPUT))
+ (port RESETM
+ (direction INPUT))
+ (port RESETC
+ (direction INPUT))
+ (port RESETD
+ (direction INPUT))
+ (port ENCLKOP
+ (direction INPUT))
+ (port ENCLKOS
+ (direction INPUT))
+ (port ENCLKOS2
+ (direction INPUT))
+ (port ENCLKOS3
+ (direction INPUT))
+ (port PLLCLK
+ (direction INPUT))
+ (port PLLRST
+ (direction INPUT))
+ (port PLLSTB
+ (direction INPUT))
+ (port PLLWE
+ (direction INPUT))
+ (port PLLADDR4
+ (direction INPUT))
+ (port PLLADDR3
+ (direction INPUT))
+ (port PLLADDR2
+ (direction INPUT))
+ (port PLLADDR1
+ (direction INPUT))
+ (port PLLADDR0
+ (direction INPUT))
+ (port PLLDATI7
+ (direction INPUT))
+ (port PLLDATI6
+ (direction INPUT))
+ (port PLLDATI5
+ (direction INPUT))
+ (port PLLDATI4
+ (direction INPUT))
+ (port PLLDATI3
+ (direction INPUT))
+ (port PLLDATI2
+ (direction INPUT))
+ (port PLLDATI1
+ (direction INPUT))
+ (port PLLDATI0
+ (direction INPUT))
+ (port CLKOP
+ (direction OUTPUT))
+ (port CLKOS
+ (direction OUTPUT))
+ (port CLKOS2
+ (direction OUTPUT))
+ (port CLKOS3
+ (direction OUTPUT))
+ (port LOCK
+ (direction OUTPUT))
+ (port INTLOCK
+ (direction OUTPUT))
+ (port REFCLK
+ (direction OUTPUT))
+ (port CLKINTFB
+ (direction OUTPUT))
+ (port DPHSRC
+ (direction OUTPUT))
+ (port PLLACK
+ (direction OUTPUT))
+ (port PLLDATO7
+ (direction OUTPUT))
+ (port PLLDATO6
+ (direction OUTPUT))
+ (port PLLDATO5
+ (direction OUTPUT))
+ (port PLLDATO4
+ (direction OUTPUT))
+ (port PLLDATO3
+ (direction OUTPUT))
+ (port PLLDATO2
+ (direction OUTPUT))
+ (port PLLDATO1
+ (direction OUTPUT))
+ (port PLLDATO0
+ (direction OUTPUT)))))
+ (cell pll_in133_out33_133_266
+ (cellType GENERIC)
+ (view view1
+ (viewType NETLIST)
+ (interface
+ (port CLKI
+ (direction INPUT))
+ (port CLKOP
+ (direction OUTPUT))
+ (port CLKOS
+ (direction OUTPUT))
+ (port CLKOS2
+ (direction OUTPUT)))
+ (property NGD_DRC_MASK (integer 1))
+ (contents
+ (instance scuba_vlo_inst
+ (viewRef view1
+ (cellRef VLO)))
+ (instance PLLInst_0
+ (viewRef view1
+ (cellRef EHXPLLJ))
+ (property DDRST_ENA
+ (string "DISABLED"))
+ (property DCRST_ENA
+ (string "DISABLED"))
+ (property MRST_ENA
+ (string "DISABLED"))
+ (property PLLRST_ENA
+ (string "DISABLED"))
+ (property INTFB_WAKE
+ (string "DISABLED"))
+ (property STDBY_ENABLE
+ (string "DISABLED"))
+ (property DPHASE_SOURCE
+ (string "DISABLED"))
+ (property PLL_USE_WB
+ (string "DISABLED"))
+ (property CLKOS3_FPHASE
+ (string "0"))
+ (property CLKOS3_CPHASE
+ (string "0"))
+ (property CLKOS2_FPHASE
+ (string "0"))
+ (property CLKOS2_CPHASE
+ (string "1"))
+ (property CLKOS_FPHASE
+ (string "0"))
+ (property CLKOS_CPHASE
+ (string "15"))
+ (property CLKOP_FPHASE
+ (string "0"))
+ (property CLKOP_CPHASE
+ (string "0"))
+ (property PLL_LOCK_MODE
+ (string "0"))
+ (property CLKOS_TRIM_DELAY
+ (string "0"))
+ (property CLKOS_TRIM_POL
+ (string "RISING"))
+ (property CLKOP_TRIM_DELAY
+ (string "0"))
+ (property CLKOP_TRIM_POL
+ (string "FALLING"))
+ (property FRACN_DIV
+ (string "0"))
+ (property FRACN_ENABLE
+ (string "DISABLED"))
+ (property OUTDIVIDER_MUXD2
+ (string "DIVD"))
+ (property PREDIVIDER_MUXD1
+ (string "0"))
+ (property VCO_BYPASS_D0
+ (string "DISABLED"))
+ (property CLKOS3_ENABLE
+ (string "DISABLED"))
+ (property FREQUENCY_PIN_CLKOS2
+ (string "266.000000"))
+ (property OUTDIVIDER_MUXC2
+ (string "DIVC"))
+ (property PREDIVIDER_MUXC1
+ (string "0"))
+ (property VCO_BYPASS_C0
+ (string "DISABLED"))
+ (property CLKOS2_ENABLE
+ (string "ENABLED"))
+ (property FREQUENCY_PIN_CLKOS
+ (string "33.250000"))
+ (property OUTDIVIDER_MUXB2
+ (string "DIVB"))
+ (property PREDIVIDER_MUXB1
+ (string "0"))
+ (property VCO_BYPASS_B0
+ (string "DISABLED"))
+ (property CLKOS_ENABLE
+ (string "ENABLED"))
+ (property FREQUENCY_PIN_CLKOP
+ (string "133.000000"))
+ (property OUTDIVIDER_MUXA2
+ (string "REFCLK"))
+ (property PREDIVIDER_MUXA1
+ (string "0"))
+ (property VCO_BYPASS_A0
+ (string "DISABLED"))
+ (property CLKOP_ENABLE
+ (string "ENABLED"))
+ (property FREQUENCY_PIN_CLKI
+ (string "133.000000"))
+ (property ICP_CURRENT
+ (string "8"))
+ (property LPF_RESISTOR
+ (string "8"))
+ (property CLKOS3_DIV
+ (string "1"))
+ (property CLKOS2_DIV
+ (string "2"))
+ (property CLKOS_DIV
+ (string "16"))
+ (property CLKOP_DIV
+ (string "1"))
+ (property CLKFB_DIV
+ (string "1"))
+ (property CLKI_DIV
+ (string "4"))
+ (property FEEDBK_PATH
+ (string "CLKOS")))
+ (net LOCK
+ (joined
+ (portRef LOCK (instanceRef PLLInst_0))))
+ (net scuba_vlo
+ (joined
+ (portRef Z (instanceRef scuba_vlo_inst))
+ (portRef PLLADDR4 (instanceRef PLLInst_0))
+ (portRef PLLADDR3 (instanceRef PLLInst_0))
+ (portRef PLLADDR2 (instanceRef PLLInst_0))
+ (portRef PLLADDR1 (instanceRef PLLInst_0))
+ (portRef PLLADDR0 (instanceRef PLLInst_0))
+ (portRef PLLDATI7 (instanceRef PLLInst_0))
+ (portRef PLLDATI6 (instanceRef PLLInst_0))
+ (portRef PLLDATI5 (instanceRef PLLInst_0))
+ (portRef PLLDATI4 (instanceRef PLLInst_0))
+ (portRef PLLDATI3 (instanceRef PLLInst_0))
+ (portRef PLLDATI2 (instanceRef PLLInst_0))
+ (portRef PLLDATI1 (instanceRef PLLInst_0))
+ (portRef PLLDATI0 (instanceRef PLLInst_0))
+ (portRef PLLWE (instanceRef PLLInst_0))
+ (portRef PLLSTB (instanceRef PLLInst_0))
+ (portRef PLLRST (instanceRef PLLInst_0))
+ (portRef PLLCLK (instanceRef PLLInst_0))
+ (portRef ENCLKOS3 (instanceRef PLLInst_0))
+ (portRef ENCLKOS2 (instanceRef PLLInst_0))
+ (portRef ENCLKOS (instanceRef PLLInst_0))
+ (portRef ENCLKOP (instanceRef PLLInst_0))
+ (portRef RESETD (instanceRef PLLInst_0))
+ (portRef RESETC (instanceRef PLLInst_0))
+ (portRef RESETM (instanceRef PLLInst_0))
+ (portRef RST (instanceRef PLLInst_0))
+ (portRef PLLWAKESYNC (instanceRef PLLInst_0))
+ (portRef STDBY (instanceRef PLLInst_0))
+ (portRef LOADREG (instanceRef PLLInst_0))
+ (portRef PHASESTEP (instanceRef PLLInst_0))
+ (portRef PHASEDIR (instanceRef PLLInst_0))
+ (portRef PHASESEL1 (instanceRef PLLInst_0))
+ (portRef PHASESEL0 (instanceRef PLLInst_0))))
+ (net CLKOS2
+ (joined
+ (portRef CLKOS2)
+ (portRef CLKOS2 (instanceRef PLLInst_0))))
+ (net CLKOS
+ (joined
+ (portRef CLKOS)
+ (portRef CLKFB (instanceRef PLLInst_0))
+ (portRef CLKOS (instanceRef PLLInst_0))))
+ (net CLKOP
+ (joined
+ (portRef CLKOP)
+ (portRef CLKOP (instanceRef PLLInst_0))))
+ (net CLKI
+ (joined
+ (portRef CLKI)
+ (portRef CLKI (instanceRef PLLInst_0))))))))
+ (design pll_in133_out33_133_266
+ (cellRef pll_in133_out33_133_266
+ (libraryRef ORCLIB)))
+)
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in133_out33_133_266" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 04 25 11:53:39.446" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_in133_out33_133_266.lpc" type="lpc" modified="2016 04 25 11:53:34.000"/>
+ <File name="pll_in133_out33_133_266.vhd" type="top_level_vhdl" modified="2016 04 25 11:53:34.000"/>
+ <File name="pll_in133_out33_133_266_tmpl.vhd" type="template_vhdl" modified="2016 04 25 11:53:34.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-1300C
+PartName=LCMXO3LF-1300C-5BG256C
+SpeedGrade=5
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_in133_out33_133_266
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/25/2016
+Time=11:53:34
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+mode=Frequency
+CLKI=133
+CLKI_DIV=4
+BW=3.223
+VCO=532.000
+fb_mode=CLKOS
+CLKFB_DIV=1
+FRACN_ENABLE=0
+FRACN_DIV=0
+DynamicPhase=STATIC
+ClkEnable=0
+Standby=0
+Enable_sel=0
+PLLRst=0
+PLLMRst=0
+ClkOS2Rst=0
+ClkOS3Rst=0
+LockSig=0
+LockStk=0
+WBProt=0
+OPBypass=1
+OPUseDiv=0
+CLKOP_DIV=1
+FREQ_PIN_CLKOP=133
+OP_Tol=0.0
+CLKOP_AFREQ=133.000000
+CLKOP_PHASEADJ=0
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+EnCLKOS=1
+OSBypass=0
+OSUseDiv=0
+CLKOS_DIV=16
+FREQ_PIN_CLKOS=33
+OS_Tol=1.0
+CLKOS_AFREQ=33.250000
+CLKOS_PHASEADJ=0
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+EnCLKOS2=1
+OS2Bypass=0
+OS2UseDiv=0
+CLKOS2_DIV=2
+FREQ_PIN_CLKOS2=266
+OS2_Tol=0.0
+CLKOS2_AFREQ=266.000000
+CLKOS2_PHASEADJ=0
+EnCLKOS3=0
+OS3Bypass=0
+OS3UseDiv=0
+CLKOS3_DIV=1
+FREQ_PIN_CLKOS3=100
+OS3_Tol=0.0
+CLKOS3_AFREQ=
+CLKOS3_PHASEADJ=0
+
+[Command]
+cmd_line= -w -n pll_in133_out33_133_266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkos 33 -fclkos_tol 1.0 -fclkos2 266 -fclkos2_tol 0.0 -bypassp -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_in133_out33_133_266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 133 -fclkos 33 -fclkos_tol 1.0 -fclkos2 266 -fclkos2_tol 0.0 -bypassp -trims 0 -phases 0 -trims_r -phases2 0 -phase_cntl STATIC -fb_mode 2
+
+-- Mon Apr 25 11:53:34 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity pll_in133_out33_133_266 is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ CLKOS2: out std_logic);
+end pll_in133_out33_133_266;
+
+architecture Structure of pll_in133_out33_133_266 is
+
+ -- internal signal declarations
+ signal LOCK: std_logic;
+ signal CLKOS2_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal CLKOS_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLJ
+ generic (INTFB_WAKE : in String; DDRST_ENA : in String;
+ DCRST_ENA : in String; MRST_ENA : in String;
+ PLLRST_ENA : in String; DPHASE_SOURCE : in String;
+ STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
+ OUTDIVIDER_MUXC2 : in String;
+ OUTDIVIDER_MUXB2 : in String;
+ OUTDIVIDER_MUXA2 : in String;
+ PREDIVIDER_MUXD1 : in Integer;
+ PREDIVIDER_MUXC1 : in Integer;
+ PREDIVIDER_MUXB1 : in Integer;
+ PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
+ PLL_LOCK_MODE : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
+ FRACN_ENABLE : in String; FEEDBK_PATH : in String;
+ CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
+ CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
+ CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
+ CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
+ VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
+ VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
+ CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
+ CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
+ CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
+ CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ PHASESEL1: in std_logic; PHASESEL0: in std_logic;
+ PHASEDIR: in std_logic; PHASESTEP: in std_logic;
+ LOADREG: in std_logic; STDBY: in std_logic;
+ PLLWAKESYNC: in std_logic; RST: in std_logic;
+ RESETM: in std_logic; RESETC: in std_logic;
+ RESETD: in std_logic; ENCLKOP: in std_logic;
+ ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
+ ENCLKOS3: in std_logic; PLLCLK: in std_logic;
+ PLLRST: in std_logic; PLLSTB: in std_logic;
+ PLLWE: in std_logic; PLLADDR4: in std_logic;
+ PLLADDR3: in std_logic; PLLADDR2: in std_logic;
+ PLLADDR1: in std_logic; PLLADDR0: in std_logic;
+ PLLDATI7: in std_logic; PLLDATI6: in std_logic;
+ PLLDATI5: in std_logic; PLLDATI4: in std_logic;
+ PLLDATI3: in std_logic; PLLDATI2: in std_logic;
+ PLLDATI1: in std_logic; PLLDATI0: in std_logic;
+ CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOS2: out std_logic; CLKOS3: out std_logic;
+ LOCK: out std_logic; INTLOCK: out std_logic;
+ REFCLK: out std_logic; CLKINTFB: out std_logic;
+ DPHSRC: out std_logic; PLLACK: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOS2 : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "266.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "33.250000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "133.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "133.000000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "8";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLJ
+ generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
+ MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0,
+ CLKOS2_FPHASE=> 0, CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 0,
+ CLKOS_CPHASE=> 15, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 0,
+ PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", FRACN_DIV=> 0,
+ FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
+ PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
+ CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB",
+ PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXA2=> "REFCLK", PREDIVIDER_MUXA1=> 0,
+ VCO_BYPASS_A0=> "DISABLED", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
+ CLKOS2_DIV=> 2, CLKOS_DIV=> 16, CLKOP_DIV=> 1, CLKFB_DIV=> 1,
+ CLKI_DIV=> 4, FEEDBK_PATH=> "CLKOS")
+ port map (CLKI=>CLKI, CLKFB=>CLKOS_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
+ PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
+ RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
+ ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
+ PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
+ PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
+ PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
+ PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
+ PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
+ PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
+ PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
+ PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
+ CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
+ REFCLK=>open, CLKINTFB=>open, DPHSRC=>open, PLLACK=>open,
+ PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
+ PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
+ PLLDATO1=>open, PLLDATO0=>open);
+
+ CLKOS2 <= CLKOS2_t;
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library MACHXO3L;
+configuration Structure_CON of pll_in133_out33_133_266 is
+ for Structure
+ for all:VLO use entity MACHXO3L.VLO(V); end for;
+ for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+BLOCK RESETPATHS ;\r
+BLOCK ASYNCPATHS ;\r
+BLOCK RD_DURING_WR_PATHS ;\r
+\r
+#################################################################\r
+# Basic Settings\r
+#################################################################\r
+\r
+SYSCONFIG MCCLK_FREQ = 133.00 JTAG_PORT = ENABLE;\r
+FREQUENCY NET clk_i 133 MHz;\r
+#FREQUENCY NET clk_i_inferred_clock 133 MHz;\r
+# \r
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
+# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;\r
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
+\r
+MULTICYCLE FROM PORT "SPI_*" 20.000000 ns ;\r
+MULTICYCLE TO PORT "SPI_*" 20.000000 ns ;\r
+\r
+\r
+BANK 0 VCCIO 3.3 V;\r
+\r
+\r
+#################################################################\r
+# I/O\r
+#################################################################\r
+LOCATE COMP "CON_1" SITE "A3";\r
+LOCATE COMP "CON_2" SITE "A4";\r
+LOCATE COMP "CON_3" SITE "A5";\r
+LOCATE COMP "CON_4" SITE "C4";\r
+LOCATE COMP "CON_5" SITE "D6";\r
+LOCATE COMP "CON_6" SITE "B7";\r
+LOCATE COMP "CON_7" SITE "E6";\r
+LOCATE COMP "CON_8" SITE "F7";\r
+LOCATE COMP "CON_9" SITE "F8";\r
+LOCATE COMP "CON_10" SITE "B9";\r
+LOCATE COMP "CON_11" SITE "D10";\r
+LOCATE COMP "CON_12" SITE "F9";\r
+LOCATE COMP "CON_13" SITE "A11";\r
+LOCATE COMP "CON_14" SITE "B11";\r
+LOCATE COMP "CON_15" SITE "C12";\r
+LOCATE COMP "CON_16" SITE "B13";\r
+DEFINE PORT GROUP "CON_group" "CON*" ;\r
+IOBUF GROUP "CON_group" IO_TYPE=LVDS25;\r
+\r
+\r
+LOCATE COMP "DISCHARGE_1" SITE "T4";\r
+LOCATE COMP "DISCHARGE_2" SITE "N6";\r
+LOCATE COMP "DISCHARGE_3" SITE "N7";\r
+LOCATE COMP "DISCHARGE_4" SITE "M6";\r
+LOCATE COMP "DISCHARGE_5" SITE "M8";\r
+LOCATE COMP "DISCHARGE_6" SITE "L10";\r
+LOCATE COMP "DISCHARGE_7" SITE "P12";\r
+LOCATE COMP "DISCHARGE_8" SITE "T13";\r
+DEFINE PORT GROUP "DISCHARGE_group" "DISCHARGE*" ;\r
+IOBUF GROUP "DISCHARGE_group" IO_TYPE=LVCMOS33 DRIVE=12 SLEWRATE=SLOW;\r
+\r
+LOCATE COMP "I2C_SCL" SITE "A9";\r
+LOCATE COMP "I2C_SDA" SITE "C9";\r
+IOBUF PORT "I2C_SCL" IO_TYPE=LVTTL33 PULLMODE=UP;\r
+IOBUF PORT "I2C_SDA" IO_TYPE=LVTTL33 PULLMODE=UP;\r
+\r
+LOCATE COMP "LED_1" SITE "P16";\r
+LOCATE COMP "LED_2" SITE "N15";\r
+LOCATE COMP "LED_3" SITE "M16";\r
+LOCATE COMP "LED_4" SITE "M15";\r
+LOCATE COMP "LED_5" SITE "L16";\r
+LOCATE COMP "LED_6" SITE "K15";\r
+LOCATE COMP "LED_7" SITE "J15";\r
+LOCATE COMP "LED_8" SITE "G15";\r
+DEFINE PORT GROUP "LED_group" "LED*" ;\r
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33 DRIVE=8;\r
+\r
+LOCATE COMP "OSC_CORE" SITE "H14";\r
+IOBUF PORT "OSC_CORE" IO_TYPE=LVDS25; #DIFFRESISTOR=100;\r
+\r
+LOCATE COMP "INP_FAST_1" SITE "T2";\r
+LOCATE COMP "INP_FAST_2" SITE "R5";\r
+LOCATE COMP "INP_FAST_3" SITE "P6";\r
+LOCATE COMP "INP_FAST_4" SITE "T7";\r
+LOCATE COMP "INP_FAST_5" SITE "R9";\r
+LOCATE COMP "INP_FAST_6" SITE "P10";\r
+LOCATE COMP "INP_FAST_7" SITE "R11";\r
+LOCATE COMP "INP_FAST_8" SITE "R13";\r
+LOCATE COMP "INP_SLOW_1" SITE "T3";\r
+LOCATE COMP "INP_SLOW_2" SITE "T5";\r
+LOCATE COMP "INP_SLOW_3" SITE "R7";\r
+LOCATE COMP "INP_SLOW_4" SITE "P8";\r
+LOCATE COMP "INP_SLOW_5" SITE "T9";\r
+LOCATE COMP "INP_SLOW_6" SITE "T11";\r
+LOCATE COMP "INP_SLOW_7" SITE "R12";\r
+LOCATE COMP "INP_SLOW_8" SITE "T15";\r
+DEFINE PORT GROUP "INP_group" "INP*" ;\r
+IOBUF GROUP "INP_group" IO_TYPE=LVDS25;\r
+\r
+LOCATE COMP "PWM_1" SITE "K1";\r
+LOCATE COMP "PWM_2" SITE "F1";\r
+LOCATE COMP "PWM_3" SITE "F3";\r
+LOCATE COMP "PWM_4" SITE "F2";\r
+LOCATE COMP "PWM_5" SITE "K2";\r
+LOCATE COMP "PWM_6" SITE "L4";\r
+LOCATE COMP "PWM_7" SITE "H6";\r
+LOCATE COMP "PWM_8" SITE "J4";\r
+LOCATE COMP "PWM_9" SITE "G11";\r
+LOCATE COMP "PWM_10" SITE "G6";\r
+LOCATE COMP "PWM_11" SITE "H11";\r
+LOCATE COMP "PWM_12" SITE "F12";\r
+LOCATE COMP "PWM_13" SITE "K14";\r
+LOCATE COMP "PWM_14" SITE "F14";\r
+LOCATE COMP "PWM_15" SITE "K16";\r
+LOCATE COMP "PWM_16" SITE "F16";\r
+DEFINE PORT GROUP "PWM_group" "PWM*" ;\r
+IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW;\r
+\r
+LOCATE COMP "SPARE_LINE" SITE "D8";\r
+IOBUF PORT "SPARE_LINE" IO_TYPE=LVDS25;\r
+\r
+LOCATE COMP "SPI_CLK" SITE "D16";\r
+LOCATE COMP "SPI_CS" SITE "C15";\r
+LOCATE COMP "SPI_IN" SITE "D14";\r
+LOCATE COMP "SPI_OUT" SITE "B14";\r
+IOBUF PORT "SPI_CLK" IO_TYPE=LVDS25; #DIFFRESISTOR=100\r
+IOBUF PORT "SPI_CS" IO_TYPE=LVDS25; #DIFFRESISTOR=100\r
+IOBUF PORT "SPI_IN" IO_TYPE=LVDS25; #DIFFRESISTOR=100\r
+IOBUF PORT "SPI_OUT" IO_TYPE=LVDS25;\r
+\r
+\r
+\r
+LOCATE COMP "TEST_LINE_0" SITE "D2";\r
+LOCATE COMP "TEST_LINE_1" SITE "D1";\r
+LOCATE COMP "TEST_LINE_2" SITE "E2";\r
+LOCATE COMP "TEST_LINE_3" SITE "E1";\r
+LOCATE COMP "TEST_LINE_4" SITE "G1";\r
+LOCATE COMP "TEST_LINE_5" SITE "H2";\r
+LOCATE COMP "TEST_LINE_6" SITE "H1";\r
+LOCATE COMP "TEST_LINE_7" SITE "J2";\r
+LOCATE COMP "TEST_LINE_8" SITE "J1";\r
+LOCATE COMP "TEST_LINE_9" SITE "L2";\r
+LOCATE COMP "TEST_LINE_10" SITE "M2";\r
+LOCATE COMP "TEST_LINE_11" SITE "M1";\r
+LOCATE COMP "TEST_LINE_12" SITE "N2";\r
+LOCATE COMP "TEST_LINE_13" SITE "P2";\r
+DEFINE PORT GROUP "TEST_group" "TEST*" ;\r
+IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS33 DRIVE=8 PULLMODE=UP ;\r
+\r
+LOCATE COMP "TMP_ALERT" SITE "A8";\r
+IOBUF PORT "TMP_ALERT" IO_TYPE=LVTTL33 PULLMODE=UP;\r
jspc29 / padiwa.git / commitdiff