added included features map to trb3_gbe design

diff --git a/trb3_gbe/config.vhd b/trb3_gbe/config.vhd
index 901f1fa7a66c7a9c37672caef2f73bc226251a58..cabbe2702891974e9990bdd1a4dc3984190cb336 120000 (symlink)
--- a/trb3_gbe/config.vhd
+++ b/trb3_gbe/config.vhd
@@ -1 +1 @@
-config_125.vhd
\ No newline at end of file
+config_default.vhd
\ No newline at end of file

diff --git a/trb3_gbe/config_125.vhd b/trb3_gbe/config_125.vhd
index 1f5a7e2d6603669d0459d1d8446fd045db5276f9..0dcdbe1ec58aa50b2b744d6f6cb133d673269aba 100644 (file)
--- a/trb3_gbe/config_125.vhd
+++ b/trb3_gbe/config_125.vhd
@@ -39,12 +39,14 @@ package config is
 
 --Statistics for generated trigger signals?
     constant INCLUDE_STATISTICS     : integer := c_YES;
+    constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;
+    constant PHYSICAL_INPUTS        : integer := 16;
     
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
 
-
+function generateIncludedFeatures return std_logic_vector;
 
 
 -- Be careful when setting the MII_NUMBER and MII_IS_* generics!
@@ -95,8 +97,6 @@ package config is
     constant CLOCK_FREQUENCY_ARR  : hub_mii_t := (100,125);
     constant MEDIA_FREQUENCY_ARR  : hub_mii_t := (200,125);
                           
-    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0) := (others => '0');       
-                          
                           
   --declare constants, filled in body                          
     constant INTERNAL_NUM         : integer;
@@ -109,11 +109,29 @@ package config is
     constant USED_CHANNELS        : hub_channel_config_t;
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
-
+    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0);
+    
+         
 end;
 
 package body config is
---compute correct configuration mode
+  --compute correct configuration mode
+  function generateIncludedFeatures return std_logic_vector is
+    variable t : std_logic_vector(63 downto 0);
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+    t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+    t(17 downto 17) := std_logic_vector(to_unsigned(1,1)); --sctrl via GbE
+    t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+    t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function; 
+
   constant CFG_MODE : integer := USE_ETHERNET;
   constant HW_INFO_MODE : integer := USE_ETHERNET + 2 * USE_RXCLOCK + 4 * USE_SCTRL_ONLY;
 
@@ -127,5 +145,5 @@ package body config is
   constant USED_CHANNELS        : hub_channel_config_t := USED_CHANNELS_ARR(USE_SCTRL_ONLY);
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
-  
+  constant INCLUDED_FEATURES    : std_logic_vector := generateIncludedFeatures;   
 end package body;

diff --git a/trb3_gbe/config_default.vhd b/trb3_gbe/config_default.vhd
index a0fe19d19f20e1184c2c8f44fc89c3a3003539d2..266f5051344234fd6f11a9007e4b7a3ac629d65a 100644 (file)
--- a/trb3_gbe/config_default.vhd
+++ b/trb3_gbe/config_default.vhd
@@ -39,12 +39,14 @@ package config is
 
 --Statistics for generated trigger signals?
     constant INCLUDE_STATISTICS     : integer := c_YES;
+    constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;
+    constant PHYSICAL_INPUTS        : integer := 16;    
     
 ------------------------------------------------------------------------------
 --End of design configuration
 ------------------------------------------------------------------------------
 
-
+function generateIncludedFeatures return std_logic_vector;
 
 
 -- Be careful when setting the MII_NUMBER and MII_IS_* generics!
@@ -94,10 +96,8 @@ package config is
     constant USED_CHANNELS_ARR    : hub_chn_t := ((1,1,0,1),(0,0,0,1));
     constant CLOCK_FREQUENCY_ARR  : hub_mii_t := (100,125);
     constant MEDIA_FREQUENCY_ARR  : hub_mii_t := (200,125);
-                          
-    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0) := (others => '0');       
-                          
-                          
+
+
   --declare constants, filled in body                          
     constant INTERNAL_NUM         : integer;
     constant INTERFACE_NUM        : integer;
@@ -109,11 +109,29 @@ package config is
     constant USED_CHANNELS        : hub_channel_config_t;
     constant CLOCK_FREQUENCY      : integer;
     constant MEDIA_FREQUENCY      : integer;
+    constant INCLUDED_FEATURES    : std_logic_vector(63 downto 0);
+
 
 end;
 
 package body config is
---compute correct configuration mode
+  --compute correct configuration mode
+  function generateIncludedFeatures return std_logic_vector is
+    variable t : std_logic_vector(63 downto 0);
+  begin
+    t               := (others => '0');
+    t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+    t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1));
+    t(17 downto 17) := std_logic_vector(to_unsigned(1,1)); --sctrl via GbE
+    t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet
+    t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+    t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+    t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1));
+    t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+    t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+    return t;
+  end function;  
+
   constant CFG_MODE : integer := USE_ETHERNET;
   constant HW_INFO_MODE : integer := USE_ETHERNET + 2 * USE_RXCLOCK + 4 * USE_SCTRL_ONLY;
 
@@ -127,5 +145,5 @@ package body config is
   constant USED_CHANNELS        : hub_channel_config_t := USED_CHANNELS_ARR(USE_SCTRL_ONLY);
   constant CLOCK_FREQUENCY      : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
   constant MEDIA_FREQUENCY      : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
-  
+  constant INCLUDED_FEATURES    : std_logic_vector := generateIncludedFeatures;
 end package body;
\ No newline at end of file

diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd
index 052920979de4e3120f7f3a95d82cde4c1cb4cdaa..ab55f2e6225db55e9bfbcb1ec277f4285fa47f1f 100644 (file)
--- a/trb3_gbe/trb3_central.vhd
+++ b/trb3_gbe/trb3_central.vhd
@@ -568,7 +568,7 @@ gen_ethernet_hub : if USE_ETHERNET = c_YES generate
     MII_IS_UPLINK_ONLY  => IS_UPLINK_ONLY,
     USE_ONEWIRE         => c_YES,
     HARDWARE_VERSION    => HARDWARE_INFO,
-    INCLUDED_FEATURES      => INCLUDED_FEATURES,
+    INCLUDED_FEATURES   => INCLUDED_FEATURES,
     INIT_ENDPOINT_ID    => x"0005",
     CLOCK_FREQUENCY     => CLOCK_FREQUENCY,
     BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
@@ -918,9 +918,10 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
 ---------------------------------------------------------------------------
 -- Trigger logic
 ---------------------------------------------------------------------------
+gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
   THE_TRIG_LOGIC : input_to_trigger_logic
     generic map(
-      INPUTS    => 16,
+      INPUTS    => PHYSICAL_INPUTS,
       OUTPUTS   => 5
       )
     port map(
@@ -936,10 +937,11 @@ THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
       ACK_OUT   => trig_ack,  
       NACK_OUT  => trig_nack, 
       ADDR_IN   => trig_addr
-      );
+      );      
 
-TRIGGER_OUT2 <= trig_outputs(0);       
-trig_inputs <= FPGA4_COMM(10 downto 7) & FPGA3_COMM(10 downto 7) & FPGA2_COMM(10 downto 7) & FPGA1_COMM(10 downto 7); 
+  TRIGGER_OUT2 <= trig_outputs(0);       
+  trig_inputs <= FPGA4_COMM(10 downto 7) & FPGA3_COMM(10 downto 7) & FPGA2_COMM(10 downto 7) & FPGA1_COMM(10 downto 7); 
+end generate;
 
 ---------------------------------------------------------------------------
 -- Input Statistics