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+ <Options/>
+ </Source>
+ <Source name="../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../tdc_releases/tdc_v1.1.1/TDC.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../tdc_releases/tdc_v1.1.1/up_counter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="trb3_periph_sodasource"/>
+ </Source>
+ <Source name="../tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
<Source name="trb3_periph_sodasource.lpf" type="Logic Preference" type_short="LPF">
<Options/>
- </Source> </Implementation> <Strategy name="Strategy1" file="SODA_source1.sty"/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="SODA_source1.sty"/>
</BaliProject>
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology LATTICE-ECP3
+set_option -part LFE3_150EA
+set_option -package FN672C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb3_periph_sodasource"
+set_option -resource_sharing true
+
+# map options
+set_option -frequency 200
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+#set_option -force_gsr
+set_option -force_gsr false
+set_option -fixgatedclocks false #3
+set_option -fixgeneratedclocks false #3
+set_option -compiler_compatible true
+
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb3_periph_sodasource.edf"
+
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+
+
+#add_file options
+
+add_file -vhdl -lib work "version.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
+
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
+
+
+
+
+###############
+#Change path to tdc release also in compile script!
+###############
+#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd"
+add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd"
+
+add_file -vhdl -lib "work" "trb3_periph_sodasource.vhd"
+
use work.trb3_components.all;
use work.version.all;
-
-entity trb3_periph_padiwa is
+entity trb3_periph_sodasource is
generic(
- SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission.
+ SYNC_MODE : integer range 0 to 1 := c_NO --use the RX clock for internal logic and transmission. 4 SFP links only.
);
port(
--Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 6
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 4 <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Manager 3
- CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1
- --CLK_PCLK_RIGHT is the only clock with external termination !?
- CLK_EXTERNAL : in std_logic; --Clock Manager 9
-
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
--- --Trigger
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
--- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
+ --Trigger
+ TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
+ TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
--Serdes
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
- SERDES_TX : out std_logic_vector(3 downto 2);
- SERDES_RX : in std_logic_vector(3 downto 2);
-
+ CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
+ CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
+-- SERDES_INT_TX : out std_logic_vector(3 downto 0);
+-- SERDES_INT_RX : in std_logic_vector(3 downto 0);
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
+
+ --Inter-FPGA Communication
FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
-
-
- --Connections
- SPARE_LINE : inout std_logic_vector(3 downto 0);
- INP : in std_logic_vector(63 downto 0);
+ --Bit 0/1 input, serial link RX active
+ --Bit 2/3 output, serial link TX active
+ --others yet undefined
+ --Connection to AddOn
+ LED_LINKOK : out std_logic_vector(6 downto 1);
+ LED_RX : out std_logic_vector(6 downto 1);
+ LED_TX : out std_logic_vector(6 downto 1);
+ SFP_MOD0 : in std_logic_vector(6 downto 1);
+ SFP_TXDIS : out std_logic_vector(6 downto 1);
+ SFP_LOS : in std_logic_vector(6 downto 1);
+-- SFP_MOD1 : inout std_logic_vector(6 downto 1);
+-- SFP_MOD2 : inout std_logic_vector(6 downto 1);
+-- SFP_RATESEL : out std_logic_vector(6 downto 1);
+-- SFP_TXFAULT : in std_logic_vector(6 downto 1);
--Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --DAC
- OUT_SDO : out std_logic_vector(4 downto 1);
- IN_SDI : in std_logic_vector(4 downto 1);
- OUT_SCK : out std_logic_vector(4 downto 1);
- OUT_CS : out std_logic_vector(4 downto 1);
+ FLASH_CLK : out std_logic;
+ FLASH_CS : out std_logic;
+ FLASH_DIN : out std_logic;
+ FLASH_DOUT : in std_logic;
+ PROGRAMN : out std_logic; --reboot FPGA
+
--Misc
TEMPSENS : inout std_logic; --Temperature Sensor
CODE_LINE : in std_logic_vector(1 downto 0);
LED_ORANGE : out std_logic;
LED_RED : out std_logic;
LED_YELLOW : out std_logic;
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
--Test Connectors
TEST_LINE : out std_logic_vector(15 downto 0)
);
- attribute syn_useioff : boolean;
+ attribute syn_useioff : boolean;
--no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of LED_GREEN : signal is false;
+ attribute syn_useioff of LED_ORANGE : signal is false;
+ attribute syn_useioff of LED_RED : signal is false;
+ attribute syn_useioff of LED_YELLOW : signal is false;
+ attribute syn_useioff of TEMPSENS : signal is false;
+ attribute syn_useioff of PROGRAMN : signal is false;
+ attribute syn_useioff of CODE_LINE : signal is false;
+ attribute syn_useioff of TRIGGER_LEFT : signal is false;
+ attribute syn_useioff of TRIGGER_RIGHT : signal is false;
+ attribute syn_useioff of LED_LINKOK : signal is false;
+ attribute syn_useioff of LED_TX : signal is false;
+ attribute syn_useioff of LED_RX : signal is false;
+ attribute syn_useioff of SFP_MOD0 : signal is false;
+ attribute syn_useioff of SFP_TXDIS : signal is false;
+ attribute syn_useioff of SFP_LOS : signal is false;
+
--important signals _with_ IO-FF
- attribute syn_useioff of OUT_SCK : signal is true;
- attribute syn_useioff of OUT_CS : signal is true;
- attribute syn_useioff of OUT_SDO : signal is true;
attribute syn_useioff of FLASH_CLK : signal is true;
attribute syn_useioff of FLASH_CS : signal is true;
attribute syn_useioff of FLASH_DIN : signal is true;
attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of TEST_LINE : signal is true;
- attribute syn_useioff of SPARE_LINE : signal is true;
+ attribute syn_useioff of FPGA5_COMM : signal is true;
+ attribute syn_useioff of TEST_LINE : signal is false;
+-- attribute syn_useioff of DQLL : signal is true;
+-- attribute syn_useioff of DQUL : signal is true;
+-- attribute syn_useioff of DQLR : signal is true;
+-- attribute syn_useioff of DQUR : signal is true;
+-- attribute syn_useioff of SPARE_LINE : signal is true;
end entity;
-architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
+architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
--Constants
constant REGIO_NUM_STAT_REGS : integer := 0;
constant REGIO_NUM_CTRL_REGS : integer := 2;
CLK_RX_FULL_OUT => rx_clock_200,
--SFP Connection
- SD_RXD_P_IN => SERDES_RX(2),
- SD_RXD_N_IN => SERDES_RX(3),
- SD_TXD_P_OUT => SERDES_TX(2),
- SD_TXD_N_OUT => SERDES_TX(3),
+ SD_RXD_P_IN => SERDES_ADDON_RX(2),
+ SD_RXD_N_IN => SERDES_ADDON_RX(3),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(2),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(3),
SD_REFCLK_P_IN => open,
SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => FPGA5_COMM(0),
STAT => open
);
----------------------------------------------------------------------------
--- DAC
----------------------------------------------------------------------------
- THE_DAC_SPI : spi_ltc2600
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => dac_addr,
- BUS_READ_IN => dac_read_en,
- BUS_WRITE_IN => dac_write_en,
- BUS_ACK_OUT => dac_ack,
- BUS_BUSY_OUT => dac_busy,
- BUS_DATA_IN => dac_data_in,
- BUS_DATA_OUT => dac_data_out,
- -- SPI connections
- SPI_CS_OUT(3 downto 0) => padiwa_cs,
- SPI_SDI_IN => padiwa_sdi,
- SPI_SDO_OUT => padiwa_sdo,
- SPI_SCK_OUT => padiwa_sck
- );
- OUT_CS <= padiwa_cs(3 downto 0);
- OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
- OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
- padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
---------------------------------------------------------------------------
-- Reboot FPGA
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
- THE_TDC : TDC
- generic map (
- CHANNEL_NUMBER => 5, -- Number of TDC channels
- STATUS_REG_NR => REGIO_NUM_STAT_REGS,
- CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
- port map (
- RESET => reset_i,
- CLK_TDC => clk_tdc, -- Clock used for the time measurement
- CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(3 downto 0), -- Channel start signals
- TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
- TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
- --
- -- Trigger signals from handler
- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
- SPIKE_DETECTED_IN => trg_spike_detected_i,
- MULTI_TMG_TRG_IN => trg_multiple_trg_i,
- SPURIOUS_TRG_IN => trg_spurious_trg_i,
- --
- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
- TRG_CODE_IN => trg_code_i, --
- TRG_INFORMATION_IN => trg_information_i, --
- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
- --
- --Response to handler
- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
- DATA_OUT => fee_data_i, -- tdc data
- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
- --
- --Hit Counter Bus
- HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
- HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
- HCB_ADDR_IN => hitreg_addr, -- bus address
- HCB_DATA_OUT => hitreg_data_out, -- bus data
- HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
- HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
- --Status Registers Bus
- SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
- SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
- SRB_ADDR_IN => srb_addr, -- bus address
- SRB_DATA_OUT => srb_data_out, -- bus data
- SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
- SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
- --Encoder Start Registers Bus
- ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
- ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
- ESB_ADDR_IN => esb_addr, -- bus address
- ESB_DATA_OUT => esb_data_out, -- bus data
- ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
- ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
- --Fifo Write Registers Bus
- FWB_READ_EN_IN => fwb_read_en, -- bus read en strobe
- FWB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe
- FWB_ADDR_IN => fwb_addr, -- bus address
- FWB_DATA_OUT => fwb_data_out, -- bus data
- FWB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe
- FWB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr
- --Lost Hit Registers Bus
- LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
- LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
- LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
- LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
- LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
- LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
- --
- LOGIC_ANALYSER_OUT => TEST_LINE,
- CONTROL_REG_IN => ctrl_reg);
-
-
- hit_in_i <= INP;
+ --THE_TDC : TDC
+ --generic map (
+ --CHANNEL_NUMBER => 5, -- Number of TDC channels
+ --STATUS_REG_NR => REGIO_NUM_STAT_REGS,
+ --CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
+ --port map (
+ --RESET => reset_i,
+ --CLK_TDC => clk_tdc, -- Clock used for the time measurement
+ --CLK_READOUT => clk_100_i, -- Clock for the readout
+ --REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ --HIT_IN => hit_in_i(3 downto 0), -- Channel start signals
+ --TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width
+ --TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width
+ ----
+ ---- Trigger signals from handler
+ --TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
+ --VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
+ --VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
+ --INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
+ --TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
+ --SPIKE_DETECTED_IN => trg_spike_detected_i,
+ --MULTI_TMG_TRG_IN => trg_multiple_trg_i,
+ --SPURIOUS_TRG_IN => trg_spurious_trg_i,
+ ----
+ --TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
+ --TRG_CODE_IN => trg_code_i, --
+ --TRG_INFORMATION_IN => trg_information_i, --
+ --TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
+ ----
+ ----Response to handler
+ --TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
+ --TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
+ --DATA_OUT => fee_data_i, -- tdc data
+ --DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
+ --DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
+ ----
+ ----Hit Counter Bus
+ --HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
+ --HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
+ --HCB_ADDR_IN => hitreg_addr, -- bus address
+ --HCB_DATA_OUT => hitreg_data_out, -- bus data
+ --HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
+ --HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
+ ----Status Registers Bus
+ --SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
+ --SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
+ --SRB_ADDR_IN => srb_addr, -- bus address
+ --SRB_DATA_OUT => srb_data_out, -- bus data
+ --SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
+ --SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
+ ----Encoder Start Registers Bus
+ --ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
+ --ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
+ --ESB_ADDR_IN => esb_addr, -- bus address
+ --ESB_DATA_OUT => esb_data_out, -- bus data
+ --ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
+ --ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
+ ----Fifo Write Registers Bus
+ --FWB_READ_EN_IN => fwb_read_en, -- bus read en strobe
+ --FWB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe
+ --FWB_ADDR_IN => fwb_addr, -- bus address
+ --FWB_DATA_OUT => fwb_data_out, -- bus data
+ --FWB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe
+ --FWB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr
+ ----Lost Hit Registers Bus
+ --LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe
+ --LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe
+ --LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address
+ --LHB_DATA_OUT => open, -- lhb_data_out, -- bus data
+ --LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe
+ --LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr
+ ----
+ --LOGIC_ANALYSER_OUT => TEST_LINE,
+ --CONTROL_REG_IN => ctrl_reg);
+
+
+ hit_in_i <= (others => '0');
--Gen_Hit_In_Signals : for i in 0 to 31 generate
-- hit_in_i(i*2) <= INP(i);
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+ SYSCONFIG MCCLK_FREQ = 20;
+
+ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+ FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
+
+#################################################################
+# Reset Nets
+#################################################################
+GSR_NET NET "GSR_N";
+
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
+
+LOCATE COMP "THE_MEDIA_DOWNLINK/gen_serdes_200/PCSD_INST" SITE "PCSB" ;
+
+
+REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+REGION "MEDIA_DOWNLINK" "R55C120D" 25 35;
+REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
+REGION "REGION_IOBUF" "R10C43D" 88 86 DEVSIZE;
+
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+
+LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "THE_MEDIA_DOWNLINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
package version is
- constant VERSION_NUMBER_TIME : integer := 1358442567;
+ constant VERSION_NUMBER_TIME : integer := 1360760605;
end package version;
jspc29 / trb3.git / commitdiff