CBM

diff --git a/cts/source/cts_trigger.vhd b/cts/source/cts_trigger.vhd
index a255a9fc40ec09f8fc9a85e49107bab01d987fd8..5bf966694caa06b972131067eb38d14fe465ea16 100755 (executable)
--- a/cts/source/cts_trigger.vhd
+++ b/cts/source/cts_trigger.vhd
@@ -4,6 +4,7 @@
    
 library work;
    use work.cts_pkg.all;
+   use work.trb_net_std.all;
    
 entity CTS_TRIGGER is
    generic (
@@ -59,7 +60,8 @@ architecture RTL of CTS_TRIGGER is
    signal channel_mask_i : std_logic_vector(15 downto 0);
    signal channel_edge_select_i : std_logic_vector(15 downto 0);
 
-   constant ITC_NUM_EXT     : integer := MIN(0, to_integer(unsigned(EXTERNAL_TRIGGER_ID)));
+   constant ITC_NUM_EXT_BUF : unsigned(0 downto 0) := (others => or_all(EXTERNAL_TRIGGER_ID));  -- oh, that's dirty, but dont know a better solution (but define a func)
+   constant ITC_NUM_EXT     : integer := to_integer( ITC_NUM_EXT_BUF )  ;
    
    constant ITC_BASE_EXT    : integer := 0; 
    constant ITC_BASE_PULSER : integer      := ITC_BASE_EXT         + ITC_NUM_EXT;
@@ -86,6 +88,8 @@ architecture RTL of CTS_TRIGGER is
    signal channel_edge_counters_i : channel_counters_t;
    
 -- Trigger Inputs (Spike Rejection, Negation, Override ...)
+   signal triggers_i : std_logic_vector(TRIGGERS_IN'RANGE);
+
    type trigger_input_configs_t is array(TRIGGER_INPUT_COUNT - 1 downto 0) of std_logic_vector(10 downto 0);
    signal trigger_input_configs_i : trigger_input_configs_t;
 
@@ -120,7 +124,15 @@ begin
 
    NUM_OF_ITC_USED_OUT <= STD_LOGIC_VECTOR(TO_UNSIGNED(ITC_NUM_USED, 5));
    EXT_CONTROL_OUT <= ext_control_i;
-   
+
+-- Modules   
+   proc_input_ffs: process(CLK_IN) is
+   begin
+      if rising_edge(CLK_IN) then
+         triggers_i <= TRIGGERS_IN;
+      end if;
+   end process;
+
    gen_ext_trigger: if EXTERNAL_TRIGGER_ID /= X"00" generate
       channels_i(ITC_BASE_EXT) <= EXT_TRIGGER_IN;
    end generate;
@@ -129,7 +141,7 @@ begin
       my_trigger_input: CTS_TRG_INPUT port map (
          CLK_IN => CLK_IN,
          RST_IN => RESET_IN,
-         DATA_IN => TRIGGERS_IN(i),
+         DATA_IN => triggers_i(i),
          DATA_OUT => trigger_inputs_i(i),
          CONFIG_IN => trigger_input_configs_i(i)
       );
@@ -177,6 +189,8 @@ begin
          end loop;
       end if;
    end process;
+
+-- Common   
    
    proc_output: process(CLK_IN) is
       variable channels_delay_v : std_logic_vector(15 downto 0) := (others => '1');
@@ -211,7 +225,7 @@ begin
    end process;
    
    proc_counter: process(CLK_IN) is
-      variable last_inputs_v : std_logic_vector(triggers_in'range);
+      variable last_inputs_v : std_logic_vector(triggers_i'range);
       variable last_itc_v : std_logic_vector(channels_i'range);
    
    begin
@@ -224,7 +238,7 @@ begin
          
          else
             for i in 0 to TRIGGER_INPUT_COUNT-1 loop
-               if TRIGGERS_IN(i) = '1' then
+               if triggers_i(i) = '1' then
                   trigger_input_counters_i(i) <= trigger_input_counters_i(i) + "1";
                   
                   if last_inputs_v(i) = '0' then
@@ -245,7 +259,7 @@ begin
             
          end if;
          
-         last_inputs_v := TRIGGERS_IN;
+         last_inputs_v := triggers_i;
          last_itc_v := channels_i;
       end if;
    end process;
@@ -462,7 +476,7 @@ begin
                      id   => 16#50#,
                      len  => TRIGGER_RAND_PULSER,
                      itc_base => ITC_BASE_RAND_PULSER,
-                     itc_num  => 1,
+                     itc_num  => TRIGGER_RAND_PULSER,
                      last => false
                   );
                end if;

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 6c751cfb509503eb06bed91cf0de7c82b78a49d9..18259f12ad71b87b5c1fd5a74d159d08f5049bf2 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -56,6 +56,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "../base/trb3_components.vhd"
+add_file -vhdl -lib work "../base/code/mbs_vulom_recv.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"

diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 929f9437b8ddd9740edc58a887fec410f701ab70..6348b08b6ab23bc386cafb8d9e3a39411d054169 100644 (file)
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -174,185 +174,237 @@ entity trb3_central is
 end entity;
 
 architecture trb3_central_arch of trb3_central is
-  attribute syn_keep : boolean;
-  attribute syn_preserve : boolean;
-  
-  signal clk_100_i   : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-  signal clk_200_i   : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-  signal pll_lock    : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
-  signal clear_i     : std_logic;
-  signal reset_i     : std_logic;
-  signal GSR_N       : std_logic;
-  attribute syn_keep of GSR_N : signal is true;
-  attribute syn_preserve of GSR_N : signal is true;
-  
-  --FPGA Test
-  signal time_counter, time_counter2 : unsigned(31 downto 0);
-  
-  --Media Interface
-  signal med_stat_op             : std_logic_vector (5*16-1  downto 0);
-  signal med_ctrl_op             : std_logic_vector (5*16-1  downto 0);
-  signal med_stat_debug          : std_logic_vector (5*64-1  downto 0);
-  signal med_ctrl_debug          : std_logic_vector (5*64-1  downto 0);
-  signal med_data_out            : std_logic_vector (5*16-1  downto 0);
-  signal med_packet_num_out      : std_logic_vector (5*3-1   downto 0);
-  signal med_dataready_out       : std_logic_vector (5*1-1   downto 0);
-  signal med_read_out            : std_logic_vector (5*1-1   downto 0);
-  signal med_data_in             : std_logic_vector (5*16-1  downto 0);
-  signal med_packet_num_in       : std_logic_vector (5*3-1   downto 0);
-  signal med_dataready_in        : std_logic_vector (5*1-1   downto 0);
-  signal med_read_in             : std_logic_vector (5*1-1   downto 0);
-  
-  --Hub
-  signal common_stat_regs        : std_logic_vector (std_COMSTATREG*32-1 downto 0);
-  signal common_ctrl_regs        : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
-  signal my_address              : std_logic_vector (16-1 downto 0);
-  signal regio_addr_out          : std_logic_vector (16-1 downto 0);
-  signal regio_read_enable_out   : std_logic;
-  signal regio_write_enable_out  : std_logic;
-  signal regio_data_out          : std_logic_vector (32-1 downto 0);
-  signal regio_data_in           : std_logic_vector (32-1 downto 0);
-  signal regio_dataready_in      : std_logic;
-  signal regio_no_more_data_in   : std_logic;
-  signal regio_write_ack_in      : std_logic;
-  signal regio_unknown_addr_in   : std_logic;
-  signal regio_timeout_out       : std_logic;
-  
-  signal spictrl_read_en         : std_logic;
-  signal spictrl_write_en        : std_logic;
-  signal spictrl_data_in         : std_logic_vector(31 downto 0);
-  signal spictrl_addr            : std_logic;
-  signal spictrl_data_out        : std_logic_vector(31 downto 0);
-  signal spictrl_ack             : std_logic;
-  signal spictrl_busy            : std_logic;
-  signal spimem_read_en          : std_logic;
-  signal spimem_write_en         : std_logic;
-  signal spimem_data_in          : std_logic_vector(31 downto 0);
-  signal spimem_addr             : std_logic_vector(5 downto 0);
-  signal spimem_data_out         : std_logic_vector(31 downto 0);
-  signal spimem_ack              : std_logic;
-
-  signal spi_bram_addr           : std_logic_vector(7 downto 0);
-  signal spi_bram_wr_d           : std_logic_vector(7 downto 0);
-  signal spi_bram_rd_d           : std_logic_vector(7 downto 0);
-  signal spi_bram_we             : std_logic;
-
-  signal gbe_cts_number                   : std_logic_vector(15 downto 0);
-  signal gbe_cts_code                     : std_logic_vector(7 downto 0);
-  signal gbe_cts_information              : std_logic_vector(7 downto 0);
-  signal gbe_cts_start_readout            : std_logic;
-  signal gbe_cts_readout_type             : std_logic_vector(3 downto 0);
-  signal gbe_cts_readout_finished         : std_logic;
-  signal gbe_cts_status_bits              : std_logic_vector(31 downto 0);
-  signal gbe_fee_data                     : std_logic_vector(15 downto 0);
-  signal gbe_fee_dataready                : std_logic;
-  signal gbe_fee_read                     : std_logic;
-  signal gbe_fee_status_bits              : std_logic_vector(31 downto 0);
-  signal gbe_fee_busy                     : std_logic;
-
-signal stage_stat_regs              : std_logic_vector (31 downto 0);
-signal stage_ctrl_regs              : std_logic_vector (31 downto 0);
-
-signal mb_stat_reg_data_wr          : std_logic_vector(31 downto 0);
-signal mb_stat_reg_data_rd          : std_logic_vector(31 downto 0);
-signal mb_stat_reg_read             : std_logic;
-signal mb_stat_reg_write            : std_logic;
-signal mb_stat_reg_ack              : std_logic;
-signal mb_ip_mem_addr               : std_logic_vector(15 downto 0); -- only [7:0] in used
-signal mb_ip_mem_data_wr            : std_logic_vector(31 downto 0);
-signal mb_ip_mem_data_rd            : std_logic_vector(31 downto 0);
-signal mb_ip_mem_read               : std_logic;
-signal mb_ip_mem_write              : std_logic;
-signal mb_ip_mem_ack                : std_logic;
-signal ip_cfg_mem_clk                          : std_logic;
-signal ip_cfg_mem_addr                         : std_logic_vector(7 downto 0);
-signal ip_cfg_mem_data                         : std_logic_vector(31 downto 0);
-signal ctrl_reg_addr                : std_logic_vector(15 downto 0);
-signal gbe_stp_reg_addr             : std_logic_vector(15 downto 0);
-signal gbe_stp_data                 : std_logic_vector(31 downto 0);
-signal gbe_stp_reg_ack              : std_logic;
-signal gbe_stp_reg_data_wr          : std_logic_vector(31 downto 0);
-signal gbe_stp_reg_read             : std_logic;
-signal gbe_stp_reg_write            : std_logic;
-signal gbe_stp_reg_data_rd          : std_logic_vector(31 downto 0);
-
-signal debug : std_logic_vector(63 downto 0);
-
-signal next_reset, make_reset_via_network_q : std_logic;
-signal reset_counter : std_logic_vector(11 downto 0);
-signal link_ok : std_logic;
-
-signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
-signal gsc_init_read, gsc_reply_read : std_logic;
-signal gsc_init_dataready, gsc_reply_dataready : std_logic;
-signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
-signal gsc_busy : std_logic;
-signal mc_unique_id  : std_logic_vector(63 downto 0);
-signal trb_reset_in  : std_logic;
-signal reset_via_gbe : std_logic;
-signal reset_via_gbe_delayed : std_logic_vector(2 downto 0);
-signal reset_i_temp  : std_logic;
-
-signal cts_rdo_trigger             : std_logic;
-signal cts_rdo_trg_data_valid      : std_logic;
-signal cts_rdo_valid_timing_trg    : std_logic;
-signal cts_rdo_valid_notiming_trg  : std_logic;
-signal cts_rdo_invalid_trg         : std_logic;
-
-signal cts_rdo_trg_status_bits     : std_logic_vector(31 downto 0);
-signal cts_rdo_data                : std_logic_vector(31 downto 0);
-signal cts_rdo_write               : std_logic;
-signal cts_rdo_finished            : std_logic;
-
-signal cts_ext_trigger             : std_logic;
-signal cts_ext_status              : std_logic_vector(31 downto 0) := (others => '0');
-signal cts_ext_control             : std_logic_vector(31 downto 0);
-
-signal cts_rdo_additional_data     : std_logic_vector(31 downto 0);
-signal cts_rdo_additional_write    : std_logic := '0';
-signal cts_rdo_additional_finished : std_logic := '1';
-
-signal cts_trg_send                : std_logic;
-signal cts_trg_type                : std_logic_vector(3 downto 0);
-signal cts_trg_number              : std_logic_vector(15 downto 0);
-signal cts_trg_information         : std_logic_vector(23 downto 0);
-signal cts_trg_code                : std_logic_vector(7 downto 0);
-signal cts_trg_status_bits         : std_logic_vector(31 downto 0);
-signal cts_trg_busy                : std_logic;
-
-signal cts_ipu_send                : std_logic;
-signal cts_ipu_type                : std_logic_vector(3 downto 0);
-signal cts_ipu_number              : std_logic_vector(15 downto 0);
-signal cts_ipu_information         : std_logic_vector(7 downto 0);
-signal cts_ipu_code                : std_logic_vector(7 downto 0);
-signal cts_ipu_status_bits         : std_logic_vector(31 downto 0);
-signal cts_ipu_busy                : std_logic;
-
-signal cts_regio_addr              : std_logic_vector(15 downto 0);
-signal cts_regio_read              : std_logic;
-signal cts_regio_write             : std_logic;
-signal cts_regio_data_out          : std_logic_vector(31 downto 0);
-signal cts_regio_data_in           : std_logic_vector(31 downto 0);
-signal cts_regio_dataready         : std_logic;
-signal cts_regio_no_more_data      : std_logic;
-signal cts_regio_write_ack         : std_logic;
-signal cts_regio_unknown_addr      : std_logic;
-
-signal cts_trigger_out             : std_logic;
-signal external_send_reset         : std_logic;
-signal timer_ticks                 : std_logic_vector(1 downto 0);
-
-signal trigger_busy_i          : std_logic;
-signal trigger_in_buf_i        : std_logic_vector(3 downto 0);
+   attribute syn_keep : boolean;
+   attribute syn_preserve : boolean;
+
+   signal clk_100_i   : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+   signal clk_200_i   : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+   signal pll_lock    : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+   signal clear_i     : std_logic;
+   signal reset_i     : std_logic;
+   signal GSR_N       : std_logic;
+   attribute syn_keep of GSR_N : signal is true;
+   attribute syn_preserve of GSR_N : signal is true;
+
+   --FPGA Test
+   signal time_counter, time_counter2 : unsigned(31 downto 0);
+
+   --Media Interface
+   signal med_stat_op             : std_logic_vector (5*16-1  downto 0);
+   signal med_ctrl_op             : std_logic_vector (5*16-1  downto 0);
+   signal med_stat_debug          : std_logic_vector (5*64-1  downto 0);
+   signal med_ctrl_debug          : std_logic_vector (5*64-1  downto 0);
+   signal med_data_out            : std_logic_vector (5*16-1  downto 0);
+   signal med_packet_num_out      : std_logic_vector (5*3-1   downto 0);
+   signal med_dataready_out       : std_logic_vector (5*1-1   downto 0);
+   signal med_read_out            : std_logic_vector (5*1-1   downto 0);
+   signal med_data_in             : std_logic_vector (5*16-1  downto 0);
+   signal med_packet_num_in       : std_logic_vector (5*3-1   downto 0);
+   signal med_dataready_in        : std_logic_vector (5*1-1   downto 0);
+   signal med_read_in             : std_logic_vector (5*1-1   downto 0);
+
+   --Hub
+   signal common_stat_regs        : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+   signal common_ctrl_regs        : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+   signal my_address              : std_logic_vector (16-1 downto 0);
+   signal regio_addr_out          : std_logic_vector (16-1 downto 0);
+   signal regio_read_enable_out   : std_logic;
+   signal regio_write_enable_out  : std_logic;
+   signal regio_data_out          : std_logic_vector (32-1 downto 0);
+   signal regio_data_in           : std_logic_vector (32-1 downto 0);
+   signal regio_dataready_in      : std_logic;
+   signal regio_no_more_data_in   : std_logic;
+   signal regio_write_ack_in      : std_logic;
+   signal regio_unknown_addr_in   : std_logic;
+   signal regio_timeout_out       : std_logic;
+
+   signal spictrl_read_en         : std_logic;
+   signal spictrl_write_en        : std_logic;
+   signal spictrl_data_in         : std_logic_vector(31 downto 0);
+   signal spictrl_addr            : std_logic;
+   signal spictrl_data_out        : std_logic_vector(31 downto 0);
+   signal spictrl_ack             : std_logic;
+   signal spictrl_busy            : std_logic;
+   signal spimem_read_en          : std_logic;
+   signal spimem_write_en         : std_logic;
+   signal spimem_data_in          : std_logic_vector(31 downto 0);
+   signal spimem_addr             : std_logic_vector(5 downto 0);
+   signal spimem_data_out         : std_logic_vector(31 downto 0);
+   signal spimem_ack              : std_logic;
+
+   signal spi_bram_addr           : std_logic_vector(7 downto 0);
+   signal spi_bram_wr_d           : std_logic_vector(7 downto 0);
+   signal spi_bram_rd_d           : std_logic_vector(7 downto 0);
+   signal spi_bram_we             : std_logic;
+
+   signal gbe_cts_number                   : std_logic_vector(15 downto 0);
+   signal gbe_cts_code                     : std_logic_vector(7 downto 0);
+   signal gbe_cts_information              : std_logic_vector(7 downto 0);
+   signal gbe_cts_start_readout            : std_logic;
+   signal gbe_cts_readout_type             : std_logic_vector(3 downto 0);
+   signal gbe_cts_readout_finished         : std_logic;
+   signal gbe_cts_status_bits              : std_logic_vector(31 downto 0);
+   signal gbe_fee_data                     : std_logic_vector(15 downto 0);
+   signal gbe_fee_dataready                : std_logic;
+   signal gbe_fee_read                     : std_logic;
+   signal gbe_fee_status_bits              : std_logic_vector(31 downto 0);
+   signal gbe_fee_busy                     : std_logic;
+
+   signal stage_stat_regs              : std_logic_vector (31 downto 0);
+   signal stage_ctrl_regs              : std_logic_vector (31 downto 0);
+
+   signal mb_stat_reg_data_wr          : std_logic_vector(31 downto 0);
+   signal mb_stat_reg_data_rd          : std_logic_vector(31 downto 0);
+   signal mb_stat_reg_read             : std_logic;
+   signal mb_stat_reg_write            : std_logic;
+   signal mb_stat_reg_ack              : std_logic;
+   signal mb_ip_mem_addr               : std_logic_vector(15 downto 0); -- only [7:0] in used
+   signal mb_ip_mem_data_wr            : std_logic_vector(31 downto 0);
+   signal mb_ip_mem_data_rd            : std_logic_vector(31 downto 0);
+   signal mb_ip_mem_read               : std_logic;
+   signal mb_ip_mem_write              : std_logic;
+   signal mb_ip_mem_ack                : std_logic;
+   signal ip_cfg_mem_clk                               : std_logic;
+   signal ip_cfg_mem_addr                              : std_logic_vector(7 downto 0);
+   signal ip_cfg_mem_data                              : std_logic_vector(31 downto 0);
+   signal ctrl_reg_addr                : std_logic_vector(15 downto 0);
+   signal gbe_stp_reg_addr             : std_logic_vector(15 downto 0);
+   signal gbe_stp_data                 : std_logic_vector(31 downto 0);
+   signal gbe_stp_reg_ack              : std_logic;
+   signal gbe_stp_reg_data_wr          : std_logic_vector(31 downto 0);
+   signal gbe_stp_reg_read             : std_logic;
+   signal gbe_stp_reg_write            : std_logic;
+   signal gbe_stp_reg_data_rd          : std_logic_vector(31 downto 0);
+
+   signal debug : std_logic_vector(63 downto 0);
+
+   signal next_reset, make_reset_via_network_q : std_logic;
+   signal reset_counter : std_logic_vector(11 downto 0);
+   signal link_ok : std_logic;
+
+   signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0);
+   signal gsc_init_read, gsc_reply_read : std_logic;
+   signal gsc_init_dataready, gsc_reply_dataready : std_logic;
+   signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0);
+   signal gsc_busy : std_logic;
+   signal mc_unique_id  : std_logic_vector(63 downto 0);
+   signal trb_reset_in  : std_logic;
+   signal reset_via_gbe : std_logic;
+   signal reset_via_gbe_delayed : std_logic_vector(2 downto 0);
+   signal reset_i_temp  : std_logic;
+
+   signal cts_rdo_trigger             : std_logic;
+   signal cts_rdo_trg_data_valid      : std_logic;
+   signal cts_rdo_valid_timing_trg    : std_logic;
+   signal cts_rdo_valid_notiming_trg  : std_logic;
+   signal cts_rdo_invalid_trg         : std_logic;
+
+   signal cts_rdo_trg_status_bits,
+      cts_rdo_trg_status_bits_cts,
+      cts_rdo_trg_status_bits_additional: std_logic_vector(31 downto 0) := (others => '0');
+   signal cts_rdo_data                : std_logic_vector(31 downto 0);
+   signal cts_rdo_write               : std_logic;
+   signal cts_rdo_finished            : std_logic;
+
+   signal cts_ext_trigger             : std_logic;
+   signal cts_ext_status              : std_logic_vector(31 downto 0) := (others => '0');
+   signal cts_ext_control             : std_logic_vector(31 downto 0);
+
+   signal cts_rdo_additional_data     : std_logic_vector(31 downto 0);
+   signal cts_rdo_additional_write    : std_logic := '0';
+   signal cts_rdo_additional_finished : std_logic := '1';
+
+   signal cts_trg_send                : std_logic;
+   signal cts_trg_type                : std_logic_vector(3 downto 0);
+   signal cts_trg_number              : std_logic_vector(15 downto 0);
+   signal cts_trg_information         : std_logic_vector(23 downto 0);
+   signal cts_trg_code                : std_logic_vector(7 downto 0);
+   signal cts_trg_status_bits         : std_logic_vector(31 downto 0);
+   signal cts_trg_busy                : std_logic;
+
+   signal cts_ipu_send                : std_logic;
+   signal cts_ipu_type                : std_logic_vector(3 downto 0);
+   signal cts_ipu_number              : std_logic_vector(15 downto 0);
+   signal cts_ipu_information         : std_logic_vector(7 downto 0);
+   signal cts_ipu_code                : std_logic_vector(7 downto 0);
+   signal cts_ipu_status_bits         : std_logic_vector(31 downto 0);
+   signal cts_ipu_busy                : std_logic;
+
+   signal cts_regio_addr              : std_logic_vector(15 downto 0);
+   signal cts_regio_read              : std_logic;
+   signal cts_regio_write             : std_logic;
+   signal cts_regio_data_out          : std_logic_vector(31 downto 0);
+   signal cts_regio_data_in           : std_logic_vector(31 downto 0);
+   signal cts_regio_dataready         : std_logic;
+   signal cts_regio_no_more_data      : std_logic;
+   signal cts_regio_write_ack         : std_logic;
+   signal cts_regio_unknown_addr      : std_logic;
+
+   signal cts_trigger_out             : std_logic;
+   signal external_send_reset         : std_logic;
+   signal timer_ticks                 : std_logic_vector(1 downto 0);
+   
+   signal trigger_busy_i              : std_logic;
+   signal trigger_in_buf_i            : std_logic_vector(3 downto 0);
+
+   component mbs_vulom_recv is
+   port(
+      CLK        : in std_logic;  -- e.g. 100 MHz
+      RESET_IN   : in std_logic;  -- could be used after busy_release to make sure entity is in correct state
+
+      --Module inputs
+      MBS_IN     : in std_logic;  -- raw input
+      CLK_200    : in std_logic;  -- internal sampling clock
+      
+      --trigger outputs
+      TRG_ASYNC_OUT  : out std_logic;  -- asynchronous rising edge, length varying, here: approx. 110 ns
+      TRG_SYNC_OUT   : out std_logic;  -- sync. to CLK
+
+      --data output for read-out
+      TRIGGER_IN   : in  std_logic;
+      DATA_OUT     : out std_logic_vector(31 downto 0);
+      WRITE_OUT    : out std_logic;
+      STATUSBIT_OUT: out std_logic_vector(31 downto 0);
+      FINISHED_OUT : out std_logic;
+      
+      --Registers / Debug    
+      CONTROL_REG_IN : in  std_logic_vector(31 downto 0);
+      STATUS_REG_OUT : out std_logic_vector(31 downto 0);
+      DEBUG          : out std_logic_vector(31 downto 0)    
+      );
+   end component;
+
 begin
---  TRIGGER_BUSY_OUT <= trigger_busy_i;
+-- MBS Module
+   THE_CMB: mbs_vulom_recv
+   port map (
+      CLK => clk_100_i,
+      RESET_IN => reset_i,
+      
+      MBS_IN => CLK_EXT(3),
+      CLK_200 => clk_200_i,
+      
+      -- TRG_ASYNC_OUT => ,
+      TRG_SYNC_OUT => cts_ext_trigger,
+      
+      TRIGGER_IN     => cts_rdo_trg_data_valid,
+      DATA_OUT       => cts_rdo_additional_data,
+      WRITE_OUT      => cts_rdo_additional_write,
+      STATUSBIT_OUT  => cts_rdo_trg_status_bits_additional,
+      FINISHED_OUT   => cts_rdo_additional_finished,
+
+      CONTROL_REG_IN => cts_ext_control,
+      STATUS_REG_OUT => cts_ext_status
+      
+      -- DEBUG => ''
+   );
 
    trigger_in_buf_i(1 downto 0) <= CLK_EXT;
    trigger_in_buf_i(3 downto 2) <= TRIGGER_EXT(3 downto 2);
 
    THE_CTS: CTS 
    generic map (
---      EXTERNAL_TRIGGER_ID  => X"00", fill in trigger logic enumeration id of external trigger logic
+      EXTERNAL_TRIGGER_ID  => X"60", --, fill in trigger logic enumeration id of external trigger logic
       TRIGGER_INPUT_COUNT  => 4,
       TRIGGER_COIN_COUNT   => 4,
       TRIGGER_PULSER_COUNT => 4,
@@ -400,12 +452,14 @@ begin
       LVL1_VALID_NOTIMING_TRG_IN=> cts_rdo_valid_notiming_trg,
       LVL1_INVALID_TRG_IN       => cts_rdo_invalid_trg,
   
-      FEE_TRG_STATUSBITS_OUT  => cts_rdo_trg_status_bits,
+      FEE_TRG_STATUSBITS_OUT  => cts_rdo_trg_status_bits_cts,
       FEE_DATA_OUT            => cts_rdo_data,
       FEE_DATA_WRITE_OUT      => cts_rdo_write,
       FEE_DATA_FINISHED_OUT   => cts_rdo_finished
    );   
    
+   cts_rdo_trg_status_bits <= cts_rdo_trg_status_bits_cts OR cts_rdo_trg_status_bits_additional;
+   
 ---------------------------------------------------------------------------
 -- Reset Generation
 ---------------------------------------------------------------------------