two procedure to generate trb register read/writes.

diff --git a/mupix/tb/MuPixInterfaceTest.vhd b/mupix/tb/MuPixInterfaceTest.vhd
index 21c1b8780acdf6dc977b3be552227dc2cd2e6648..1fd75b128abbfcd65456d5d355dca6c3775c293d 100644 (file)
--- a/mupix/tb/MuPixInterfaceTest.vhd
+++ b/mupix/tb/MuPixInterfaceTest.vhd
@@ -8,6 +8,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.StdTypes.all;
+use work.TRBSimulationPkg.all;
 
 entity MuPixInterfaceTest is
 end entity MuPixInterfaceTest;
@@ -104,53 +105,29 @@ begin
                mupixreadout.priout <= '0';
                wait for 100 ns;
                --generate hit
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(32, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(32, 16)), x"0500");
                if endofevent = '0' then
                        wait until endofevent ='1';
                        wait for 2*clk_period;
                end if;
                --generate hits: set wait time and start hit generation
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0503";
-               slv_data_in  <= std_logic_vector(to_unsigned(10, 32));
-               wait for clk_period;
-               slv_write_in <= '0';
-               wait for clk_period;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(64, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(10, 32)), x"0503");
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(64, 16)), x"0500"); 
                --let it run for 600 ns and then stop generation
                wait for 600 ns;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(0, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(0, 16)), x"0500");
                if endofevent = '0' then
                        wait until endofevent ='1';
                        wait for 2*clk_period;
                end if;
                --try hit generation after trigger
                wait for 2*clk_period;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(257, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(257, 16)), x"0500");
                wait for 5*clk_period;
                trigger_ext <= '1';
                wait for 2*clk_period;
@@ -164,29 +141,17 @@ begin
                wait for clk_period;
                eventcounterreset_in <= '0';
                --setup chip readout (pause and delay registers)
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0504";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)) 
-                                               & std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8));
-               wait for clk_period;
-               slv_addr_in  <= x"0507";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)) 
-                                               & std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8));
-               wait for clk_period;
-               slv_addr_in  <= x"0506";
-               slv_data_in  <= x"00000006";
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)) 
+                       & std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)), x"0504");
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                       std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)) 
+                       & std_logic_vector(to_unsigned(5, 8)) & std_logic_vector(to_unsigned(5, 8)), x"0507");
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                                                x"00000006", x"0506");
                --read now
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(4, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                                                std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(4, 16)), x"0500");
                wait for 5*clk_period;
                --continous readout
                if endofevent = '0' then
@@ -194,34 +159,15 @@ begin
                        wait for 2*clk_period;
                end if;
                wait for 5*clk_period;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(2, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                                                std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(2, 16)), x"0500");
                wait for 600 ns;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(0, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
-               --triggered readout
-               --if endofevent = '0' then
-               --      wait until endofevent ='1';
-               --      wait for 2*clk_period;
-               --end if;
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                                                std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(0, 16)), x"0500");
+               --triggered readout test
                wait for 400 ns;
-               slv_write_in <= '1';
-               slv_addr_in  <= x"0500";
-               slv_data_in  <= std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(1, 16));
-               wait for clk_period;
-               slv_write_in <= '0';
-               slv_addr_in <= (others => '0');
-               slv_data_in <= (others => '0');
+               TRBRegisterWrite(slv_write_in, slv_data_in, slv_addr_in, 
+                                                std_logic_vector(to_unsigned(5, 16)) & std_logic_vector(to_unsigned(1, 16)), x"0500");
                wait for 5*clk_period;
                trigger_ext <= '1';
                wait for clk_period;

diff --git a/mupix/tb/TRBSimulation.vhd b/mupix/tb/TRBSimulation.vhd
new file mode 100644 (file)
index 0000000..2e8dfce
--- /dev/null
+++ b/mupix/tb/TRBSimulation.vhd
@@ -0,0 +1,66 @@
+------------------------------------------------------------
+--! @file
+--! @brief Function and Procedures useful for TRB Simulation
+--! @author Tobias Weber
+--! @date August 2017
+------------------------------------------------------------ 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package TRBSimulationPkg is
+       
+       procedure TRBRegisterWrite(signal SLV_Write : out std_logic;
+               signal SLV_Data : out std_logic_vector(31 downto 0);
+               signal SLV_Addr : out std_logic_vector(15 downto 0);
+               constant data : in std_logic_vector(31 downto 0);
+               constant addr : in std_logic_vector(15 downto 0);
+               constant clk_period : in time := 10 ns);
+               
+       procedure TRBRegisterRead(signal SLV_Read : out std_logic;
+               signal SLV_Data : out std_logic_vector(31 downto 0);
+               signal SLV_Addr : out std_logic_vector(15 downto 0);
+               constant data : in std_logic_vector(31 downto 0);
+               constant addr : in std_logic_vector(15 downto 0);
+               constant clk_period : in time := 10 ns);        
+               
+end package TRBSimulationPkg;
+
+package body TRBSimulationPkg is
+
+       procedure TRBRegisterWrite(signal SLV_Write : out std_logic;
+               signal SLV_Data : out std_logic_vector(31 downto 0);
+               signal SLV_Addr : out std_logic_vector(15 downto 0);
+               constant data : in std_logic_vector(31 downto 0);
+               constant addr : in std_logic_vector(15 downto 0);
+               constant clk_period : in time := 10 ns) is
+       begin
+               SLV_Write <= '1';
+               SLV_Data <= data;
+               SLV_Addr <= addr;
+               wait for clk_period;
+               SLV_Write <= '0';
+               SLV_Data <= (others => '0');
+               SLV_Addr <= (others => '0');
+               wait for clk_period;
+       end TRBRegisterWrite;
+       
+       procedure TRBRegisterRead(signal SLV_Read : out std_logic;
+               signal SLV_Data : out std_logic_vector(31 downto 0);
+               signal SLV_Addr : out std_logic_vector(15 downto 0);
+               constant data : in std_logic_vector(31 downto 0);
+               constant addr : in std_logic_vector(15 downto 0);
+               constant clk_period : in time := 10 ns) is
+       begin
+               SLV_Read <= '1';
+               SLV_Data <= data;
+               SLV_Addr <= addr;
+               wait for clk_period;
+               SLV_Read <= '0';
+               SLV_Data <= (others => '0');
+               SLV_Addr <= (others => '0');
+               wait for clk_period;
+       end procedure TRBRegisterRead;
+       
+
+end TRBSimulationPkg;
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