made project compatible with the last tdc version

diff --git a/tdc_release b/tdc_release
index 8d7edcef0e0c758c299febe268b9dd5b7b91212a..01b50d4071b24a0e47da42049867b4332abb2193 120000 (symlink)
--- a/tdc_release
+++ b/tdc_release
@@ -1 +1 @@
-../tdc/releases/tdc_v2.2
\ No newline at end of file
+../tdc/releases/tdc_v2.3
\ No newline at end of file

diff --git a/tdctemplate/trb3sc_tdctemplate.lpf b/tdctemplate/trb3sc_tdctemplate.lpf
index c7024267f5b2975c101f09fbea5bcbec346b53bd..a5f0b63bbb757476f4a5b0dce68b0fbb795dd82a 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.lpf
+++ b/tdctemplate/trb3sc_tdctemplate.lpf
@@ -1,8 +1,8 @@
-MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full_osc" 1 X ;
-MULTICYCLE FROM CLKNET "clk_full_osc" TO CLKNET "clk_sys" 2 X ;
+#MULTICYCLE FROM CLKNET "clk_sys" TO CLKNET "clk_full_osc" 1 X ;
+#MULTICYCLE FROM CLKNET "clk_full_osc" TO CLKNET "clk_sys" 2 X ;
 
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_full_osc TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_full_osc TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
+#MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_full_osc TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
+#MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_full_osc TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_sys 2x;
 
-MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
-MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk_sys TO CLKNET clk_sys 5x;
+#MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x;

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index e2e16ebb8b7f75365c1f97387e5e231ddd13ac76..0085b3d9ae21f2eccd85cd95e16ca9c19b728dc6 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -456,6 +456,7 @@ TEST_LINE <=   med_stat_debug(15 downto 0);
       BUS_RX             => bustdc_rx,
       BUS_TX             => bustdc_tx,
       -- Dubug signals
+      INFO_IN            => timer,
       LOGIC_ANALYSER_OUT => logic_analyser_i
       );