Skip ADC1, also problematic...

diff --git a/ADC/config.vhd b/ADC/config.vhd
index e8edcfb3c315ae5f20c04f0a6946633a82aa52eb..15ca097e7770145f5eb093562667a761b90087c3 100644 (file)
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -35,9 +35,9 @@ package config is
   --These are currently used for the included features table only
   constant ADC_BASELINE_LOGIC : integer := c_YES;
   constant ADC_TRIGGER_LOGIC  : integer := c_YES;
-  -- ADC channels may be 48 or 40, the latter for enabling compilation 
+  -- ADC channels may be 48 or 36, the latter for enabling compilation 
   -- with TDC and lattice diamond version >2.1
-  constant ADC_CHANNELS       : integer := 40;
+  constant ADC_CHANNELS       : integer := 36;
 
   --Include the TDC (only usefule for CFD readout mode) 
   constant INCLUDE_TDC : integer := c_YES;

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 2096dec0576d92ea1fdf7b008f755f1e9a9c3b4b..d032e1c480dc6d398d2d08e07d6fee1729a0ca5d 100644 (file)
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -120,8 +120,8 @@ begin
 
   restart_i <= RESTART_IN when rising_edge(clk_data);
 
-  assert    (ADC_CHANNELS = 48 or ADC_CHANNELS = 40)
-    report "The number of either 48 or 40." severity error;
+  assert    (ADC_CHANNELS = 48 or ADC_CHANNELS = 36)
+    report "The number of either 48 or 36." severity error;
 
 
   gen_7 : if NUM_DEVICES = 7 and ADC_CHANNELS = 48 generate
@@ -161,17 +161,16 @@ begin
       );
   end generate;
   
-  -- skip ADC5, connected to problematic input for Diamond >2.1
-  gen_6 : if NUM_DEVICES = 7 and ADC_CHANNELS = 40 generate
-    THE_7 : entity work.dqsinput_6x5
+  -- skip ADC1 and ADC5, connected to problematic input for Diamond >2.1
+  gen_7_skip : if NUM_DEVICES = 7 and ADC_CHANNELS = 36 generate
+    THE_7 : entity work.dqsinput_5x5
       port map(
-        clk_0        => ADC_DCO(1),
-        clk_1        => ADC_DCO(2),
-        clk_2        => ADC_DCO(3),
-        clk_3        => ADC_DCO(4),
-        -- skip here as well
-        clk_4        => ADC_DCO(6),
-        clk_5        => ADC_DCO(7),
+        -- skip ADC_DCO(1) and ADC_DCO(5) as well
+        clk_0        => ADC_DCO(2),
+        clk_1        => ADC_DCO(3),
+        clk_2        => ADC_DCO(4),
+        clk_3        => ADC_DCO(6),
+        clk_4        => ADC_DCO(7),
         clkdiv_reset => RESTART_IN,
         eclk         => clk_adcfast_i,
         reset_0      => restart_i,
@@ -179,23 +178,21 @@ begin
         reset_2      => restart_i,
         reset_3      => restart_i,
         reset_4      => restart_i,
-        reset_5      => restart_i,
         sclk         => clk_data,
-        datain_0     => ADC_DATA(4 downto 0),
-        datain_1     => ADC_DATA(9 downto 5),
-        datain_2     => ADC_DATA(14 downto 10),
-        datain_3     => ADC_DATA(19 downto 15),
-        -- ADC_DATA(24 downto 20) corresponds to ADC5
-        datain_4     => ADC_DATA(29 downto 25),
-        datain_5     => ADC_DATA(34 downto 30),
-        q_0          => q(0),
-        q_1          => q(1),
-        q_2          => q(2),
-        q_3          => q(3),
-        -- skip here as well
-        q_4          => q(5),
-        q_5          => q(6)
+        -- ADC_DATA(4 downto 0) is ADC1
+        -- ADC_DATA(24 downto 20) is ADC5
+        datain_0     => ADC_DATA(9 downto 5),
+        datain_1     => ADC_DATA(14 downto 10),
+        datain_2     => ADC_DATA(19 downto 15),
+        datain_3     => ADC_DATA(29 downto 25),
+        datain_4     => ADC_DATA(34 downto 30),
+        q_0          => q(1),
+        q_1          => q(2),
+        q_2          => q(3),
+        q_3          => q(5),
+        q_4          => q(6)
       );
+      q(0) <= (others => '0');
       q(4) <= (others => '0');
   end generate;
 
@@ -229,8 +226,8 @@ begin
   end generate;
   
   -- skip ADC10, connected to problematic input for Diamond >2.1
-  gen_4 : if NUM_DEVICES = 5 and ADC_CHANNELS = 40 generate
-    THE_4 : entity work.dqsinput_4x5
+  gen_5_skip : if NUM_DEVICES = 5 and ADC_CHANNELS = 36 generate
+    THE_5 : entity work.dqsinput_4x5
       port map(
         clk_0        => ADC_DCO(1),
         clk_1        => ADC_DCO(2),